TWI740227B - Methods, apparatus, and system for high-bandwidth on-mold antennas - Google Patents
Methods, apparatus, and system for high-bandwidth on-mold antennas Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 182
- 238000004891 communication Methods 0.000 claims abstract description 86
- 229920000642 polymer Polymers 0.000 claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 claims description 65
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000012545 processing Methods 0.000 description 43
- 238000010586 diagram Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 12
- 238000000151 deposition Methods 0.000 description 10
- 238000013461 design Methods 0.000 description 10
- 230000005540 biological transmission Effects 0.000 description 9
- 230000008901 benefit Effects 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000001914 filtration Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000010267 cellular communication Effects 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012067 mathematical method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/13124—Aluminium [Al] as principal constituent
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract
Description
本發明大體有關於精密半導體裝置的製造,且更特別的是,有關於提供用於半導體裝置之射頻(RF)天線的各種方法及系統。 The present invention generally relates to the manufacture of precision semiconductor devices, and more particularly, it relates to various methods and systems for providing radio frequency (RF) antennas for semiconductor devices.
製造工業的技術爆發已促成許多新穎且創新之產品製程。所謂毫米波(mm-wave)應用包括基於電磁光譜頻率範圍在約30吉赫茲(GHz)至約300GHz之間之射頻波段運作的裝置。有些應用,例如5G通訊及物聯網(IoT)的應用,可在30GHz以下的頻率運作,例如約28GHz。毫米波射頻波有在約1毫米(mm)至約10毫米之間的波長,其對應至30GHz至約300GHz的射頻。此頻率的頻帶有時被稱為極高頻(EHF)頻帶範圍。 The technological explosion of the manufacturing industry has led to many novel and innovative product processes. The so-called millimeter wave (mm-wave) applications include devices based on the radio frequency band operating in the electromagnetic spectrum frequency range between about 30 gigahertz (GHz) and about 300 GHz. Some applications, such as 5G communications and Internet of Things (IoT) applications, can operate at frequencies below 30 GHz, such as about 28 GHz. The millimeter-wave radio frequency wave has a wavelength between about 1 millimeter (mm) and about 10 millimeters, which corresponds to a radio frequency of 30 GHz to about 300 GHz. This frequency band is sometimes referred to as the extremely high frequency (EHF) band range.
在實現5G及IoT應用時,在設計這些應用的電路時會產生許多挑戰。EHF應用要求無不連續性、低損失的傳送路徑。彼等也受益於與其他組件緊密整合的天線。不過,天線與其他組件的緊密整合通常導致低天線頻寬。典型的晶粒上(on-die)天線有約30%的效率以及約3dBi的增益。 When implementing 5G and IoT applications, many challenges arise when designing circuits for these applications. EHF applications require a transmission path with no discontinuity and low loss. They also benefit from antennas that are tightly integrated with other components. However, the tight integration of the antenna with other components usually results in a low antenna bandwidth. A typical on-die antenna has an efficiency of about 30% and a gain of about 3dBi.
本發明可應付及/或至少減少上述之一或多個問題。 The present invention can cope with and/or at least reduce one or more of the above-mentioned problems.
以下提出本發明的簡化概要以提供本揭示內容之一些方面的基本理解。此概要並非本發明的窮舉式總覽。它不是旨在鑒定本發明的關鍵或重要元件或者是敘述本發明的範疇。唯一的目的是要以簡要的形式提出一些概念作為以下更詳細之說明的前言。 The following presents a simplified summary of the present invention to provide a basic understanding of some aspects of the present disclosure. This summary is not an exhaustive overview of the invention. It is not intended to identify key or important elements of the invention or to describe the scope of the invention. The sole purpose is to present some concepts in a brief form as a prelude to the more detailed description below.
在一具體實施例中,本發明係有關於一種半導體裝置,其包括:半導體層,包括第一表面與第二表面;聚合物層,包括第一表面及第二表面,其中,該聚合物層之該第一表面靠近該半導體層之該第二表面;模具,包含第一表面及第二表面,其中,該模具之該第一表面靠近該聚合物層之該第二表面;複數個節點,靠近該半導體層之該第一表面設置;天線,設置於該模具之該第二表面上;第一傳導元件,提供在至少一第一節點與該天線之間之電性通訊;接地元件,設置於該聚合物層中或於該聚合物層之該第二表面上;以及第二傳導元件,提供在至少一第二節點與該接地元件之間之電性通訊。 In a specific embodiment, the present invention relates to a semiconductor device, which includes: a semiconductor layer including a first surface and a second surface; a polymer layer including a first surface and a second surface, wherein the polymer layer The first surface is close to the second surface of the semiconductor layer; the mold includes a first surface and a second surface, wherein the first surface of the mold is close to the second surface of the polymer layer; a plurality of nodes, Disposed near the first surface of the semiconductor layer; antenna disposed on the second surface of the mold; first conductive element providing electrical communication between at least one first node and the antenna; grounding element disposed In the polymer layer or on the second surface of the polymer layer; and a second conductive element providing electrical communication between at least one second node and the ground element.
在一具體實施例中,本發明係有關於一種設備,其包括複數個半導體裝置,其中,各半導體裝置為一上述者,且其中,該等半導體裝置的第一子集經配置為接收器天線陣列,該等半導體裝置的第二子集經配置為傳送器天線陣列,或二者。 In a specific embodiment, the present invention relates to a device including a plurality of semiconductor devices, wherein each semiconductor device is one of the foregoing, and wherein a first subset of the semiconductor devices is configured as a receiver antenna Array, the second subset of the semiconductor devices is configured as a transmitter antenna array, or both.
在一具體實施例中,本發明係有關於一種方法,其包括:形成包含第一表面及第二表面的半導體層;形成包括第一表面及第二表面的聚合物層,其中,該聚合物層之該第一表面靠近該半導體層之該第二表面; 形成包括第一表面及第二表面的模具,其中,該模具之該第一表面靠近該聚合物層之該第二表面;形成靠近該半導體層之該第一表面設置的複數個節點;形成設置於該模具之該第二表面上的天線;形成提供在至少一第一節點與該天線之間之電性通訊的第一傳導元件;形成設置於該聚合物層中或於該聚合物層之該第二表面上的接地元件;以及形成提供在至少一第二節點與該接地元件之間之電性通訊的第二傳導元件。 In a specific embodiment, the present invention relates to a method including: forming a semiconductor layer including a first surface and a second surface; forming a polymer layer including the first surface and the second surface, wherein the polymer The first surface of the layer is close to the second surface of the semiconductor layer; Forming a mold including a first surface and a second surface, wherein the first surface of the mold is close to the second surface of the polymer layer; forming a plurality of nodes disposed close to the first surface of the semiconductor layer; forming a setting An antenna on the second surface of the mold; forming a first conductive element that provides electrical communication between at least one first node and the antenna; forming a first conductive element disposed in the polymer layer or on the polymer layer A ground element on the second surface; and a second conductive element that provides electrical communication between at least one second node and the ground element.
然而不受限於理論,本發明的半導體裝置及設備在約28GHz的工作頻率可具有約15-30%的頻寬。 However, without being limited to theory, the semiconductor device and equipment of the present invention may have a bandwidth of about 15-30% at an operating frequency of about 28 GHz.
100:系統、通訊裝置 100: System, communication device
110:毫米波裝置、通訊裝置 110: Millimeter wave device, communication device
120:通訊前端單元、通訊單元 120: Communication front-end unit, communication unit
130:天線單元 130: antenna unit
140:控制器單元 140: Controller unit
150:訊號處理單元 150: signal processing unit
170:資料庫 170: database
180:馬達控制器 180: motor controller
210:記憶體單元 210: memory unit
212:RAM 212: RAM
214:非揮發性記憶體 214: Non-volatile memory
220:邏輯單元 220: Logic Unit
230:處理器單元 230: processor unit
310:訊號產生單元 310: signal generating unit
320:傳送器單元、傳送單元 320: conveyor unit, conveyor unit
330:接收器單元 330: receiver unit
340:訊號處理單元 340: signal processing unit
410a-410n:傳送器 410a-410n: teleporter
510a-510n:接收器 510a-510n: receiver
610:類比濾波器單元 610: analog filter unit
620:A/D轉換器 620: A/D converter
630:DSP單元 630: DSP unit
640:記憶體 640: memory
710:傳送天線、傳送器天線 710: Transmission antenna, transmitter antenna
715:傳送天線部分、傳送器天線部分 715: Transmission antenna part, transmitter antenna part
720:接收天線、接收器天線 720: receiving antenna, receiver antenna
725:接收天線部分、接收器天線部分 725: receiving antenna part, receiver antenna part
730:第一設備 730: first device
731:第二設備 731: second device
735:半導體裝置 735: semiconductor device
736:半導體裝置 736: Semiconductor Device
910:半導體層、晶片 910: semiconductor layer, wafer
912:第一表面 912: first surface
914:第二表面 914: second surface
920:聚合物層 920: polymer layer
921:第一聚合物次層 921: The first polymer sublayer
922:第一表面 922: first surface
923:第二聚合物次層 923: second polymer sublayer
924:第二表面 924: second surface
925:第二聚合物層 925: second polymer layer
930:模具 930: Mould
932:第一表面 932: first surface
934:第二表面 934: second surface
942:節點、第二節點 942: node, second node
944:節點、第一節點 944: node, first node
946:節點、第三節點 946: node, third node
950:天線 950: Antenna
961:第一傳導次層 961: first conduction sublayer
962:第一傳導元件 962: first conductive element
963:第二傳導次層 963: second conduction sublayer
964:第二傳導元件 964: second conductive element
965:通孔條 965: Through Hole Strip
966:第三傳導元件 966: third conductive element
970:接地元件 970: Grounding element
980:射頻(RF)濾波器 980: Radio Frequency (RF) Filter
990:氧化物層 990: oxide layer
995:第二氧化物層 995: second oxide layer
1026:犧牲載體層 1026: Sacrificial carrier layer
1111:溝槽 1111: groove
1427:位置 1427: location
1567:位置 1567: location
1867:通孔開孔 1867: Through hole opening
2162:第一傳導元件 2162: The first conductive element
2250:天線 2250: Antenna
2270:接地元件、第二接地元件 2270: Grounding element, second grounding element
2275:通孔籠 2275: Through hole cage
2277:環狀物 2277: Ring
2363:第二傳導次層 2363: second conduction sublayer
2667:通孔開孔 2667: Through hole opening
2900:方法 2900: method
2910-2991:步驟 2910-2991: steps
3000:系統 3000: System
3010:半導體裝置加工系統、加工系統 3010: Semiconductor device processing system, processing system
3015:積體電路/裝置、物件 3015: Integrated circuit/device, object
3016:度量衡工具 3016: Weights and Measures Tools
3020:加工控制器 3020: Processing Controller
3040:積體電路設計單元 3040: Integrated Circuit Design Unit
3050:搬運機構 3050: handling mechanism
本發明可藉由參考以下結合附圖的說明了解,其中類似的元件以相同的元件符號表示,且其中: The present invention can be understood by referring to the following description in conjunction with the accompanying drawings, in which similar components are represented by the same component symbols, and among them:
第1圖根據本文數個具體實施例圖示代表通訊系統的非寫實方塊圖; Figure 1 illustrates a non-realistic block diagram representing a communication system according to several specific embodiments in this document;
第2圖根據本文數個具體實施例圖示描繪控制器單元140的非寫實方塊圖;
Figure 2 illustrates a non-realistic block diagram of the
第3圖根據本文數個具體實施例圖示描繪第1圖之通訊前端單元的非寫實方塊圖; Figure 3 illustrates a non-realistic block diagram of the communication front-end unit of Figure 1 according to several specific embodiments in this document;
第4圖根據本文數個具體實施例圖示第3圖之傳送器單元的非寫實方塊圖; Fig. 4 illustrates a non-realistic block diagram of the transmitter unit of Fig. 3 according to several specific embodiments herein;
第5圖根據本文數個具體實施例圖示第3圖之接收器單元的非寫實方塊圖; Fig. 5 illustrates a non-realistic block diagram of the receiver unit of Fig. 3 according to several specific embodiments herein;
第6圖根據本文數個具體實施例圖示描繪第1圖之訊號處理單元的非寫實方塊圖; Fig. 6 illustrates a non-realistic block diagram of the signal processing unit of Fig. 1 according to several specific embodiments herein;
第7圖根據本文數個具體實施例描繪第1圖之天線單元的非寫實方塊圖; Fig. 7 depicts a non-realistic block diagram of the antenna unit of Fig. 1 according to several specific embodiments herein;
第8圖根據本文之一具體實施例圖示包含各自包括天線之複數個半導體裝置的第一設備的非寫實遠視平面圖; FIG. 8 illustrates a non-realistic far view plan view of a first device including a plurality of semiconductor devices each including an antenna according to a specific embodiment of this document;
第9圖根據本文數個具體實施例圖示描繪於第8圖的半導體裝置的非寫實X切面剖視圖; Fig. 9 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device depicted in Fig. 8 according to several specific embodiments herein;
第10圖根據第一具體實施例圖示第8圖至第9圖之半導體裝置在第一製造階段之後的非寫實X切面剖視圖; FIG. 10 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIGS. 8 to 9 after the first manufacturing stage according to the first specific embodiment;
第11圖根據第一具體實施例圖示第8圖至第10圖之半導體裝置在第二製造階段之後的非寫實X切面剖視圖; FIG. 11 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 10 after the second manufacturing stage according to the first specific embodiment;
第12圖根據第一具體實施例圖示第8圖至第11圖之半導體裝置在第三製造階段之後的非寫實X切面剖視圖; FIG. 12 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 11 after the third manufacturing stage according to the first specific embodiment;
第13圖根據第一具體實施例圖示第8圖至第12圖之半導體裝置在第四製造階段之後的的非寫實X切面剖視圖; FIG. 13 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 12 after the fourth manufacturing stage according to the first specific embodiment;
第14圖根據第一具體實施例圖示第8圖至第13圖之半導體裝置在第五製造階段之後的非寫實X切面剖視圖; FIG. 14 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 13 after the fifth manufacturing stage according to the first specific embodiment;
第15圖根據第一具體實施例圖示第8圖至第14圖之半導體裝置在第六製造階段之後的非寫實X切面剖視圖; FIG. 15 illustrates a non-realistic X-section cross-sectional view of the semiconductor device in FIG. 8 to FIG. 14 after the sixth manufacturing stage according to the first specific embodiment;
第16圖根據第一具體實施例圖示第8圖至第15圖之半導體裝置在第七製造階段之後的非寫實X切面剖視圖; FIG. 16 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 15 after the seventh manufacturing stage according to the first specific embodiment;
第17圖根據第一具體實施例圖示第8圖至第16圖之半導體裝置在第八製造階段之後的非寫實X切面剖視圖; FIG. 17 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 16 after the eighth manufacturing stage according to the first specific embodiment;
第18圖根據第一具體實施例圖示第8圖至第17圖之半導體裝置在第九製造階段之後的非寫實X切面剖視圖; FIG. 18 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 17 after the ninth manufacturing stage according to the first embodiment;
第19圖根據第一具體實施例圖示第8圖至第18圖之半導體裝置在第十製造階段之後的非寫實X切面剖視圖; FIG. 19 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 18 after the tenth manufacturing stage according to the first specific embodiment;
第20圖根據第一具體實施例圖示第8圖至第19圖之半導體裝置在第十一製造階段之後的非寫實X切面剖視圖; FIG. 20 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 8 to FIG. 19 after the eleventh manufacturing stage according to the first embodiment;
第21圖根據本文之第二具體實施例圖示包括各自含有天線之複數個半導體裝置的第二設備的非寫實遠視平面圖; FIG. 21 illustrates a non-realistic far view plan view of a second device including a plurality of semiconductor devices each containing an antenna according to the second specific embodiment of this document;
第22圖根據本文數個具體實施例圖示描繪於第21圖之半導體裝置的非寫實X切面剖視圖; FIG. 22 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device depicted in FIG. 21 according to several specific embodiments herein;
第23圖根據第二具體實施例圖示第21圖至第22圖之半導體裝置在第一製造階段之後的非寫實X切面剖視圖; FIG. 23 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 21 to FIG. 22 after the first manufacturing stage according to the second embodiment;
第24圖根據第二具體實施例圖示第21圖至第23圖之半導體裝置在第二製造階段之後的非寫實X切面剖視圖; FIG. 24 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 21 to FIG. 23 after the second manufacturing stage according to the second embodiment;
第25圖根據第二具體實施例圖示第21圖至第24圖之半導體裝置在第三製造階段之後的非寫實X切面剖視圖; FIG. 25 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 21 to FIG. 24 after the third manufacturing stage according to the second embodiment;
第26圖根據第二具體實施例圖示第21圖至第25圖之半導體裝置在第四製造階段之後的非寫實X切面剖視圖; FIG. 26 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 21 to FIG. 25 after the fourth manufacturing stage according to the second embodiment;
第27圖根據第二具體實施例圖示第21圖至第26圖之半導體裝置在第五製造階段之後的非寫實X切面剖視圖; FIG. 27 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 21 to FIG. 26 after the fifth manufacturing stage according to the second embodiment;
第28圖根據第二具體實施例圖示第21圖至第27圖之半導體裝置在第六製造階段之後的非寫實X切面剖視圖; FIG. 28 illustrates a non-realistic X-sectional cross-sectional view of the semiconductor device in FIG. 21 to FIG. 27 after the sixth manufacturing stage according to the second embodiment;
第29圖根據本文數個具體實施例提供描繪用於製造半導體裝置之方法的流程圖;以及 Figure 29 provides a flowchart depicting a method for manufacturing a semiconductor device according to several specific embodiments herein; and
第30圖根據本文數個具體實施例圖示用於製造半導體裝置之系統的非寫實繪圖。 FIG. 30 illustrates a non-realistic drawing of a system for manufacturing a semiconductor device according to several specific embodiments herein.
儘管本文揭露的專利標的容易做成各種修改及替代形式,本文仍以附圖為例圖示本發明的幾個特定具體實施例且詳述於本文。不過,應瞭解本文所描述的特定具體實施例並非旨在把本發明限定於本文所揭示的特定形式,反而是,為了涵蓋落在如隨附申請專利範圍所界定之本發明之精神及範疇內的所有修改、等效及替代性陳述。 Although the patented subject matter disclosed herein is easy to make various modifications and alternative forms, this article still uses the accompanying drawings as an example to illustrate several specific embodiments of the present invention and are described in detail herein. However, it should be understood that the specific embodiments described herein are not intended to limit the present invention to the specific forms disclosed herein, but to cover the spirit and scope of the present invention as defined by the scope of the appended application. All modifications, equivalents and alternative statements of.
以下描述本發明的各種例示性具體實施例。為了清楚說明,本發明說明書並未描述實際具體實作的所有特徵。當然,應瞭解,在開發任一此類的實際具體實施例時,必需做許多與具體實作有關的決策以達成開發人員的特定目標,例如遵循與系統相關及商務有關的限制,這些都會隨著每一個具體實作而有所不同。此外,應瞭解,此類開發工作可能複雜又花時間,但是對於本技術領域一般技術人員來說係為在閱讀本發明後即可承擔的例行工作。 Various exemplary specific embodiments of the present invention are described below. For clarity, the specification of the present invention does not describe all the features of the actual implementation. Of course, it should be understood that when developing any such actual specific embodiment, many decisions related to the specific implementation must be made to achieve the specific goals of the developer, such as complying with system-related and business-related restrictions. It is different for each specific implementation. In addition, it should be understood that such development work may be complicated and time-consuming, but for those skilled in the art, it is a routine work that can be undertaken after reading the present invention.
本發明標的此時將參照附圖來描述。附圖中示意圖示的各種結構、系統及裝置係僅供解釋以及避免被熟諳此藝者所習知的細節混淆本 發明。儘管如此,附圖仍被納入以描述及解釋本發明的例示性實施例。使用於本文的字彙及片語應使用與相關技藝技術人員所熟悉之意思一致的方式理解及解釋。本文沒有特別定義的術語或片語(亦即,與熟諳此藝者所理解之普通慣用意思不同的定義)旨在用術語或片語的一致用法來說明。如果術語或片語旨在具有特定的意思時(亦即,不同於熟諳此藝者所理解的意思),則會清楚地陳述在本發明說明書中以直接明白的方式為該術語或片語提供特定定義。 The subject of the present invention will now be described with reference to the accompanying drawings. The various structures, systems and devices schematically shown in the drawings are for explanation purposes only and to avoid confusion with the details that are familiar to those who are familiar with the art. invention. Nonetheless, the drawings are included to describe and explain exemplary embodiments of the present invention. The vocabulary and phrases used in this article should be understood and explained in a manner consistent with the meaning familiar to the relevant art and technical personnel. Terms or phrases not specifically defined herein (that is, definitions that are different from the common and usual meaning understood by those familiar with the art) are intended to be explained by consistent usage of the terms or phrases. If a term or phrase is intended to have a specific meaning (that is, different from the meaning understood by those familiar with the art), it will be clearly stated that the term or phrase is provided in a straightforward manner in the specification of the present invention Specific definition.
本文的具體實施例可用於在封裝中有改良頻寬的射頻(RF)及毫米波整合天線二者。 The specific embodiments herein can be used for both radio frequency (RF) and millimeter wave integrated antennas with improved bandwidth in the package.
為了便於圖解說明,本文的具體實施例係在通訊裝置的背景下描繪,不過,熟諳此藝者應瞭解,揭露於本文的概念可實現於其他類型的裝置,例如高速通訊裝置、網路裝置等等。此時請看第1圖,其係根據本文數個具體實施例圖示通訊系統的非寫實方塊圖。 For ease of illustration, the specific embodiments of this document are described in the context of a communication device. However, those familiar with the art should understand that the concepts disclosed in this document can be implemented in other types of devices, such as high-speed communication devices, network devices, etc. Wait. At this time, please refer to Figure 1, which is a non-realistic block diagram of a communication system according to several specific embodiments in this document.
系統100可包括毫米波裝置110、資料庫170及馬達控制器180。毫米波裝置110可為雷達裝置、無線通訊裝置、資料網路裝置、視頻裝置或其類似者。為了圖解說明和清楚及便於描述,毫米波裝置110是在通訊應用的背景下描述。因此,毫米波裝置110在以下可能常被稱為通訊裝置110。不過,受益於本發明內容的熟諳此藝者應瞭解,描述於本文的概念可應用於各種類型的毫米波應用,包括使用雷達訊號的車輛應用、無線網路應用、資料網路應用、影音應用等等。
The
通訊裝置110能夠傳送通訊訊號及/或接收通訊訊號。
The
通訊裝置110可包括通訊前端單元120、天線單元130、控制器單元140及訊號處理單元150。通訊前端單元120可包含複數個組件、電路、及/或模組,且能夠送出、接收及/或處理通訊訊號。在一具體實施例中,通訊裝置110可包含在單一積體電路(IC)晶片中。在一些具體實施例中,通訊裝置110可形成於位在單一IC晶片上的複數個積體電路上。在其他具體實施例中,通訊裝置110可形成於包裹在IC晶片中的單一積體電路上。在一些實例中,通訊前端單元120可簡稱為通訊單元120。
The
通訊前端單元120能夠提供通訊訊號。在一具體實施例中,由通訊裝置110處理之通訊訊號的頻率範圍可在約10GHz至約90GHz之間。通訊前端單元120能夠產生在預定頻率範圍內的通訊訊號。裝置110可處理用於各種通訊應用的網路通訊,例如封包資料網路通訊、無線(例如,蜂巢式通訊、IEEE 802.11ad WiGig技術等等)、資料通訊等等。揭露於本文的在通訊應用背景下的概念也可用於其他類型的應用,例如雷達、無線通訊、高解析度視頻等等。
The communication front-
繼續參考第1圖,天線單元130也可包括傳送天線及/或接收器天線。此外,傳送及接收器天線各自可包括形成天線陣列的子部分。傳送天線用於傳送通訊訊號,同時接收器天線用於接收通訊訊號。天線單元130的更詳細描述係提供於第7圖及以下隨附說明中。
Continuing to refer to Figure 1, the
繼續參考第1圖,通訊裝置110也可包含訊號處理單元150。訊號處理單元150能夠執行被通訊裝置110傳送及/或接收之訊號的各種類比及/或數位處理。例如,可在傳送前放大被通訊裝置傳送的通訊訊號。此外,被通訊裝置110接收的訊號可被傳送通過一或多個類比濾波器級
(analog filter stage)。然後,可用訊號處理單元150中的一或多個類比數位轉換器(DAC)將反射訊號轉換為數位訊號。可對已數位化的訊號執行數位訊號處理(DSP)。訊號處理單元150的更詳細描述係提供於第6圖及以下隨附說明中。
Continuing to refer to FIG. 1, the
繼續參考第1圖,通訊裝置100也可包括控制器單元140。控制器單元140可執行通訊裝置110的各種控制運作。這些功能包括產生通訊訊號、傳送通訊訊號、接收通訊訊號及/或處理反射訊號。
Continuing to refer to FIG. 1, the
此時請看第2圖,其根據本文數個具體實施例提供描述控制器單元140的非寫實方塊圖。控制器單元140可包括能夠控制通訊裝置110之各種功能的處理器單元230。處理器單元230可包含微處理器,微控制器,現場可程式閘陣列(FPGA),特殊應用積體電路(ASIC),及/或類似者。
At this time, please refer to FIG. 2, which provides a non-realistic block diagram describing the
控制器單元140也可包括邏輯單元220。邏輯單元220可包括能夠執行各種邏輯運作、接收資料、執行與輸入資料(data_in)及輸出資料(data_out)有關之介面功能的電路。訊號data_in可代表從處理及分析反射訊號導出的資料。訊號data_out可代表由於通訊訊號傳送及接收訊號而產生的用於執行一或多個任務的資料。例如,訊號data_out可用來執行基於通訊訊號傳送及/或接收的動作。
The
控制器單元140也可包含記憶體單元210。記憶體單元210可包括非揮發性記憶體214與RAM 212。非揮發性記憶體214可包括FLASH記憶體及/或可程式化唯讀(PROM)裝置。記憶體單元210能夠儲存用於控制通訊裝置110之操作的操作參數。此外,記憶體單元210可儲存上述的狀態資料及反應資料。記憶體單元210也可儲存可用來程式化通訊
裝置110中之任何FPGA裝置的資料。因此,記憶體單元210可細分成程式資料記憶體、狀態資料記憶體等等。此種細分可用邏輯或實體之方式執行。
The
此時請看第3圖,其根據本文數個具體實施例圖示通訊前端單元120的非寫實方塊圖。通訊前端單元120可包含訊號產生單元310、傳送器單元320、訊號處理單元340及接收器單元330。訊號產生單元310能夠以預定頻率產生通訊訊號。例如,可產生在約70GHz至約85GHz之範圍內的訊號。訊號產生單元310可包括真差分倍頻器(FD)。FD可以推-推式組態(push-push configuration)形成。訊號產生單元310能夠提供用以傳送的通訊訊號。以下提供訊號產生單元310的更詳細說明。
At this time, please refer to FIG. 3, which illustrates a non-realistic block diagram of the communication front-
繼續參考第3圖,用於處理及傳送的訊號由訊號產生單元310提供給傳送器單元320。傳送器單元320可包括複數個濾波器、訊號調節電路、緩衝器、放大器等等,以用來處理來自訊號產生單元310的訊號。傳送單元320提供將會傳送至天線單元130的通訊訊號。
Continuing to refer to FIG. 3, the signal for processing and transmission is provided by the
第4圖根據本文數個具體實施例圖示傳送器單元320的非寫實方塊圖。請同時參考第3圖及第4圖,傳送器單元320可包含複數個相似的傳送器,亦即,第一傳送器410a、第二傳送器420b至第N傳送器410n(合稱“410”)。在一具體實施例中,第一至第N傳送器410可各自處理來自訊號產生單元310的單一訊號且提供輸出傳送訊號給一或多個天線。在另一具體實施例中,訊號產生單元310可提供複數個訊號給第一至第N傳送器410。例如,訊號產生單元310可提供訊號傳送訊號給各個傳送器
410,或替換地,提供第一傳送訊號給第一組傳送器410,以及提供第二傳送訊號給第二組傳送器410。
FIG. 4 illustrates a non-realistic block diagram of the
繼續參考第3圖,接收訊號係提供給接收器單元330。接收器單元330能夠從訊號處理單元150接收已予處理的接收訊號。接收器單元330能夠執行類比至數位(A/D)轉換、訊號緩衝、DSP等等。在一些具體實施例中,訊號處理單元150可執行A/D轉換及DSP;不過,在其他具體實施例中,這些任務可由接收器單元330執行。接收器單元330能夠導向控制器單元140。
Continuing to refer to FIG. 3, the receiving signal is provided to the
第5圖根據本文數個具體實施例圖示接收器單元330的非寫實方塊圖。請同時參考第3圖及第5圖,接收器單元330可包括複數個相似的接收器,亦即,第一接收器510a、第二接收器520b至第N接收器510n(合稱“510”)。在一具體實施例中,第一至第N接收器510可各自處理來自訊號產生單元310的單一訊號且提供訊號給控制器單元140。在另一具體實施例中,可提供複數個訊號給第一至第N接收器510。例如,訊號處理單元150可提供訊號接收訊號給各個接收器510,或替換地,提供第一接收器訊號給第一組接收器510以及提供第二接收器訊號給第二組接收器510。
FIG. 5 illustrates a non-realistic block diagram of the
此時請看第6圖,其根據本文數個具體實施例圖示訊號處理單元150的非寫實方塊圖。訊號處理單元150可包括類比濾波器單元610、A/D轉換器620、DSP單元630、及記憶體640。類比濾波器單元610能夠執行由訊號處理單元150接收之毫米波訊號向下轉換(down-convert)的
類比訊號的濾波及放大。在執行放大從毫米波訊號向下轉換的類比訊號之前,可用類比濾波器單元610執行雜訊濾波。
At this time, please refer to FIG. 6, which illustrates a non-realistic block diagram of the
A/D轉換器620能夠把經濾波及/或經放大的類比訊號轉換成數位訊號。A/D轉換器620能夠執行預定或不同準確度的轉換。例如,A/D轉換器620可有12-bit、24-bit、36-bit、48-bit、64-bit、96-bit、128-bit、256-bit、512-bit、1024-bit的準確度或更大的準確度。經轉換的數位毫米波訊號係提供給DSP單元630。
The A/
DSP單元630能夠執行數位毫米波訊號的各種DSP運作。例如,可用DSP單元630執行從毫米波頻率向下轉換之數位化類比訊號的數位濾波。例如,在例如70GHz至約85GHz之預定頻率範圍外的訊號分量可過濾成有較低的振幅。在其他情況下,可對毫米波訊號執行例如快速傅立葉轉換(FFT)的數學方法。來自DSP單元630的經處理之數位輸出可送到控制器單元140進行分析。在其他情況下,可緩衝或儲存此數位輸出於記憶體640中。在一些實例中,記憶體640可為先進先出(FIFO)記憶體。在其他實例中,可儲存來自DSP單元630的經處理之數位輸出於控制器單元140的記憶體單元210中。
The
此時請看第7圖,其根據本文數個具體實施例圖示第1圖之天線單元的非寫實方塊圖。可由傳送器單元320(第3圖)提供將會送出的毫米波訊號(例如,雷達訊號、網路資料訊號、無線通訊訊號等等)給傳送天線710。在一具體實施例中,傳送天線710可包含複數個傳送天線部分715。傳送天線部分715可排列成預定圖案,例如,第7圖所例示的陣列矩陣。
At this time, please refer to Fig. 7, which illustrates a non-realistic block diagram of the antenna unit of Fig. 1 according to several specific embodiments in this document. The transmitter unit 320 (FIG. 3) can provide millimeter wave signals (for example, radar signals, network data signals, wireless communication signals, etc.) to be sent to the transmitting
將會被接收的毫米波訊號(例如,雷達訊號、網路資料訊號、無線通訊訊號等等)可由接收天線720擷取。接收天線720提供收到的毫米波訊號給接收器單元330(第3圖)。在一具體實施例中,接收天線720可包括複數個接收天線部分725。接收天線部分725也排列成預定圖案,例如,第7圖所例示的陣列矩陣。
The millimeter wave signal to be received (for example, radar signal, network data signal, wireless communication signal, etc.) can be captured by the receiving
第8圖根據本文之一具體實施例圖示第一設備730的非寫實遠視平面圖,其包括各自含有天線950的複數個半導體裝置735。半導體裝置735之各者可對應至圖示於第7圖之方塊圖的傳送器天線部分715或接收器天線部分725。第一設備730可對應至圖示於第7圖之方塊圖的傳送器天線710、接收器天線720或彼等之組合。
FIG. 8 illustrates a non-realistic far view plan view of the
第8圖中的平面圖圖示以下將更詳細地描述的天線950與模具930。天線950在平面圖中的形狀並非關鍵性的,且可根據本技術領域一般技術人員之例行工作需要而與第8圖的E字形狀不同。為了圖示射頻(RF)濾波器980設置在模具930中的位置,平面圖為遠視圖,這在下文會更詳細地描述。
The plan view in FIG. 8 illustrates the
可將複數個半導體裝置735組配為可接收特定頻率的射頻(RF)訊號,例如通訊訊號。由於此特定頻率,想要接收的RF訊號也會有特定波長λ。因此,在一具體實施例中,半導體裝置735在第一設備730中可排成致使毗鄰半導體裝置735的天線950分離半個特定波長λ/2的陣列。雖不受限於理論,此分離可改善第一設備730之訊號收集或傳播的效率、敏感度、及/或訊號雜訊比。
A plurality of
第8圖也圖示後續圖式會圖示的第一設備730之半導體裝置735的X切面線。X切面線係對分模具930、天線950及RF濾波器980。
FIG. 8 also shows the X-section line of the
請看第9圖,其根據本文數個具體實施例圖示描繪第8圖之半導體裝置735的非寫實X切面剖面圖。半導體裝置735包括具有第一表面912及第二表面914的半導體層910。半導體層910可包括任何半導體材料,例如矽或矽-鍺,等等。當半導體層910包含矽-鍺時,可根據受益於本發明內容的本技術領域一般技術人員之例行工作需要選擇鍺的莫耳%。
Please refer to FIG. 9, which illustrates a non-realistic X-section cross-sectional view of the
半導體裝置735也包括具有第一表面922及第二表面924的聚合物層920。聚合物層920的第一表面922係靠近半導體層910的第二表面914。聚合物層920可包含本技術領域所習知的任何聚合物材料。在一具體實施例中,聚合物層920包括聚亞醯胺。
The
半導體裝置735進一步包括上述的模具930。模具930包括第一表面932及第二表面934。模具930的第一表面932靠近聚合物層920的第二表面924。模具930可包含本技術領域所習知的任何模具材料。在一具體實施例中,模具930包括Ajinomoto MI-11(日本東京Ajinomoto股份有限公司)。
The
受益於本發明內容的本技術領域一般技術人員可改變模具930的厚度。在一具體實施例中,模具930具有約500微米(μm)至約1000微米的厚度。在又一具體實施例中,模具930有約750微米至約800微米的厚度,例如約775微米。
Those of ordinary skill in the art who benefit from the content of the present invention can change the thickness of the
半導體裝置735另外包括靠近半導體層910之第一表面912設置的複數個節點942、944、946。各節點942、944或946包含導電材料,例如金屬,例如銅或鋁,或共晶焊錫合金等等。
The
雖然第9圖圖示3個節點942、944、946,然而受益於本發明內容的本技術領域一般技術人員根據例行工作之需要可改變節點的個數。
Although Fig. 9 illustrates three
半導體裝置735也包括設置在模具930之第二表面934上的天線950。天線950包括導電材料,例如金屬,例如銅或鋁,等等。
The
第一傳導元件962被包括在半導體裝置735中以提供在至少一第一節點944與天線950之間的電性通訊。被天線950接收的RF訊號可通過第一節點944提供給包含半導體裝置735之系統的其他組件,或是由包括半導體裝置735之系統的其他組件產生之要由天線950傳送的RF訊號可通過第一節點944提供給天線950。儘管為了便於理解而以沿著整個高度有均一寬度的方式圖示,然而,如以下所述及本技術領域一般技術人員會明白的,第一傳導元件962可具有較寬及較窄的部分、不同材料的部分等等。
The first
半導體裝置735也包括設置於聚合物層920中或於聚合物層之第二表面上的接地元件970。接地元件970可包含任何導電材料,例如金屬,例如銅或鋁等等。第二傳導元件964提供在至少一第二節點942與接地元件970之間的電性通訊。雖不受限於理論,接地元件970可減少通過第一節點944被天線950接收且提供給包括半導體裝置735之系統之其他組件或將由天線950傳送且由系統之其他組件產生之RF訊號的干涉。
The
在例如圖示於第9圖的具體實施例中,半導體裝置735可進一步包括設置於模具930中的射頻(RF)濾波器980。替代地(未圖示),RF濾波器980可設置在聚合物層920的第二表面924上。在晶粒對晶圓(D2W)製程中整合RF濾波器980可改善包含半導體裝置735之裝置的效能。再者,如圖示,半導體裝置735可進一步包括:第三傳導元件966,其提供在至少一第三節點946與RF濾波器980之間的電性通訊。儘管第9圖為了方便及簡潔只圖示在節點與RF濾波器980之間的一個傳導元件,亦即,第三傳導元件966提供在至少一第三節點946與RF濾波器980之間的電性通訊,然而在其他具體實施例中,半導體裝置735可包含兩個、三個、四個或其他數量的節點以及從節點到RF濾波器980的對應數量的傳導元件。
In the specific embodiment shown in FIG. 9, for example, the
半導體裝置735也可包括本技術領域一般技術人員所習知可使用於半導體裝置的各種層件。例如,半導體裝置735可包含靠近複數個節點942、944及946設置的第二聚合物層925。第二聚合物層925可包括適合用作印刷電路板之基材的材料。第二聚合物層925可包括,但是非必要,與聚合物層920相同的材料。
The
在另一個實施例中,半導體裝置735可包含設置在半導體層910與聚合物層920之間的氧化物層990。氧化物層990可包括氧化矽且可用任何習知技術形成。替代地或額外地,半導體裝置735可包括設置在第二聚合物層925與半導體層910之間的第二氧化物層995。
In another embodiment, the
為了簡潔起見,第9圖可能省略本技術領域一般技術人員常規地會納入半導體裝置的一或多個結構。 For the sake of brevity, FIG. 9 may omit one or more structures conventionally incorporated into semiconductor devices by those skilled in the art.
第10圖的非寫實X切面剖示圖根據第一具體實施例圖示在第一製造階段之後的半導體裝置735。在第一製造階段中,形成半導體層910,可使用習知技術黏合使第二氧化物層995靠近半導體層910的第一表面912、第二聚合物層925靠盡第二氧化物層995、以及犧牲載體層1026靠近第二聚合物層925。
The non-realistic X-sectional cross-sectional view of FIG. 10 illustrates the
第11圖的非寫實X切面剖示圖根據第一具體實施例圖示在第二製造階段之後的半導體裝置735。在第二製造階段中,溝槽1111從半導體層910之第二表面914蝕刻到第一表面912,從而暴露第二氧化物層995。然後,沉積靠近半導體層910之第二表面914且共形襯裡溝槽1111的氧化物層990。受益於本發明內容的本技術領域一般技術人員按例行工作可使用習知技術執行溝槽1111的蝕刻以及沉積氧化物層990。
The non-realistic X-sectional cross-sectional view of FIG. 11 illustrates the
第12圖的非寫實X切面剖示圖根據第一具體實施例圖示在第三製造階段之後的半導體裝置735。沉積第一聚合物次層921於氧化物層990上方,包括於溝槽1111中。理想的是,第一聚合物次層921在溝槽1111底部被蝕刻以顯露可放置第一傳導次層961(圖示於第13圖)的晶粒金屬。沉積第一聚合物次層921對於受益於本發明內容的本技術領域一般技術人員來說為例行公事,且不需詳述。
The non-realistic X-sectional cross-sectional view of FIG. 12 illustrates the
第13圖的非寫實X切面剖示圖根據第一具體實施例圖示在第四製造階段之後的半導體裝置735。在第四製造階段中,第一傳導次層961被電鍍於第一聚合物次層921上方。在電鍍第一傳導次層961之前可放置擴散阻擋層(未圖示)。在電鍍第一傳導次層961之前,可先鋪設遮罩(未圖示)至第一聚合物次層921上覆半導體層910的部分,再執行電鍍。
可用任何標準濺鍍製程來沉積薄種子層以供電鍍第一傳導次層961於第一聚合物次層921上。然後可移除遮罩,以產生圖示於第13圖的半導體裝置735。
The non-realistic X-sectional cross-sectional view of FIG. 13 illustrates the
第14圖的非寫實X切面剖示圖根據第一具體實施例圖示在第五製造階段之後的半導體裝置735。在此製造階段中,第二聚合物次層923被沉積於第一傳導次層961上方。在用遮罩防止電鍍第一傳導次層961的位置中,例如,在位置1427處,第二聚合物次層923可接觸第一聚合物次層921,從而提供第一傳導次層961之數個部分的互相電氣隔離。可用第一傳導次層961之此等部分的電氣隔離來界定接地元件970。
The non-realistic X-sectional cross-sectional view of FIG. 14 illustrates the
可用習知技術執行第二聚合物次層923的沉積。並且,在沉積第二聚合物次層923之前,可先鋪設遮罩(未圖示)至第一傳導次層961的數個部分,再執行沉積且移除遮罩,以產生圖示於第14圖的半導體裝置735。
The deposition of the
第15圖的非寫實X切面剖示圖根據第一具體實施例圖示在第六製造階段之後的半導體裝置735。在此製造階段中,第二傳導次層963被電鍍於第二聚合物次層923上方。在用遮罩防止沉積第二聚合物次層923的位置中,例如,位置1567處,第二傳導次層963可接觸第一傳導次層961。
The non-realistic X-sectional cross-sectional view of FIG. 15 illustrates the
第16圖的非寫實X切面剖示圖根據第一具體實施例圖示在第七製造階段之後的半導體裝置735。在此製造階段中,可形成各自與第二傳導次層963接觸且與第一傳導次層961之部分電性通訊的通孔條(via
bar)965及RF濾波器980。通孔條965及RF濾波器980的形成可使用習知技術來執行且不需進一步描述。
The non-realistic X-sectional cross-sectional view of FIG. 16 illustrates the
第17圖的非寫實X切面剖示圖根據第一具體實施例圖示在第八製造階段之後的半導體裝置735。在此製造階段中,模具930被形成於通孔條965及RF濾波器980上方。用於形成模具930的技術為本技術領域一般技術人員所習知且不需詳述。
The non-realistic X-sectional cross-sectional view of FIG. 17 illustrates the
第18圖的非寫實X切面剖示圖根據第一具體實施例圖示在第九製造階段之後的半導體裝置735。在此製造階段中,通孔開孔(via opening)1867係形成於模具930中。在一具體實施例中,通孔開孔1867可藉由在模具930上執行雷射開孔技術形成。通孔開孔1867之形成使通孔條965暴露於後續加工步驟。
The non-realistic X-sectional cross-sectional view of FIG. 18 illustrates the
第19圖的非寫實X切面剖示圖根據第一具體實施例圖示在第十製造階段之後的半導體裝置735。在第十製造階段中,係藉由沉積導電材料於模具930上,包括沉積於第18圖先前圖示的通孔開孔1867上方及填滿通孔開孔1867,以形成天線950,。天線950的沉積可能需要擴散阻擋層。任何標準濺鍍製程可用來沉積用於天線950的薄種子層於模具930上。因此,天線950與通孔條965、第二傳導次層963的至少一部分、以及第一傳導次層961的至少一部分電性接觸。通孔條965,第二傳導次層963之至少一部分以及第一傳導次層961的至少一部分一起界定第一傳導元件962。
The non-realistic X-sectional cross-sectional view of FIG. 19 illustrates the
第20圖的非寫實X切面剖示圖根據第一具體實施例圖示在第十一製造階段之後的半導體裝置735。在此製造階段中,犧牲載體層1026
被移除,且執行前側C4或CuP植球(frontside C4 or CuP bumping),以產生設置於第二聚合物層925上的複數個節點942、944及946。
The non-realistic X-sectional cross-sectional view of FIG. 20 illustrates the
然而不受限於理論,半導體裝置735對於28GHz訊號可具有約4.4GHz的頻寬與約8dBi的增益。
However, without being limited to theory, the
第21圖的非寫實遠視平面圖根據本文之第二具體實施例圖示包含各自包括天線2250之複數個半導體裝置736的第二設備731。第21圖有與第8圖相同的許多元件。這些相同元件用與第8圖中首先提及的元件符號標示且依本文所述。大體上,第二設備731與圖示於第9圖的第一設備730實質相似。第二設備731包括與第9圖之半導體裝置735相似的複數個半導體裝置736。
The non-realistic far view plan view of FIG. 21 illustrates a
最新圖示於第21圖的是與第9圖之天線950實質相似的天線2250。
The latest figure shown in FIG. 21 is an
第21圖也圖示環狀物2277。在平面圖中,環狀物2277包圍天線2250,但是藉由模具930的一部分與天線2250分離。環狀物2277的納入可減少各個半導體裝置736的訊號不連續性及/或訊號損失。
Figure 21 also shows the
第21圖也圖示用於擷取第22圖至第28圖之剖示圖的X切線。 Fig. 21 also shows the X tangents used to extract the cross-sectional views of Figs. 22 to 28.
第22圖的非寫實X切面剖示圖根據第二具體實施例圖示描繪於第21圖的半導體裝置。第22圖圖示的許多組件與圖示於第10圖的組件相同或實質相似而且以相同的元件符號表示。 The non-realistic X-sectional cross-sectional view of FIG. 22 illustrates the semiconductor device depicted in FIG. 21 according to the second embodiment. Many of the components shown in FIG. 22 are the same as or substantially similar to the components shown in FIG. 10 and are denoted by the same reference numerals.
第22圖與第10圖之間的許多差異將顯而易見。其一是,第一傳導元件2162設置於在天線2250之下的聚合物層920中。第一傳導元
件2162為提供天線2250與第一節點944(或在另一具體實施例中,晶片910)之電性通訊的饋入層(feeding layer)。由第一傳導元件2162提供的電性通訊不需要實體連接;反而,在此具體實施例中,接地元件2270的狹縫藉由耦合電磁場以使天線共振。
Many differences between Figure 22 and Figure 10 will be apparent. One is that the first
在此具體實施例中,半導體裝置736的接地元件2270設置在聚合物層920的第二表面924上且包含低於天線2250並高於第一傳導元件2162的狹縫。接地元件2270的狹縫允許第一傳導元件2162饋入(feed)天線2250。
In this specific embodiment, the
第22圖也圖示通孔籠(viacage)2275,其係從接地元件2270延伸到模具930的第二表面934且提供電性通訊給環狀物2277。通孔籠2275與環狀物2277在本文中可合稱為“接地屏蔽”。
FIG. 22 also shows a via
第23圖的非寫實X切面剖示圖根據第二具體實施例圖示在第一製造階段之後的半導體裝置736。在此所指的第一製造階段不是裝置的第一製造階段。反而,第二具體實施例的第一製造階段是對於圖示於第14圖的結構執行。在第二具體實施例的第一製造階段中,第二傳導次層2363被沉積於第二聚合物次層923上以產生接地元件2270以及第二傳導次層2363中不會成為半導體裝置736接地路徑之一部分的部分。接地元件2270與第一傳導次層961接觸。第一傳導次層961的另一部分會提供描繪於第22圖的第一傳導元件2162。
The non-realistic X-sectional cross-sectional view of FIG. 23 illustrates the
第24圖的非寫實X切面剖示圖根據第二具體實施例圖示在第二製造階段之後的半導體裝置736。在此製造階段中,RF濾波器980係以上述之方式形成。
The non-realistic X-sectional cross-sectional view of FIG. 24 illustrates the
第25圖的非寫實X切面剖示圖根據第二具體實施例圖示在第三製造階段之後的半導體裝置736。在此製造階段中,模具930係以上述之方式形成。
The non-realistic X-sectional cross-sectional view of FIG. 25 illustrates the
第26圖的非寫實X切面剖示圖根據第二具體實施例圖示在第四製造階段之後的半導體裝置736。在此製造階段中,數個通孔開孔2667係形成在模具930中。在一具體實施例中,通孔開孔2667可藉由在模具930上執行雷射開孔技術形成。形成通孔開孔2667使接地元件2270及第二接地元件2270暴露於後續加工步驟。
The non-realistic X-sectional cross-sectional view of FIG. 26 illustrates the
第27圖的非寫實X切面剖示圖根據第二具體實施例圖示在第五製造階段之後的半導體裝置736。在此製造階段中,天線2250被如以上在說明天線950時所述方式予以電鍍。此時也被電鍍的是第26圖的通孔開孔2667中的通孔籠2275,接著電鍍環狀物2277。環狀物2277可包含鋁。環狀物2277可改善半導體裝置736的指向性(directivity)。
The non-realistic X-sectional cross-sectional view of FIG. 27 illustrates the
第28圖的非寫實X切面剖示圖根據第二具體實施例圖示在第六製造階段之後的半導體裝置736。在第六製造階段中,節點942、944及946被如上述之方式形成。
The non-realistic X-sectional cross-sectional view of FIG. 28 illustrates the
然而不受限於理論,半導體裝置736對於28GHz訊號可具有約8.1GHz的頻寬與約7.5dBi的增益。
However, without being limited to theory, the
第29圖的流程圖根據本文數個具體實施例描繪用於製造半導體裝置的方法2900。具體言之,方法2900包括:形成(在步驟2910處)包括第一表面及第二表面的半導體層。在一具體實施例中,半導體層可從矽-鍺形成(在步驟2910處)。
The flowchart in FIG. 29 depicts a
在一些具體實施例中,方法2900可進一步包含:形成(在步驟2915處)鄰接半導體層之第二表面的氧化物層。
In some embodiments, the
方法2900也包括形成(在步驟2920處)包括第一表面及第二表面的聚合物層,其中,聚合物層之第一表面靠近半導體層之第二表面。在有執行形成(在步驟2915處)氧化物層的具體實施例中,氧化物層設置在半導體層與聚合物層之間。
The
方法2900進一步包含:形成(在步驟2930處)包括第一表面及第二表面的模具,其中,模具的第一表面靠近聚合物層的第二表面。在一具體實施例中,模具可被形成(在步驟2930處)以具有500微米至1000微米的厚度。在又一具體實施例中,模具可被形成(在步驟2930處)以具有750微米至800微米的厚度。在一特定具體實施例中,模具可被形成(在步驟2930處)以具有775微米的厚度。
The
方法2900另外包括:形成(在步驟2940處)靠近半導體層之第一表面設置的複數個節點。方法2900也進一步包含:形成(在步驟2950處)設置在模具之第二表面上的天線。方法2900又另外包括:形成(在步驟2960處)第一傳導元件,其提供在至少一第一節點與天線之間的電性通訊。
The
方法2900也包括形成(在步驟2970處)設置於聚合物層中或聚合物層之第二表面上的接地元件。方法2900進一步包含:形成(在步驟2980處)第二傳導元件,其提供在至少一第二節點與接地元件之間的電性通訊。
The
在一具體實施例中,當形成(在步驟2970處)半導體裝置之接地元件的步驟包括形成接地元件於聚合物層之第二表面上時,方法2900
可另外包括:形成(在步驟2972處)從接地元件延伸到模具之第二表面且包圍天線的接地屏蔽。
In one embodiment, when the step of forming (at step 2970) the ground element of the semiconductor device includes forming the ground element on the second surface of the polymer layer,
替代地或除了形成(在步驟2972處)接地屏蔽以外,方法2900可進一步包含:形成(在步驟2982處)設置在模具中的射頻(RF)濾波器;以及形成(在步驟2984處)第三傳導元件,其提供在至少一第三節點與RF濾波器之間的電性通訊。
Alternatively or in addition to forming (at step 2972) a ground shield, the
替代地或除了形成(在步驟2972處)接地屏蔽及/或形成(在步驟2982處)RF濾波器以外,方法2900可另外包括:形成(在步驟2985處)複數個半導體裝置;以及下列步驟中(在步驟2987處)之至少一者:將複數個半導體裝置的第一子集配置為接收器天線陣列、將複數個半導體裝置的第二子集配置為傳送器天線陣列、或二者。在此具體實施例中,方法可進一步包括:判定(在步驟2989處)供半導體裝置接收、傳送或二者之RF訊號的第一波長;以及定位(在步驟2991處)此等複數個半導體裝置,致使靠近半導體裝置之天線之間的間隔約為第一波長的一半。
Alternatively or in addition to forming (at step 2972) a ground shield and/or forming (at step 2982) an RF filter, the
第30圖的非寫實繪圖根據本文數個具體實施例圖示用於製造半導體裝置的系統。系統3000提供用於形成具有以上在說明第8圖至第28圖中之一或多個時提及之特徵的積體電路,且可形成具有以上在說明第1圖至第28圖之一或多個時提及之特徵的產品。
The non-realistic drawing in FIG. 30 illustrates a system for manufacturing semiconductor devices according to several specific embodiments herein. The
第30圖的系統3000可包含半導體裝置加工系統3010與積體電路設計單元3040。半導體裝置加工系統3010可基於由積體電路設計單元3040提供之一或多個設計製造積體電路裝置。
The
半導體裝置加工系統3010可包括各種加工工作站,例如沉積(例如,ALD、PECVD等等)工作站、蝕刻製程工作站、光刻製程工作站、CMP製程工作站等等。由加工系統3010執行的一或多個加工步驟可由加工控制器3020控制。加工控制器3020可為工作站電腦、桌上電腦、膝上電腦、平板電腦、或任何其他類型的運算裝置,其包含能夠控制製程、接收製程回饋、接收測試結果數據、執行學習循環調整、執行製程調整等等的一或多個軟體產品。
The semiconductor
半導體裝置加工系統3010可於媒體,例如矽晶圓,上產生積體電路。更特別的是,半導體裝置加工系統3010可產生包含一或多個半導體裝置735及/或736的積體電路。
The semiconductor
裝置加工系統3010的積體電路生產可基於積體電路設計單元3040所提供的電路設計。加工系統3010可提供已加工的積體電路/裝置3015於搬運機構3050上,例如輸送帶系統。在一些具體實施例中,搬運系統可為能夠搬運半導體晶圓的精密無塵室搬運系統。在一具體實施例中,半導體裝置加工系統3010可包括用於執行包括本質應力之材料沉積至閘極切斷區域(gate cut region)中的的複數個加工步驟。
The integrated circuit production of the
在一些具體實施例中,以“3015”標示的物件可代表個別晶圓,且在其他具體實施例中,物件3015可代表半導體晶圓的群組,例如,一“批次”的半導體晶圓。積體電路或裝置3015可為電晶體、電容器、電阻器、記憶格、處理器、及/或類似者。
In some specific embodiments, the object labeled "3015" may represent an individual wafer, and in other specific embodiments, the
系統3000的積體電路設計單元3040能夠提供電路設計讓半導體加工系統3010用來製造描述於本文的裝置。
The integrated
系統3000能夠執行涉及各種技術的各種產品之分析及製造。例如,系統3000可設計及產生用於製造CMOS技術、Flash技術、BiCMOS技術及/或各種其他半導體技術之裝置的資料。
The
上述方法可用存儲在非暫時性電腦可讀儲存媒體且由例如運算裝置之處理器執行的指令管控。描述於本文的每個操作可對應至存儲在非暫時性電腦記憶體或電腦可讀儲存媒體的指令。在各種具體實施例中,非暫時性電腦可讀儲存媒體包括磁性或光碟儲存裝置、例如快閃記憶體的固態儲存裝置、或其他非揮發性記憶體裝置或數個裝置。儲存在非暫時性電腦可讀儲存媒體上的電腦可讀指令可為原始碼、組合語言碼、目的碼、或可由一或多個處理器解譯及/或執行的其他指令格式。 The above methods can be controlled by instructions stored in a non-transitory computer-readable storage medium and executed by a processor such as a computing device. Each operation described herein can correspond to instructions stored in non-transitory computer memory or computer-readable storage media. In various embodiments, the non-transitory computer-readable storage medium includes magnetic or optical disk storage devices, solid-state storage devices such as flash memory, or other non-volatile memory devices or several devices. The computer-readable instructions stored on the non-transitory computer-readable storage medium may be source code, combined language code, object code, or other instruction formats that can be interpreted and/or executed by one or more processors.
以上所揭露的特定具體實施例均僅供圖解說明,本發明可由熟諳此藝者在受益於本文的教導後以明顯之不同但等效的方式來修改及實施。例如,可用不同的順序完成以上所提出的製程步驟。此外,除非在以下申請專利範圍中有提及,本發明並不受限於本文所示之構造或設計的細節。因此,顯然可改變或修改以上所揭露的特定具體實施例而所有此類變化都被認為仍然是在本發明的範疇與精神內。因此,本文尋求的保護係如以下提出的申請專利範圍所述。 The specific embodiments disclosed above are for illustrative purposes only, and the present invention can be modified and implemented in obviously different but equivalent ways by those who are familiar with the art and benefit from the teachings herein. For example, the process steps proposed above can be completed in a different order. In addition, unless mentioned in the scope of the following patent applications, the present invention is not limited to the details of the construction or design shown herein. Therefore, it is obvious that the specific embodiments disclosed above can be changed or modified, and all such changes are considered to still be within the scope and spirit of the present invention. Therefore, the protection sought in this article is as described in the scope of the patent application filed below.
2900:方法 2900: method
2910~2991:步驟 2910~2991: steps
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