TWI739075B - Method and computer program product for performing data writes into a flash memory - Google Patents

Abstract

A method for performing data writes of a flash memory device, performed by a processing unit, includes: determining whether a host write command of a submission queue has required to execute immediately before an execution of a portion of Host-Flash (H2F) table update or Garbage Collection (GC) process; and when the determination is positive, executing the host write command that has required to execute immediately in a batch, and then, executing the portion of H2F table update or GC process.

Description

Flash memory data writing method and computer program product

The invention relates to a storage device, in particular to a flash memory data writing method and a computer program product.

Flash memory is generally divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address to access the NOR flash memory on the address pin, and obtain the data stored at that address from the data pin of the NOR flash memory in time material. On the contrary, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processing unit needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , Read, write, erase, etc.), and the address used in this command. The address can point to a page (the smallest data block for a write operation in the flash memory) or a block (the smallest data block for an erase operation in the flash memory).

Latency of data writing is one of the important measurement items of Quality of Service QoS. In this test, 4K data can be randomly written into the storage unit for several hours, and the storage unit is in Dirty Mode. Then, the QD1/QD128 command depth can be used to randomly write 4K data for 180 seconds, and the delay time can be measured. Because the storage unit is in the dirty mode, NAND flash memory also needs to arrange time to write the updated logical-physical comparison table (Host-Flash H2F Table) in the static random access memory or dynamic random access memory to the storage unit. It is used to reduce the time to perform SPO Recovery SPOR after Sudden Power Off SPO. In addition, NAND flash memory needs time to be arranged in the dirty mode Perform garbage collection (Garbage Collection GC) operation to avoid the storage unit being unable to write user data due to insufficient space. The present invention provides a flash memory data writing method and a computer program product, which can be used to meet the test item requirements of the delay time when the storage unit is in the dirty mode.

In view of this, how to reduce or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

The present invention provides a flash memory data writing method, which is implemented by a processing unit when loading and executing the program code of a software or firmware module, including: performing a part of the logic-physical comparison table update or garbage collection Before the program, determine whether there is a host write command that needs to be processed immediately in the submission queue; and when there is a host write command that needs to be processed immediately, first execute the host write command in a batch, and then execute the part of the logic -Physical comparison table update or garbage collection procedure.

The present invention also provides a computer program product, which is loaded and executed by a processing unit, and includes the following program code: before executing a part of the logic-physical comparison table update or garbage collection process, it is determined whether there is a submission queue The host write command that needs to be processed immediately; and when there is a host write command that needs to be processed immediately, the host write command is executed in one batch, and then the logic-physical comparison table update or garbage collection procedure is executed.

One of the advantages of the above-mentioned embodiment is that through the above-mentioned judgment, it is possible to avoid too long waiting time for submitting some host write commands in the queue due to the update of the logical-physical comparison table or the execution of the garbage collection program.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

100: electronic device

110: central processing unit

120, 131: random access memory

130: storage device

132: Host Interface

133: Processing Unit

135: Flash Controller

137: Flash memory interface

139: LUN

139#0~139#11:LUN

CH#0~CH#3: Input and output channels

CE#0~CE#2: Enabling signal

310: Submission Queue

330: Complete Queue

CQH, CQT, SQH, SQT: indicators

410, 430, 450, 470: software or firmware module

S510~S590, S611~S635, S810~S870, S1010~S1070: method steps

70: Execution of a batch of host write commands

70a: start execution time

70b, T0, T1, T2, T3: end execution time point

W0~W12: Host write command

910: H2F Form

930: Physical address information

930-0: (physical) block number

930-1: (physical) page number and offset

930-2: (Entity) Plane Number

930-3: Logical unit number

FIG. 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

Figure 2 is a schematic diagram of the connection between the flash memory interface and the LUN.

Figure 3 is a schematic diagram of a command queue.

Figure 4 is a schematic diagram of the Flash Translation Layer (Flash Translation Layer FTL) architecture.

FIG. 5 is a flowchart of a data writing method according to some embodiments.

Fig. 6 is a flowchart of a method for processing a host write command according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of the arrival and processing of a host write command according to an embodiment of the present invention.

FIG. 8 is a flowchart of a method for updating a logical-physical comparison table (Host-Flash H2F Table) according to an embodiment of the present invention.

Figure 9 is a schematic diagram of physical storage comparison.

FIG. 10 is a flowchart of a method for executing a garbage collection (Garbage Collection GC) program according to an embodiment of the present invention.

The following descriptions are preferred implementations for completing the invention, and their purpose is to describe the basic spirit of the invention, but not to limit the invention. The actual content of the invention must refer to the scope of the claims that follow.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, elements, and/or components, but they do not exclude the possibility of adding More technical features, values, method steps, job processing, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is a precedence, prerequisite relationship, or an element. Prior to another element, or the chronological order of execution of method steps, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being “connected” or “coupled” to another element, it can be directly connected or coupled to other elements, and intermediate elements may appear. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other terms used to describe the relationship between elements can also be interpreted in a similar manner, such as "between" and "directly between", or "adjacent" as opposed to "directly abutting" and so on.

Refer to Figure 1. The electronic device 100 includes a central processing unit 110, a random access memory (Random Access Memory RAM) 120 and a storage device 130. When the central processing unit 110 operates, a queue can be established according to its requirements. The electronic device 100 is, for example, an electronic product such as a personal computer, a laptop PC, a tablet computer, a mobile phone, a digital camera, and a digital video camera. The specific area in the random access memory 120 can be configured as a data buffer, a queue, and so on. The storage device 130 may include a processing unit 133, or may further include a random access memory 131 to improve the performance of the storage device 130. The processing unit 133 can receive commands from the central processing unit 110 through a host interface 132, and instruct the flash controller 135 to perform data reading, writing, and erasing operations accordingly. The central processing unit 110 and the processing unit 133 can use universal flash storage (Universal Flash Storage UFS), fast non-volatile memory (Non-Volatile Memory Express NVMe), universal serial bus (Universal Serial Bus USB), advanced technology Attach (advanced technology attachment ATA), serial advanced technology attachment (SATA), rapid peripheral component interconnect (peripheral component interconnect express PCI-E) and other communication protocols for communication. Any one of the central processing unit 110 and the processing unit 133 can be implemented in a variety of ways, such as using general-purpose hardware (for example, a single processor, a multi-processor with parallel processing capabilities, a graphics processor, or other processors with computing capabilities. ), and provide the functions described later when executing software and/or firmware commands. The random access memories 120 and 131 can store data needed during execution, such as variables, data tables, and so on.

The Logical Unit Number LUN 139 provides a large amount of storage space, usually hundreds of Gigabytes, or even Terabytes, which can be used to store a large amount of user data, such as high-resolution pictures, videos, and so on. The LUN 139 includes a control circuit and a memory array. The memory cells in the memory array can be triple level cells (TLCs) or quad-level cells (QLCs). The random access memory 131 can be used to cache the use of the CPU 110 to be written into the LUN 139 User data, the user data read from LUN 139 and will be knocked out to CPU 110, and the logical-physical mapping table (Logical-Physical Mapping Table, L2P table) required for searching. The random access memory 131 can also store data needed in the process of executing software and firmware commands, such as variables, data tables, and so on. The random access memory 131 may include a static random access memory (State Random Access Memory SRAM), a dynamic random access memory (Dynamic Random Access Memory DRAM), or both.

The storage device 130 further includes a flash controller 135, a flash memory interface 137 and a LUN 139, and the flash controller 135 communicates with the LUN 139 through the flash memory interface 137. Specifically, double data rate (DDR) communication can be used Protocols, such as Open NAND Flash Interface ONFI, DDR Toggle or other interfaces. The flash controller 135 of the storage device 130 writes user data to the specified address (destination address) in LUN 139 through the flash memory interface 137, and reads the user from the specified address (source address) in LUN 139 material. The flash memory interface 137 uses several electronic signals to coordinate data and command transmission between the flash controller 135 and the LUN 139, including data lines, clock signals, and control signals. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transfer Chip Enable CE, Address Latch Enable ALE, and Command Extraction Enable ( Control signals such as Command Latch Enable CLE and Write Enable WE. The processing unit 133 and the flash controller 135 may exist separately or be integrated in the same chip.

Referring to Figure 2, the flash memory interface 137 may include four I/O channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to three LUNs, for example, channel CH#0 is connected to LUN139#0 , 139#4 and 139#8. It should be noted that, in order to meet different system requirements, those skilled in the art can set multiple channels in the flash memory interface 137 and connect each channel to at least one LUN. The present invention is not limited thereby. Flash control The controller 135 can drive the flash memory interface 137 to send one of the enabling signals CE#0 to CE#2 to enable LUN139#0 to 139#3, 139#4 to 139#7, or 139#8 to 139#11, Then read user data from the enabled LUN in a parallel manner, or write user data to the enabled LUN.

3, the command queue may include a submission queue (Submission Queue SQ) 310 and a completion queue (Completion Queue CQ) 330, which are used to temporarily store CPU commands and completion elements (Completion Element CE), respectively. The submission queue 310 and the completion queue 330 are preferably created in the same device. For example, the submission queue 310 and the completion queue 330 are preferably created in the random access memory 120 on the host side. In the random access memory 131 of the storage device 130. The submission queue 310 and the completion queue 330 can also be created in different devices. Each of the submission queue 310 and the completion queue 330 includes a collection of multiple entries. Each item in the submission queue 310 can store an I/O command, such as erase, read, and write commands. The items in the collection are stored in order. The basic principle of the set operation is to add new entries (which can be called enqueues) from the end position (such as the position pointed by the indicator SQT or CQT), and remove the entries from the starting position (such as the position pointed by the indicator SQH or CQH) ( Can be called dequeue). In other words, the first instruction added to the submission queue 310 will also be the first to be removed. The central processing unit 110 can write a plurality of write instructions to the delivery queue 310, and the processing unit 133 reads (or fetches) the earliest arrival write instruction from the delivery queue 310 and executes it. After the execution of the write instruction is completed, the processing unit 133 writes the completed element to the completion queue 330, and the central processing unit 110 can read or retrieve the completed element to determine the execution result of the write instruction.

4, the Flash Translation Layer (Flash Translation Layer FTL) architecture includes a write command read module 410, a write command execution module 430, an H2F table write module 450, and a garbage collection (Garbage Collection GC) operation module 470. The function HW_PushIOCmdInfoPrdInfo() can include the code of the write command reading module 410, and read a specified number of hosts from the delivery queue when the processing unit 133 is loaded and executed Write commands (Host Write Commands), and temporarily store user data of a specific logical address (Logical Address) to be written by the host write command to the random access memory 131. The function FTL_HandlePrdInfo() can include the program code of the write command execution module 430, and when the processing unit 133 is loaded and executed, the user data temporarily stored in the random access memory 131 is passed through the flash controller 135 and according to the host write command when the processing unit 133 is loaded and executed. Flash memory interface 137 writes LUN 139, obtains the physical address (Physical Address) from the response message from flash controller 135, and then updates the correspondence between logical address and physical address to H2F in random access memory 131 The appropriate location of the table. The function SaveMap() may include the code of the H2F table writing module 450, and when the processing unit 133 is loaded and executed, the updated H2F table is written into the LUN 139 through the flash controller 135 and the flash memory interface 137. When the processing unit 133 loads and executes the GC operation module 470, it collects broken user data in multiple physical pages, and writes the collected user data into the LUN 139 through the flash controller 135 and the flash memory interface 137 The new physical pages are used to allow the released physical pages to be used by other users' data after being erased.

In some embodiments, the processing unit 133 may implement the method flow shown in FIG. 5 when loading and executing the program code of the control module. When the processing unit 133 detects that the CPU 110 starts to write the host write command into the submission queue 310, it can repeat the loop (steps S510 to S590) until there is no host write command in the submission queue 310 ( The path of "No" in step S590). In each round (Iteration), the processing unit 133 may sequentially execute the write instruction reading module 410, the write instruction execution module 430, the H2F table writing module 450, and the GC operation module 470 in sequence. However, when the execution time of the H2F table writing module 450 or the GC operation module 470 is too long, the waiting time for submitting the host write command in the queue 310 may be too long, and the quality of service (Quality of Service QoS) may not be satisfied. ) Requirements for the delay time measurement items. In addition, since the central processing unit 110 can write any number of host write commands to the submission queue 310 at any point in time, the host interface 132 (which can be referred to as Hardware HW for short) can only read the upper limit number of host write commands. . If the central processing unit 110 issues a host write command exceeding the upper limit at a time, the host The machine interface 132 can only read the upper limit number of host write commands for the write command reading module 410 to process. The remaining host write commands can only be processed by the command reading module 410 in the next round. Due to the lack of information about the time when each host write command arrives in the submission queue 310, the control module (referred to as the Firmware FW for short) cannot know how long the host write command obtained from the hardware has been delayed.

表1中的每個項目可關聯於一個指令集，包含指令集編號、此資料集包含的主機寫指令的編號以及關聯於所有主機寫指令的到達時間戳記。例如，指令集“S0”包含主機寫指令“W0”至“W4”，並且它們到達遞交佇列310的時間為“T0”。“W0”至“W4”亦可代表遞交佇列310中第0至4個項目的主機寫指令。處理單元133可使用公式(1)來判斷一個指令集中的主機寫指令是否需要立即處理：Tnow-Ti>Ttr 其中，Tnow代表目前時間，i代表正整數，Ti代表遞交佇列310中第i個主機寫指令的到達時間點，Ttr代表閥值。閥值的設定可參考延遲時間測項的需求，例如，如果延遲時間測項要求99%的主機寫指令的延遲時間需要小於5毫秒(ms)，則閥值可設為介於4~5毫秒間的值。當公式(1)的條件滿足時，代表遞交佇列310中第i個主機寫指令需要立即處理。 In order to supplement the time information when the host write command arrives in the submission queue 310, in some embodiments, the write command reading module 410 can be modified to add a time stamp to the host newly arrived in the submission queue 310 during the processing of the host write command. Write instructions. Referring to the embodiment of the method for processing a host write command shown in FIG. 6, this method is implemented when the processing unit 133 loads and executes the program code of the write command reading module 410. First, a loop is repeatedly executed (steps S611 to S613) for reading all host write commands in the delivery queue 310 that need to be processed immediately in one batch (Batch). Due to hardware limitations, the processing unit 133 reads host write commands that do not exceed the upper limit number per round. In step S611 when the loop is entered for the first time, the processing unit 133 can read the time information of the host write command arriving at the delivery queue 310 from the random access memory 131, and determine the host write command that needs to be processed immediately according to the time information. The time information of arrival in the submission queue 310 can be implemented using Table 1 below:

Each item in Table 1 can be associated with a command set, including the command set number, the host write command number contained in this data set, and the arrival timestamp associated with all host write commands. For example, the command set "S0" contains the host write commands "W0" to "W4", and the time they arrive at the delivery queue 310 is "T0". "W0" to "W4" can also represent host write commands for submitting the 0th to 4th items in the queue 310. The processing unit 133 can use formula (1) to determine whether a host write command in an instruction set needs to be processed immediately: Tnow-Ti>Ttr where Tnow represents the current time, i represents a positive integer, and Ti represents the i-th in the submission queue 310 The arrival time point of the host write command, Ttr represents the threshold. The threshold setting can refer to the requirements of the delay time measurement item. For example, if the delay time measurement item requires 99% of the host's write command delay time to be less than 5 milliseconds (ms), the threshold can be set between 4~5 milliseconds Value between. When the condition of formula (1) is satisfied, it means that the write command of the i-th host in the submission queue 310 needs to be processed immediately.

In Cache Mode, the processing unit 133 can obtain each host write command from the submission queue 310 through the host interface 132, and access the memory 120 from the random access memory 120 through the host interface 132 according to the address information in the host write command. Read user data to be written into LUN 139, and store the user data in random access memory 131. Because the host write command is executed when the user data is stored in the random access memory 131, the processing unit 133 can write the completion element (Completion Element CE) corresponding to the host write command to the completion queue 330 through the host interface 132. After that, the processing unit 133 can schedule time to execute the program code of the write command execution module 430 for writing the user data temporarily stored in the random access memory 131 into the LUN 139 through the flash controller 135 and the flash memory interface 137.

In the non-cache mode or the storage device 130 is not configured with a memory space for temporarily storing user data, the processing unit 133 obtains one or more host write commands and the user data to be written through the host interface 132 , The program code of the write command execution module 430 can be skipped directly, which is used to write user data into the LUN 139 through the flash memory interface 137. After the LUN 139 is successfully written, the processing unit 133 can switch back to the program code of the execution module 430 for executing the write command for writing the completion components corresponding to the host write command(s) to the completion queue 330. In some embodiments, the write command read module 410 and the write command execution module 430 can be integrated into a single module without being limited to the FTL architecture.

After the loop is executed, the processing unit 133 obtains from the random access memory 131 the time stamp Tpre representing the end of the reading of the host write command of the previous batch (step S631), and updates the arrival time in the random access memory 131 Information, used to delete processed host writes The record of the command, and the record of the new host write command added Tpre to the submission queue 310 (step S633), and update Tpre as a time stamp representing the current time for reference for the execution of the host write command in the next batch (step S633) S635).

雖然主機寫指令“W10”至“W12”的實際到達時間晚於時間點T2，但由於寫指令讀取模組410不知道任何主機寫指令的實際到達時間，使用最早可能到達時間T2當作時間戳記，可降低主機寫指令的實際 延遲時間超出時間測項需求的可能性。 The following examples are given to assist in explaining the process of the method described in FIG. 6. Referring to FIG. 7, the execution of the write command reading module 410 of the previous batch ends at time T2 and the execution 70 of the write command reading module 410 of this batch starts at time 70a and ends at time T3. (70b). At time 70a, the random access memory 131 stores the execution end time stamp Tpre of the host write command of the previous batch as time T2, and the host write commands "W0" to "W9" as described in Table 1 arrive and are delivered Queue 310 time information. Assume that the instruction set "S0" (that is, the host write instructions "W0" to "W4") meets the condition of formula (1) and needs to be processed immediately. Then, the processing unit 133 reads the host write commands "W0" to "W4" in the delivery queue 310 (step S631). When approaching the time point T3, the read operation of the host write commands "W0" to "W4" ends. After the operation ends, the processing unit 133 reads the execution end time stamp Tpre (=T2) of the host write command of the previous batch from the random access memory 131 (step S633). Suppose that between time points T2 and T3, the central processing unit 110 writes the host write commands “W10” to “W12” to the submission queue 310 and changes the index SQT to point to the thirteenth item in the submission queue 310. By comparing the arrival time information in the random access memory 131 with the address currently pointed to by the indicator SQT, the processing unit 133 can know that the CPU 110 newly writes the host write commands "W10" to "W12" to the submission queue 310. Next, the processing unit 133 updates the arrival time information as shown in Table 2 (step S633):

Although the actual arrival time of the host write commands "W10" to "W12" is later than the time point T2, since the write command reading module 410 does not know the actual arrival time of any host write commands, the earliest possible arrival time T2 is used as the time Stamping can reduce the possibility that the actual delay time of the host writing command exceeds the time measurement item requirement.

Although FIG. 3 only shows two queues 310 and 330, the host can create more submission sub-queues and completion sub-queues according to different application requirements. Table 1 can be modified to include the arrival time information of the host write commands in different submission sub-queues, and make a general judgment on whether the host write commands in all submission sub-queues need to be processed immediately. The present invention is not affected by this. limit.

In order to solve the technical problem when LUN 139 is in the dirty mode, the method flow shown in Figure 8 and Figure 10 is a flash memory data writing method, this method is loaded and executed by the processing unit 133 related software or firmware module The program code is implemented, including the following steps: before performing a part of the H2F table update or GC operation, determine whether there is at least one host write command in the submission queue 310 that needs to be processed immediately; and when there is a host that needs to be processed immediately When writing commands, first execute the host write command(s) in one batch, and then execute this part of the H2F table update or GC operation; and when there is no host write command that needs to be processed immediately, execute this part directly H2F table update or GC operation. Those skilled in the art understand that H2F table update and GC operations are operations that the storage device 130 initiates to optimize the performance of the storage device 130, rather than being initiated by the CPU 110 like a host write command. The detailed description is as follows: To avoid frequent updating of the H2F table in LUN 139, the processing unit 133 can temporarily store all or part of the H2F table in the random access memory 131 (usually DRAM), and update the temporary storage after the write operation is completed. The contents of the H2F table. In order to shorten the time required to perform SPO Recovery SPOR after a sudden power off (Sudden Power Off SPO), the processing unit 133 must write the updated content of the temporary H2F table into the LUN every time a certain number of records are updated. 139. When the storage device 130 is in the dirty mode, such H2F table write operations may be more frequent. However, it takes a period of time for the processing unit 133 and the flash memory interface 137 to complete the entire write operation that needs to be updated, which may cause the waiting time of submitting some host write commands in the queue 310 to be too long to meet the requirements of the QoS delay time measurement item. . In order to avoid the above-mentioned problems, in some embodiments, the H2F table writes The module 450 can be modified to divide all the updated content in the H2F table into several segments, and before writing a segment of the updated content, first determine whether there is a host write command that needs to be processed immediately. When there are host write commands that need to be processed immediately, these host write commands are processed first.

Referring to FIG. 9, the H2F table 910 preferably stores the physical address information corresponding to each logical address (or logical block address LBA) in order. The space required by the H2F table 910 is preferably proportional to the total number of logical addresses. The logical address can be represented by a logical block address, and each LBA corresponds to a fixed-size logical block, such as 512 bytes (Bytes), and is stored in a physical address. For example, the H2F table 910 sequentially stores the physical address information from LBA#0 to LBA#65535. The data of several consecutive logical addresses (such as LBA#0 to LBA#7) can form a host page. The physical address information 930 includes, for example, four bytes, in which 930-0 records the (physical) block number ((Physical) Block Number), and 930-1 records the (physical) page number and offset (offset). ; 930-2 records the (physical) plane number, 930-3 records the logical unit number and the input/output channel number and so on. For example, the physical address information 930 corresponding to LBA#2 may point to an area 951 in the block 950.

Referring to the embodiment of the method for updating the H2F table shown in FIG. 8, this method is implemented when the processing unit 133 loads and executes the program code of the H2F table writing module 450. The processing unit 133 may repeatedly execute a loop (steps S810 to S870) for writing all the updated content in the H2F table to the LUN 139 in sections. For example, when the physical address information about LBA#0 to LBA#2047 in the temporary H2F table is updated, the processing unit 133 can write information about LBA#0 to LBA#1023 (that is, the first paragraph) in one batch. ), and write the physical address information about LBA#1024 to LBA#2047 (that is, the second paragraph) in the next batch. In each round, the processing unit 133 first determines whether there is a host write command that needs to be processed immediately (step S810). For the judgment of the host write command, refer to the description of Table 1, step S613 and formula (1) as described above, and will not be repeated for the sake of brevity. When there is a host write command that needs to be processed immediately (the "Yes" path in step S810), the processing unit 133 first reads the host write command that needs to be processed immediately (step S830), and then Then, the updated content in the H2F table is stored in LUN 139 (step S850). When there is no host write command that needs to be processed immediately (the "No" path in step S810), directly store an updated content in the H2F table to LUN 139 (step S850).

When the storage device 130 is in dirty mode, many physical pages in LUN 139 may contain valid and invalid sections (also called expired sections). The valid section stores valid user data, and the invalid section stores invalid sections. 'S (old) user data. When the processing unit 133 detects that the available space of LUN 139 is insufficient, it can instruct the flash controller 135 to read and collect user data in the valid section of the source block, and then instruct the flash controller 135 to rewrite The collected valid user data is sent to the empty physical page of the active block (or destination block), so that the data blocks (source blocks) containing invalid user data can be changed to idle blocks. Afterwards, the idle blocks can be used as active blocks to provide data storage space after being erased. The procedure described above is called garbage collection.

However, it takes some time for the processing unit 133 and the flash memory interface 137 to complete the entire GC procedure, which may cause the waiting time for submitting some host write commands in the queue 310 to be too long to meet the QoS delay time measurement requirements. In order to avoid the above-mentioned problems, in some embodiments, the GC operation module 470 can be modified to divide the entire garbage collection process into several stages, and determine whether there is a host write command that needs to be processed immediately before performing a stage of work. . When there are host write commands that need to be processed immediately, these host write commands are processed first.

In some embodiments, the entire GC process can be divided into five stages of operations: the processing unit 133 can determine the source address of the valid user data in the source block and the destination address of the destination block in the first stage. In the second stage, the processing unit 133 can instruct the flash controller 135 to read the user data from the source address of the LUN 139, and instruct the flash controller 135 to write the read user data to the destination address of the LUN 139. In the third and fourth stages, the processing unit 133 can update the H2F table and the physical-logical mapping table (P2L table) respectively. The processing unit 133 can be used in the fifth Phase changes the source block to an idle block. The above five stages are just examples. Those skilled in the art can combine several stages into a single stage in the GC operation module 470 according to the working speed of the processing unit 133, the flash controller 135 and the flash memory interface 137, or one The stage is divided into several sub-stages. In addition, the GC operation module 470 can optimize the execution sequence of these five stages according to the processing status, for example, arrange the first to second stages into a loop until the destination block can no longer be written to the user from the source block After the information is collected, the third to fifth stages will be executed.

Referring to the embodiment of the execution method of the GC program shown in FIG. 10, this method is implemented when the processing unit 133 loads and executes the code of the GC operation module 470. The processing unit 133 may repeatedly execute a loop (steps S1010 to S1070) for executing the GC program in stages. For each batch, the processing unit 133 first determines whether there is a host write command that needs to be processed immediately (step S1010). For the judgment of the host write command, refer to the description of Table 1, step S613 and formula (1) as described above, and will not be repeated for the sake of brevity. When there is a host write command that needs to be processed immediately (the "Yes" path in step S1010), the processing unit 133 first reads the host write command that needs to be processed immediately (step S1030), and then executes the first or next stage GC operation (step S1050). When there is no host write command that needs to be processed immediately (the "No" path in step S1010), the first or next stage of GC operation is directly executed (step S1050).

In some embodiments of step S830 or S1030, the processing unit 133 may call and execute the function HW_PushIOCmdInfoPrdInfo() to complete the method steps described in FIG. 6. In other embodiments of step S830 or S1030, the H2F table writing module 450 or the GC operation module 470 can embed the program code of the method steps described in FIG. 6 for the processing unit 133 to execute.

All or part of the steps in the method of the present invention can be implemented by a computer program, such as a computer operating system, a specific hardware driver in the computer, or a software application program. In addition, it can also be implemented in other types of programs as shown above. Those with ordinary knowledge in the technical field can write the method of the embodiment of the present invention into a computer program, and it will not be added for the sake of brevity. To describe. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer readable medium, such as DVD, CD-ROM, USB disk, hard disk, and can also be placed on a network (such as the Internet, or Other appropriate vehicles).

Although FIG. 1 includes the above-described elements, it is not excluded that, without violating the spirit of the invention, more other additional elements can be used to achieve better technical effects. In addition, although the flowcharts in Figures 6, 8 and 10 are executed in the specified order, those skilled in the art can modify the order of these steps on the premise of achieving the same effect without violating the spirit of the invention. Therefore, the present invention is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of applied claims must be interpreted in the broadest way to include all obvious modifications and similar settings.

S810~S870: method steps

Claims (10)

A method for writing flash memory data, implemented by a processing unit when loading and executing the code of a software or firmware module, including: dividing the logic-physical comparison table update or the execution of the garbage collection process into multiple parts ; Before executing part of the above-mentioned logical-physical comparison table update or the above-mentioned garbage collection process, determine whether there is a host write command in the submission queue that needs to be processed immediately based on the information of the time when the host write command arrives in a submission queue ; And when there is a host write command that needs to be processed immediately, execute the host write command in a batch, and then execute the part of the logical-physical comparison table update or garbage collection process, where the submission queue The host write command that needs to be processed immediately means that the time distance for the host write command to reach the submission queue has now exceeded a threshold. The data writing method of the flash memory as described in claim 1, including: when there is no host write command that needs to be processed immediately, executing the logical-physical comparison table update or garbage collection procedure of this part. The method for writing flash memory data as described in claim 1, including: using a formula to determine whether there is a host write command that needs to be processed immediately in the submission queue: Tnow-Ti>Ttr, where Tnow represents the current time, and i represents A positive integer, Ti represents the arrival time of the i-th host write command in the submission queue, and Ttr represents the threshold; when the condition of the formula is met, it means that the i-th host write command in the submission queue needs to be processed immediately . The data writing method for flash memory according to claim 3, wherein the arrival time of each host write command in the submission queue is the last batch when the processing unit detects that the host write command enters the submission queue A point in time when the execution of the second host write command ends. The data writing method of flash memory as described in claim 1, wherein the logical-physical part of The update of the look-up table includes writing physical address information associated with a continuous logical address to a logical unit number through a flash memory interface. The method for writing data to a flash memory according to claim 1, wherein the garbage collection procedure is divided into multiple stages, and the part of the garbage collection procedure includes one stage of operation. The method for writing data to a flash memory according to claim 6, wherein the multi-stage operations include: determining a source address of a source block containing valid user data, and a destination bit of a destination block Address; instruct a flash controller to read user data from the source address of a logical unit number, and instruct the flash controller to write the read user data to the destination address of the logical unit number; Update a logical-physical comparison table; update a physical-logical comparison table; or change the source block to an idle block. The method for writing data to a flash memory according to claim 1, wherein the operation of executing each host write command includes obtaining the host write command from the submission queue through a host interface; according to the address information in the host write command Read user data to be written into a logical unit number from a first random access memory through the host interface; store the user data in a second random access memory; and write the data through the host interface A completion element of the command should be written by the host to a completion queue. The method for writing data to a flash memory according to claim 1, wherein the operation of executing each host write command includes obtaining the host write command from the submission queue through a host interface; according to the address information in the host write command Read user data to be written into a logical unit number from a random access memory through the host interface; write the user data to the logical unit number through a flash memory interface; and write the corresponding data through the host interface A completion element of the command should be written by the host to a completion queue. A computer program product includes a program code, and when the program code is loaded and executed by a processing unit, the method for writing data to the flash memory as described in any one of the request items 1 to 9 is implemented.

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