TWI738417B - Display device and driving method thereof - Google Patents

Abstract

A display device includes a common electrode layer, a driving electrode layer, a liquid crystal layer, and a driving circuit. The common electrode layer is configured to receive a common signal. The driving electrode layer is configured to receive a driving signal. The liquid crystal layer is set between the common electrode layer and the driving electrode layer. The driving circuit, configured to control a voltage difference between the common electrode layer and the driving electrode layer, includes a boost converter, a comparator and a half-unit gain buffer. The boost converter is configured to provide different DC voltages according to different level of a control signal. When the driving signal has a first voltage range, the display device is in a sharing mode. When the driving signal has a second voltage range, the display device is in a privacy mode.

Description

Display device and driving method

The present disclosure relates to a display device and a driving method, in particular to a display device and a driving method for a peep-proof display screen.

The existing privacy display screens add an additional privacy layer to the general liquid crystal display, and apply a voltage to the electrode plates on the upper and lower sides of the privacy layer to generate a voltage difference, so that the liquid crystal in the privacy layer changes the transmittance according to different voltage differences. , And then achieve the effect of changing the viewing angle of the display screen.

However, the current technology usually adopts a structure in which the electrode plate under the anti-peep layer inputs an AC voltage signal switched between positive and negative voltages, and the upper electrode plate is grounded. As far as the circuit design is concerned, the conversion efficiency of the negative voltage in this drive architecture is not good. In addition, based on the characteristics of the display panel manufacturing process, the voltage difference required for each display panel to change the transmittance is different, so the applied voltage needs to be adjusted for each display panel. In summary, how to solve the above-mentioned shortcomings is an urgent problem in the industry.

The present disclosure provides a display device, which includes a common electrode layer, a driving electrode layer, a liquid crystal layer, and a driving circuit. The common electrode layer is used for receiving common signals. The driving electrode layer is used for receiving the driving voltage signal. The liquid crystal layer is arranged between the common electrode layer and the driving electrode layer. The driving circuit is used to control the voltage difference between the driving electrode layer and the common electrode layer, and includes: a boost converter, a comparator, and a half-voltage converter. The boost converter is used to provide DC voltage signals of different magnitudes according to different levels of the control signal. The comparator is used to use the DC voltage signal as the working voltage to generate a driving voltage signal whose voltage range corresponds to the magnitude of the DC voltage signal. The half-voltage device is used to provide a public signal, wherein the voltage level of the public signal is half of the voltage level of the DC voltage signal. Wherein, when the driving voltage signal has the first voltage range, the display device is in the sharing mode, and when the driving voltage signal has the second voltage range, the display device is in the privacy mode.

The present disclosure provides a driving method suitable for a display device, wherein the driving method includes: using the display device to receive a control signal, wherein the display device includes a common electrode layer, a driving electrode layer, a liquid crystal layer, and a driving circuit, and the driving circuit includes a booster Converters, comparators, and half-voltage converters; use boost converters to provide DC voltage signals of different magnitudes to the comparator and half-voltage based on different levels of the control signal; use comparators to use DC voltage signals as operating voltages to generate The voltage range corresponds to the driving voltage signal of the DC voltage signal, and the driving voltage signal is transmitted to the driving electrode layer; and the half-voltage device is used to provide the common signal to the common electrode layer, where the voltage level of the common signal is that of the DC voltage signal A half of the voltage level; wherein, when the driving voltage signal has a first voltage range, the display device is in a sharing mode, and when the driving voltage signal has a second voltage range, the display device is in a privacy mode.

With the above-mentioned display device and driving method, it is provided that the problem of poor conversion efficiency of negative voltage can be solved.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only used to explain the present invention and are not used to limit the present invention. The description of structural operations is not used to limit the order of its execution. The recombined structure of the components produces devices with equal effects, which are all covered by the disclosure of the present invention.

Unless otherwise specified, the terms used in the entire specification and the scope of the patent application usually have the usual meaning of each term used in this field, in the content disclosed here, and in the special content. Some terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance on the description of the present disclosure.

In this text, when an element is referred to as "connection" or "coupling", it can refer to "electrical connection" or "electrical coupling". "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used to describe different elements in this document, the terms are only used to distinguish elements or operations described in the same technical terms.

FIG. 1 is a schematic diagram of a display device 100 according to some embodiments of the present disclosure. As shown in FIG. 1, the display device 100 includes a liquid crystal display panel 10, a backlight panel BL, a privacy module 110 and a driving circuit 120. In some embodiments, the privacy module 110 includes a first substrate 101, a second substrate 102 and a liquid crystal layer 103. In some embodiments, the liquid crystal display panel 10 includes a plurality of pixel circuits, a gate driving circuit, a data driving circuit, a plurality of data lines and scan lines. For the sake of brevity, these elements in the liquid crystal display panel 10 are not shown Shown in Figure 1.

Fig. 2 is a cross-sectional view of the privacy module 110 of Fig. 1 in an embodiment. As shown in Figure 2, the liquid crystal layer 103 is disposed between the first substrate 101 and the second substrate 102. The side of the first substrate 101 facing the liquid crystal layer 103 is provided with a common electrode layer 201, and the second substrate 102 faces the liquid crystal layer. One side is provided with a driving electrode layer 202, that is, the liquid crystal layer is located between the common electrode layer 201 and the driving electrode layer 202.

Structurally, the driving circuit 120 is coupled to the privacy module 110. More specifically, the driving circuit 120 is coupled to the common electrode layer 201 and the driving electrode layer 202, respectively.

In operation, the driving circuit 120 controls the voltage difference between the common electrode layer 201 and the driving electrode layer 202 by providing the common signal Hf_AVDD to the common electrode layer 201 and the driving voltage signal DS to the driving electrode layer 202 to switch the display of the display device 100. model.

In the embodiment of the present disclosure, the display device 100 includes two display modes: a sharing mode and a privacy mode. 3A and 3B are schematic diagrams of display modes according to some embodiments of the present disclosure. As shown in Figures 3A and 3B, the display device 100 has a wide viewing angle Ɵ1 when in the sharing mode, and a narrow viewing angle Ɵ2 when the display device 100 is in the privacy mode, and the wide viewing angle Ɵ1 is greater than the narrow viewing angle Ɵ2 .

FIG. 4 is a schematic diagram of a driving circuit 400 according to some embodiments of the present disclosure. The driving circuit 400 can be used to implement the driving circuit 120 in FIG. 1 and FIG. 2. In some embodiments, as shown in FIG. 4, the driving circuit 400 includes a boost converter 410, a comparator 420 and a voltage half 430. The boost converter 410 is coupled to the comparator 420 and the half-voltage 430 through the first node N1.

The comparator 420 includes a first operational amplifier 421, a first resistor R1, and a second resistor R2. The first operational amplifier 421 includes a positive input terminal VA+, a negative input terminal VA-, an output terminal VAO, a positive power terminal VAS+, and a negative power terminal VAS-, wherein the positive input terminal VA+ of the first operational amplifier 421 is used to receive the first clock The signal CLK1, the positive power terminal VAS+ of the first operational amplifier 421 is used to receive the DC voltage signal AVDD and is coupled to the boost converter 410 at the first node N1, the negative power terminal VAS- of the first operational amplifier 421 is coupled to the ground terminal . The first resistor R1 includes a first terminal and a second terminal. The first terminal of the first resistor R1 is used to receive the reference voltage VX, and the second terminal of the first resistor R1 is coupled to the negative input terminal VA- of the first operational amplifier 421 At the second node N2. The second resistor R2 is coupled between the second node N2 and the ground terminal. In some embodiments, the resistance values of the first resistor R1 and the second resistor R2 are the same.

The half-voltage 430 includes a second operational amplifier 431, a third resistor R3, and a fourth resistor R4. The second operational amplifier 431 includes a positive input terminal VB+, a negative input terminal VB-, an output terminal VBo, a positive power supply terminal VBS+, and a negative power supply terminal VBS-, wherein the negative input terminal VB- of the second operational amplifier 431 is coupled to the output terminal VBo , The positive power terminal VBS+ of the second operational amplifier 431 is coupled to the first node N1, and the negative power terminal VBS- of the second operational amplifier 431 is coupled to the ground terminal. The third resistor R3 includes a first terminal and a second terminal. The first terminal of the third resistor R3 is coupled to the first node N1, and the second terminal of the third resistor R3 is coupled to the positive input terminal VB+ of the second operational amplifier 431. The third node N3. The fourth resistor R4 is coupled between the ground terminal and the third node N3. In some embodiments, the third resistor R3 and the fourth resistor R4 have the same resistance value.

Hereinafter, the operation of the driving circuit 400 will be further described with reference to FIG. 4 and FIG. 5 at the same time. FIG. 5 is a timing diagram of signal waveforms of the display device 100 according to some embodiments of the present disclosure. In some embodiments, the boost converter 410 provides the DC voltage signal AVDD with different magnitudes according to different levels of the control signal CS.

For example, when the control signal CS is low in the first period T1, the boost converter 410 provides the DC voltage signal AVDD with the first voltage level V1, and when the control signal CS is high in the second period T2 When the voltage level is set, the boost converter 410 provides a DC voltage signal AVDD having a second voltage level V2, and the first voltage level V1 is different from the second voltage level V2. That is, by switching the control signal CS between different levels, the boost converter 410 can boost the input voltage Vin to a DC voltage signal having the first voltage level V1 or the second voltage level V2 AVDD.

In some embodiments, the comparator 420 is used to use the DC voltage signal AVDD as the operating voltage to generate the driving voltage signal DS with a voltage range corresponding to the magnitude of the DC voltage signal AVDD. In more detail, the first operational amplifier 421 compares the voltage between the positive input terminal VA+ and the negative input terminal VA- to output the driving voltage signal DS whose voltage range is positively correlated with the voltage level of the DC voltage signal AVDD.

For example, in the first time period T1, the DC voltage signal AVDD has a first voltage level V1, and the driving voltage signal DS has a first voltage range Ra (that is, 0~V1) corresponding to the first voltage level V1. Yu the second During the period, the DC voltage signal AVDD has a second voltage level V2, and the driving voltage signal DS has a second voltage range (ie, 0~V2) corresponding to the second voltage level V2. In summary, the first voltage range Ra is different from the second voltage range Rb, and the voltage values in the first voltage range Ra and the second voltage range Rb are not less than zero.

In some embodiments, when the driving voltage signal DS has the first voltage range Ra, the display device 100 is in the sharing mode, and when the driving voltage signal DS has the second voltage range Rb, the display device 100 is in the privacy mode.

In some embodiments, the voltage range of the first clock signal CLK1 is between the ground voltage and the divided voltage of the reference voltage VX at the second node N2. Therefore, the voltage of the first clock signal CLK1 is periodically greater than or less than the voltage of the second node N2, resulting in the output driving voltage signal DS having the same frequency as the first clock signal CLK1.

In some embodiments, the voltage half 430 is used to provide the common signal Hf_AVDD to the common electrode layer 201 in FIG. 2. More specifically, the second operational amplifier 431 outputs the common signal Hf_AVDD with the same voltage level as the positive input terminal VB+ (that is, the third node N3). Since the third resistor R3 and the fourth resistor R4 have the same resistance value, the voltage of the third node N3 is half of the voltage level of the DC voltage signal AVDD. In other words, the voltage level of the common signal Hf_AVDD is half of the voltage level of the DC voltage signal AVDD.

For example, in the first time period T1, the DC voltage signal AVDD has the first voltage level V1, and the voltage level of the common signal Hf_AVDD is half of the first voltage level V1 (marked as 1/2 in Figure 5). V1). In the second period, the DC voltage signal AVDD has the second voltage level V2, and the voltage level of the common signal Hf_AVDD is half of the second voltage level V2 (labeled as 1/2 V2 in FIG. 5).

It can be seen from the above that by generating a driving voltage signal DS whose voltage value is not less than 0 in the first voltage range Ra and the second voltage range Rb to drive the display device 100, it will be possible to prevent the driving circuit 400 from being inefficient in converting negative voltages. The problem. For example, the first voltage range Ra of the driving voltage signal DS is 0-20V, the half-voltage 430 generates a common signal Hf_AVDD of 10V to make the display device 100 in the sharing mode; and the second voltage range Rb of the driving voltage signal DS is 0 ~10V, the half-voltage 430 generates a 5V common signal Hf_AVDD so that the display device 100 is in the privacy mode.

In other embodiments, the driving circuit 400 in FIG. 4 further includes an internal bus 440, an integrated circuit interface bus 450, a register 460, and a memory 470. The boost converter 410 is coupled to the integrated circuit interface bus 450, the register 460, and the memory 470 through the internal bus 440.

In some embodiments, the integrated circuit interface bus 450 is used to receive the data signal SData and the second clock signal CLK2. The integrated circuit interface bus 450 stores a plurality of specified voltage values Vdata1~VdataN included in the data signal SData in the register 460 through the internal bus 440.

In some embodiments, during the pre-factory test phase of the display device 100, the boost converter 410 can access the register 460 through the internal bus 440 to gradually increase (or decrease) according to the specified voltage values Vdata1~VdataN. ) The first voltage level V1 or the second voltage level V2 of the DC voltage signal AVDD, so as to gradually adjust the liquid crystal deflection angle of the privacy module 110 in Figure 2. Therefore, the production line personnel can test the anti-peeping effect of each display device 100 to appropriately calibrate the first voltage level V1 and the second voltage level V2 of the DC voltage signal AVDD, that is, calibrate its wide viewing angle Ɵ1 and Narrow viewing angle Ɵ2. When the wide viewing angle Ɵ1 and the narrow viewing angle Ɵ2 meet the respective test standards, the boost converter 410 can store one or more of the specified voltage values Vdata1~VdataN in the memory 470 to fix the first voltage level The values of V1 and the second voltage level V2 in subsequent operations. In this way, the wide viewing angle Ɵ1 and the narrow viewing angle Ɵ2 (that is, the anti-peeping effect) of different display devices 100 will tend to be the same.

For example, the boost converter 410 accesses the specified voltage value Vdata2 in the register 460, and in the first period T1, the boost converter 410 adjusts the first voltage level V1 of the DC voltage signal AVDD to the specified voltage The value Vdata2 enables the display device 100 to have a wide viewing angle Ɵ1. At this time, if the production line personnel determine that the value of the wide viewing angle Ɵ1 meets the test standard, the boost converter 410 may store the specified voltage value Vdata2 in the memory 470.

For another example, the boost converter 410 accesses the specified voltage value Vdata4 in the register 460, and in the second time period T2, the boost converter 410 adjusts the second voltage level V2 of the DC voltage signal AVDD to the specified voltage value Vdata4 enables the display device 100 to have a narrow viewing angle Ɵ2. At this time, if the production line personnel determine that the value of the narrow viewing angle Ɵ2 meets the test standard, the boost converter 410 may store the specified voltage value Vdata4 in the memory 470.

In some embodiments, the memory 470 may be implemented by various suitable non-volatile memories, such as Programmable Read-Only Memory (PROM). In other embodiments, the register 460 can be implemented by various suitable non-volatile memory, volatile memory, or a combination thereof, such as flash memory.

FIG. 6 is a flowchart of a driving method 600 according to some embodiments of the present disclosure. As shown in Figure 6, the driving method 600 includes a process S601, a process S602, a process S603, a process S604, and a process S605. The following process is described with reference to Fig. 4 and Fig. 5, but not limited to them.

In the process S601, the display device 100 is used to receive the control signal CS. In some embodiments, the control signal CS is at a low level in the first time period T1, so that the display device 100 is in the sharing mode; the control signal CS is at a high level in the second time period, so that the display device 100 is in the privacy mode.

In the process S602, the boost converter 410 is used to provide the DC voltage signal AVDD with different magnitudes to the comparator 420 and the half-voltage 430 according to different levels of the control signal CS. In some embodiments, the boost converter 410 provides the DC voltage signal AVDD having the first voltage level V1 during the first period T1, and provides the DC voltage signal AVDD having the second voltage level V2 during the second period T2.

In the process S603, the comparator 420 uses the DC voltage signal AVDD as the working voltage to generate a driving voltage signal DS with a voltage range corresponding to the magnitude of the DC voltage signal AVDD, and transmits the driving voltage signal DS to the driving electrode layer 202. In some embodiments, the comparator 420 provides the driving voltage signal DS having the first voltage range Ra during the first period T1, and provides the driving voltage signal DS having the second voltage range Rb during the second period T2.

In the process S604, the voltage half 430 is used to provide the common signal Hf_AVDD to the common electrode layer 201, wherein the voltage level of the common signal Hf_AVDD is half of the voltage level of the DC voltage signal AVDD. In some embodiments, the voltage level of the common signal Hf_AVDD in the first period T1 is half of the first voltage level V1, and the voltage level of the common signal Hf_AVDD in the second period T2 is half of the second voltage level V2 .

In the process S605, the display device 100 is operated in the sharing mode or the privacy mode according to the driving voltage signal DS. For example, if the driving voltage signal DS has the first voltage range Ra, the display device 100 is in the sharing mode. For another example, when the driving voltage signal DS has the second voltage range Rb, the display device 100 is in the privacy mode.

In some embodiments, when the display device 100 is in the sharing mode, there is a first voltage difference between the common electrode layer 201 and the driving electrode layer 202, and the liquid crystal in the liquid crystal layer 103 has a first transmittance; In the peep mode, there is a second voltage difference between the common electrode layer 201 and the driving electrode layer 202, and the liquid crystal in the liquid crystal layer 103 has a second transmittance, wherein the first voltage difference is greater than the second voltage difference, and the first transmittance is greater than The second transmittance. In other words, the display device 100 in the sharing mode has a wider viewing angle Ɵ1 because of the liquid crystal layer 103 with higher transmittance. On the other hand, the display device 100 in the privacy mode has a liquid crystal layer 103 with a lower transmittance, and thus has a narrow viewing angle Ɵ2.

In some embodiments, the above-mentioned first voltage difference is positively related to the first voltage level V1, and the second voltage difference is positively related to the second voltage level V2.

Although the content of this disclosure has been disclosed in the above embodiments, it is not intended to limit the content of this disclosure. Anyone with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection scope of this disclosure shall be subject to those defined by the attached patent application scope.

100: display device 10: LCD panel 101: first substrate 102: second substrate 103: liquid crystal layer 110: Privacy module 120: drive circuit 201: Common electrode layer 202: drive electrode layer 400: drive circuit 410: Boost converter 420: Comparator 421: Operational amplifier 430: Half Pressure 431: Operational Amplifier 440: internal bus 450: Integrated circuit interface bus 460: register 470: memory BL: Backlight panel N1, N2, N3: Node AVDD: DC voltage signal Hf_AVDD: public signal VX: Reference voltage DS: drive voltage signal R1~R4: resistance VA+, VB+: Positive input VA-, VB-: negative input VAS+, VBS+: Positive power supply terminal VAS-, VBS-: negative power supply terminal VAo, VBo: output terminal Vin: input voltage CS: Control signal CLK1, CLK2: clock signal GND: Ground voltage V1, V2: voltage level T1: the first period T2: second period SData: data signal Vdata1~VdataN: Specified voltage value S601, S602, S603, S604, S605: Process Ɵ1, Ɵ2: viewing angle

FIG. 1 is a schematic diagram of a display device according to some embodiments of the present disclosure. Figure 2 is a cross-sectional view of the privacy module of Figure 1 in an embodiment. 3A and 3B are schematic diagrams of display modes according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram of a driving circuit according to some embodiments of the present disclosure. FIG. 5 is a timing diagram of signal waveforms of the display device according to some embodiments of the present disclosure. FIG. 6 is a flowchart of a driving method according to some embodiments of the present disclosure.

400: drive circuit

410: Boost converter

420: Comparator

421: Operational amplifier

430: Half Pressure

431: Operational Amplifier

440: internal bus

450: Integrated circuit interface bus

460: register

470: memory

N1, N2, N3: Node

AVDD: DC voltage signal

Hf_AVDD: public signal

VX: Reference voltage

DS: drive voltage signal

R1~R4: resistance

VA+, VB+: Positive input

VA-, VB-: negative input

VAS+, VBS+: Positive power supply terminal

VAS-, VBS-: negative power supply terminal

VAo, VBo: output terminal

Vin: input voltage

CS: Control signal

CLK1, CLK2: clock signal

SData: data signal

Claims (10)

A display device includes: a common electrode layer for receiving a common signal; a driving electrode layer for receiving a driving voltage signal; a liquid crystal layer disposed between the common electrode layer and the driving electrode layer; and A driving circuit for controlling the voltage difference between the driving electrode layer and the common electrode layer, and comprising: a boost converter for providing DC voltage signals of different magnitudes according to different levels of a control signal; A comparator for using the DC voltage signal as a working voltage to generate the driving voltage signal with a voltage range corresponding to the magnitude of the DC voltage signal; and a half-voltage device for providing the common signal, wherein the voltage of the common signal is accurate The position is half of the voltage level of the DC voltage signal; wherein, when the driving voltage signal has a first voltage range, the display device is in a sharing mode, and when the driving voltage signal has a second voltage range, The display device is in a privacy mode. The display device according to claim 1, wherein the comparator includes: a first operational amplifier including a positive input terminal, a negative input terminal, an output terminal, a positive power terminal, and a negative power terminal, wherein the first operational amplifier The positive input terminal of an operational amplifier is used to receive a first clock signal, and the first operational amplifier The positive power terminal of the amplifier is used to receive the DC voltage signal and is coupled to the boost converter at a first node. The negative power terminal of the first operational amplifier is coupled to a ground terminal; a first resistor, Comprising a first terminal and a second terminal, the first terminal of the first resistor is used for receiving a reference voltage, the second terminal of the first resistor and the negative input terminal of the first operational amplifier are coupled to a A second node; and a second resistor, coupled between the second node and the ground terminal. The display device according to claim 1, wherein the voltage half includes: a second operational amplifier including a positive input terminal, a negative input terminal, an output terminal, a positive power terminal and a negative power terminal, wherein the The negative input terminal of the second operational amplifier is coupled to the output terminal, the positive power terminal of the second operational amplifier is coupled to a first node, and the negative power terminal of the second operational amplifier is coupled to a ground terminal ; A third resistor, including a first end and a second end, the first end of the third resistor is coupled to the first node, the second end of the third resistor and the second operational amplifier The positive input terminal is coupled to a third node; and a fourth resistor is coupled between the ground terminal and the third node, wherein the third resistor and the fourth resistor have the same resistance value. The display device according to claim 1, wherein the first voltage range is different from the second voltage range, and the voltage value in the first voltage range and the second voltage range is not less than zero. The display device according to claim 1, wherein the driving circuit further comprises: an integrated circuit interfaced with the bus, for receiving a data signal, wherein the data signal includes a plurality of specified voltage values; a register for Storing the plurality of specified voltage values, wherein the boost converter is used to access the register to sequentially adjust the DC voltage signal to the plurality of specified voltage values; and a memory for storing the plurality Specify one or more of the voltage values. The display device according to claim 1, wherein when the display device is in the sharing mode, there is a first voltage difference between the common electrode layer and the driving electrode layer, and the liquid crystal in the liquid crystal layer has a first transmittance, When the display device is in the privacy mode, there is a second voltage difference between the common electrode layer and the driving electrode layer, and the liquid crystal in the liquid crystal layer has a second transmittance, wherein the first voltage difference is greater than the first voltage difference. Two voltage differences, and the first transmittance is greater than the second transmittance. A driving method suitable for a display device, wherein the driving method includes: using the display device to receive a control signal, wherein the display device includes a common electrode layer, a driving electrode layer, a liquid crystal layer, and a driving circuit, and the The driving circuit includes a boost converter, a comparator and a half-voltage converter; The boost converter is used to provide a DC voltage signal with different magnitudes to the comparator and the half-voltage according to the different levels of the control signal; the comparator is used to use the DC voltage signal as the working voltage to generate a corresponding voltage range A driving voltage signal based on the magnitude of the DC voltage signal, and transmitting the driving voltage signal to the driving electrode layer; and using the half-voltage device to provide a common signal to the common electrode layer, wherein the voltage level of the common signal Is half of the voltage level of the DC voltage signal; wherein, when the driving voltage signal has a first voltage range, the display device is in a sharing mode, and when the driving voltage signal has a second voltage range, the The display device is in a privacy mode. The driving method according to claim 7, wherein the first voltage range is different from the second voltage range, and the voltage value in the first voltage range and the second voltage range is not less than zero. The driving method according to claim 7, wherein when the display device is in the sharing mode, it has a wide viewing angle, and when the display device is in the privacy mode, it has a narrow viewing angle. The driving method according to claim 7, wherein when the control signal is a low logic level, the boost converter provides the DC voltage signal with a first voltage level, and when the control signal is a high logic level When the voltage level is reached, the boost converter provides the DC voltage signal with a second voltage level, And the first voltage level is different from the second voltage level.

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