TWI737973B - Electrical device and manufacturing method thereof - Google Patents

Abstract

An electrical device includes a substrate, a gate, a two-dimensional material layer, a gate insulating layer, a source and a drain. The gate is over the substrate. The two-dimensional material layer is over the substrate. The two-dimensional material layer includes a channel and first and second contacts on two sides of the channel. The channel includes a first polycrystalline transition metal dichalcogenide. The gate insulating layer is between the gate and the two-dimensional material layer. The source and the drain are on two sides of the two-dimensional material layer and electrically connected to the two-dimensional material layer, respectively.

Description

Electronic device and manufacturing method thereof

This disclosure relates to an electronic device and its manufacturing method.

In flat panel display technology, thin film transistor (TFT) is a widely used semiconductor device, such as liquid crystal display (LCD) and organic light emitting diode (OLED). ) Displays and electronic paper (electronic paper, E-paper) and other flat-panel displays. The thin-film electrocrystalline system is used to provide voltage or current switching, so that the display pixels in various displays can show bright, dark, and grayscale display effects. The structure design or material selection of thin film transistors that are used in a large number of displays will directly affect the performance of the product.

Generally speaking, a thin film transistor has at least a gate, a source, a drain, and a channel layer. The conductivity of the channel layer can be changed by controlling the voltage of the gate, so that the source and the drain are connected. (On) or insulated (off) state. In addition, an ohmic contact layer with N-type doping or P-type doping is usually formed on the channel layer to reduce the contact resistance between the channel layer and the source, or the channel layer and the drain. In the conventional thin film transistors, the channel layer material used is large Mostly amorphous silicon (a-Si). However, due to the low carrier mobility of amorphous silicon thin film transistors and poor reliability, the application range of amorphous silicon thin film transistors is still subject to many restrictions.

The embodiments of the present disclosure provide an electronic device and a manufacturing method thereof, which can effectively provide low-resistance ohmic contact through the contact terminal of the first structural phase (such as 1T' phase) with high carrier mobility, low contact resistance and high thermal stability The contact interface between the source and drain of the active device and the channel layer improves the performance and thermal stability of the device. And through the use of an amorphous two-dimensional material layer for laser and annealing processes to obtain and coexist polycrystalline contact ends and polycrystalline channel layers with different structural phases, which has the advantage of large process flexibility. Furthermore, the position of the channel layer that needs to exhibit semiconductor characteristics and the position of the contact terminal that exhibits metal characteristics can be selected according to product requirements.

In one embodiment, an electronic device includes a substrate, a gate electrode, a two-dimensional material layer, a gate insulating layer, a source electrode, and a drain electrode. The gate is located above the substrate. The two-dimensional material layer is located above the substrate. The two-dimensional material layer includes a channel layer and first and second contact ends on both sides of the channel layer. The channel layer includes a first polycrystalline transition metal chalcogenide compound. The gate insulating layer is located between the gate and the two-dimensional material layer. The source electrode and the drain electrode are located on both sides of the two-dimensional material layer and are respectively electrically connected to the two-dimensional material layer.

In one embodiment, a method of manufacturing an electronic device includes the following steps. A layer of amorphous two-dimensional material is deposited on the substrate. Irradiate the laser on the first part of the amorphous two-dimensional material layer so that the first part includes the seed part and the amorphous part, the seed crystal The part has a first structural phase, and the amorphous two-dimensional material layer has a second part adjacent to the first part, and the second part is protected from laser irradiation. Perform an annealing process to transform the seed part and amorphous part of the first part into contact ends, and transform the second part into a channel layer. The contact ends have the first structural phase, the channel layer has the second structural phase, and the first structural phase The conductivity of is higher than the conductivity of the second structural phase.

10, 10a‧‧‧Electronic device

100‧‧‧Substrate

102‧‧‧Buffer layer

104‧‧‧Gate

106‧‧‧Gate insulation layer

108‧‧‧Two-dimensional material layer

108a‧‧‧Part One

108a’‧‧‧Contact terminal

108b‧‧‧Part Two

108b’‧‧‧passage layer

110‧‧‧Protection layer

112‧‧‧Source

114‧‧‧Dip pole

116‧‧‧Active Components

118‧‧‧Inorganic protective layer

120‧‧‧Organic protective layer

122‧‧‧Pixel electrode

124‧‧‧Interlayer dielectric layer

P1‧‧‧Laser

P2‧‧‧Annealing process

T1, T1’, T2, T2’‧‧‧Thickness

TH1‧‧‧Pixel electrode connecting hole

TH2‧‧‧Contact hole

Read the following detailed description and match the corresponding diagrams to understand many aspects of this disclosure. It should be noted that many of the features in the drawing are not drawn in actual proportions according to the standard practice in the industry. In fact, the size of the feature can be increased or decreased arbitrarily to facilitate the clarity of the discussion.

1A to 1H are schematic cross-sectional views of the manufacturing process of an electronic device according to an embodiment; and FIGS. 2A to 2G are schematic cross-sectional views of the manufacturing process of an electronic device according to another embodiment.

The following will clearly illustrate the spirit of the present disclosure with figures and detailed descriptions. Anyone with ordinary knowledge in the relevant technical field who understands the embodiments of the present disclosure can change and modify the techniques taught in the present disclosure, which is not Depart from the spirit and scope of this disclosure. For example, the statement that "the first feature is formed on or on the second feature" will include the first feature and the second feature having direct contact; and will also include the first feature and the second feature being indirect The contact has an additional feature formed between the first feature and the second feature. also, In this disclosure, component numbers and/or text are reused in multiple examples. The purpose of repetition is to simplify and clarify, and it does not determine the relationship between multiple embodiments and/or the discussed configurations.

In addition, relative terms such as "below", "below", "below", "above" or "up" or similar words are used in this article to facilitate the description of what is shown in the diagram The relationship of one element or feature to another element or feature. In addition to describing the orientation of the device in the diagram, the relative orientation vocabulary includes the different orientations of the device under use or operation. When the device is additionally set (rotated by 90 degrees or other facing orientation), the relative terms used in this article can also be explained accordingly.

1A to 1H are schematic cross-sectional views of the manufacturing process of the electronic device 10 according to an embodiment. First, referring to FIG. 1A, a substrate 100 is provided, a buffer layer 102 is formed on the substrate 100, and a gate 104 is formed on the buffer layer 102. The material of the substrate 100 is, for example, sapphire, metal foil, monocrystalline silicon, polycrystalline silicon, amorphous silicon, glass, quartz, plastic or ceramics, etc. The material of the buffer layer 102 is, for example, oxide. However, this disclosure is not limited to this. In other embodiments of the present disclosure, the buffer layer 102 may not be included, as long as the substrate 100 can withstand the subsequent lithographic etching process. Next, a first conductive material (not shown) is formed on the substrate 100 on which the buffer layer 102 has been formed, and the first conductive material is patterned to form the gate 104. The patterning method is, for example, a photolithographic etching process. The gate electrode 104 can be a single-layer structure or a multi-layer stack structure, and its material is, for example, titanium, molybdenum, chromium, iridium, aluminum, copper, silver, gold, or any combination or alloy of the foregoing.

1B, a gate insulating layer 106 is formed on the substrate 100 and covers the gate 104. Then, a two-dimensional material is deposited on the substrate 100 and covers the gate insulating layer 106, and then the two-dimensional material is patterned It is a two-dimensional material layer 108. The material of the gate insulating layer 106 is, for example, an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon aluminum oxide, or a stacked layer of at least two of the foregoing materials), an organic material, or a combination of the foregoing. Of course, this embodiment is not limited to this, and any material that can provide insulating properties can be selectively applied to this embodiment to make the gate insulating layer 106. The two-dimensional material layer 108 is an amorphous two-dimensional material layer. The material of the two-dimensional material layer 108 is, for example, Transition metal dichalcogenides (TMDs), such as molybdenum disulfide (MoS ₂ ), molybdenum ditelluride (MoTe ₂ ), tungsten ditelluride (WTe ₂ ), Analogs or combinations of the above. Specifically, the transition metal chalcogen compound includes at least one transition metal and at least one chalcogen element as two-dimensional material elements. The transition metal is selected from the group consisting of molybdenum, tungsten, chromium, vanadium, niobium, tantalum, platinum, titanium, hafnium, zirconium, and rhenium, and the chalcogen element is selected from the group consisting of sulfur, selenium, and tellurium 'S group.

In one embodiment, the two-dimensional material can be formed by physical vapor deposition. Taking the two-dimensional material made from transition metals and chalcogens as an example, in the step of forming the amorphous two-dimensional material, the above-mentioned The targets of two types of two-dimensional material elements are sputtered or evaporated. In one embodiment, a single target may be used, and the transition metal and chalcogen on the target have an equivalent ratio. In other embodiments, co-sputtering or co-evaporation of multiple targets containing two-dimensional material elements (such as transition metals and chalcogen elements) may be used to form amorphous two-dimensional materials depending on the process requirements. In one embodiment, an inert gas (such as argon) can be introduced into the deposition environment of the two-dimensional material. For example, an inert gas with a flow rate of about 15 sccm to about 25 sccm and a working pressure of about 8 mTorr to about 12 mTorr can be introduced. Under the conditions of deposition about 25 seconds to about 35 seconds.

Referring to FIG. 1C, the first part 108a of the two-dimensional material layer 108 is irradiated with a laser P1, so that the first part 108a includes a seed part and an amorphous part, and the seed part has a first structural phase. In other words, when the laser P1 irradiates the first part 108a of the two-dimensional material layer 108, a part of the first part 108a will be transformed into a seed crystal with the first structural phase (ie, the seed part), and the remaining part of the first part 108a Will not be transformed and maintain the amorphous state (that is, the amorphous part). The first part 108a is located on both sides of the gate 104. In other words, the vertical projection of the first part 108a on the substrate 100 does not overlap with the vertical projection of the gate 104 on the substrate 100. The two-dimensional material layer 108 has a second part 108b adjacent to the first part 108a. The second portion 108b is located between the first portions 108a, and the second portion 108b is located directly above the gate 104. In other words, the vertical projection of the second portion 108b on the substrate 100 overlaps the vertical projection of the gate 104 on the substrate 100. Because the second part 108b is protected from the laser P1, the second part 108b remains amorphous. In one embodiment, a laser with a wavelength of about 532 nm, a laser power of about 15 mW to about 25 mW, and a beam size of about 1 micron can be used to irradiate the first portion 108a. The first portion 108a has a thickness T1, the second portion 108b has a thickness T2, and the thickness T1 is substantially the same as the thickness T2. In one embodiment, the thickness T1 and the thickness T2 are between about 4 nanometers and about 6 nanometers.

Referring to FIG. 1D, a protective layer 110 is deposited on the two-dimensional material layer 108 to cover the first portion 108a and the second portion 108b. The protective layer 110 includes at least one oxide. For example, the protective layer 110 may include silicon oxide. In other embodiments, the protective layer 110 may include silicon nitride, silicon oxynitride, silicon aluminum oxide, the like, or a combination thereof. The protective layer 110 can prevent the two-dimensional material elements (such as transition metals, such as molybdenum) in the two-dimensional material layer 108 from being lost in the subsequent process (such as the annealing process P2 shown in FIG. 1E), so as to improve the two-dimensional material layer 108 Quality.

Referring to Figure 1E, an annealing process P2 is performed to transform the seed part and amorphous part of the first part 108a into the contact end 108a', and transform the second part 180b into the channel layer 108b'. In this embodiment, the contact end 108a' has a first structural phase, and the channel layer 108b' has a second structural phase. In one embodiment, the contact end 108a' has a polycrystalline first structure phase, and the channel layer 108b' has a polycrystalline second structure phase. In some embodiments in which the two-dimensional material layer 108 includes a transition metal chalcogenide compound, the channel layer 108b' includes a first polycrystalline transition metal chalcogenide compound having a second structural phase, and the contact end 108a' includes a first structural phase The second polycrystalline transition metal chalcogenide compound. The constituent elements of the first polycrystalline transition metal chalcogen compound are the same as the constituent elements of the second polycrystalline transition metal chalcogen compound. The contact end 108a' has a thickness T1'. The channel layer 108b' has a thickness T2'. In this embodiment, the second structural phase is different from the first structural phase. For example, the conductivity of the first structural phase is higher than the conductivity of the second structural phase. In this embodiment, the first structural phase is a polycrystalline 1T' phase, and the second structural phase is a polycrystalline 2H phase. The 1T' phase exhibits metallic characteristics. For example, the 1T' phase has high carrier mobility and low contact. Therefore, it can effectively provide a low-resistance ohmic contact interface between the source/drain of the active device and the channel layer (for example, the source 112, the drain 114, and the channel layer 108b' in Figure 1G), thereby enhancing the device Performance, and the 1T' phase obtained by the laser P1 and annealing process P2 has high thermal stability. As a result, the thermal stability of the device can be improved. The 2H phase has semiconductor characteristics, and therefore, the channel layer 108b' can be used as a channel of the active device.

By using the amorphous two-dimensional material layer 108 to perform the laser P1 and the annealing process P2, the polycrystalline contact ends 108a' and the polycrystalline channel layer 108b' with different structural phases are obtained and coexist, which has great process flexibility. For example, there is no need to prepare a single crystal two-dimensional material, and even the position of the channel layer 108b' that needs to exhibit semiconductor characteristics and the position of the contact end 108a' that exhibits metal characteristics can be selected according to product requirements.

The annealing process P2 turns the first portion 108a having a thickness T1 into a contact end 108a' having a thickness T1', and the thickness T1' is between about 7 nanometers and about 10 nanometers. The annealing process P2 turns the second portion 108b having a thickness T2 into a channel layer 108b' having a thickness T2', and the thickness T2' is between about 2 nanometers and about 4 nanometers. The annealing process P2 makes the thickness T1' of the contact end 108a' greater than the thickness T2' of the channel layer 108b'.

The method of the annealing process P2 can be, for example, furnace annealing, rapid thermal annealing, laser annealing or microwave annealing. For example, the annealing process P2 may be to place the two-dimensional material layer 108 in an annealing environment of an inert gas (such as nitrogen) with a pressure of about 25 Torr to about 35 Torr, and a temperature range of about 600° C. to about 700° C. Maintain for about 20 hours to about 30 hours for annealing.

Referring to Figure 1F, the protective layer 110 is etched with a patterned photoresist layer (not shown) as a mask to form a patterned protective layer 110' to expose the contact ends 108a' located on both sides of the channel layer 108b', and The protective layer 110 still partially covers the contact end 108a' adjacent to the channel layer 108b', in other words, the patterned protective layer 110' completely covers the channel layer 108b' and partially covers the contact end 108a adjacent to the channel layer 108b' '. In other embodiments, the protective layer 110 can be completely removed after the annealing process P2, and the contact end 108a' and the channel layer 108b' can be completely exposed.

Referring to FIG. 1G, a source 112 and a drain 114 are formed on both sides of the channel layer 108b'. Specifically, the channel layer 108b' and the contact end 108a' can be used first A second conductive layer (not shown) is formed thereon, and then the second conductive layer is patterned to form a source 112 and a drain 114. In this embodiment, the material of the second conductive layer (or the source 112 and the drain 114) can be titanium, molybdenum, chromium, iridium, aluminum, copper, silver, gold, or any combination or alloy of the foregoing. The second conductive layer (or the source 112 and the drain 114) may be formed by a physical vapor deposition method, such as a sputtering method. The method of patterning the second conductive layer can be, for example, photolithography and etching.

After the steps in Figure 1G are completed, the gate 104, the gate insulating layer 106, the contact end 108a', the channel layer 108b', the source 112 and the drain 114 together constitute the active device 116. In this embodiment, the active device 116 is a bottom gate type thin film transistor, but this does not limit the disclosure. In fact, the active device 116 can also be another type of active device, such as a top gate type thin film transistor. Those with ordinary knowledge in the technical field of the present invention, The embodiment of the active element 116 should be flexibly selected according to actual needs.

Next, refer to Figure 1H. An inorganic protective layer 118, an organic protective layer 120, and a pixel electrode 122 are sequentially formed on the source 112 and the drain 114. The inorganic protective layer 118 covers the active device 116. The material of the inorganic protective layer 118 can be any inorganic dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or any combination of the foregoing. The formation method of the inorganic protective layer 118 may be, for example, a chemical vapor deposition method.

In this embodiment, the organic protective layer 120 covers the inorganic protective layer 118, but this does not limit the disclosure. If the active device 116 or the inorganic protective layer 118 has other stacked layers, such as other dielectric layers or barrier layers, organic The protective layer 120 can also cover these stacked layers. That is, the organic protective layer 120 may directly or indirectly cover the inorganic protective layer 118. The material of the organic protective layer 120 can be any organic dielectric material Material, for example: acrylic polymer (acrylic polymer). The formation method of the organic protective layer 120 may be, for example, a spin coating method.

The pixel electrode 122 is electrically connected to the active device 116. Specifically, the pixel electrode through hole TH1 can be formed first, and the pixel electrode through hole TH1 penetrates the stacked layer above the drain 114 to expose the drain 114. In this embodiment, since the stacked layer above the drain 114 includes an inorganic protective layer 118 and an organic protective layer 120, the pixel electrode through hole TH1 will penetrate through the inorganic protective layer 118 and the organic protective layer 120 to expose the drain 114 .

Then, a third conductive layer is formed to cover the organic protective layer 120 and the pixel electrode communication hole TH1, and then the third conductive layer is patterned to form the pixel electrode 122. The formed pixel electrode 122 will be electrically connected to the drain 114 through the pixel electrode through hole TH1. In this way, the electronic device 10 is completed.

The material of the aforementioned third conductive layer (or the pixel electrode 122) can be any conductive material. In this embodiment, the material of the third conductive layer (or the pixel electrode 122) can be a transparent conductive material, such as indium tin oxide, indium zinc oxide, zinc aluminum oxide or other conductive oxides or any combination of the foregoing . Alternatively, the material of the third conductive layer (or the pixel electrode 122) can also be other opaque conductive materials, such as titanium, molybdenum, chromium, iridium, aluminum, copper, silver, gold, or any combination or alloy of the foregoing . The formation method of the third conductive layer can be, for example, a physical vapor deposition method or a chemical vapor deposition method. The method of forming the pixel electrode communication hole TH1 and patterning the third conductive layer can be, for example, a photolithography and etching method.

2A to 2G are schematic cross-sectional views of the manufacturing process of the electronic device 10a according to another embodiment. First, referring to Figure 2A, a substrate 100 is provided, a buffer layer 102 is formed on the substrate 100, and a two-dimensional material layer 108 is formed on the substrate 100. On the buffer layer 102. The materials and formation methods of the substrate 100, the buffer layer 102, and the two-dimensional material layer 108 are the same as those of the embodiment shown in FIG. 1A and FIG. 1B, and therefore will not be repeated here.

Referring to FIG. 2B, a gate insulating layer 106 is formed on the substrate 100 to cover the two-dimensional material layer 108, and then a gate 104 is formed on the gate insulating layer 106. The material and forming method of the gate insulating layer 106 and the gate 104 are the same as those of the embodiment shown in FIG. 1A and FIG. 1B, so they will not be repeated here.

Referring to FIG. 2C, the first portion 108a of the two-dimensional material layer 108 is irradiated with the laser P1, so that the first portion 108a includes a seed part and an amorphous part, and the seed part has a first structural phase. In other words, when the laser P1 irradiates the first part 108a of the two-dimensional material layer 108, a part of the first part 108a will be transformed into a seed crystal with the first structural phase (ie, the seed part), and the remaining part of the first part 108a Will not be transformed and maintain the amorphous state (that is, the amorphous part). The first part 108a is located on both sides of the gate 104. In other words, the vertical projection of the first part 108a on the substrate 100 does not overlap with the vertical projection of the gate 104 on the substrate 100. The two-dimensional material layer 108 has a second part 108b adjacent to the first part 108a. The second portion 108b is located between the first portions 108a, and the second portion 108b is located directly above the gate 104. In other words, the vertical projection of the second portion 108b on the substrate 100 overlaps the vertical projection of the gate 104 on the substrate 100. The second part 108b is protected from the laser P1. In other embodiments, the laser P1 can also be irradiated on the entire substrate 100. Because the gate 104 is made of metal, the laser P1 can be reflected, so that the second part 108b directly under the gate 104 is protected from the laser. Irradiation of P1. It is possible to choose to irradiate only the first part 108a or irradiate the entire substrate 100 at the same time according to different laser equipment, so that only the first part 108a is irradiated by the laser P1, thereby achieving the advantage of greater process flexibility.

Because the second part 108b is protected from the laser P1, the second part 108b is protected from crystallization, in other words, the second part 108b remains amorphous. The method of irradiating the laser P1 is the same as the method of irradiating the laser P1 in FIG. 1C, and will not be repeated here.

Referring to FIG. 2D, an annealing process P2 is performed to transform the seed part and amorphous part of the first part 108a into the contact end 108a', and transform the second part 180b into the channel layer 108b'. In this embodiment, the contact end 108a' has a first structural phase, and the channel layer 108b' has a second structural phase. In one embodiment, the contact end 108a' has a polycrystalline first structure phase, and the channel layer 108b' has a polycrystalline second structure phase. In some embodiments in which the two-dimensional material layer 108 includes a transition metal chalcogenide compound, the channel layer 108b' includes a first polycrystalline transition metal chalcogenide compound having a second structural phase, and the contact end 108a' includes a first structural phase The second polycrystalline transition metal chalcogenide compound. The constituent elements of the first polycrystalline transition metal chalcogen compound are the same as the constituent elements of the second polycrystalline transition metal chalcogen compound. The contact end 108a' has a thickness T1' and the channel layer 108b' has a thickness T2'. In this embodiment, the second structural phase is different from the first structural phase. For example, the conductivity of the first structural phase is higher than the conductivity of the second structural phase. In this embodiment, the first structural phase is a polycrystalline 1T' phase, and the second structural phase is a polycrystalline 2H phase. The 1T' phase exhibits metallic characteristics. For example, the 1T' phase has high carrier mobility and low contact. Therefore, it can effectively provide a low-resistance ohmic contact interface between the source/drain of the active device and the channel layer (for example, the source 112, the drain 114, and the channel layer 108b' in Figure 1G), thereby enhancing the device Performance, and the 1T' phase obtained by the laser P1 and annealing process P2 has high thermal stability. As a result, the thermal stability of the device can be improved. The 2H phase has semiconductor characteristics, and therefore, the channel layer 108b' can be used as a channel of the active device. The gate insulating layer 106 can prevent the two-dimensional material elements (such as transition metals, such as molybdenum) in the two-dimensional material layer 108 from being lost due to the annealing process P2, so as to improve the quality of the two-dimensional material layer 108. The thickness and structure phase of the contact end 108a' and the channel layer 108b' and the way of the annealing process P2 are the same as those of the embodiment in FIG. 1E, so they will not be repeated here.

Referring to Figure 2E, the gate 104 is then used as an etching mask, and the gate insulating layer 106 is etched to form a patterned gate insulating layer 106', exposing the contact ends 108a' on both sides of the channel layer 108b' .

Referring to FIG. 2F, an interlayer dielectric layer 124 is formed on the substrate 100, and a plurality of contact holes TH2 are formed through the interlayer dielectric layer 124, exposing the contact terminals 108a' located on both sides of the channel layer 108b', and forming the source electrode 112 and the drain electrode. The pole 114 is on the interlayer dielectric layer 124, and is in contact with the contact end 108a' through different contact holes TH2, respectively. The material and forming method of the source electrode 112 and the drain electrode 114 are the same as those of the embodiment in FIG. 1G, so they will not be repeated here.

After the steps in FIG. 2F are completed, the gate 104, the gate insulating layer 106, the contact terminal 108a', the channel layer 108b', the source 112 and the drain 114 together constitute the active device 116. In this embodiment, the active device 116 is a top gate type thin film transistor, but this does not limit the disclosure. In fact, the active device 116 can also be another type of active device. Those with ordinary knowledge in the technical field of the present invention should choose the active device flexibly according to actual needs. Example of element 116.

Next, referring to FIG. 2G, an inorganic protective layer 118, an organic protective layer 120, and a pixel electrode 122 are sequentially formed on the source 112 and the drain 114. The materials and forming methods of the inorganic protective layer 118, the organic protective layer 120, and the pixel electrode 122 are the same as those of the embodiment shown in FIG. 1H, so they will not be repeated here.

The electronic devices 10 and 10a have high carrier mobility and low connection The contact end 108a' of the contact resistance and the first structural phase with high thermal stability (for example, 1T' phase) can effectively provide low-resistance ohmic contact between the source 112, the drain 114 and the channel layer 108b' of the active device. Interface, and improve component performance and thermal stability. And by using the amorphous two-dimensional material layer 108 to perform the laser P1 and annealing process P2 to obtain the polycrystalline contact end 108a' and the polycrystalline channel layer 108b' with different structural phases and make them coexist, which has process flexibility Great advantages. For example, there is no need to prepare single-crystal two-dimensional materials, and even the position of the channel layer 108b' that needs to exhibit semiconductor characteristics (such as 2H phase) can be selected according to product requirements, and to exhibit metal characteristics (such as : 1T' phase) the position of the contact end 108a'.

The above summarizes the characteristics of several implementations or embodiments, so that those with ordinary knowledge in the field can better understand the present disclosure from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the present disclosure, so as to achieve the same purpose and/or the implementation modes or embodiments introduced herein The same advantages. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the disclosure. Without departing from the spirit and scope of this disclosure, various changes, substitutions or modifications can be made to this disclosure.

10‧‧‧Electronic device

100‧‧‧Substrate

102‧‧‧Buffer layer

104‧‧‧Gate

106‧‧‧Gate insulation layer

108a’‧‧‧Contact terminal

108b’‧‧‧passage layer

110’‧‧‧Protection layer

112‧‧‧Source

114‧‧‧Dip pole

116‧‧‧Active Components

118‧‧‧Inorganic protective layer

120‧‧‧Organic protective layer

122‧‧‧Pixel electrode

TH1‧‧‧Pixel electrode connecting hole

Claims (12)

An electronic device comprising: a substrate; a gate electrode located above the substrate; a two-dimensional material layer located above the substrate, the two-dimensional material layer including a channel layer and a first contact located on both sides of the channel layer End and a second contact end, the channel layer includes a first polycrystalline transition metal chalcogen compound, the first contact end and the second contact end include a second polycrystalline transition metal chalcogen compound, the second polycrystalline chalcogenide The crystalline transition metal chalcogenide compound has a first structural phase, the first polycrystalline transition metal chalcogenide compound has a second structural phase, the first structural phase is a 1T' phase, and the second structural phase is a 2H phase; The gate insulating layer is located between the gate and the two-dimensional material layer; and a source and a drain are located on both sides of the two-dimensional material layer and are electrically connected to the two-dimensional material layer. The electronic device according to claim 1, wherein the substrate is sapphire, metal foil, monocrystalline silicon, amorphous silicon, polycrystalline silicon, glass, quartz, plastic or ceramic. The electronic device according to claim 1, wherein the conductivity of the first structural phase is higher than the conductivity of the second structural phase. The electronic device according to claim 1, wherein the constituent elements of the first polycrystalline transition metal chalcogen compound and the second polycrystalline transition metal sulfur The constituent elements of the genus compounds are the same. The electronic device according to claim 1, wherein the first and second polycrystalline transition metal chalcogen compounds comprise at least one transition metal and at least one chalcogen element, and the transition metal is selected from molybdenum, tungsten, chromium, and vanadium , Niobium, tantalum, platinum, titanium, hafnium, zirconium, rhenium, and the chalcogen element is selected from the group consisting of sulfur, selenium, and tellurium. The electronic device according to claim 1, wherein the thickness of the first contact end and the thickness of the second contact end are respectively greater than the thickness of the channel layer. The electronic device according to claim 1, further comprising: a pixel electrode located above the two-dimensional material layer and electrically connected to the drain electrode. A method for manufacturing an electronic device includes: depositing an amorphous two-dimensional material layer on a substrate; irradiating a laser on a first part of the amorphous two-dimensional material layer so that the first part includes a seed part and an amorphous part Part, wherein the seed part has a first structure phase, the amorphous two-dimensional material layer has a second part adjacent to the first part, and the second part is protected from the laser; and an annealing process is performed to make the The seed part and the amorphous part of the first part are transformed into a contact end, and the second part is transformed into a channel layer, the contact end has the first structural phase, and the channel layer has a second structural phase, wherein Should The conductivity of the first structural phase is higher than the conductivity of the second structural phase. The method according to claim 8, wherein the annealing process is furnace annealing, rapid thermal annealing, laser annealing or microwave annealing. The method according to claim 8, wherein after the annealing process, the contact end has the polycrystalline first structural phase. The method according to claim 8, wherein before the laser irradiation, the first part has a first thickness and the second part has a second thickness, and the annealing process makes the first thickness greater than the second thickness. The method according to claim 8, further comprising: before the annealing process, depositing a protective layer on the amorphous two-dimensional material layer to cover the first part and the second part, wherein the protective layer comprises silicon nitride , Silicon oxynitride, silicon aluminum oxide or a combination of the above.

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