TWI737374B - Non-volatile memory structure - Google Patents

Non-volatile memory structure Download PDF

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TWI737374B
TWI737374B TW109122202A TW109122202A TWI737374B TW I737374 B TWI737374 B TW I737374B TW 109122202 A TW109122202 A TW 109122202A TW 109122202 A TW109122202 A TW 109122202A TW I737374 B TWI737374 B TW I737374B
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layer
charge storage
substrate
storage layer
volatile memory
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TW109122202A
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TW202203426A (en
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許漢杰
許正源
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力晶積成電子製造股份有限公司
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Abstract

A non-volatile memory structure including a substrate, a first conductive layer, a second conductive layer, a first charge storage layer, and a second charge storage layer is provided. There is a trench in the substrate. The first conductive layer is disposed in the trench. The second conductive layer is disposed in the trench and is located on the first conductive layer. The first charge storage layer and the second charge storage layer are disposed in the trench and are respectively located on one side and the other side of the first conductive layer. The first conductive layer, the second conductive layer, the first charge storage layer, the second charge storage layer, and the substrate are isolated from each other.

Description

非揮發性記憶體結構Non-volatile memory structure

本發明是有關於一種記憶體結構，且特別是有關於一種非揮發性記憶體結構。The present invention relates to a memory structure, and particularly relates to a non-volatile memory structure.

由於非揮發性記憶體(non-volatile memory)可進行多次資料的存入、讀取與抹除等操作，且具有當電源供應中斷時所儲存的資料不會消失、資料存取時間短以及低消耗功率等優點，所以已成為個人電腦和電子設備所廣泛採用的一種記憶體。Because non-volatile memory (non-volatile memory) can perform multiple data storage, reading, and erasing operations, and the stored data will not disappear when the power supply is interrupted, the data access time is short, and Because of its advantages of low power consumption, it has become a kind of memory widely used in personal computers and electronic devices.

然而，如何能夠進一步地縮小記憶體元件的尺寸並提升元件積集度為目前業界持續努力的目標。However, how to further reduce the size of the memory device and increase the device integration is the goal of continuous efforts in the industry.

本發明提供一種非揮發性記憶體結構，其可有效地縮小記憶體元件的尺寸並提升元件積集度。The present invention provides a non-volatile memory structure, which can effectively reduce the size of memory components and increase the integration of components.

本發明提出一種非揮發性記憶體結構，包括基底、第一導體層、第二導體層、第一電荷儲存層與第二電荷儲存層。在基底中具有溝渠。第一導體層設置在溝渠中。第二導體層設置在溝渠中，且位在第一導體層上。第一電荷儲存層與第二電荷儲存層設置在溝渠中，且分別位在第一導體層的一側與另一側。第一導體層、第二導體層、第一電荷儲存層、第二電荷儲存層與基底彼此隔離。The present invention provides a non-volatile memory structure including a substrate, a first conductor layer, a second conductor layer, a first charge storage layer and a second charge storage layer. There are trenches in the base. The first conductor layer is arranged in the trench. The second conductor layer is arranged in the trench and is located on the first conductor layer. The first charge storage layer and the second charge storage layer are arranged in the trench, and are respectively located on one side and the other side of the first conductive layer. The first conductor layer, the second conductor layer, the first charge storage layer, the second charge storage layer and the substrate are isolated from each other.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，第一電荷儲存層可具有朝向第二導體層的第一尖端。第二電荷儲存層可具有朝向第二導體層的第二尖端。According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the first charge storage layer may have a first tip facing the second conductive layer. The second charge storage layer may have a second tip toward the second conductor layer.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，第二導體層可環繞(wrap-around)第一尖端與第二尖端。According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the second conductive layer may wrap-around the first tip and the second tip.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，第一電荷儲存層的頂面與第二電荷儲存層的頂面可低於基底的頂面。According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the top surface of the first charge storage layer and the top surface of the second charge storage layer may be lower than the top surface of the substrate.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，第一導體層的頂面可低於第一電荷儲存層的頂面與第二電荷儲存層的頂面。According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the top surface of the first conductive layer may be lower than the top surface of the first charge storage layer and the top surface of the second charge storage layer.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，第二導體層的頂面可高於基底的頂面。According to an embodiment of the present invention, in the above-mentioned non-volatile memory structure, the top surface of the second conductive layer may be higher than the top surface of the substrate.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，更可包括介電層。介電層位在第一導體層與基底之間、第一導體層與第一電荷儲存層之間以及第一導體層與第二電荷儲存層之間。According to an embodiment of the present invention, the non-volatile memory structure may further include a dielectric layer. The dielectric layer is located between the first conductive layer and the substrate, between the first conductive layer and the first charge storage layer, and between the first conductive layer and the second charge storage layer.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，更可包括介電層。介電層位在第二導體層與第一導體層之間、第二導體層與第一電荷儲存層之間、第二導體層與第二電荷儲存層之間以及第二導體層與基底之間。According to an embodiment of the present invention, the non-volatile memory structure may further include a dielectric layer. The dielectric layer is located between the second conductor layer and the first conductor layer, between the second conductor layer and the first charge storage layer, between the second conductor layer and the second charge storage layer, and between the second conductor layer and the substrate between.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，更可包括第一介電層與第二介電層。第一介電層位在第一電荷儲存層與基底之間。第二介電層位在第二電荷儲存層與基底之間。According to an embodiment of the present invention, the non-volatile memory structure may further include a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the first charge storage layer and the substrate. The second dielectric layer is located between the second charge storage layer and the substrate.

依照本發明的一實施例所述，在上述非揮發性記憶體結構中，更可包括第一摻雜區、第二摻雜區與第三摻雜區。第一摻雜區位在溝渠下方的基底中。第二摻雜區位在溝渠的一側的基底中。第三摻雜區位在溝渠的另一側的基底中。According to an embodiment of the present invention, the non-volatile memory structure may further include a first doped region, a second doped region, and a third doped region. The first doped region is located in the substrate under the trench. The second doped region is located in the substrate on one side of the trench. The third doped region is located in the substrate on the other side of the trench.

基於上述，在本發明所提出的非揮發性記憶體結構中，由於第一導體層、第二導體層、第一電荷儲存層與第二電荷儲存層設置在溝渠中，因此可有效地縮小記憶體元件的尺寸並提升元件積集度。此外，由於第一電荷儲存層與第二電荷儲存層設置在溝渠中，且分別位在第一導體層的一側與另一側，因此可實現單一記憶胞中儲存二位元資料(two bits per cell)的記憶體元件，且可提升位元密度(bit density)。Based on the above, in the non-volatile memory structure proposed by the present invention, since the first conductor layer, the second conductor layer, the first charge storage layer and the second charge storage layer are arranged in the trench, the memory can be effectively reduced. The size of the body components and improve the integration of components. In addition, since the first charge storage layer and the second charge storage layer are arranged in the trench and are respectively located on one side and the other side of the first conductor layer, it is possible to store two bits of data in a single memory cell. Per cell) memory devices, and can increase the bit density (bit density).

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

圖1為根據本發明一實施例的非揮發性記憶體結構的剖面圖。FIG. 1 is a cross-sectional view of a non-volatile memory structure according to an embodiment of the invention.

請參照圖1，非揮發性記憶體結構10包括基底100、導體層102、導體層104、電荷儲存層106與電荷儲存層108。非揮發性記憶體結構10例如是快閃記憶體。在基底100中具有溝渠T。基底100可為半導體基底，如矽基底。Please refer to FIG. 1, the non-volatile memory structure 10 includes a substrate 100, a conductive layer 102, a conductive layer 104, a charge storage layer 106 and a charge storage layer 108. The non-volatile memory structure 10 is, for example, a flash memory. There is a trench T in the substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate.

導體層102設置在溝渠T中。導體層102可作為控制閘極。導體層102的頂面S1可低於電荷儲存層106的頂面S2與電荷儲存層108的頂面S3。導體層102的材料例如是摻雜多晶矽等導體材料。The conductor layer 102 is provided in the trench T. The conductor layer 102 can be used as a control gate. The top surface S1 of the conductive layer 102 may be lower than the top surface S2 of the charge storage layer 106 and the top surface S3 of the charge storage layer 108. The material of the conductive layer 102 is, for example, a conductive material such as doped polysilicon.

導體層104設置在溝渠T中，且位在導體層102上。導體層104可作為抹除閘極。導體層104的頂面S4可高於基底100的頂面S5。導體層104的材料例如是摻雜多晶矽等導體材料。The conductive layer 104 is disposed in the trench T and is located on the conductive layer 102. The conductor layer 104 can be used as an erasing gate. The top surface S4 of the conductive layer 104 may be higher than the top surface S5 of the substrate 100. The material of the conductive layer 104 is, for example, a conductive material such as doped polysilicon.

電荷儲存層106與電荷儲存層108設置在溝渠T中，且分別位在導體層102的一側與另一側。電荷儲存層106可具有朝向導體層104的尖端T1。電荷儲存層108可具有朝向導體層104的尖端T2。此外，導體層104可環繞尖端T1與尖端T2，藉此可降低抹除電壓，且可增加抹除速度。電荷儲存層106的頂面S2與電荷儲存層108的頂面S3可低於基底100的頂面S5。在一些實施例中，電荷儲存層106與電荷儲存層108可為浮置閘極。電荷儲存層106與電荷儲存層108的材料例如是摻雜多晶矽、未摻雜多晶矽、氮化矽、氮氧化矽或其組合。The charge storage layer 106 and the charge storage layer 108 are disposed in the trench T, and are located on one side and the other side of the conductive layer 102, respectively. The charge storage layer 106 may have a tip T1 facing the conductor layer 104. The charge storage layer 108 may have a tip T2 facing the conductor layer 104. In addition, the conductive layer 104 can surround the tip T1 and the tip T2, thereby reducing the erasing voltage and increasing the erasing speed. The top surface S2 of the charge storage layer 106 and the top surface S3 of the charge storage layer 108 may be lower than the top surface S5 of the substrate 100. In some embodiments, the charge storage layer 106 and the charge storage layer 108 may be floating gates. The materials of the charge storage layer 106 and the charge storage layer 108 are, for example, doped polysilicon, undoped polysilicon, silicon nitride, silicon oxynitride, or a combination thereof.

此外，導體層102、導體層104、電荷儲存層106、電荷儲存層108與基底100彼此隔離。舉例來說，非揮發性記憶體結構10更可包括介電層110、介電層112、介電層114與介電層116中的至少一者，以使得導體層102、導體層104、電荷儲存層106、電荷儲存層108與基底100彼此隔離。In addition, the conductor layer 102, the conductor layer 104, the charge storage layer 106, the charge storage layer 108 and the substrate 100 are isolated from each other. For example, the non-volatile memory structure 10 may further include at least one of the dielectric layer 110, the dielectric layer 112, the dielectric layer 114, and the dielectric layer 116, so that the conductive layer 102, the conductive layer 104, and the electric charge The storage layer 106, the charge storage layer 108, and the substrate 100 are isolated from each other.

介電層110位在導體層102與基底100之間、導體層102與電荷儲存層106之間以及導體層102與電荷儲存層108之間，藉此導體層102可與基底100、電荷儲存層106以及電荷儲存層108進行隔離。介電層110可為單層結構或多層結構。介電層110的材料例如是氧化矽、氮化矽或其組合。舉例來說，介電層110可為氧化矽層/氮化矽層/氧化矽層(ONO)的複合層。The dielectric layer 110 is located between the conductor layer 102 and the substrate 100, between the conductor layer 102 and the charge storage layer 106, and between the conductor layer 102 and the charge storage layer 108, so that the conductor layer 102 can be connected to the substrate 100 and the charge storage layer. 106 and the charge storage layer 108 are isolated. The dielectric layer 110 may be a single-layer structure or a multi-layer structure. The material of the dielectric layer 110 is, for example, silicon oxide, silicon nitride, or a combination thereof. For example, the dielectric layer 110 may be a composite layer of silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO).

介電層112位在導體層104與導體層102之間、導體層104與電荷儲存層106之間、導體層104與電荷儲存層108之間以及導體層104與基底100之間，藉此導體層104可與導體層102、電荷儲存層106、電荷儲存層108以及基底100進行隔離。介電層112的材料例如是氧化矽等介電材料。The dielectric layer 112 is located between the conductor layer 104 and the conductor layer 102, between the conductor layer 104 and the charge storage layer 106, between the conductor layer 104 and the charge storage layer 108, and between the conductor layer 104 and the substrate 100, whereby the conductor The layer 104 can be isolated from the conductor layer 102, the charge storage layer 106, the charge storage layer 108, and the substrate 100. The material of the dielectric layer 112 is, for example, a dielectric material such as silicon oxide.

介電層114位在電荷儲存層106與基底100之間，藉此電荷儲存層106可與基底100進行隔離。介電層114的材料例如是氧化矽等介電材料。The dielectric layer 114 is located between the charge storage layer 106 and the substrate 100, so that the charge storage layer 106 can be isolated from the substrate 100. The material of the dielectric layer 114 is, for example, a dielectric material such as silicon oxide.

介電層116位在電荷儲存層108與基底100之間，藉此電荷儲存層108可與基底100進行隔離。介電層116的材料例如是氧化矽等介電材料。The dielectric layer 116 is located between the charge storage layer 108 and the substrate 100, so that the charge storage layer 108 can be isolated from the substrate 100. The material of the dielectric layer 116 is, for example, a dielectric material such as silicon oxide.

此外，非揮發性記憶體結構10中更可包括摻雜區118、摻雜區120與摻雜區122中的至少一者。摻雜區118位在溝渠T下方的基底100中。摻雜區118可作為源極。在本實施例中，摻雜區118可為埋入式源極線(buried source line)。摻雜區120位在溝渠T的一側的基底100中。摻雜區120可作為汲極。摻雜區122位在溝渠T的另一側的基底100中。摻雜區122可作為汲極。摻雜區118、摻雜區120與摻雜區122可具有相同的導電型，如同為N型或同為P型。在本實施例中，摻雜區118、摻雜區120與摻雜區122是以同為N型為例，但本發明並不以此為限。In addition, the non-volatile memory structure 10 may further include at least one of the doped region 118, the doped region 120, and the doped region 122. The doped region 118 is located in the substrate 100 under the trench T. The doped region 118 can serve as a source. In this embodiment, the doped region 118 may be a buried source line. The doped region 120 is located in the substrate 100 on one side of the trench T. The doped region 120 can be used as a drain. The doped region 122 is located in the substrate 100 on the other side of the trench T. The doped region 122 can be used as a drain. The doped region 118, the doped region 120, and the doped region 122 may have the same conductivity type, as if they were N-type or both were P-type. In this embodiment, the doped region 118, the doped region 120, and the doped region 122 are all N-type as an example, but the invention is not limited to this.

基於上述實施例可知，在非揮發性記憶體結構10中，由於導體層102、導體層104、電荷儲存層106與電荷儲存層108設置在溝渠T中，因此可有效地縮小記憶體元件的尺寸並提升元件積集度。此外，由於電荷儲存層106與電荷儲存層108設置在溝渠T中，且分別位在導體層102的一側與另一側，因此可實現單一記憶胞中儲存二位元資料的記憶體元件，且可提升位元密度。Based on the above embodiment, it can be seen that in the non-volatile memory structure 10, since the conductor layer 102, the conductor layer 104, the charge storage layer 106 and the charge storage layer 108 are disposed in the trench T, the size of the memory device can be effectively reduced. And improve the integration of components. In addition, since the charge storage layer 106 and the charge storage layer 108 are disposed in the trench T and are respectively located on one side and the other side of the conductor layer 102, a memory device that stores two-bit data in a single memory cell can be realized. And can increase the bit density.

綜上所述，由於上述實施例的非揮發性記憶體結構為溝渠式記憶體結構，因此可有效地縮小記憶體元件的尺寸並提升元件積集度與位元密度。In summary, since the non-volatile memory structure of the above embodiment is a trench memory structure, the size of the memory device can be effectively reduced and the device integration and bit density can be improved.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10:非揮發性記憶體結構10: Non-volatile memory structure

100:基底100: base

102,104:導體層102, 104: Conductor layer

106,108:電荷儲存層106, 108: charge storage layer

110,112,114,116:介電層110, 112, 114, 116: Dielectric layer

118,120,122:摻雜區118, 120, 122: doped area

S1,S2,S3,S4,S5:頂面S1, S2, S3, S4, S5: top surface

T:溝渠T: Ditch

T1,T2:尖端T1, T2: Tip

圖1為根據本發明一實施例的非揮發性記憶體結構的剖面圖。FIG. 1 is a cross-sectional view of a non-volatile memory structure according to an embodiment of the invention.

10:非揮發性記憶體結構 10: Non-volatile memory structure

100:基底 100: base

102,104:導體層 102, 104: Conductor layer

106,108:電荷儲存層 106, 108: charge storage layer

110,112,114,116:介電層 110, 112, 114, 116: Dielectric layer

118,120,122:摻雜區 118, 120, 122: doped area

S1,S2,S3,S4,S5:頂面 S1, S2, S3, S4, S5: top surface

T:溝渠 T: Ditch

T1,T2:尖端 T1, T2: Tip

Claims (9)

一種非揮發性記憶體結構，包括：基底，其中在所述基底中具有溝渠；第一導體層，設置在所述溝渠中；第二導體層，設置在所述溝渠中，且位在所述第一導體層上；以及第一電荷儲存層與第二電荷儲存層，設置在所述溝渠中，且分別位在所述第一導體層的一側與另一側，其中所述第一電荷儲存層具有朝向所述第二導體層的第一尖端，且所述第二電荷儲存層具有朝向所述第二導體層的第二尖端，其中所述第一尖端的角度與所述第二尖端的角度皆小於90度角，其中所述第一導體層、所述第二導體層、所述第一電荷儲存層、所述第二電荷儲存層與所述基底彼此隔離。 A non-volatile memory structure includes: a substrate, wherein a trench is provided in the substrate; a first conductive layer is provided in the trench; a second conductive layer is provided in the trench and is located in the trench On the first conductor layer; and a first charge storage layer and a second charge storage layer are disposed in the trench and are respectively located on one side and the other side of the first conductor layer, wherein the first charge The storage layer has a first tip toward the second conductor layer, and the second charge storage layer has a second tip toward the second conductor layer, wherein the angle of the first tip is greater than that of the second tip The angles of are all less than 90 degrees, wherein the first conductor layer, the second conductor layer, the first charge storage layer, the second charge storage layer and the substrate are isolated from each other. 如請求項1所述的非揮發性記憶體結構，其中所述第二導體層環繞所述第一尖端與所述第二尖端。 The non-volatile memory structure according to claim 1, wherein the second conductive layer surrounds the first tip and the second tip. 如請求項1所述的非揮發性記憶體結構，其中所述第一電荷儲存層的頂面與所述第二電荷儲存層的頂面低於所述基底的頂面。 The non-volatile memory structure according to claim 1, wherein the top surface of the first charge storage layer and the top surface of the second charge storage layer are lower than the top surface of the substrate. 如請求項1所述的非揮發性記憶體結構，其中所述第一導體層的頂面低於所述第一電荷儲存層的頂面與所述第二電荷儲存層的頂面。 The non-volatile memory structure according to claim 1, wherein the top surface of the first conductor layer is lower than the top surface of the first charge storage layer and the top surface of the second charge storage layer. 如請求項1所述的非揮發性記憶體結構，其中所述第二導體層的頂面高於所述基底的頂面。 The non-volatile memory structure according to claim 1, wherein the top surface of the second conductive layer is higher than the top surface of the substrate. 如請求項1所述的非揮發性記憶體結構，更包括：介電層，位在所述第一導體層與所述基底之間、所述第一導體層與所述第一電荷儲存層之間以及所述第一導體層與所述第二電荷儲存層之間。 The non-volatile memory structure according to claim 1, further comprising: a dielectric layer located between the first conductor layer and the substrate, the first conductor layer and the first charge storage layer And between the first conductor layer and the second charge storage layer. 如請求項1所述的非揮發性記憶體結構，更包括：介電層，位在所述第二導體層與所述第一導體層之間、所述第二導體層與所述第一電荷儲存層之間、所述第二導體層與所述第二電荷儲存層之間以及所述第二導體層與所述基底之間。 The non-volatile memory structure according to claim 1, further comprising: a dielectric layer located between the second conductor layer and the first conductor layer, and the second conductor layer and the first conductor layer Between charge storage layers, between the second conductor layer and the second charge storage layer, and between the second conductor layer and the substrate. 如請求項1所述的非揮發性記憶體結構，更包括：第一介電層，位在所述第一電荷儲存層與所述基底之間；以及第二介電層，位在所述第二電荷儲存層與所述基底之間。 The non-volatile memory structure according to claim 1, further comprising: a first dielectric layer located between the first charge storage layer and the substrate; and a second dielectric layer located on the Between the second charge storage layer and the substrate. 如請求項1所述的非揮發性記憶體結構，更包括：第一摻雜區，位在所述溝渠下方的所述基底中；第二摻雜區，位在所述溝渠的一側的所述基底中；以及第三摻雜區，位在所述溝渠的另一側的所述基底中。 The non-volatile memory structure according to claim 1, further comprising: a first doped region located in the substrate below the trench; a second doped region located on one side of the trench In the substrate; and a third doped region located in the substrate on the other side of the trench.
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