儘管討論了具體的配置和佈置，但是應該理解的是，這僅僅是為了說明的目的而進行的。相關領域的技術人員將認識到，在不脫離本發明內容的精神和範圍的情況下，可以使用其它配置和佈置。對於相關領域的技術人員將顯而易見的是，本發明內容還可以用在各種其它應用中。
Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present invention. It will be obvious to those skilled in the related art that the content of the present invention can also be used in various other applications.
應注意的是，在說明書中對“一個實施例”、“實施例”、“示例性實施例”、“一些實施例”等的引用指示所描述的實施例可以包括特定的特徵、結構或特性，但是各個實施例可能不一定包括該特定的特徵、結構或特性。此外，這樣的短語不一定指代相同的實施例。此外，當結合實施例描述特定特徵、結構或特性時，無論是否明確地描述，結合其它實施例來實施這樣的特徵、結構或特性都在相關領域的技術人員的知識範圍內。
It should be noted that references to "one embodiment", "embodiments", "exemplary embodiments", "some embodiments", etc. in the specification indicate that the described embodiments may include specific features, structures, or characteristics However, each embodiment may not necessarily include the specific feature, structure or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether it is explicitly described or not, it is within the knowledge of those skilled in the relevant art to implement such a feature, structure, or characteristic in combination with other embodiments.
通常，可以至少部分地從上下文中的用法理解術語。例如，至少部分地取決於上下文，如本文所使用的術語“一個或多個”可以用於以單數意義描述任何特徵、結構或特性，或者可以用於以複數意義描述特徵、結構或特性的組合。類似地，至少部分地取決於上下文，例如“一(a)”、“一個(an)”或“該(the)”之類的術語同樣可以被理解為傳達單數用法或者傳達複數用法。另外，術語“基於”可以被理解為不一定旨在傳達排他性的因素集合，而是可以允許存在不一定明確地描述的額外因素，這同樣至少部分地取決於上下文。
Generally, terms can be understood at least partially from the usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular, or can be used to describe a feature, structure, or combination of characteristics in the plural. . Similarly, depending at least in part on the context, terms such as "a", "an" or "the" can also be understood to convey singular usage or convey plural usage. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.
應當容易理解的是，本發明內容中的“在......上”、“在......上方”和“在......之上”的含義應當以最寬泛的方式來解釋，使得“在......上”不僅意味著
“直接在某物上”，而且包括“在某物上”且在其之間具有中間特徵或層的含義，並且“在......上方”或“在......之上”不僅意味著“在某物上方”或“在某物之上”的含義，而且可以包括“在某物上方”或“在某物之上”且在其之間沒有中間特徵或層的含義(即，直接在某物上)。
It should be easily understood that the meaning of "on", "above" and "above" in the content of the present invention should be broadest To explain in such a way that “on” not only means
"Directly on something", and includes "on something" with the meaning of intermediate features or layers in between, and "on" or "on" "上" not only means "above something" or "above something", but can also include "above something" or "above something" without intervening features or layers in between. Meaning (ie, directly on something).
此外，為了便於描述，可以在本文中使用例如“在......之下”、“在......下方”、“下部”、“在......之上”、“上部”等的空間相對術語來描述如圖所示的一個元件或特徵與另一個元件或特徵的關係。除了在附圖中所描繪的取向之外，空間相對術語旨在涵蓋設備在使用或操作步驟中的不同取向。裝置可以以其它方式定向(旋轉90度或處於其它取向)並且同樣可以相應地解釋本文使用的空間相對描述詞。
In addition, for the convenience of description, for example, "below", "below", "lower", "above" can be used in this text. Spatial relative terms such as "upper" and "upper" describe the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device during use or operation steps. The device can be oriented in other ways (rotated by 90 degrees or in other orientations) and the spatial relative descriptors used herein can also be interpreted accordingly.
如本文所使用的，術語“基底”是指在其上添加後續材料層的材料。
基底本身可以被圖案化。被添加在基底頂部的材料可以被圖案化或者可以保持未被圖案化。此外，基底可以包括多種半導體材料，例如矽、鍺、砷化鎵、磷化銦等。替代地，基底可以由非導電材料製成，例如玻璃、塑膠或藍寶石晶圓。
As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added.
The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
如本文所使用的，術語“層”是指包括具有厚度的區域的材料部分。
層可以在整個下層或上覆結構之上延伸，或者可以具有小於下層或上覆結構的範圍。此外，層可以是均勻或不均勻連續結構的區域，其具有小於該連續結構的厚度。例如，層可以位於連續結構的頂表面和底表面之間或在頂表面和底表面處的任何一對水平平面之間。層可以水平地、垂直地和/或沿著錐形表面延伸。
基底可以是層，其中可以包括一個或多個層，和/或可以在其上、在其上方和/或其下方具有一個或多個層。層可以包括多個層。例如，互連層可以包括一個或
多個導體和接觸層(其中形成有互連線和/或垂直互連通道(via)接觸)以及一個或多個介電層。
As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness.
The layer may extend over the entire lower layer or the overlying structure, or may have a smaller range than the lower layer or the overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure, which has a thickness smaller than the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and/or along a tapered surface.
The substrate may be a layer, which may include one or more layers, and/or may have one or more layers on, above, and/or below it. The layer may include multiple layers. For example, the interconnection layer may include one or
A plurality of conductors and contact layers (in which interconnect lines and/or vertical interconnect via contacts are formed) and one or more dielectric layers.
如本文所使用的，術語“標稱/標稱地(nominal)”是指在產品或製程的設計階段期間針對元件或製程操作步驟設定的特性或參數的期望值或目標值、以及高於和/或低於期望值的值範圍。值範圍可以是由於製造製程或公差的輕微變化而引起的。如本文所使用的，術語“大約”指示可以基於與主題半導體元件相關聯的特定技術節點而變化的給定量的值。基於特定的技術節點，術語“大約”可以指示給定量的值，該給定量在該值的例如10-30%內變化(例如，值的±10%、±20%或±30%)。
As used herein, the term "nominal" refers to the expected value or target value of a characteristic or parameter set during the design phase of a product or process for a component or process operation step, as well as higher than and/ Or a range of values lower than expected. The value range can be caused by slight changes in manufacturing processes or tolerances. As used herein, the term "about" indicates a given amount of value that can vary based on the specific technology node associated with the subject semiconductor element. Based on a particular technical node, the term "about" may indicate a value of a given amount that varies within, for example, 10-30% of the value (for example, ±10%, ±20%, or ±30% of the value).
如本文所使用的，術語“立體記憶體元件”是指在橫向取向的基底上具有垂直取向的儲存單元電晶體串(在本文中被稱為“記憶體串”，例如NAND記憶體串)的半導體元件，使得記憶體串相對於基底在垂直方向上延伸。如本文所使用的，術語“垂直/垂直地”意味著標稱地垂直於基底的橫向表面。
As used herein, the term "three-dimensional memory device" refers to a string of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) that have vertical orientation on a laterally oriented substrate. The semiconductor device makes the memory string extend in the vertical direction relative to the substrate. As used herein, the term "vertical/perpendicularly" means nominally perpendicular to the lateral surface of the substrate.
一些立體記憶體元件(例如，3D NAND記憶體元件)中，縫隙結構(例如，閘極線縫隙(GLS))用於提供從元件的正面到記憶體陣列的源極(例如，陣列公共源極(ACS))的電性連接。然而，正面源極接觸可能透過在字元線和源極接觸之間引入漏電流和寄生電容，而影響立體記憶體元件的電性能，即使在它們之間存在間隙壁的情況下。間隙壁的形成也使製造製程複雜化。除了影響電性能，縫隙結構通常還包括壁狀多晶矽和/或金屬填充物，其可能引入局部應力而造成晶圓彎曲或翹曲，進而降低生產成品率。
In some three-dimensional memory devices (for example, 3D NAND memory devices), the gap structure (for example, gate line gap (GLS)) is used to provide the source of the memory array from the front of the device (for example, the common source of the array). (ACS)) electrical connection. However, the front source contact may affect the electrical performance of the three-dimensional memory device by introducing leakage current and parasitic capacitance between the word line and the source contact, even when there are gaps between them. The formation of the spacer also complicates the manufacturing process. In addition to affecting electrical performance, the gap structure usually includes wall-shaped polysilicon and/or metal fillers, which may introduce local stress and cause wafer bending or warping, thereby reducing production yield.
此外，在一些3D NAND記憶體元件中，選擇性地生長半導體插塞以圍繞通道結構的側壁，例如，被稱為側壁選擇性磊晶生長(SEG)。與在通道結構的下端處形成的另一類型的半導體插塞(例如，底部SEG)相比，側壁SEG的形成，避免了對通道孔的底表面處的儲存膜以及半導體通道的蝕刻(也被稱為“SONO”穿通)，進而增加製程視窗(window)，尤其是當用先進技術(例如，具有96個或更多個具有多堆疊架構的層級)製造3D NAND記憶體元件時。側壁SEG通常透過利用側壁SEG替換在基底和堆疊結構之間的犧牲層來形成，這涉及透過縫隙開口的多次沉積和蝕刻製程。然而，隨著3D NAND記憶體元件的層級持續增加，延伸穿過堆疊結構的縫隙開口的高寬比變得更大，使得由於增加的成本以及減小的成品率，穿過縫隙開口的沉積以及蝕刻製程對於使用已知方法形成側壁SEG更具挑戰性，並且是有待改進的。
In addition, in some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of the channel structure, for example, it is called sidewall selective epitaxial growth (SEG). Compared with another type of semiconductor plug (eg, bottom SEG) formed at the lower end of the channel structure, the formation of the sidewall SEG avoids the etching of the storage film at the bottom surface of the channel hole and the semiconductor channel (also Known as "SONO" pass-through), and thus increase the process window (window), especially when using advanced technology (for example, with 96 or more layers with a multi-stack architecture) to manufacture 3D NAND memory devices. The sidewall SEG is usually formed by replacing the sacrificial layer between the substrate and the stacked structure with the sidewall SEG, which involves multiple deposition and etching processes through the slit opening. However, as the level of 3D NAND memory devices continues to increase, the aspect ratio of the slit openings extending through the stacked structure becomes larger, so that due to increased cost and reduced yield, the deposition through the slit openings and The etching process is more challenging for forming the sidewall SEG using known methods, and needs to be improved.
此外，側壁SEG結構可以與背面製程結合，以從基底的背面形成源極接觸，進而避免在正面源極接觸和字元線之間的漏電流和寄生電容，並且增加有效元件面積。然而，由於背面製程需要減薄基底，在減薄製程中，難以在晶圓級別控制厚度均勻性，進而限制了具有側壁SEG結構和背面製程的3D NAND記憶體元件的生產成品率。
In addition, the sidewall SEG structure can be combined with the backside process to form source contacts from the backside of the substrate, thereby avoiding leakage current and parasitic capacitance between the front source contacts and the word lines, and increasing the effective device area. However, since the backside process requires thinning of the substrate, it is difficult to control the thickness uniformity at the wafer level during the thinning process, which limits the production yield of 3D NAND memory devices with sidewall SEG structures and backside processes.
根據本發明內容的各個實施例，提供了具有背面源極接觸的立體記憶體元件。透過將源極接觸從正面移到背面，由於可以增加有效儲存單元陣列面積，所以可以降低各個儲存單元的成本，並且可以省略間隙壁形成製程。例如，透過避免在字元線和源極接觸之間的漏電流和寄生電容，以及透過減小由正面縫隙結構(作為源極接觸)引起的局部應力，也可以改善元件性能。側壁SEG(例如，半導體插塞)可以從基底的背面形成，所以不需要進行穿過延伸在
基底的正面處的堆疊結構的開口的任何沉積或蝕刻製程。因此，可以降低製造製程的複雜性和成本，並且提高生產成品率。此外，由於側壁SEG的製造製程不再受穿過堆疊結構的開口的高寬比的影響，即，不受儲存堆疊層的層級的限制，因此立體記憶體元件的可縮放性也可以得到改善。
According to various embodiments of the present invention, a three-dimensional memory device with backside source contacts is provided. By moving the source contact from the front to the back, since the effective memory cell array area can be increased, the cost of each memory cell can be reduced, and the spacer formation process can be omitted. For example, by avoiding the leakage current and parasitic capacitance between the word line and the source contact, and by reducing the local stress caused by the front slit structure (as the source contact), the device performance can also be improved. The sidewall SEG (for example, semiconductor plug) can be formed from the backside of the substrate, so there is no need to extend through
Any deposition or etching process of the openings of the stacked structure at the front surface of the substrate. Therefore, the complexity and cost of the manufacturing process can be reduced, and the production yield can be improved. In addition, since the manufacturing process of the sidewall SEG is no longer affected by the aspect ratio of the opening through the stack structure, that is, it is not limited by the level of the storage stack layer, the scalability of the three-dimensional memory device can also be improved.
在形成側壁SEG之前，可以從背面去除在其上形成儲存堆疊層的基底，以曝露通道結構。因此，對基底的選擇可以擴展到例如虛設晶圓，以降低成本。在本發明的其中一些實施例中，使用一個或多個停止層來自動地停止背面減薄製程，使得可以完全去除基底以避免晶圓厚度均勻性控制問題，並且降低背面製程的製造複雜性。在本發明的其中一些實施例中，使用相同的停止層或另一停止層來自動地停止通道孔蝕刻，這可以更好地控制在不同通道結構之間的開槽變化，並且進一步增加背面製程視窗。
Before forming the sidewall SEG, the substrate on which the storage stack layer is formed may be removed from the back surface to expose the channel structure. Therefore, the choice of substrates can be extended to, for example, dummy wafers to reduce costs. In some embodiments of the present invention, one or more stop layers are used to automatically stop the backside thinning process, so that the substrate can be completely removed to avoid wafer thickness uniformity control problems and reduce the manufacturing complexity of the backside process. In some of the embodiments of the present invention, the same stop layer or another stop layer is used to automatically stop the channel hole etching, which can better control the groove change between different channel structures and further increase the backside process Windows.
在去除基底之後，可以從背面形成導電層，以將多個通道結構的源極電性連接，進而增加通道結構的陣列公共源極(ACS)的導電性。在本發明的其中一些實施例中，導電層包括與通道結構的半導體通道接觸，以減小接觸電阻的金屬矽化物層，並且還包括與金屬矽化物層接觸以進一步減小總電阻的金屬層。結果，可以減小作為ACS的一部分的半導體層(N型摻雜或P型摻雜)的厚度，而不影響ACS導電性。
After the substrate is removed, a conductive layer can be formed from the back side to electrically connect the sources of the multiple channel structures, thereby increasing the conductivity of the array common source (ACS) of the channel structure. In some embodiments of the present invention, the conductive layer includes a metal silicide layer in contact with the semiconductor channel of the channel structure to reduce the contact resistance, and further includes a metal layer in contact with the metal silicide layer to further reduce the total resistance . As a result, the thickness of the semiconductor layer (N-type doping or P-type doping) that is a part of the ACS can be reduced without affecting the ACS conductivity.
在本發明內容中，公開了各種立體記憶體元件架構以及其製造方法(例如，具有不同的擦除操作步驟機制)，以適應不同的要求和應用。在本發明的其中一些實施例中，側壁SEG是N型摻雜半導體層的一部分，以使得能夠由立體記憶體元件進行閘極致汲極洩漏(GIDL)擦除。在本發明的其中一些實施例
中，側壁SEG是P型摻雜半導體層的一部分，以使得能夠由立體記憶體元件進行P阱體擦除。
In the content of the present invention, various three-dimensional memory device architectures and their manufacturing methods (for example, having different erasing operation step mechanisms) are disclosed to meet different requirements and applications. In some of the embodiments of the present invention, the sidewall SEG is a part of the N-type doped semiconductor layer, so that gate-drain leakage (GIDL) erasure can be performed by the three-dimensional memory device. In some of the embodiments of the present invention
Among them, the sidewall SEG is a part of the P-type doped semiconductor layer, so that the P-well body can be erased by the three-dimensional memory device.
圖1A示出了根據本發明內容的一些實施例的示例性立體記憶體元件100的橫截面的側視圖。在本發明的其中一些實施例中，立體記憶體元件100是鍵合晶片，其包括第一半導體結構102以及堆疊在第一半導體結構102之上的第二半導體結構104。根據一些實施例，第一半導體結構102和第二半導體結構104在其之間的鍵合介面106處接合。如圖1A所示，第一半導體結構102可以包括基底101，其可以包括矽(例如，單晶矽(c-Si))、矽鍺(SiGe)、砷化鎵(GaAs)、鍺(Ge)、SOI或任何其它合適的材料。
FIG. 1A shows a cross-sectional side view of an exemplary three-dimensional memory element 100 according to some embodiments of the present disclosure. In some embodiments of the present invention, the three-dimensional memory device 100 is a bonded wafer, which includes a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are joined at a bonding interface 106 therebetween. As shown in FIG. 1A, the first semiconductor structure 102 may include a substrate 101, which may include silicon (for example, single crystal silicon (c-Si)), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge) , SOI or any other suitable material.
立體記憶體元件100的第一半導體結構102可以包括在基底101上的週邊電路108。注意的是，將x和y軸包括在圖1A中以進一步示出具有基底101的立體記憶體元件100中的部件的空間關係。基底101包括在x方向(即，橫向方向)上橫向地延伸的兩個橫向表面(例如，頂表面和底表面)。如本文所使用的，在y方向(即垂直方向)上相對於半導體元件(例如，立體記憶體元件100)的基底(例如，基底101)確定一個部件(例如，層或元件)是在半導體元件的另一部件(例如，層或元件)“上”、“上方”還是“下方”(當該基底在y方向上位於半導體元件的最低平面中時)。在整個本發明內容中應用了用於描述空間關係的相同概念。
The first semiconductor structure 102 of the three-dimensional memory device 100 may include a peripheral circuit 108 on the substrate 101. It is noted that the x and y axes are included in FIG. 1A to further illustrate the spatial relationship of the components in the three-dimensional memory device 100 with the substrate 101. The substrate 101 includes two lateral surfaces (for example, a top surface and a bottom surface) that extend laterally in the x direction (ie, the lateral direction). As used herein, relative to the substrate (for example, substrate 101) of the semiconductor element (for example, three-dimensional memory element 100) in the y direction (ie, the vertical direction), it is determined that a component (for example, layer or element) is in the semiconductor element Another component (for example, a layer or element) is "above", "above" or "below" (when the substrate is located in the lowest plane of the semiconductor element in the y direction). The same concepts used to describe spatial relationships are applied throughout the content of the present invention.
在本發明的其中一些實施例中，週邊電路108被配置為控制和感測立體記憶體元件100。週邊電路108可以是用於促進立體記憶體元件100的操作步驟的任何合適的數位、類比和/或混合信號控制和感測電路，包括但不限於頁緩衝
器、解碼器(例如，行解碼器和列解碼器)、感測放大器、驅動器(例如，字元線驅動器)、電荷泵、電流或電壓參考、或者該電路的任何主動或被動部件(例如，電晶體、二極體、電阻器或電容器)。週邊電路108可以包括形成於基底101“上”的電晶體，其中電晶體的全部或部分形成於基底101中(例如，在基底101的頂表面下方)和/或直接形成於基底101上。隔離區(例如，淺溝槽隔離(STI))和摻雜區(例如，電晶體的源極區和汲極區)也可以形成在基底101中。根據一些實施例，電晶體是高速的且具有先進邏輯製程(例如，90奈米、65奈米、45奈米、32奈米、28奈米、20奈米、16奈米、14奈米、10奈米、7奈米、5奈米、3奈米、2奈米等的技術)。應理解，在本發明的其中一些實施例中，週邊電路108還可以包括與先進邏輯製程相容的任何其它電路，包括邏輯電路(例如，處理器和可程式設計邏輯元件(PLD))或記憶體電路(例如，靜態隨機存取記憶體(SRAM)和動態RAM(DRAM))。
In some embodiments of the present invention, the peripheral circuit 108 is configured to control and sense the three-dimensional memory device 100. The peripheral circuit 108 may be any suitable digital, analog, and/or mixed-signal control and sensing circuit for facilitating the operation steps of the three-dimensional memory device 100, including but not limited to page buffering
Converters, decoders (for example, row decoders and column decoders), sense amplifiers, drivers (for example, word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (for example, Transistor, diode, resistor or capacitor). The peripheral circuit 108 may include a transistor formed "on" the substrate 101, wherein all or part of the transistor is formed in the substrate 101 (for example, below the top surface of the substrate 101) and/or directly formed on the substrate 101. Isolation regions (for example, shallow trench isolation (STI)) and doped regions (for example, the source and drain regions of the transistor) may also be formed in the substrate 101. According to some embodiments, the transistor is high-speed and has an advanced logic process (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10 nanometers, 7 nanometers, 5 nanometers, 3 nanometers, 2 nanometers, etc.). It should be understood that in some embodiments of the present invention, the peripheral circuit 108 may also include any other circuits compatible with advanced logic processes, including logic circuits (for example, processors and programmable logic devices (PLD)) or memory Body circuits (for example, static random access memory (SRAM) and dynamic RAM (DRAM)).
在本發明的其中一些實施例中，立體記憶體元件100的第一半導體結構102還包括在週邊電路108上方的互連層(未示出)，以向週邊電路108傳送電信號以及從週邊電路108傳送電信號。互連層可以包括多個互連(本文中也被稱為“接觸”)，其包括橫向互連線和垂直互連通道(VIA)接觸。如本文所使用的，術語“互連”可以廣義地包括任何適當類型的互連，例如中段制程(MEOL)互連和後段制程(BEOL)互連。互連層還可以包括互連線和VIA接觸可以形成在其中的一個或多個層間介電(ILD)層(也被稱為“金屬間介電(IMD)層”)。也就是說，互連層可以包括在多個層間介電層中的互連線和VIA接觸。互連層中的互連線和VIA接觸可以包括導電材料，導電材料包括但不限於鎢(W)、鈷(Co)、銅(Cu)、鋁(Al)、矽化物或其任何組合。互連層中的層間介電層可以包括介電材料，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低介電常數(低k)
介電或其任何組合。
In some embodiments of the present invention, the first semiconductor structure 102 of the three-dimensional memory device 100 further includes an interconnection layer (not shown) above the peripheral circuit 108 to transmit electrical signals to and from the peripheral circuit 108 108 transmits electrical signals. The interconnection layer may include a plurality of interconnections (also referred to herein as "contacts") including lateral interconnection lines and vertical interconnection via (VIA) contacts. As used herein, the term "interconnect" can broadly include any suitable type of interconnection, such as mid-end of line (MEOL) interconnection and back-end of line (BEOL) interconnection. The interconnection layer may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") in which interconnection lines and VIA contacts may be formed. That is, the interconnection layer may include interconnection lines and VIA contacts in a plurality of interlayer dielectric layers. The interconnection lines and VIA contacts in the interconnection layer may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The interlayer dielectric layer in the interconnection layer may include a dielectric material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant (low-k)
Dielectric or any combination thereof.
如圖1A所示，立體記憶體元件100的第一半導體結構102還可以包括在鍵合介面106處並且在互連層和週邊電路108上方的鍵合層110。鍵合層110可以包括多個鍵合接觸111以及將鍵合接觸111電性隔離的介電。鍵合接觸111可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、矽化物或其任何組合。
鍵合層110的其餘區域可以利用介電材料來形成，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電或其任何組合。鍵合層110中的鍵合接觸111和周圍介電可以用於混合鍵合。
As shown in FIG. 1A, the first semiconductor structure 102 of the three-dimensional memory device 100 may also include a bonding layer 110 at the bonding interface 106 and above the interconnection layer and the peripheral circuit 108. The bonding layer 110 may include a plurality of bonding contacts 111 and a dielectric that electrically isolates the bonding contacts 111. The bonding contact 111 may include a conductive material, and the conductive material includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof.
The remaining area of the bonding layer 110 can be formed using a dielectric material. The dielectric material includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric or any combination thereof. The bonding contact 111 and the surrounding dielectric in the bonding layer 110 may be used for hybrid bonding.
類似地，如圖1A所示，立體記憶體元件100的第二半導體結構104也可以包括在鍵合介面106處並且在第一半導體結構102的鍵合層110上方的鍵合層112。鍵合層112可以包括多個鍵合接觸113以及將鍵合接觸113電性隔離的介電層。鍵合接觸113可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、矽化物或其任何組合。鍵合層112的剩餘區域可以利用介電來形成，介電包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電或其任何組合。鍵合層112中的鍵合接觸113和周圍介電可以用於混合鍵合。根據一些實施例，鍵合接觸113是在鍵合介面106處與鍵合接觸111接觸的。
Similarly, as shown in FIG. 1A, the second semiconductor structure 104 of the three-dimensional memory device 100 may also include a bonding layer 112 at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 may include a plurality of bonding contacts 113 and a dielectric layer that electrically isolates the bonding contacts 113. The bonding contact 113 may include a conductive material, and the conductive material includes, but is not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 112 can be formed by using a dielectric, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contact 113 and the surrounding dielectric in the bonding layer 112 can be used for hybrid bonding. According to some embodiments, the bonding contact 113 is in contact with the bonding contact 111 at the bonding interface 106.
如以下詳細描述的，第二半導體結構104可以在鍵合介面106處以面對面的方式被鍵合在第一半導體結構102的頂部上。在本發明的其中一些實施例中，作為混合鍵合(也被稱為“金屬/介電混合鍵合”)的結構，鍵合介面106被設置在鍵合層110和鍵合層112之間，混合鍵合是一種直接鍵合技術(例如，在表面之間形成鍵合而不使用例如焊料或黏合劑之類的中間層)，並且可以同時獲得
金屬-金屬鍵合和介電-介電鍵合。在本發明的其中一些實施例中，鍵合介面106是鍵合層112和鍵合層110相遇並且鍵合的位置。實際上，鍵合介面106可以是具有特定厚度的層，其包括第一半導體結構102的鍵合層110的頂表面和第二半導體結構104的鍵合層112的底表面。
As described in detail below, the second semiconductor structure 104 may be bonded on top of the first semiconductor structure 102 at the bonding interface 106 in a face-to-face manner. In some of the embodiments of the present invention, as a hybrid bonding (also called "metal/dielectric hybrid bonding") structure, the bonding interface 106 is disposed between the bonding layer 110 and the bonding layer 112 , Hybrid bonding is a direct bonding technique (for example, forming a bond between surfaces without using an intermediate layer such as solder or adhesive), and can be obtained at the same time
Metal-metal bonding and dielectric-dielectric bonding. In some embodiments of the present invention, the bonding interface 106 is a position where the bonding layer 112 and the bonding layer 110 meet and bond. In fact, the bonding interface 106 may be a layer with a specific thickness, which includes the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.
在本發明的其中一些實施例中，立體記憶體元件100的第二半導體結構104還包括在鍵合層112上方的互連層(未示出)以傳送電信號。互連層可以包括多個互連，例如中段(MEOL)互連和後段(BEOL)互連。互連層還可以包括互連線和VIA接觸可以形成在其中的一個或多個層間介電層。互連層中的互連線和VIA接觸可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、矽化物或其任何組合。互連層中的層間介電層可以包括介電材料，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電或其任何組合。
In some embodiments of the present invention, the second semiconductor structure 104 of the three-dimensional memory device 100 further includes an interconnection layer (not shown) above the bonding layer 112 to transmit electrical signals. The interconnection layer may include a plurality of interconnections, such as a middle-level (MEOL) interconnection and a back-end (BEOL) interconnection. The interconnection layer may also include one or more interlayer dielectric layers in which interconnection lines and VIA contacts may be formed. The interconnection lines and VIA contacts in the interconnection layer may include conductive materials, which include but are not limited to W, Co, Cu, Al, silicide, or any combination thereof. The interlayer dielectric layer in the interconnection layer may include a dielectric material. The dielectric material includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.
在本發明的其中一些實施例中，立體記憶體元件100是NAND快閃記憶體元件，其中儲存單元是以NAND記憶體串陣列的形式提供的。如圖1A所示，立體記憶體元件100的第二半導體結構104可以包括用作NAND記憶體串陣列的通道結構124的陣列。如圖1A所示，各個通道結構124可以垂直地延伸穿過各自包括導電層116和介電層118的多個對。交錯的導電層116和介電層118是儲存堆疊層114的一部分。儲存堆疊層114中的導電層116和介電層118的對數量(例如，32、64、96、128、160、192、224、256或更多)確定立體記憶體元件100中的儲存單元的數量。應理解，在本發明的其中一些實施例中，儲存堆疊層114可以具有多堆疊架構(未示出)，其包括堆疊在彼此之上的多個記憶體堆疊。各個記憶體堆疊中的導電層116和介電層118的對數量可以相同或不同。
In some embodiments of the present invention, the three-dimensional memory device 100 is a NAND flash memory device, and the storage unit is provided in the form of a NAND memory string array. As shown in FIG. 1A, the second semiconductor structure 104 of the three-dimensional memory device 100 may include an array of channel structures 124 used as an array of NAND memory strings. As shown in FIG. 1A, each channel structure 124 may extend vertically through multiple pairs each including a conductive layer 116 and a dielectric layer 118. The interleaved conductive layer 116 and the dielectric layer 118 are part of the storage stack 114. The number of pairs (for example, 32, 64, 96, 128, 160, 192, 224, 256 or more) of the conductive layer 116 and the dielectric layer 118 in the storage stack layer 114 determines the size of the storage unit in the three-dimensional memory device 100 quantity. It should be understood that, in some embodiments of the present invention, the storage stack layer 114 may have a multi-stack structure (not shown), which includes a plurality of memory stacks stacked on top of each other. The number of pairs of conductive layers 116 and dielectric layers 118 in each memory stack may be the same or different.
儲存堆疊層114可以包括多個交錯的導電層116和介電層118。儲存堆疊層114中的導電層116和介電層118可以在垂直方向上交替。換言之，除了在儲存堆疊層114的頂部或底部的層之外，各個導電層116可以被在兩側的兩個介電層118鄰接，並且各個介電層118可以被在兩側上的兩個導電層116鄰接。導電層116可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、多晶矽、摻雜矽、矽化物或其任何組合。各個導電層116可以包括由黏合層和閘極介電層圍繞的閘電極(閘極線)。導電層116的閘電極可以作為字元線橫向地延伸，在儲存堆疊層114的一個或多個階梯結構處終止。介電層118可以包括介電材料，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽或其任何組合。
The storage stack layer 114 may include a plurality of interlaced conductive layers 116 and dielectric layers 118. The conductive layers 116 and the dielectric layers 118 in the storage stack layer 114 may alternate in the vertical direction. In other words, in addition to the layers on the top or bottom of the storage stack 114, each conductive layer 116 may be abutted by two dielectric layers 118 on both sides, and each dielectric layer 118 may be abutted by two dielectric layers 118 on both sides. The conductive layer 116 adjoins. The conductive layer 116 may include a conductive material, and the conductive material includes, but is not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 116 may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the conductive layer 116 may extend laterally as a word line and terminate at one or more stepped structures of the storage stack layer 114. The dielectric layer 118 may include a dielectric material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
如圖1A所示，立體記憶體元件100的第二半導體結構104還可以包括在儲存堆疊層114上方的N型摻雜半導體層120。N型摻雜半導體層120可以是如上所述的“側壁SEG”的示例。N型摻雜半導體層120可以包括半導體材料，例如矽。
在本發明的其中一些實施例中，N型摻雜半導體層120包括透過沉積技術形成的多晶矽，如以下詳細描述的。N型摻雜半導體層120可以摻雜有任何合適的N型摻雜劑(例如，磷(P)、砷(Ar)或銻(Sb))，其貢獻自由電子並且增加本征半導體的導電性。例如，N型摻雜半導體層120可以是摻雜有N型摻雜劑(例如，P、Ar或Sb)的多晶矽層。
As shown in FIG. 1A, the second semiconductor structure 104 of the three-dimensional memory device 100 may further include an N-type doped semiconductor layer 120 above the storage stack layer 114. The N-type doped semiconductor layer 120 may be an example of the “sidewall SEG” described above. The N-type doped semiconductor layer 120 may include a semiconductor material, such as silicon.
In some embodiments of the present invention, the N-type doped semiconductor layer 120 includes polysilicon formed by a deposition technique, as described in detail below. The N-type doped semiconductor layer 120 may be doped with any suitable N-type dopant (for example, phosphorus (P), arsenic (Ar), or antimony (Sb)), which contributes free electrons and increases the conductivity of the intrinsic semiconductor . For example, the N-type doped semiconductor layer 120 may be a polysilicon layer doped with N-type dopants (for example, P, Ar, or Sb).
在本發明的其中一些實施例中，各個通道結構124包括填充有半導體層(例如，作為半導體通道128)和複合介電層(例如，作為儲存膜126)的通道孔。在本發明的其中一些實施例中，半導體通道128包括矽，例如非晶矽、多晶矽或單晶矽。在本發明的其中一些實施例中，儲存膜126是包括穿隧層、儲存層(也被稱為“電荷捕獲層”)和阻擋層的複合層。通道結構124的剩餘空間可以
部分地或完全地利用包括例如氧化矽之類的介電材料的封蓋層和/或氣隙填充。
通道結構124可以具有圓柱形(例如，柱形)。根據一些實施例，封蓋層、半導體通道128、儲存膜126的穿隧層、儲存層和阻擋層從柱的中心朝向外表面徑向地以該順序排列。穿隧層可以包括氧化矽、氮氧化矽或其任何組合。儲存層可以包括氮化矽、氮氧化矽、矽或其任何組合。阻擋層可以包括氧化矽、氮氧化矽、高k介電或其任何組合。在一個示例中，儲存膜126可以包括氧化矽/氮氧化矽/氧化矽(ONO)的複合層。
In some embodiments of the present invention, each channel structure 124 includes a channel hole filled with a semiconductor layer (for example, as a semiconductor channel 128) and a composite dielectric layer (for example, as a storage film 126). In some embodiments of the present invention, the semiconductor channel 128 includes silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon. In some embodiments of the present invention, the storage film 126 is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a blocking layer. The remaining space of the channel structure 124 can be
A capping layer including a dielectric material such as silicon oxide and/or air gap filling is partially or completely utilized.
The channel structure 124 may have a cylindrical shape (for example, a cylindrical shape). According to some embodiments, the capping layer, the semiconductor channel 128, the tunneling layer of the storage film 126, the storage layer, and the barrier layer are arranged in this order radially from the center of the pillar toward the outer surface. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the storage film 126 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
在本發明的其中一些實施例中，通道結構124還包括在通道結構124的底部部分(例如，在下端)中的通道插塞129。如本文所使用的，當基底101位於立體記憶體元件100的最低平面中時，部件(例如，通道結構124)的“上端”是在y方向上較遠離基底101的端部，而部件(例如，通道結構124)的“下端”是在y方向上較靠近基底101的端部。通道插塞129可以包括半導體材料(例如，多晶矽)。在本發明的其中一些實施例中，通道插塞129用作NAND記憶體串的汲極。
In some of the embodiments of the present invention, the channel structure 124 further includes a channel plug 129 in the bottom portion (for example, at the lower end) of the channel structure 124. As used herein, when the substrate 101 is located in the lowest plane of the three-dimensional memory device 100, the "upper end" of the component (for example, the channel structure 124) is the end farther from the substrate 101 in the y direction, and the component (for example The "lower end" of the channel structure 124) is the end closer to the substrate 101 in the y direction. The channel plug 129 may include a semiconductor material (for example, polysilicon). In some embodiments of the present invention, the channel plug 129 is used as the drain of the NAND memory string.
如圖1A所示，各個通道結構124可以垂直地延伸穿過儲存堆疊層114的交錯的導電層116和介電層118進入N型摻雜半導體層120中。各個通道結構124的上端可以是與N型摻雜半導體層120的頂表面齊平或者在其下方。也就是說，根據一些實施例，通道結構124不延伸超過N型摻雜半導體層120的頂表面。在本發明的其中一些實施例中，如圖1A所示，儲存膜126的上端在通道結構124中的半導體通道128的上端下方。在本發明的其中一些實施例中，儲存膜126的上端在N型摻雜半導體層120的頂表面下方，並且半導體通道128的上端是與N型摻雜半導體層120的頂表面齊平或者在其下方。例如，如圖1A所示，儲存膜126可以在N型摻雜半導體層120的底表面處終止，而半導體通道128可以在N型摻雜半導
體層120的底表面上方延伸，使得N型摻雜半導體層120可以圍繞半導體通道128的延伸進入N型摻雜半導體層120中的頂部部分127。在本發明的其中一些實施例中，半導體通道128的延伸進入N型摻雜半導體層120中的頂部部分127的摻雜濃度，是不同於半導體通道128的其餘部分的摻雜濃度的。例如，除了頂部部分127之外，半導體通道128可以包括未摻雜的多晶矽，頂部部分127可以包括摻雜多晶矽，以在與周圍的N型摻雜半導體層120形成電性連接時增加其導電性。
As shown in FIG. 1A, each channel structure 124 may extend vertically through the staggered conductive layer 116 and the dielectric layer 118 of the storage stack layer 114 into the N-type doped semiconductor layer 120. The upper end of each channel structure 124 may be flush with the top surface of the N-type doped semiconductor layer 120 or below it. That is, according to some embodiments, the channel structure 124 does not extend beyond the top surface of the N-type doped semiconductor layer 120. In some embodiments of the present invention, as shown in FIG. 1A, the upper end of the storage film 126 is below the upper end of the semiconductor channel 128 in the channel structure 124. In some embodiments of the present invention, the upper end of the storage film 126 is below the top surface of the N-type doped semiconductor layer 120, and the upper end of the semiconductor channel 128 is flush with or at the top surface of the N-type doped semiconductor layer 120. Below it. For example, as shown in FIG. 1A, the storage film 126 may be terminated at the bottom surface of the N-type doped semiconductor layer 120, and the semiconductor channel 128 may be terminated in the N-type doped semiconductor layer.
The body layer 120 extends above the bottom surface, so that the N-type doped semiconductor layer 120 can surround the extension of the semiconductor channel 128 into the top portion 127 of the N-type doped semiconductor layer 120. In some embodiments of the present invention, the doping concentration of the top portion 127 of the semiconductor channel 128 extending into the N-type doped semiconductor layer 120 is different from the doping concentration of the rest of the semiconductor channel 128. For example, in addition to the top portion 127, the semiconductor channel 128 may include undoped polysilicon, and the top portion 127 may include doped polysilicon to increase its conductivity when forming an electrical connection with the surrounding N-type doped semiconductor layer 120. .
在本發明的其中一些實施例中，立體記憶體元件100的第二半導體結構104包括在通道結構124的上端上方，並且與其接觸的導電層122。導電層122可以將多個通道結構124電性連接。儘管在圖1A的側視圖中未示出，但是應理解，導電層122可以是與多個通道結構124接觸的連續導電層(例如，其中具有孔(網格)以允許源極接觸132在平面圖中穿過的導電板)。結果，導電層122和N型摻雜半導體層120可以一起提供在相同塊中的NAND記憶體串的陣列的源極(即ACS)之間的電性連接。如圖1A所示，在本發明的其中一些實施例中，導電層122在橫向方向上包括兩個部分：在N型摻雜半導體層120上的第一部分(在通道結構124的區域之外)、以及鄰接N型摻雜半導體層120並且與通道結構124的上端接觸的第二部分(在通道結構124的區域內)。也就是說，根據一些實施例，導電層122的至少一部分(即，第一部分)在N型摻雜半導體層120上。根據一些實施例，導電層122的圍繞各個通道結構124的上端(其延伸進入N型摻雜半導體層120中)的剩餘一部分(即，第二部分)是與半導體通道128的頂部部分127接觸的。如以下詳細描述的，儲存堆疊層114以及導電層122和半導體通道128的頂部部分127分別形成在N型摻雜半導體層120的相對側，這可以避免穿過延伸穿過儲存堆疊層114的開口的任何沉積或蝕刻製程，進而減少製造複雜性和成本並且增加成品率和垂直可縮放性。
In some embodiments of the present invention, the second semiconductor structure 104 of the three-dimensional memory device 100 includes a conductive layer 122 above the upper end of the channel structure 124 and in contact therewith. The conductive layer 122 can electrically connect the plurality of channel structures 124. Although not shown in the side view of FIG. 1A, it should be understood that the conductive layer 122 may be a continuous conductive layer in contact with the plurality of channel structures 124 (for example, having holes (mesh) therein to allow the source contact 132 to be in plan view). Through the conductive plate). As a result, the conductive layer 122 and the N-type doped semiconductor layer 120 can together provide an electrical connection between the sources (ie, ACS) of the array of NAND memory strings in the same block. As shown in FIG. 1A, in some embodiments of the present invention, the conductive layer 122 includes two parts in the lateral direction: the first part on the N-type doped semiconductor layer 120 (outside the area of the channel structure 124) , And a second portion (in the region of the channel structure 124) adjacent to the N-type doped semiconductor layer 120 and in contact with the upper end of the channel structure 124. That is, according to some embodiments, at least a portion (ie, the first portion) of the conductive layer 122 is on the N-type doped semiconductor layer 120. According to some embodiments, the remaining portion (ie, the second portion) of the conductive layer 122 surrounding the upper end of each channel structure 124 (which extends into the N-type doped semiconductor layer 120) is in contact with the top portion 127 of the semiconductor channel 128 . As described in detail below, the storage stack 114 and the top portion 127 of the conductive layer 122 and the semiconductor channel 128 are respectively formed on opposite sides of the N-type doped semiconductor layer 120, which can avoid passing through the opening extending through the storage stack 114 Any deposition or etching process, thereby reducing manufacturing complexity and cost and increasing yield and vertical scalability.
在本發明的其中一些實施例中，導電層122包括在垂直方向上的多個層，包括金屬矽化物層121和在金屬矽化物層121上方的金屬層123。金屬矽化物層121和金屬層123中的每一個可以是連續膜。金屬矽化物層121可以被設置在N型摻雜半導體層120(在導電層122的第一部分中)和通道結構124的上端(在導電層122的第二部分中)上方並且與其接觸。在本發明的其中一些實施例中，金屬矽化物層121的一部分圍繞並且接觸半導體通道128的延伸進入N型摻雜半導體層120中的頂部部分127，以與多個通道結構124進行電性連接。金屬矽化物層121可以包括金屬矽化物，例如，矽化銅、矽化鈷、矽化鎳、矽化鈦、矽化鎢、矽化銀、矽化鋁、矽化金、矽化鉑、任何其它合適的金屬矽化物、或其任何組合。根據一些實施例，金屬層123在金屬矽化物層121上方並且與其接觸。金屬層123可以包括金屬，例如，W、Co、Cu、Al、鎳(Ni)、鈦(Ti)、任何其它合適的金屬、或其任何組合。應理解，金屬層123中的金屬可以廣義地包括任何合適的導電金屬化合物以及金屬合金，例如氮化鈦和氮化鉭。金屬矽化物層121可以減小在導電層122和半導體通道128的頂部部分127之間的接觸電阻，以及用作導電層122中的金屬層123的阻隔層。
In some embodiments of the present invention, the conductive layer 122 includes multiple layers in the vertical direction, including a metal silicide layer 121 and a metal layer 123 above the metal silicide layer 121. Each of the metal silicide layer 121 and the metal layer 123 may be a continuous film. The metal silicide layer 121 may be disposed over and in contact with the N-type doped semiconductor layer 120 (in the first part of the conductive layer 122) and the upper end of the channel structure 124 (in the second part of the conductive layer 122). In some embodiments of the present invention, a portion of the metal silicide layer 121 surrounds and contacts the top portion 127 of the semiconductor channel 128 that extends into the N-type doped semiconductor layer 120 to be electrically connected to the plurality of channel structures 124 . The metal silicide layer 121 may include metal silicide, for example, copper silicide, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, silver silicide, aluminum silicide, gold silicide, platinum silicide, any other suitable metal silicide, or Any combination. According to some embodiments, the metal layer 123 is above and in contact with the metal silicide layer 121. The metal layer 123 may include a metal, for example, W, Co, Cu, Al, nickel (Ni), titanium (Ti), any other suitable metal, or any combination thereof. It should be understood that the metal in the metal layer 123 may broadly include any suitable conductive metal compound and metal alloy, such as titanium nitride and tantalum nitride. The metal silicide layer 121 can reduce the contact resistance between the conductive layer 122 and the top portion 127 of the semiconductor channel 128, and serves as a barrier layer for the metal layer 123 in the conductive layer 122.
與單獨的N型摻雜半導體層120相比，透過將導電層122和N型摻雜半導體層120組合，可以增加通道結構124之間(即，在同一塊中的NAND記憶體串的ACS處)的導電性，由此改善立體記憶體元件100的電氣性能。透過引入導電層122，為了維持在通道結構124之間的相同導電性/電阻，可以將N型摻雜半導體層120的厚度例如減小到小於大約50奈米，例如小於50奈米。在本發明的其中一些實施例中，N型摻雜半導體層120的厚度在大約10奈米與大約30奈米之間，例如在10奈米與30奈米之間(例如，10奈米、11奈米、12奈米、13奈
米、14奈米、15奈米、16奈米、17奈米、18奈米、19奈米、20奈米、21奈米、22奈米、23奈米、24奈米、25奈米、26奈米、27奈米、28奈米、29奈米、30奈米、由這些值中的任何一個為下限界定的任何範圍、或者在由這些值中的任何兩個值限定的任何範圍中)。N型摻雜半導體層120與圍繞通道結構124的半導體通道128的頂部部分127的導電層122組合可以實現用於立體記憶體元件100的擦除操作步驟的GIDL輔助體偏壓。在NAND記憶體串的源極選擇閘極周圍的GIDL可以生成進入NAND記憶體串的電洞電流，以提高用於擦除操作步驟的體電勢(body potential)。也就是說，根據一些實施例，立體記憶體元件100被配置為在執行擦除操作步驟時生成GIDL輔助體偏壓。
Compared with the single N-type doped semiconductor layer 120, by combining the conductive layer 122 and the N-type doped semiconductor layer 120, the channel structure 124 can be increased (that is, at the ACS of the NAND memory string in the same block). ), thereby improving the electrical performance of the three-dimensional memory device 100. By introducing the conductive layer 122, in order to maintain the same conductivity/resistance between the channel structures 124, the thickness of the N-type doped semiconductor layer 120 can be reduced to less than about 50 nanometers, for example, less than 50 nanometers. In some embodiments of the present invention, the thickness of the N-type doped semiconductor layer 120 is between about 10 nanometers and about 30 nanometers, such as between 10 nanometers and 30 nanometers (for example, 10 nanometers, 11nm, 12nm, 13nm
Meter, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, any range defined by any one of these values as the lower limit, or any range defined by any two of these values ). The combination of the N-type doped semiconductor layer 120 and the conductive layer 122 surrounding the top portion 127 of the semiconductor channel 128 of the channel structure 124 can realize the GIDL auxiliary body bias for the erase operation step of the three-dimensional memory device 100. The GIDL around the source selection gate of the NAND memory string can generate a hole current into the NAND memory string to increase the body potential for the erase operation step. That is, according to some embodiments, the three-dimensional memory device 100 is configured to generate a GIDL auxiliary body bias when the erasing operation step is performed.
如圖1A所示，立體記憶體元件100的第二半導體結構104還可以包括絕緣結構130，其各自垂直地延伸穿過儲存堆疊層114的交錯的導電層116和介電層118。根據一些實施例，與進一步延伸進入N型摻雜半導體層120中的通道結構124不同，絕緣結構130在N型摻雜半導體層120的底表面處停止，即，並不垂直地延伸進入N型摻雜半導體層120中。也就是說，絕緣結構130的頂表面可以是與N型摻雜半導體層120的底表面齊平。各個絕緣結構130還可以橫向地延伸以將通道結構124分成多個塊。也就是說，儲存堆疊層114可以被絕緣結構130劃分成多個記憶體塊，使得可以將通道結構124的陣列分成各個記憶體塊。與上述現有的3D NAND記憶體元件中的包括正面ACS接觸的縫隙結構不同，根據一些實施例，絕緣結構130其中不包括任何接觸(即，不用作源極接觸)，並且因此不引入與導電層116(包括字元線)的寄生電容以及漏電流。在本發明的其中一些實施例中，各個絕緣結構130包括填充有一種或多種介電材料的開口(例如，縫隙)，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、或其任何組合。在一個示例中，各個絕緣結構130可以填充有氧化矽。
As shown in FIG. 1A, the second semiconductor structure 104 of the three-dimensional memory device 100 may also include insulating structures 130, each of which extends vertically through the interlaced conductive layer 116 and the dielectric layer 118 of the storage stack 114. According to some embodiments, unlike the channel structure 124 that further extends into the N-type doped semiconductor layer 120, the insulating structure 130 stops at the bottom surface of the N-type doped semiconductor layer 120, that is, does not extend vertically into the N-type doped semiconductor layer 120. Doped in the semiconductor layer 120. That is, the top surface of the insulating structure 130 may be flush with the bottom surface of the N-type doped semiconductor layer 120. Each insulating structure 130 may also extend laterally to divide the channel structure 124 into a plurality of blocks. That is, the storage stack layer 114 can be divided into a plurality of memory blocks by the insulating structure 130, so that the array of the channel structure 124 can be divided into individual memory blocks. Unlike the above-mentioned existing 3D NAND memory device including the front-side ACS contact gap structure, according to some embodiments, the insulating structure 130 does not include any contact therein (that is, not used as a source contact), and therefore does not introduce a conductive layer 116 (including the word line) parasitic capacitance and leakage current. In some embodiments of the present invention, each insulating structure 130 includes openings (for example, gaps) filled with one or more dielectric materials. The dielectric materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or Any combination of it. In one example, each insulating structure 130 may be filled with silicon oxide.
此外，如以下詳細描述的，因為用於形成絕緣結構130的開口不用於形成N型摻雜半導體層120以及導電層122的第二部分，所以開口隨著交錯的導電層116和介電層118的數量的增加而增加的高寬比(例如，大於50)將不影響N型摻雜半導體層120和導電層122的形成。
In addition, as described in detail below, because the opening used to form the insulating structure 130 is not used to form the N-type doped semiconductor layer 120 and the second portion of the conductive layer 122, the opening follows the staggered conductive layer 116 and the dielectric layer 118. The increased aspect ratio (for example, greater than 50) due to the increase in the number of λ will not affect the formation of the N-type doped semiconductor layer 120 and the conductive layer 122.
如圖1A所示，代替正面源極接觸，立體記憶體元件100可以包括在儲存堆疊層114上方並且與N型摻雜半導體層120接觸的背面源極接觸132。源極接觸132和儲存堆疊層114(以及穿過其中的絕緣結構130)可以被設置在N型摻雜半導體層120的相對側，並且因此被視為“背面”源極接觸。在本發明的其中一些實施例中，源極接觸132穿過N型摻雜半導體層120，電性連接到通道結構124的半導體通道128。在本發明的其中一些實施例中，源極接觸132不是與絕緣結構130橫向對準的，而是接近通道結構124，以減小在其之間的電性連接的電阻。
例如，源極接觸132可以橫向地位於絕緣結構130和通道結構124之間(例如，在圖1中的x方向上)。源極接觸132可以包括任何合適類型的接觸。在本發明的其中一些實施例中，源極接觸132包括VIA接觸。在本發明的其中一些實施例中，源極接觸132包括橫向地延伸的壁狀接觸。源極接觸132可以包括一個或多個導電層，例如被黏合層(例如，氮化鈦(TiN))圍繞的金屬層(例如，W、Co、Cu或Al)或矽化物層。
As shown in FIG. 1A, instead of the front source contact, the three-dimensional memory device 100 may include a back source contact 132 above the storage stack layer 114 and in contact with the N-type doped semiconductor layer 120. The source contact 132 and the storage stack layer 114 (and the insulating structure 130 passing therethrough) may be disposed on the opposite side of the N-type doped semiconductor layer 120, and therefore are regarded as a "backside" source contact. In some embodiments of the present invention, the source contact 132 passes through the N-type doped semiconductor layer 120 and is electrically connected to the semiconductor channel 128 of the channel structure 124. In some embodiments of the present invention, the source contact 132 is not aligned laterally with the insulating structure 130, but is close to the channel structure 124 to reduce the electrical resistance of the electrical connection therebetween. For example, the source contact 132 may be located laterally between the insulating structure 130 and the channel structure 124 (for example, in the x direction in FIG. 1). The source contact 132 may include any suitable type of contact. In some embodiments of the present invention, the source contact 132 includes a VIA contact. In some embodiments of the present invention, the source contact 132 includes a wall-shaped contact extending laterally. The source contact 132 may include one or more conductive layers, such as a metal layer (for example, W, Co, Cu, or Al) surrounded by an adhesion layer (for example, titanium nitride (TiN)) or a silicide layer.
如圖1A所示，立體記憶體元件100還可以包括後段(BEOL)互連層133，其在源極接觸132上方，並且電性連接到源極接觸132以用於襯墊輸出(pad-out)，例如，在立體記憶體元件100與外部電路之間傳送電信號。在本發明的其中一些實施例中，互連層133包括在N型摻雜半導體層120上的一個或多個
層間介電層134以及在層間介電層134上的重佈線層136。根據一些實施例，源極接觸132的上端是與層間介電層134的頂表面和重佈線層136的底表面齊平，並且源極接觸132垂直地延伸穿過層間介電層134和導電層122進入N型摻雜半導體層120中。互連層133中的層間介電層134可以包括介電材料，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電、或其任何組合。互連層133中的重佈線層136可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、矽化物、或其任何組合。在一個示例中，重佈線層136可以包括Al。在本發明的其中一些實施例中，互連層133還包括鈍化層138，作為用於立體記憶體元件100的鈍化和保護的最外層。重佈線層136的一部分可以從鈍化層138曝露作為接觸襯墊140。
也就是說，立體記憶體元件100的互連層133還可以包括用於導線鍵合和/或與中間層鍵合的接觸襯墊140。
As shown in FIG. 1A, the three-dimensional memory device 100 may further include a back-end (BEOL) interconnection layer 133, which is above the source contact 132 and is electrically connected to the source contact 132 for pad-out (pad-out). ), for example, transmitting electrical signals between the three-dimensional memory device 100 and an external circuit. In some embodiments of the present invention, the interconnection layer 133 includes one or more on the N-type doped semiconductor layer 120
The interlayer dielectric layer 134 and the rewiring layer 136 on the interlayer dielectric layer 134. According to some embodiments, the upper end of the source contact 132 is flush with the top surface of the interlayer dielectric layer 134 and the bottom surface of the redistribution layer 136, and the source contact 132 extends vertically through the interlayer dielectric layer 134 and the conductive layer 122 enters the N-type doped semiconductor layer 120. The interlayer dielectric layer 134 in the interconnection layer 133 may include a dielectric material. The dielectric material includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The rewiring layer 136 in the interconnection layer 133 may include a conductive material, and the conductive material includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof. In one example, the rewiring layer 136 may include Al. In some embodiments of the present invention, the interconnection layer 133 further includes a passivation layer 138 as the outermost layer for passivation and protection of the three-dimensional memory device 100. A part of the redistribution layer 136 may be exposed from the passivation layer 138 as a contact pad 140.
That is, the interconnection layer 133 of the three-dimensional memory device 100 may further include a contact pad 140 for wire bonding and/or bonding with an intermediate layer.
在本發明的其中一些實施例中，立體記憶體元件100的第二半導體結構104還包括穿過N型摻雜半導體層120的接觸142和接觸144。根據一些實施例，由於N型摻雜半導體層120可以包括多晶矽，所以接觸142和接觸144是貫穿矽接觸(TSC)。在本發明的其中一些實施例中，接觸142延伸穿過N型摻雜半導體層120和層間介電層134以與重佈線層136接觸，使得N型摻雜半導體層120透過源極接觸132和互連層133的重佈線層136電性連接到接觸142。在本發明的其中一些實施例中，接觸144延伸穿過N型摻雜半導體層120和層間介電層134以與接觸襯墊140接觸。接觸142和接觸144各自可以包括一個或多個導電層，例如被黏合層(例如，TiN)圍繞的金屬層(例如，W、Co、Cu或Al)或矽化物層。在本發明的其中一些實施例中，至少接觸144還包括間隙壁(例如，介電層)以將接觸144與N型摻雜半導體層120電性隔離。
In some embodiments of the present invention, the second semiconductor structure 104 of the three-dimensional memory device 100 further includes a contact 142 and a contact 144 passing through the N-type doped semiconductor layer 120. According to some embodiments, since the N-type doped semiconductor layer 120 may include polysilicon, the contact 142 and the contact 144 are through silicon contacts (TSC). In some embodiments of the present invention, the contact 142 extends through the N-type doped semiconductor layer 120 and the interlayer dielectric layer 134 to contact the rewiring layer 136, so that the N-type doped semiconductor layer 120 passes through the source contact 132 and The rewiring layer 136 of the interconnection layer 133 is electrically connected to the contact 142. In some embodiments of the present invention, the contact 144 extends through the N-type doped semiconductor layer 120 and the interlayer dielectric layer 134 to contact the contact pad 140. Each of the contact 142 and the contact 144 may include one or more conductive layers, such as a metal layer (for example, W, Co, Cu, or Al) surrounded by an adhesion layer (for example, TiN) or a silicide layer. In some embodiments of the present invention, at least the contact 144 further includes a spacer (for example, a dielectric layer) to electrically isolate the contact 144 from the N-type doped semiconductor layer 120.
在本發明的其中一些實施例中，立體記憶體元件100還包括週邊接觸146和週邊接觸148，其各自在儲存堆疊層114的外部垂直地延伸。各個週邊接觸146或148可以具有比儲存堆疊層114的深度更大的深度，以在儲存堆疊層114的外部的週邊區域中從鍵合層112垂直地延伸到N型摻雜半導體層120。在本發明的其中一些實施例中，週邊接觸146在接觸142下方並且與其接觸，使得N型摻雜半導體層120至少透過源極接觸132、互連層133、接觸142和週邊接觸146電性連接到第一半導體結構102中的週邊電路108。在本發明的其中一些實施例中，週邊接觸148在接觸144下方並且與其接觸，使得第一半導體結構102中的週邊電路108至少透過接觸144和週邊接觸148電性連接到用於襯墊輸出的接觸襯墊140。
週邊接觸146和週邊接觸148各自可以包括一個或多個導電層，例如被黏合層(例如，TiN)圍繞的金屬層(例如，W、Co、Cu或Al)或矽化物層。在本發明的其中一些實施例中，導電層122在儲存堆疊層114的區域內，即，並不橫向地延伸到週邊區域中，使得接觸142和接觸144不垂直地延伸穿過導電層122以便分別與週邊接觸148和144接觸。
In some embodiments of the present invention, the three-dimensional memory device 100 further includes a peripheral contact 146 and a peripheral contact 148, each of which extends vertically outside the storage stacked layer 114. Each peripheral contact 146 or 148 may have a depth greater than the depth of the storage stack layer 114 to extend vertically from the bonding layer 112 to the N-type doped semiconductor layer 120 in the peripheral region outside the storage stack layer 114. In some embodiments of the present invention, the peripheral contact 146 is under and in contact with the contact 142, so that the N-type doped semiconductor layer 120 is electrically connected through at least the source contact 132, the interconnection layer 133, the contact 142, and the peripheral contact 146 To the peripheral circuit 108 in the first semiconductor structure 102. In some of the embodiments of the present invention, the peripheral contact 148 is below and in contact with the contact 144, so that the peripheral circuit 108 in the first semiconductor structure 102 is electrically connected to the pad output through at least the contact 144 and the peripheral contact 148 Contact pad 140.
Each of the peripheral contact 146 and the peripheral contact 148 may include one or more conductive layers, such as a metal layer (for example, W, Co, Cu, or Al) surrounded by an adhesion layer (for example, TiN) or a silicide layer. In some embodiments of the present invention, the conductive layer 122 is in the area of the storage stack layer 114, that is, does not extend laterally into the peripheral area, so that the contact 142 and the contact 144 do not extend perpendicularly through the conductive layer 122 so as to Make contact with peripheral contacts 148 and 144, respectively.
如圖1A所示，立體記憶體元件100還包括作為互連結構的一部分的各種局部接觸(也被稱為“C1”)，其直接與儲存堆疊層114中的結構接觸。在本發明的其中一些實施例中，局部接觸包括通道局部接觸150，其各自在相應的通道結構124的下端下方並且與其接觸。各個通道局部接觸150可以電性連接到位元線接觸(未示出)以用於位元線扇出(fan out)。在本發明的其中一些實施例中，局部接觸還包括字元線局部接觸152，其各自在儲存堆疊層114的階梯結構處的相應導電層116(包括字元線)下方，並且與其接觸以用於字元線扇出。局部接觸(例如，通道局部接觸150和字元線局部接觸152)可以至少透過鍵合層112和鍵合層110電性連接到第一半導體結構102的週邊電路108。局部接觸(例如，通
道局部接觸150和字元線局部接觸152)各自可以包括一個或多個導電層，例如被黏合層(例如，TiN)圍繞的金屬層(例如，W、Co、Cu或Al)或矽化物層。
As shown in FIG. 1A, the three-dimensional memory device 100 also includes various local contacts (also referred to as “C1”) as part of the interconnect structure, which directly contact the structure in the storage stack 114. In some of the embodiments of the present invention, the local contact includes channel local contacts 150, each of which is below and in contact with the lower end of the corresponding channel structure 124. Each channel partial contact 150 may be electrically connected to a bit line contact (not shown) for bit line fan out. In some of the embodiments of the present invention, the local contact further includes the word line local contact 152, each of which is under the corresponding conductive layer 116 (including the word line) at the step structure of the storage stack layer 114 and is in contact with it. Fan out on the character line. The partial contacts (for example, the channel partial contact 150 and the word line partial contact 152) may be electrically connected to the peripheral circuit 108 of the first semiconductor structure 102 through at least the bonding layer 112 and the bonding layer 110. Local contact (for example, through
The track local contact 150 and the word line local contact 152) each may include one or more conductive layers, such as a metal layer (for example, W, Co, Cu, or Al) surrounded by an adhesion layer (for example, TiN) or a silicide layer .
圖1B示出了根據本發明內容的一些實施例的另一示例性立體記憶體元件155的橫截面的側視圖。立體記憶體元件155類似於立體記憶體元件100，不同之處在於導電層122和通道結構124的上端的不同結構。應理解，為了便於描述，沒有重複立體記憶體元件155和100兩者中的其它相同結構的細節。
FIG. 1B shows a cross-sectional side view of another exemplary three-dimensional memory element 155 according to some embodiments of the present disclosure. The three-dimensional memory device 155 is similar to the three-dimensional memory device 100, except that the conductive layer 122 and the upper end of the channel structure 124 have different structures. It should be understood that, for ease of description, other details of the same structure in both the three-dimensional memory elements 155 and 100 are not repeated.
如圖1B所示，根據一些實施例，各個通道結構124還包括鄰接N型摻雜半導體層120的通道插塞125。在本發明的其中一些實施例中，各個通道插塞125圍繞並且接觸半導體通道128的相應頂部部分127。通道插塞125的頂表面可以是與N型摻雜半導體層120的頂表面齊平。通道插塞125可以具有與半導體通道128的頂部部分127相同的材料(例如，摻雜多晶矽)，並且因此可以被視為通道結構124的半導體通道128的一部分。也就是說，在本發明內容中，被N型摻雜半導體層120圍繞的整個摻雜多晶矽結構可以被視為通道結構124的上端。因此，根據一些實施例，立體記憶體元件100和立體記憶體元件155兩者中的導電層122(以及其中的金屬矽化物層121)是與通道結構124的上端接觸的。
As shown in FIG. 1B, according to some embodiments, each channel structure 124 further includes a channel plug 125 adjacent to the N-type doped semiconductor layer 120. In some of the embodiments of the present invention, each channel plug 125 surrounds and contacts the corresponding top portion 127 of the semiconductor channel 128. The top surface of the channel plug 125 may be flush with the top surface of the N-type doped semiconductor layer 120. The channel plug 125 may have the same material as the top portion 127 of the semiconductor channel 128 (for example, doped polysilicon), and therefore may be regarded as a part of the semiconductor channel 128 of the channel structure 124. That is, in the context of the present invention, the entire doped polysilicon structure surrounded by the N-type doped semiconductor layer 120 can be regarded as the upper end of the channel structure 124. Therefore, according to some embodiments, the conductive layer 122 (and the metal silicide layer 121 therein) in both the three-dimensional memory device 100 and the three-dimensional memory device 155 is in contact with the upper end of the channel structure 124.
與立體記憶體元件100中的導電層122不同(如圖1A所示，在立體記憶體元件100中，導電層122的第二部分在N型摻雜半導體層120的頂表面下方，並且圍繞通道結構124的上端)，因為通道結構124的上端還包括圖1B中的通道插塞125，所以整個導電層122在N型摻雜半導體層120的頂表面上方。如圖1B所示，通道結構124的上端的頂表面是與N型摻雜半導體層120的頂表面齊平，並且導電層122被設置在N型摻雜半導體層120和通道結構124的上端上。換句話說，立體
記憶體元件100中的導電層122中填充N型摻雜半導體層120與半導體通道128的頂部部分127之間的凹部的一部分，可以被立體記憶體元件155中的通道插塞125代替，使得導電層122可以形成在N型摻雜半導體層120和通道結構124的頂表面上的相同平面中。
Unlike the conductive layer 122 in the three-dimensional memory device 100 (as shown in FIG. 1A, in the three-dimensional memory device 100, the second portion of the conductive layer 122 is below the top surface of the N-type doped semiconductor layer 120 and surrounds the channel The upper end of the structure 124), because the upper end of the channel structure 124 also includes the channel plug 125 in FIG. 1B, the entire conductive layer 122 is above the top surface of the N-type doped semiconductor layer 120. As shown in FIG. 1B, the top surface of the upper end of the channel structure 124 is flush with the top surface of the N-type doped semiconductor layer 120, and the conductive layer 122 is disposed on the upper ends of the N-type doped semiconductor layer 120 and the channel structure 124 . In other words, three-dimensional
The conductive layer 122 in the memory device 100 fills a part of the recess between the N-type doped semiconductor layer 120 and the top portion 127 of the semiconductor channel 128, which can be replaced by the channel plug 125 in the three-dimensional memory device 155, making it conductive The layer 122 may be formed in the same plane on the top surface of the N-type doped semiconductor layer 120 and the channel structure 124.
圖1C示出了根據本發明內容的一些實施例的又一示例性立體記憶體元件160的橫截面的側視圖。立體記憶體元件160類似於立體記憶體元件100，不同之處在於導電層122的不同結構。應理解，為了便於描述，沒有重複立體記憶體元件160和立體記憶體元100兩者中的其它相同結構的細節。
FIG. 1C shows a cross-sectional side view of yet another exemplary three-dimensional memory element 160 according to some embodiments of the present disclosure. The three-dimensional memory device 160 is similar to the three-dimensional memory device 100, and the difference lies in the different structure of the conductive layer 122. It should be understood that, for ease of description, other details of the same structure in both the three-dimensional memory element 160 and the three-dimensional memory element 100 are not repeated.
如圖1C所示，根據一些實施例，導電層122的金屬層123是與半導體通道128接觸的，並且金屬層123的一部分在金屬矽化物層121上方並且與其接觸。與立體記憶體元件100中的導電層122不同(在立體記憶體元件100中，金屬矽化物層121的一部分在N型摻雜半導體層120的頂表面下方，並且圍繞半導體通道128的頂部部分127)，在立體記憶體元件160中，僅金屬層123在N型摻雜半導體層120的頂表面下方，並且圍繞半導體通道128的頂部部分127。然而，在立體記憶體元件100、立體記憶體元件155和立體記憶體元件160中，導電層122的第一部分具有相同的結構，即，具有在N型摻雜半導體層120上的金屬矽化物層121，以及在金屬矽化物層121上方並且與其接觸的金屬層123。至於導電層122的第二部分(在通道結構124的區域內)，立體記憶體元件100、立體記憶體元件155和立體記憶體元件160中的各種結構可以是透過以下關於製造製程詳細描述的用於形成導電層122的不同示例(例如，如何填充在N型摻雜半導體層120與半導體通道128的頂部部分127之間的凹部的方式)描述。
As shown in FIG. 1C, according to some embodiments, the metal layer 123 of the conductive layer 122 is in contact with the semiconductor channel 128, and a portion of the metal layer 123 is above and in contact with the metal silicide layer 121. Different from the conductive layer 122 in the three-dimensional memory device 100 (in the three-dimensional memory device 100, a part of the metal silicide layer 121 is below the top surface of the N-type doped semiconductor layer 120 and surrounds the top portion 127 of the semiconductor channel 128 ), in the three-dimensional memory device 160, only the metal layer 123 is below the top surface of the N-type doped semiconductor layer 120 and surrounds the top portion 127 of the semiconductor channel 128. However, in the three-dimensional memory device 100, the three-dimensional memory device 155 and the three-dimensional memory device 160, the first part of the conductive layer 122 has the same structure, that is, has a metal silicide layer on the N-type doped semiconductor layer 120 121, and a metal layer 123 above and in contact with the metal silicide layer 121. As for the second part of the conductive layer 122 (in the area of the channel structure 124), the various structures in the three-dimensional memory device 100, the three-dimensional memory device 155, and the three-dimensional memory device 160 can be used through the following detailed description of the manufacturing process. Different examples of forming the conductive layer 122 (for example, how to fill the recesses between the N-type doped semiconductor layer 120 and the top portion 127 of the semiconductor channel 128) are described.
例如，如以下詳細描述的，圖1C中的立體記憶體元件160的金屬矽化物層121，可以是用於自動地停止對通道結構124的通道孔的蝕刻的停止層的一部分。可以對停止層進行圖案化，以從N型摻雜半導體層120的背面曝露通道結構124的上端，並且停止層的剩餘部分可以作為金屬矽化物層121，保留在立體記憶體元件160中。然後，金屬層123可以被形成以填充在N型摻雜半導體層120和半導體通道128的頂部部分127之間的凹部，以及被形成在金屬矽化物層121上。相反，在形成導電層122之前，可以去除立體記憶體元件100和立體記憶體元件155中的相同停止層。因此，在從N型摻雜半導體層120的背面去除停止層之後，可以形成立體記憶體元件100和立體記憶體元件155中的金屬矽化物層121，以與通道結構124的上端接觸，其中在立體記憶體元件100中沒有通道插塞125，或者在立體記憶體元件155中具有通道插塞125，這與立體記憶體元件160中的導電層122相比，可以降低與通道結構124的接觸電阻，但是增加了製程的數量與時間。
For example, as described in detail below, the metal silicide layer 121 of the three-dimensional memory device 160 in FIG. 1C may be a part of a stop layer for automatically stopping the etching of the channel hole of the channel structure 124. The stop layer may be patterned to expose the upper end of the channel structure 124 from the backside of the N-type doped semiconductor layer 120, and the remaining part of the stop layer may serve as the metal silicide layer 121 and remain in the three-dimensional memory device 160. Then, the metal layer 123 may be formed to fill the recess between the N-type doped semiconductor layer 120 and the top portion 127 of the semiconductor channel 128 and be formed on the metal silicide layer 121. On the contrary, before forming the conductive layer 122, the same stop layer in the three-dimensional memory element 100 and the three-dimensional memory element 155 may be removed. Therefore, after removing the stop layer from the backside of the N-type doped semiconductor layer 120, the metal silicide layer 121 in the three-dimensional memory device 100 and the three-dimensional memory device 155 can be formed to contact the upper end of the channel structure 124, wherein There is no channel plug 125 in the three-dimensional memory device 100, or there is a channel plug 125 in the three-dimensional memory device 155. Compared with the conductive layer 122 in the three-dimensional memory device 160, the contact resistance with the channel structure 124 can be reduced. , But increased the number and time of the process.
圖2A示出了根據本發明內容的一些實施例的又一示例性立體記憶體元件200的橫截面的側視圖。在本發明的其中一些實施例中，立體記憶體元件200是包括第一半導體結構202和堆疊在第一半導體結構202之上的第二半導體結構204的鍵合晶片。根據一些實施例，第一半導體結構202和第二半導體結構204在其之間的鍵合介面206處接合。如圖2A所示，第一半導體結構202可以包括基底201，其可以包括矽(例如，單晶矽(c-Si))、SiGe、GaAs、Ge、SOI、或任何其它合適的材料。
FIG. 2A shows a cross-sectional side view of yet another exemplary three-dimensional memory element 200 according to some embodiments of the present disclosure. In some embodiments of the present invention, the three-dimensional memory device 200 is a bonded wafer including a first semiconductor structure 202 and a second semiconductor structure 204 stacked on the first semiconductor structure 202. According to some embodiments, the first semiconductor structure 202 and the second semiconductor structure 204 are joined at a bonding interface 206 therebetween. As shown in FIG. 2A, the first semiconductor structure 202 may include a substrate 201, which may include silicon (for example, single crystal silicon (c-Si)), SiGe, GaAs, Ge, SOI, or any other suitable material.
立體記憶體元件200的第一半導體結構202可以包括在基底201上的週邊電路208。在本發明的其中一些實施例中，週邊電路208被配置為控制和感
測立體記憶體元件200。週邊電路208可以是用於促進立體記憶體元件200的操作步驟的任何合適的數位、類比和/或混合信號控制和感測電路，包括(但不限於)頁緩衝器、解碼器(例如，行解碼器和列解碼器)、感測放大器、驅動器(例如，字元線驅動器)、電荷泵、電流或電壓參考、或該電路的任何主動或被動部件(例如，電晶體、二極體、電阻器或電容器)。週邊電路208可以包括形成於基底201“上”的電晶體，其中電晶體的全部或部分形成於基底201中(例如，在基底201的頂表面下方)和/或直接形成於基底201上。隔離區(例如，淺溝槽隔離(STI))和摻雜區(例如，電晶體的源極區和汲極區)也可以形成在基底201中。根據一些實施例，電晶體是高速的且具有先進邏輯製程(例如，90奈米、65奈米、45奈米、32奈米、28奈米、20奈米、16奈米、14奈米、10奈米、7奈米、5奈米、3奈米、2奈米等的技術節點)。應理解，在本發明的其中一些實施例中，週邊電路208還可以包括與先進邏輯製程相容的任何其它電路，包括邏輯電路(例如，處理器和PLD)或記憶體電路(例如，SRAM和DRAM)。
The first semiconductor structure 202 of the three-dimensional memory device 200 may include a peripheral circuit 208 on the substrate 201. In some of the embodiments of the present invention, the peripheral circuit 208 is configured to control and sense
Measure the three-dimensional memory device 200. The peripheral circuit 208 may be any suitable digital, analog, and/or mixed-signal control and sensing circuit for facilitating the operation steps of the three-dimensional memory element 200, including (but not limited to) page buffers, decoders (e.g., row Decoders and column decoders), sense amplifiers, drivers (for example, word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (for example, transistors, diodes, resistors) Device or capacitor). The peripheral circuit 208 may include a transistor formed "on" the substrate 201, wherein all or part of the transistor is formed in the substrate 201 (for example, below the top surface of the substrate 201) and/or directly formed on the substrate 201. Isolation regions (for example, shallow trench isolation (STI)) and doped regions (for example, the source and drain regions of the transistor) may also be formed in the substrate 201. According to some embodiments, the transistor is high-speed and has advanced logic processes (for example, 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, Technology nodes of 10nm, 7nm, 5nm, 3nm, 2nm, etc.). It should be understood that in some embodiments of the present invention, the peripheral circuit 208 may also include any other circuits compatible with advanced logic processes, including logic circuits (for example, processors and PLDs) or memory circuits (for example, SRAM and DRAM).
在本發明的其中一些實施例中，立體記憶體元件200的第一半導體結構202還包括在週邊電路208上方的互連層(未示出)，以向週邊電路208傳送電信號以及從週邊電路208傳送電信號。互連層可以包括多個互連(本文中也被稱為“接觸”)，包括橫向互連線和VIA接觸。如本文所使用的，術語“互連”可以廣義地包括任何適當類型的互連，例如中段(MEOL)互連和後段(BEOL)互連。
互連層還可以包括其中可以形成互連線和VIA接觸的一個或多個層間介電層(也被稱為“IMD層”)。也就是說，互連層可以包括在多個層間介電層中的互連線和VIA接觸。在互連層中的互連線和VIA接觸可以包括導電材料，導電材料包括但不限於W、Co、u、Al、矽化物、或其任何組合。在互連層中的層間介電層可以包括介電材料，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電、
或其任何組合。
In some embodiments of the present invention, the first semiconductor structure 202 of the three-dimensional memory device 200 further includes an interconnection layer (not shown) above the peripheral circuit 208 to transmit electrical signals to and from the peripheral circuit 208 208 transmits electrical signals. The interconnect layer may include multiple interconnects (also referred to herein as "contacts"), including lateral interconnect lines and VIA contacts. As used herein, the term "interconnect" can broadly include any suitable type of interconnection, such as mid-stage (MEOL) interconnection and back-end (BEOL) interconnection.
The interconnection layer may also include one or more interlayer dielectric layers (also referred to as "IMD layers") in which interconnection lines and VIA contacts may be formed. That is, the interconnection layer may include interconnection lines and VIA contacts in a plurality of interlayer dielectric layers. The interconnection lines and VIA contacts in the interconnection layer may include conductive materials, including but not limited to W, Co, u, Al, silicide, or any combination thereof. The interlayer dielectric layer in the interconnection layer may include a dielectric material. The dielectric material includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric,
Or any combination thereof.
如圖2A所示，立體記憶體元件200的第一半導體結構202還可以包括在鍵合介面206處並且在互連層和週邊電路208上方的鍵合層210。鍵合層210可以包括多個鍵合接觸211以及將鍵合接觸211電性隔離的介電材料。鍵合接觸211可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、矽化物、或其任何組合。鍵合層210的剩餘區域可以利用介電材料來形成，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電、或其任何組合。在鍵合層210中的鍵合接觸211和周圍介電可以用於混合鍵合。
As shown in FIG. 2A, the first semiconductor structure 202 of the three-dimensional memory device 200 may further include a bonding layer 210 at the bonding interface 206 and above the interconnection layer and the peripheral circuit 208. The bonding layer 210 may include a plurality of bonding contacts 211 and a dielectric material that electrically isolates the bonding contacts 211. The bonding contact 211 may include a conductive material, and the conductive material includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 210 can be formed using a dielectric material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contact 211 and the surrounding dielectric in the bonding layer 210 may be used for hybrid bonding.
類似地，如圖2A所示，立體記憶體元件200的第二半導體結構204也可以包括在鍵合介面206處並且在第一半導體結構202的鍵合層210上方的鍵合層212。鍵合層212可以包括多個鍵合接觸213以及將鍵合接觸213電性隔離的介電材料。鍵合接觸213可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、矽化物、或其任何組合。鍵合層212的剩餘區域可以利用介電來形成，介電包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電、或其任何組合。在鍵合層212中的鍵合接觸213和周圍介電材料可以用於混合鍵合。根據一些實施例，鍵合接觸213是在鍵合介面206處與鍵合接觸211接觸的。
Similarly, as shown in FIG. 2A, the second semiconductor structure 204 of the three-dimensional memory device 200 may also include a bonding layer 212 at the bonding interface 206 and above the bonding layer 210 of the first semiconductor structure 202. The bonding layer 212 may include a plurality of bonding contacts 213 and a dielectric material that electrically isolates the bonding contacts 213. The bonding contact 213 may include a conductive material, and the conductive material includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 212 can be formed using a dielectric, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contact 213 and the surrounding dielectric material in the bonding layer 212 may be used for hybrid bonding. According to some embodiments, the bonding contact 213 is in contact with the bonding contact 211 at the bonding interface 206.
如以下詳細描述的，第二半導體結構204可以在鍵合介面206處以面對面的方式被鍵合在第一半導體結構202的頂部上。在本發明的其中一些實施例中，作為混合鍵合(也被稱為“金屬/介電混合鍵合”)的結構，鍵合介面206被設置在鍵合層210和鍵合層212之間，混合鍵合是一種直接鍵合技術(例如，在表面之間形成鍵合而不使用例如焊料或黏合劑之類的中間層)，並且可以同時獲得
金屬-金屬鍵合和介電-介電鍵合。在本發明的其中一些實施例中，鍵合介面206是鍵合層212和鍵合層210相遇並且鍵合的位置。實際上，鍵合介面206可以是具有特定厚度的層，其包括第一半導體結構202的鍵合層210的頂表面和第二半導體結構204的鍵合層212的底表面。
As described in detail below, the second semiconductor structure 204 may be bonded on top of the first semiconductor structure 202 at the bonding interface 206 in a face-to-face manner. In some embodiments of the present invention, as a hybrid bonding (also called "metal/dielectric hybrid bonding") structure, the bonding interface 206 is provided between the bonding layer 210 and the bonding layer 212 , Hybrid bonding is a direct bonding technique (for example, forming a bond between surfaces without using an intermediate layer such as solder or adhesive), and can be obtained at the same time
Metal-metal bonding and dielectric-dielectric bonding. In some embodiments of the present invention, the bonding interface 206 is a position where the bonding layer 212 and the bonding layer 210 meet and bond. In fact, the bonding interface 206 may be a layer with a specific thickness, which includes the top surface of the bonding layer 210 of the first semiconductor structure 202 and the bottom surface of the bonding layer 212 of the second semiconductor structure 204.
在本發明的其中一些實施例中，立體記憶體元件200的第二半導體結構204還包括在鍵合層212上方的互連層(未示出)以傳送電信號。互連層可以包括多個互連，例如中段(MEOL)互連和後段(BEOL)互連。互連層還可以包括互連線和VIA接觸可以形成在其中的一個或多個層間介電層。在互連層中的互連線和VIA接觸可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、矽化物、或其任何組合。在互連層中的層間介電層可以包括介電材料，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電、或其任何組合。
In some embodiments of the present invention, the second semiconductor structure 204 of the three-dimensional memory device 200 further includes an interconnection layer (not shown) above the bonding layer 212 to transmit electrical signals. The interconnection layer may include a plurality of interconnections, such as a middle-level (MEOL) interconnection and a back-end (BEOL) interconnection. The interconnection layer may also include one or more interlayer dielectric layers in which interconnection lines and VIA contacts may be formed. The interconnection lines and VIA contacts in the interconnection layer may include conductive materials, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The interlayer dielectric layer in the interconnection layer may include a dielectric material. The dielectric material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.
在本發明的其中一些實施例中，立體記憶體元件200是NAND快閃記憶體元件，其中儲存單元是以NAND記憶體串陣列的形式提供的。如圖2A所示，立體記憶體元件200的第二半導體結構204可以包括用作NAND記憶體串陣列的通道結構224的陣列。如圖2A所示，各個通道結構224可以垂直地延伸穿過各自包括導電層216和介電層218的多個對。交錯的導電層216和介電層218是儲存堆疊層214的一部分。儲存堆疊層214中的導電層216和介電層218的對數量(例如，32、64、96、128、160、192、224、256或更多)確定立體記憶體元件200中的儲存單元的數量。應理解，在本發明的其中一些實施例中，儲存堆疊層214可以具有多堆疊架構(未示出)，其包括堆疊在彼此之上的多個記憶體堆疊。各個記憶體堆疊中的導電層216和介電層218的對數量可以相同或不同。
In some embodiments of the present invention, the three-dimensional memory device 200 is a NAND flash memory device, and the storage unit is provided in the form of a NAND memory string array. As shown in FIG. 2A, the second semiconductor structure 204 of the three-dimensional memory device 200 may include an array of channel structures 224 used as an array of NAND memory strings. As shown in FIG. 2A, each channel structure 224 may extend vertically through multiple pairs each including a conductive layer 216 and a dielectric layer 218. The interleaved conductive layers 216 and dielectric layers 218 are part of the storage stack 214. The number of pairs (for example, 32, 64, 96, 128, 160, 192, 224, 256 or more) of the conductive layer 216 and the dielectric layer 218 in the storage stack 214 determines the size of the storage unit in the three-dimensional memory device 200 quantity. It should be understood that, in some embodiments of the present invention, the storage stack 214 may have a multi-stack structure (not shown), which includes a plurality of memory stacks stacked on top of each other. The number of pairs of conductive layers 216 and dielectric layers 218 in each memory stack may be the same or different.
儲存堆疊層214可以包括多個交錯的導電層216和介電層218。儲存堆疊層214中的導電層216和介電層218可以在垂直方向上交替。換句話說，除了在儲存堆疊層214的頂部或底部的層之外，各個導電層216可以被在兩側的兩個介電層218鄰接，並且各個介電層218可以被在兩側的兩個導電層216鄰接。導電層216可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、多晶矽、摻雜矽、矽化物、或其任何組合。各個導電層216可以包括被黏合層和閘極介電層圍繞的閘電極(閘極線)。導電層216的閘電極可以作為字元線橫向地延伸，在儲存堆疊層214的一個或多個階梯結構處終止。介電層218可以包括介電材料，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、或其任何組合。
The storage stack 214 may include a plurality of interlaced conductive layers 216 and dielectric layers 218. The conductive layers 216 and the dielectric layers 218 in the storage stack 214 may alternate in the vertical direction. In other words, in addition to the layers on the top or bottom of the storage stack 214, each conductive layer 216 may be abutted by two dielectric layers 218 on both sides, and each dielectric layer 218 may be abutted by two dielectric layers 218 on both sides. Two conductive layers 216 are adjacent to each other. The conductive layer 216 may include a conductive material, and the conductive material includes but is not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 216 may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the conductive layer 216 may extend laterally as a word line and terminate at one or more stepped structures of the storage stack 214. The dielectric layer 218 may include a dielectric material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
如圖2A所示，立體記憶體元件200的第二半導體結構204還可以包括在儲存堆疊層214上方的P型摻雜半導體層220。P型摻雜半導體層220可以是如上所述的“側壁SEG”的示例。P型摻雜半導體層220可以包括半導體材料，例如矽。
在本發明的其中一些實施例中，P型摻雜半導體層220包括透過沉積技術形成的多晶矽，如以下詳細描述的。P型摻雜半導體層220可以是利用任何合適的P型摻雜劑(例如，硼(B)、鎵(Ga)或鋁(Al))摻雜到本征半導體中，產生被稱為“電洞”的價電子的缺陷。例如，P型摻雜半導體層220可以是摻雜有P型摻雜劑(例如，B、Ga或Al)的多晶矽層。
As shown in FIG. 2A, the second semiconductor structure 204 of the three-dimensional memory device 200 may further include a P-type doped semiconductor layer 220 above the storage stack layer 214. The P-type doped semiconductor layer 220 may be an example of the “sidewall SEG” described above. The P-type doped semiconductor layer 220 may include a semiconductor material, such as silicon.
In some embodiments of the present invention, the P-type doped semiconductor layer 220 includes polysilicon formed by a deposition technique, as described in detail below. The P-type doped semiconductor layer 220 may be doped with any suitable P-type dopant (for example, boron (B), gallium (Ga), or aluminum (Al)) into the intrinsic semiconductor to produce what is called "electricity". The defect of the valence electron of the hole. For example, the P-type doped semiconductor layer 220 may be a polysilicon layer doped with P-type dopants (for example, B, Ga, or Al).
在本發明的其中一些實施例中，立體記憶體元件200的第二半導體結構204還包括P型摻雜半導體層220中的N阱221。N阱221可以摻雜有任何合適的N型摻雜劑(例如，磷(P)、砷(Ar)或銻(Sb))，其貢獻自由電子並且增加本征半導體的導電性。在本發明的其中一些實施例中，N阱221是從P型摻雜半導體層220的底表面摻雜的。應理解，N阱221可以在P型摻雜半導體層220的整個厚度
中垂直地延伸(即，延伸至P型摻雜半導體層220的頂表面)，或者在P型摻雜半導體層220的整個厚度的一部分中垂直地延伸。
In some embodiments of the present invention, the second semiconductor structure 204 of the three-dimensional memory device 200 further includes an N well 221 in the P-type doped semiconductor layer 220. The N-well 221 may be doped with any suitable N-type dopant (for example, phosphorus (P), arsenic (Ar), or antimony (Sb)), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. In some embodiments of the present invention, the N-well 221 is doped from the bottom surface of the P-type doped semiconductor layer 220. It should be understood that the N-well 221 may be within the entire thickness of the P-type doped semiconductor layer 220
It extends vertically (ie, extends to the top surface of the P-type doped semiconductor layer 220), or extends vertically in a portion of the entire thickness of the P-type doped semiconductor layer 220.
在本發明的其中一些實施例中，各個通道結構224包括填充有半導體層(例如，作為半導體通道228)和複合介電層(例如，作為儲存膜226)的通道孔。在本發明的其中一些實施例中，半導體通道228包括矽，例如非晶矽、多晶矽或單晶矽。在本發明的其中一些實施例中，儲存膜226是包括穿隧層、儲存層(也被稱為“電荷捕獲層”)和阻擋層的複合層。通道結構224的剩餘空間，可以部分地或完全地利用包括例如氧化矽之類的介電材料的封蓋層和/或氣隙填充。通道結構224可以具有圓柱形(例如，柱形)。根據一些實施例，封蓋層、半導體通道228、儲存膜226的穿隧層、儲存層和阻擋層是從柱的中心朝向外表面徑向地按此順序佈置的。穿隧層可以包括氧化矽、氮氧化矽或其任何組合。
儲存層可以包括氮化矽、氮氧化矽、矽或其任何組合。阻擋層可以包括氧化矽、氮氧化矽、高k介電或其任何組合。在一個示例中，儲存膜226可以包括氧化矽/氮氧化矽/氧化矽(ONO)的複合層。
In some embodiments of the present invention, each channel structure 224 includes a channel hole filled with a semiconductor layer (for example, as a semiconductor channel 228) and a composite dielectric layer (for example, as a storage film 226). In some embodiments of the present invention, the semiconductor channel 228 includes silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon. In some embodiments of the present invention, the storage film 226 is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trap layer"), and a blocking layer. The remaining space of the channel structure 224 may be partially or completely filled with a capping layer including a dielectric material such as silicon oxide and/or an air gap. The channel structure 224 may have a cylindrical shape (for example, a cylindrical shape). According to some embodiments, the capping layer, the semiconductor channel 228, the tunneling layer of the storage film 226, the storage layer, and the barrier layer are arranged in this order radially from the center of the pillar toward the outer surface. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof.
The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the storage film 226 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
在本發明的其中一些實施例中，通道結構224還包括在通道結構224的底部部分中(例如，在下端處)的通道插塞227。如本文所使用的，當基底201位於立體記憶體元件200的最低平面中時，部件(例如，通道結構224)的“上端”是在y方向上較遠離基底201的端部，而部件(例如，通道結構224)的“下端”是在y方向上較靠近基底201的端部。通道插塞227可以包括半導體材料(例如，多晶矽)。在本發明的其中一些實施例中，通道插塞227用作由NAND記憶體串的汲極。
In some of the embodiments of the present invention, the channel structure 224 further includes a channel plug 227 in the bottom portion of the channel structure 224 (for example, at the lower end). As used herein, when the substrate 201 is located in the lowest plane of the three-dimensional memory element 200, the "upper end" of the component (for example, the channel structure 224) is the end farther from the substrate 201 in the y direction, and the component (for example The "lower end" of the channel structure 224) is the end closer to the substrate 201 in the y direction. The channel plug 227 may include a semiconductor material (for example, polysilicon). In some embodiments of the present invention, the channel plug 227 is used as the drain electrode of the NAND memory string.
如圖2A所示，各個通道結構224可以垂直地延伸，穿過儲存堆疊層214的交錯的導電層216和介電層218，而進入P型摻雜半導體層220中。各個通道結構224的上端可以是與P型摻雜半導體層220的頂表面齊平或在其下方。也就是說，根據一些實施例，通道結構224不延伸超過P型摻雜半導體層220的頂表面。
在本發明的其中一些實施例中，如圖2A所示，儲存膜226的上端在通道結構224中的半導體通道228的上端下方。在本發明的其中一些實施例中，儲存膜226的上端在P型摻雜半導體層220的頂表面下方，並且半導體通道228的上端是與P型摻雜半導體層220的頂表面齊平或在其下方。例如，如圖2A所示，儲存膜226可以在P型摻雜半導體層220的底表面處終止，而半導體通道228可以在P型摻雜半導體層220的底表面上方延伸，使得P型摻雜半導體層220可以圍繞半導體通道228中的延伸進入P型摻雜半導體層220中的頂部部分229，並且與其接觸。在本發明的其中一些實施例中，半導體通道228的延伸進入P型摻雜半導體層220中的頂部部分229的摻雜濃度，不同於半導體通道228的其餘部分的摻雜濃度。例如，除了頂部部分229之外，半導體通道228可以包括未摻雜的多晶矽，頂部部分229可以包括摻雜的多晶矽，以在形成與周圍的P型摻雜半導體層220的電性連接時增加其導電性。
As shown in FIG. 2A, each channel structure 224 may extend vertically, passing through the staggered conductive layer 216 and the dielectric layer 218 of the storage stack 214, and into the P-type doped semiconductor layer 220. The upper end of each channel structure 224 may be flush with or below the top surface of the P-type doped semiconductor layer 220. That is, according to some embodiments, the channel structure 224 does not extend beyond the top surface of the P-type doped semiconductor layer 220.
In some embodiments of the present invention, as shown in FIG. 2A, the upper end of the storage film 226 is below the upper end of the semiconductor channel 228 in the channel structure 224. In some embodiments of the present invention, the upper end of the storage film 226 is below the top surface of the P-type doped semiconductor layer 220, and the upper end of the semiconductor channel 228 is flush with or on the top surface of the P-type doped semiconductor layer 220. Below it. For example, as shown in FIG. 2A, the storage film 226 may terminate at the bottom surface of the P-type doped semiconductor layer 220, and the semiconductor channel 228 may extend above the bottom surface of the P-type doped semiconductor layer 220, so that the P-type doped semiconductor layer 220 The semiconductor layer 220 may surround and contact the top portion 229 in the semiconductor channel 228 extending into the P-type doped semiconductor layer 220. In some embodiments of the present invention, the doping concentration of the top portion 229 of the semiconductor channel 228 extending into the P-type doped semiconductor layer 220 is different from the doping concentration of the rest of the semiconductor channel 228. For example, in addition to the top portion 229, the semiconductor channel 228 may include undoped polysilicon, and the top portion 229 may include doped polysilicon to increase its electrical connection with the surrounding P-type doped semiconductor layer 220. Conductivity.
在本發明的其中一些實施例中，立體記憶體元件200的第二半導體結構204包括在通道結構224的上端上方，並且與其接觸的導電層222。導電層222可以將多個通道結構224電性連接。儘管在圖2A的側視圖中未示出，但是應當理解，導電層222可以是與多個通道結構224接觸的連續導電層(例如，其中具有孔(網格)以允許源極接觸132在平面圖中穿過的導電板)。結果，導電層222和P型摻雜半導體層220可以一起提供在相同塊中的NAND記憶體串陣列的源極(即ACS)之間的電性連接。如圖2A所示，在本發明的其中一些實施例中，導
電層222在橫向方向上包括兩個部分：在P型摻雜半導體層220上的第一部分(在通道結構224的區域外部)，以及鄰接P型摻雜半導體層220並且與通道結構224的上端接觸的第二部分(在通道結構224的區域內)。也就是說，根據一些實施例，導電層222的至少部分(即，第一部分)在P型摻雜半導體層220上。根據一些實施例，導電層222的圍繞各個通道結構224的上端(其延伸進入P型摻雜半導體層220中)的剩餘部分(即，第二部分)是與半導體通道228的頂部部分229接觸的。
如以下詳細描述的，儲存堆疊層214以及導電層222和半導體通道228的頂部部分229，分別形成發生在P型摻雜半導體層220的相對側，這可以不用進行穿過延伸穿過儲存堆疊層214的開口的任何沉積或蝕刻製程，進而降低製造複雜性和成本並且增加成品率和垂直可縮放性。
In some embodiments of the present invention, the second semiconductor structure 204 of the three-dimensional memory device 200 includes a conductive layer 222 above the upper end of the channel structure 224 and in contact therewith. The conductive layer 222 can electrically connect the plurality of channel structures 224. Although not shown in the side view of FIG. 2A, it should be understood that the conductive layer 222 may be a continuous conductive layer in contact with the plurality of channel structures 224 (for example, having holes (mesh) therein to allow the source contact 132 to be in plan view). Through the conductive plate). As a result, the conductive layer 222 and the P-type doped semiconductor layer 220 can together provide an electrical connection between the sources (ie, ACS) of the NAND memory string array in the same block. As shown in Figure 2A, in some of the embodiments of the present invention, the guide
The electrical layer 222 includes two parts in the lateral direction: the first part on the P-type doped semiconductor layer 220 (outside the region of the channel structure 224), and the upper end adjacent to the P-type doped semiconductor layer 220 and connected to the channel structure 224. The second part of the contact (in the area of the channel structure 224). That is, according to some embodiments, at least part (ie, the first part) of the conductive layer 222 is on the P-type doped semiconductor layer 220. According to some embodiments, the remaining portion (ie, the second portion) of the conductive layer 222 surrounding the upper end of each channel structure 224 (which extends into the P-type doped semiconductor layer 220) is in contact with the top portion 229 of the semiconductor channel 228 .
As described in detail below, the storage stack layer 214 and the conductive layer 222 and the top portion 229 of the semiconductor channel 228 are formed on opposite sides of the P-type doped semiconductor layer 220, respectively, which may not need to extend through the storage stack layer. Any deposition or etching process of the opening of 214, thereby reducing manufacturing complexity and cost, and increasing yield and vertical scalability.
在本發明的其中一些實施例中，導電層222包括在垂直方向上的多個層，包括金屬矽化物層219和在金屬矽化物層219上方的金屬層223。金屬矽化物層219和金屬層223中的每一個可以是連續膜。金屬矽化物層219可以被設置在P型摻雜半導體層220(在導電層222的第一部分中)和通道結構224的上端(在導電層222的第二部分中)上方並且與其接觸。在本發明的其中一些實施例中，金屬矽化物層219的一部分圍繞並且接觸半導體通道228的延伸進入P型摻雜半導體層220中的頂部部分229，以與多個通道結構224進行電性連接。金屬矽化物層219可以包括金屬矽化物，例如矽化銅、矽化鈷、矽化鎳、矽化鈦、矽化鎢、矽化銀、矽化鋁、矽化金、矽化鉑、任何其它合適的金屬矽化物、或其任何組合。
根據一些實施例，金屬層223在金屬矽化物層219上方並且與其接觸。金屬層223可以包括金屬，例如W、Co、Cu、Al、Ni、Ti、任何其它合適的金屬、或其任何組合。應理解，金屬層223中的金屬可以廣義地包括任何合適的導電金屬化合物以及金屬合金，例如氮化鈦和氮化鉭。金屬矽化物層219可以減小在導電層222
與半導體通道228的頂部部分229之間的接觸電阻，以及用作導電層222中的金屬層223的阻隔層。
In some embodiments of the present invention, the conductive layer 222 includes multiple layers in the vertical direction, including a metal silicide layer 219 and a metal layer 223 above the metal silicide layer 219. Each of the metal silicide layer 219 and the metal layer 223 may be a continuous film. The metal silicide layer 219 may be disposed over and in contact with the P-type doped semiconductor layer 220 (in the first part of the conductive layer 222) and the upper end of the channel structure 224 (in the second part of the conductive layer 222). In some embodiments of the present invention, a portion of the metal silicide layer 219 surrounds and contacts the top portion 229 of the semiconductor channel 228 that extends into the P-type doped semiconductor layer 220 to be electrically connected to the plurality of channel structures 224 . The metal silicide layer 219 may include metal silicide, such as copper silicide, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, silver silicide, aluminum silicide, gold silicide, platinum silicide, any other suitable metal silicide, or any of them. combination.
According to some embodiments, the metal layer 223 is over and in contact with the metal silicide layer 219. The metal layer 223 may include a metal, such as W, Co, Cu, Al, Ni, Ti, any other suitable metal, or any combination thereof. It should be understood that the metal in the metal layer 223 may broadly include any suitable conductive metal compound and metal alloy, such as titanium nitride and tantalum nitride. The metal silicide layer 219 can be reduced in the conductive layer 222
The contact resistance with the top portion 229 of the semiconductor channel 228, and serves as a barrier layer for the metal layer 223 in the conductive layer 222.
與單獨的P型摻雜半導體層220相比，透過組合導電層222和P型摻雜半導體層220，可以增加在通道結構224之間(即，在同一塊中的NAND記憶體串的ACS處)的導電性，由此改善立體記憶體元件200的電氣性能。透過引入導電層222，為了維持在通道結構224之間的相同導電性/電阻，可以將P型摻雜半導體層220的厚度例如減小到小於大約50奈米，例如小於50奈米。在本發明的其中一些實施例中，P型摻雜半導體層220的厚度在大約10奈米與大約30奈米之間，例如在10奈米與30奈米之間(例如，10奈米、11奈米、12奈米、13奈米、14奈米、15奈米、16奈米、17奈米、18奈米、19奈米、20奈米、21奈米、22奈米、23奈米、24奈米、25奈米、26奈米、27奈米、28奈米、29奈米、30奈米、由這些值中的任何一個值為下限界定的任何範圍、或在由這些值中的任何兩個值限定的任何範圍中)。P型摻雜半導體層220與圍繞通道結構224的半導體通道228的頂部部分229的導電層222相組合可以實現用於立體記憶體元件200的P阱體擦除操作步驟。本文公開的立體記憶體元件200的設計，可以實現電洞電流路徑與電子電流路徑的分離，以用於分別形成擦除操作步驟和讀取操作步驟。在本發明的其中一些實施例中，根據一些實施例，立體記憶體元件200被配置為在電子源(例如，N阱221)與通道結構224的半導體通道228之間形成電子電流路徑，以在執行讀取操作步驟時向NAND記憶體串提供電子。
相反，根據一些實施例，立體記憶體元件200被配置為在電洞源(例如，P型摻雜半導體層220)與通道結構224的半導體通道228之間形成電洞電流路徑，以在執行P阱體擦除操作步驟時向NAND記憶體串提供電洞。
Compared with the P-type doped semiconductor layer 220 alone, by combining the conductive layer 222 and the P-type doped semiconductor layer 220, the gap between the channel structures 224 (that is, at the ACS of the NAND memory string in the same block) can be increased. ), thereby improving the electrical performance of the three-dimensional memory device 200. By introducing the conductive layer 222, in order to maintain the same conductivity/resistance between the channel structures 224, the thickness of the P-type doped semiconductor layer 220 can be reduced to less than about 50 nanometers, for example, less than 50 nanometers. In some embodiments of the present invention, the thickness of the P-type doped semiconductor layer 220 is between about 10 nanometers and about 30 nanometers, such as between 10 nanometers and 30 nanometers (for example, 10 nanometers, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, 21nm, 22nm, 23nm Meters, 24 nanometers, 25 nanometers, 26 nanometers, 27 nanometers, 28 nanometers, 29 nanometers, 30 nanometers, any range defined by the lower limit of any one of these values, or any range defined by these values Any two values in any range defined by). The combination of the P-type doped semiconductor layer 220 and the conductive layer 222 surrounding the top portion 229 of the semiconductor channel 228 of the channel structure 224 can implement the P-well erase operation step for the three-dimensional memory device 200. The design of the three-dimensional memory device 200 disclosed herein can realize the separation of the hole current path and the electron current path, so as to form the erase operation step and the read operation step respectively. In some embodiments of the present invention, according to some embodiments, the three-dimensional memory device 200 is configured to form an electron current path between the electron source (for example, the N-well 221) and the semiconductor channel 228 of the channel structure 224, so as to Provide electrons to the NAND memory string when performing the read operation step.
In contrast, according to some embodiments, the three-dimensional memory device 200 is configured to form a hole current path between the hole source (for example, the P-type doped semiconductor layer 220) and the semiconductor channel 228 of the channel structure 224 to perform P Holes are provided to the NAND memory string during the process of erasing the well body.
如圖2A所示，立體記憶體元件200的第二半導體結構204還可以包括絕緣結構230，其各自垂直地延伸穿過儲存堆疊層214的交錯的導電層216和介電層218。根據一些實施例，與進一步延伸進入P型摻雜半導體層220中的通道結構224不同，絕緣結構230在P型摻雜半導體層220的底表面處停止，即，不垂直地延伸進入P型摻雜半導體層220中。也就是說，絕緣結構230的頂表面可以是與P型摻雜半導體層220的底表面齊平。各個絕緣結構230還可以橫向地延伸以將通道結構224分成多個塊。也就是說，儲存堆疊層214可以被絕緣結構230劃分成多個記憶體塊，使得可以將通道結構224的陣列分成各個記憶體塊。與上述現有的3D NAND記憶體元件中的包括正面ACS接觸的縫隙結構不同，根據一些實施例，絕緣結構230其中不包括任何接觸(即，不用作源極接觸)，並且因此不引入與導電層216(包括字元線)的寄生電容和漏電流。在本發明的其中一些實施例中，各個絕緣結構230包括填充有一種或多種介電材料的開口(例如，縫隙)，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽或其任何組合。在一個示例中，各個絕緣結構230可以填充有氧化矽。
As shown in FIG. 2A, the second semiconductor structure 204 of the three-dimensional memory device 200 may further include an insulating structure 230, each of which extends vertically through the interlaced conductive layer 216 and the dielectric layer 218 of the storage stack 214. According to some embodiments, unlike the channel structure 224 that further extends into the P-type doped semiconductor layer 220, the insulating structure 230 stops at the bottom surface of the P-type doped semiconductor layer 220, that is, does not extend vertically into the P-type doped semiconductor layer 220. In the hetero semiconductor layer 220. That is, the top surface of the insulating structure 230 may be flush with the bottom surface of the P-type doped semiconductor layer 220. Each insulating structure 230 may also extend laterally to divide the channel structure 224 into a plurality of blocks. That is, the storage stack 214 can be divided into a plurality of memory blocks by the insulating structure 230, so that the array of the channel structure 224 can be divided into individual memory blocks. Unlike the above-mentioned existing 3D NAND memory device including the front-side ACS contact gap structure, according to some embodiments, the insulating structure 230 does not include any contact therein (that is, not used as a source contact), and therefore does not introduce a conductive layer 216 (including word line) parasitic capacitance and leakage current. In some embodiments of the present invention, each insulating structure 230 includes openings (for example, gaps) filled with one or more dielectric materials. The dielectric materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride or the like. Any combination. In one example, each insulating structure 230 may be filled with silicon oxide.
此外，如以下詳細描述的，因為用於形成絕緣結構230的開口不用於形成P型摻雜半導體層220，所以開口隨著交錯的導電層216和介電層218的數量的增加而增加的高寬比(例如，大於50)將不影響P型摻雜半導體層220和導電層222的形成。
In addition, as described in detail below, because the opening used to form the insulating structure 230 is not used to form the P-type doped semiconductor layer 220, the opening increases as the number of interlaced conductive layers 216 and dielectric layers 218 increases. The aspect ratio (for example, greater than 50) will not affect the formation of the P-type doped semiconductor layer 220 and the conductive layer 222.
如圖2A所示，代替正面源極接觸，立體記憶體元件200可以包括在儲存堆疊層214上方，並且分別與N阱221和P型摻雜半導體層220接觸的背面源極接觸231和源極接觸232。源極接觸231和源極接觸232以及儲存堆疊層214(以及穿過其中的絕緣結構230)可以被設置在P型摻雜半導體層220的相對側，並且因此
被視為“背面”源極接觸。在本發明的其中一些實施例中，與P型摻雜半導體層220接觸的源極接觸232透過P型摻雜半導體層220電性連接到通道結構224的半導體通道228。在本發明的其中一些實施例中，與N阱221接觸的源極接觸231，透過P型摻雜半導體層220，電性連接到通道結構224的半導體通道228。在本發明的其中一些實施例中，源極接觸232不是與絕緣結構230橫向地對準，而是接近通道結構224，以減小在其之間的電性連接的電阻。應理解，雖然如圖2A所示源極接觸231是與絕緣結構230橫向地對準的，但是在一些示例中，源極接觸231可以不是與絕緣結構230橫向地對準的，而是接近通道結構224(例如，橫向地位於絕緣結構230與通道結構224之間)以同樣減小在其之間的電性連接的電阻。如上所述，源極接觸231和源極接觸232可以用於分別在讀取操作步驟和擦除操作步驟期間，單獨地控制電子電流和電洞電流。源極接觸231和源極接觸232可以包括任何合適類型的接觸。在本發明的其中一些實施例中，源極接觸231和源極接觸232包括VIA接觸。在本發明的其中一些實施例中，源極接觸231和源極接觸232包括橫向地延伸的壁狀接觸。源極接觸231和源極接觸232可以包括一個或多個導電層，例如被黏合層(例如，TiN)圍繞的金屬層(例如，W、Co、Cu或Al)或矽化物層。
As shown in FIG. 2A, instead of the front source contact, the three-dimensional memory device 200 may include a back source contact 231 and a source electrode above the storage stack layer 214 and contacting the N well 221 and the P-type doped semiconductor layer 220, respectively. Contact 232. The source contact 231 and the source contact 232 and the storage stack layer 214 (and the insulating structure 230 passing therethrough) may be disposed on opposite sides of the P-type doped semiconductor layer 220, and therefore
It is considered a "backside" source contact. In some embodiments of the present invention, the source contact 232 contacting the P-type doped semiconductor layer 220 is electrically connected to the semiconductor channel 228 of the channel structure 224 through the P-type doped semiconductor layer 220. In some embodiments of the present invention, the source contact 231 contacting the N well 221 is electrically connected to the semiconductor channel 228 of the channel structure 224 through the P-type doped semiconductor layer 220. In some embodiments of the present invention, the source contact 232 is not aligned laterally with the insulating structure 230, but is close to the channel structure 224 to reduce the electrical resistance of the electrical connection therebetween. It should be understood that although the source contact 231 is laterally aligned with the insulating structure 230 as shown in FIG. 2A, in some examples, the source contact 231 may not be laterally aligned with the insulating structure 230, but close to the channel. The structure 224 (for example, laterally located between the insulating structure 230 and the channel structure 224) can also reduce the electrical resistance of the electrical connection therebetween. As described above, the source contact 231 and the source contact 232 can be used to separately control the electron current and the hole current during the read operation step and the erase operation step, respectively. The source contact 231 and the source contact 232 may include any suitable type of contact. In some embodiments of the present invention, the source contact 231 and the source contact 232 include VIA contacts. In some embodiments of the present invention, the source contact 231 and the source contact 232 include laterally extending wall-shaped contacts. The source contact 231 and the source contact 232 may include one or more conductive layers, such as a metal layer (for example, W, Co, Cu, or Al) surrounded by an adhesion layer (for example, TiN) or a silicide layer.
如圖2A所示，立體記憶體元件200還可以包括後段(BEOL)互連層233，其在源極接觸231和源極接觸232上方，並且電性連接到源極接觸231和源極接觸232以用於襯墊輸出，例如，在立體記憶體元件200與外部電路之間傳送電信號。在本發明的其中一些實施例中，互連層233包括在P型摻雜半導體層220上的一個或多個層間介電層234以及在層間介電層234上的重佈線層236。源極接觸231或源極接觸232的上端是與層間介電層234的頂表面和重佈線層236的底表面齊平。源極接觸231和源極接觸232可以透過層間介電層234電性隔離。在本發
明的其中一些實施例中，源極接觸232垂直地延伸穿過層間介電層234和導電層222，進入P型摻雜半導體層220中，以與P型摻雜半導體層220進行電性連接。在本發明的其中一些實施例中，源極接觸231垂直地延伸穿過層間介電層234、導電層222和P型摻雜半導體層220進入N阱221中，以與N阱221進行電性連接。源極接觸231可以包括圍繞其側壁的間隙壁(例如，介電層)，以與P型摻雜半導體層220電性隔離。重佈線層236可以包括兩個電性隔離的互連：與源極接觸232接觸的第一互連236-1以及與源極接觸231接觸的第二互連236-2。
As shown in FIG. 2A, the three-dimensional memory device 200 may further include a back-end (BEOL) interconnection layer 233, which is above the source contact 231 and the source contact 232, and is electrically connected to the source contact 231 and the source contact 232 It is used for pad output, for example, to transmit electrical signals between the three-dimensional memory device 200 and an external circuit. In some embodiments of the present invention, the interconnection layer 233 includes one or more interlayer dielectric layers 234 on the P-type doped semiconductor layer 220 and a rewiring layer 236 on the interlayer dielectric layer 234. The upper end of the source contact 231 or the source contact 232 is flush with the top surface of the interlayer dielectric layer 234 and the bottom surface of the redistribution layer 236. The source contact 231 and the source contact 232 can be electrically isolated by the interlayer dielectric layer 234. In this hair
In some of the embodiments disclosed, the source contact 232 extends vertically through the interlayer dielectric layer 234 and the conductive layer 222, and enters the P-type doped semiconductor layer 220 to be electrically connected to the P-type doped semiconductor layer 220 . In some embodiments of the present invention, the source contact 231 extends vertically through the interlayer dielectric layer 234, the conductive layer 222, and the P-type doped semiconductor layer 220 into the N well 221 to be electrically connected to the N well 221. connect. The source contact 231 may include spacers (for example, a dielectric layer) surrounding its sidewalls to be electrically isolated from the P-type doped semiconductor layer 220. The rewiring layer 236 may include two electrically isolated interconnections: a first interconnection 236-1 in contact with the source contact 232 and a second interconnection 236-2 in contact with the source contact 231.
在互連層233中的層間介電層234可以包括介電材料，介電材料包括但不限於氧化矽、氮化矽、氮氧化矽、低k介電或其任何組合。在互連層233中的重佈線層236可以包括導電材料，導電材料包括但不限於W、Co、Cu、Al、矽化物或其任何組合。在一個示例中，重佈線層236包括Al。在本發明的其中一些實施例中，互連層233還包括鈍化層238，作為用於立體記憶體元件200的鈍化和保護的最外層。重佈線層236的一部分可以從鈍化層238曝露作為接觸襯墊240。
也就是說，立體記憶體元件200的互連層233還可以包括用於導線鍵合和/或與中間層鍵合的接觸襯墊240。
The interlayer dielectric layer 234 in the interconnection layer 233 may include a dielectric material. The dielectric material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The rewiring layer 236 in the interconnection layer 233 may include a conductive material, and the conductive material includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof. In one example, the rewiring layer 236 includes Al. In some embodiments of the present invention, the interconnection layer 233 further includes a passivation layer 238 as the outermost layer for passivation and protection of the three-dimensional memory device 200. A part of the redistribution layer 236 may be exposed from the passivation layer 238 as the contact pad 240.
That is, the interconnection layer 233 of the three-dimensional memory device 200 may further include a contact pad 240 for wire bonding and/or bonding with an intermediate layer.
在本發明的其中一些實施例中，立體記憶體元件200的第二半導體結構204還包括穿過P型摻雜半導體層220的接觸242、接觸243和接觸244。根據一些實施例，由於P型摻雜半導體層220可以包括多晶矽，所以接觸242、接觸243和接觸244是TSC。在本發明的其中一些實施例中，接觸242延伸穿過P型摻雜半導體層220和層間介電層234以與重佈線層236的第一互連236-1接觸，使得P型摻雜半導體層220透過源極接觸232和互連層233的第一互連236-1，電性連接到接觸242。在本發明的其中一些實施例中，接觸243延伸穿過P型摻雜半導體層220和
層間介電層234以與重佈線層236的第二互連236-2接觸，使得N阱221透過源極接觸231和互連層233的第二互連236-2，電性連接到接觸243。在本發明的其中一些實施例中，接觸244延伸穿過P型摻雜半導體層220和層間介電層234，以與接觸襯墊240接觸。接觸242、接觸243和接觸244各自可以包括一個或多個導電層，例如被黏合層(例如，TiN)圍繞的金屬層(例如，W、Co、Cu或Al)或矽化物層。在本發明的其中一些實施例中，至少接觸243和接觸244各自還包括間隙壁(例如，介電層)以將接觸243和接觸244與P型摻雜半導體層220電性隔離。
In some embodiments of the present invention, the second semiconductor structure 204 of the three-dimensional memory device 200 further includes a contact 242, a contact 243 and a contact 244 passing through the P-type doped semiconductor layer 220. According to some embodiments, since the P-type doped semiconductor layer 220 may include polysilicon, the contact 242, the contact 243, and the contact 244 are TSC. In some of the embodiments of the present invention, the contact 242 extends through the P-type doped semiconductor layer 220 and the interlayer dielectric layer 234 to contact the first interconnection 236-1 of the redistribution layer 236, so that the P-type doped semiconductor The layer 220 is electrically connected to the contact 242 through the source contact 232 and the first interconnection 236-1 of the interconnection layer 233. In some of the embodiments of the present invention, the contact 243 extends through the P-type doped semiconductor layer 220 and
The interlayer dielectric layer 234 is in contact with the second interconnection 236-2 of the rewiring layer 236, so that the N well 221 is electrically connected to the contact 243 through the source contact 231 and the second interconnection 236-2 of the interconnection layer 233 . In some embodiments of the present invention, the contact 244 extends through the P-type doped semiconductor layer 220 and the interlayer dielectric layer 234 to contact the contact pad 240. Each of the contact 242, the contact 243, and the contact 244 may include one or more conductive layers, such as a metal layer (for example, W, Co, Cu, or Al) surrounded by an adhesion layer (for example, TiN) or a silicide layer. In some embodiments of the present invention, at least the contact 243 and the contact 244 each further include a spacer (for example, a dielectric layer) to electrically isolate the contact 243 and the contact 244 from the P-type doped semiconductor layer 220.
在本發明的其中一些實施例中，立體記憶體元件200還包括週邊接觸246、週邊接觸247和週邊接觸248，其各自在儲存堆疊層214的外部垂直地延伸。
各個週邊接觸246、週邊接觸247或週邊接觸248可以具有比儲存堆疊層214的深度更大的深度，以在儲存堆疊層214的外部的週邊區域中，從鍵合層212垂直地延伸到P型摻雜半導體層220。在本發明的其中一些實施例中，週邊接觸246在接觸242下方並且與其接觸，使得P型摻雜半導體層220至少透過源極接觸232、互連層233的第一互連236-1、接觸242和週邊接觸246電性連接到第一半導體結構202中的週邊電路208。在本發明的其中一些實施例中，週邊接觸247在接觸243下方並且與其接觸，使得N阱221至少透過源極接觸231、互連層233的第二互連236-2、接觸243和週邊接觸247電性連接到第一半導體結構202中的週邊電路208。也就是說，用於讀取操作步驟和擦除操作步驟的電子電流和電洞電流，可以由週邊電路208透過不同的電性連接來分別控制。在本發明的其中一些實施例中，週邊接觸248在接觸244下方並且與其接觸，使得第一半導體結構202中的週邊電路208至少透過接觸244和週邊接觸248，電性連接到用於襯墊輸出的接觸襯墊240。週邊接觸246、週邊接觸247和週邊接觸248各自可以包括一個或多個導電層，例如被黏合層(例如，TiN)圍繞的金屬層(例如，W、Co、Cu或Al)或
矽化物層。在本發明的其中一些實施例中，導電層222在儲存堆疊層214的區域內，即，不橫向地延伸到週邊區域中，使得接觸242、接觸244和接觸243不垂直地延伸穿過導電層222以便分別與週邊接觸246、接觸248和接觸247接觸。
In some embodiments of the present invention, the three-dimensional memory device 200 further includes a peripheral contact 246, a peripheral contact 247 and a peripheral contact 248, each of which extends vertically outside the storage stack 214.
Each of the peripheral contact 246, the peripheral contact 247, or the peripheral contact 248 may have a greater depth than the depth of the storage stacked layer 214 so as to extend vertically from the bonding layer 212 to the P-type in the peripheral area outside the storage stacked layer 214 The semiconductor layer 220 is doped. In some embodiments of the present invention, the peripheral contact 246 is under and in contact with the contact 242, so that the P-type doped semiconductor layer 220 at least penetrates the source contact 232, the first interconnection 236-1 of the interconnection layer 233, and the contact 242 and the peripheral contact 246 are electrically connected to the peripheral circuit 208 in the first semiconductor structure 202. In some embodiments of the present invention, the peripheral contact 247 is under and in contact with the contact 243, so that the N-well 221 at least penetrates the source contact 231, the second interconnection 236-2 of the interconnection layer 233, the contact 243 and the peripheral contact 247 is electrically connected to the peripheral circuit 208 in the first semiconductor structure 202. In other words, the electron current and hole current used in the reading operation step and the erasing operation step can be separately controlled by the peripheral circuit 208 through different electrical connections. In some of the embodiments of the present invention, the peripheral contact 248 is under and in contact with the contact 244, so that the peripheral circuit 208 in the first semiconductor structure 202 is electrically connected to the pad for output through at least the contact 244 and the peripheral contact 248的contact pad 240. The peripheral contact 246, the peripheral contact 247, and the peripheral contact 248 may each include one or more conductive layers, such as a metal layer (for example, W, Co, Cu, or Al) surrounded by an adhesion layer (for example, TiN) or
Silicide layer. In some embodiments of the present invention, the conductive layer 222 is in the area of the storage stack 214, that is, does not extend laterally into the peripheral area, so that the contact 242, the contact 244, and the contact 243 do not extend vertically through the conductive layer. 222 so as to be in contact with peripheral contact 246, contact 248, and contact 247, respectively.
如圖2A所示，立體記憶體元件200還包括作為互連結構的一部分的各種局部接觸(也被稱為“C1”)，其直接與儲存堆疊層214中的結構接觸。在本發明的其中一些實施例中，局部接觸包括通道局部接觸250，其各自在相應的通道結構224的下端下方，並且與其接觸。各個通道局部接觸250可以電性連接到位元線接觸(未示出)以用於位元線扇出。在本發明的其中一些實施例中，局部接觸還包括字元線局部接觸252，其各自在儲存堆疊層214的階梯結構處的相應導電層216(包括字元線)下方，並且與其接觸以用於字元線扇出。局部接觸(例如，通道局部接觸250和字元線局部接觸252)可以至少透過鍵合層212和鍵合層220電性連接到第一半導體結構202的週邊電路208。局部接觸(例如，通道局部接觸250和字元線局部接觸252)各自可以包括一個或多個導電層，例如被黏合層(例如，TiN)圍繞的金屬層(例如，W、Co、Cu或Al)或矽化物層。
As shown in FIG. 2A, the three-dimensional memory device 200 also includes various local contacts (also referred to as “C1”) as part of the interconnect structure, which directly contact the structures in the storage stack 214. In some of the embodiments of the present invention, the localized contact includes channel localized contacts 250, each of which is below and in contact with the lower end of the corresponding channel structure 224. Each channel partial contact 250 may be electrically connected to a bit line contact (not shown) for bit line fan-out. In some of the embodiments of the present invention, the local contact further includes the word line local contact 252, each of which is under the corresponding conductive layer 216 (including the word line) at the step structure of the storage stack 214 and is in contact with it. Fan out on the character line. The partial contacts (for example, the channel partial contact 250 and the word line partial contact 252) may be electrically connected to the peripheral circuit 208 of the first semiconductor structure 202 through at least the bonding layer 212 and the bonding layer 220. The local contacts (for example, the channel local contact 250 and the word line local contact 252) may each include one or more conductive layers, such as a metal layer (for example, W, Co, Cu, or Al) surrounded by an adhesion layer (for example, TiN). ) Or silicide layer.
圖2B示出了根據本發明內容的一些實施例的又一示例性立體記憶體元件255的橫截面的側視圖。立體記憶體元件255類似於立體記憶體元件200，不同之處在於導電層222和通道結構224的上端的不同結構。應理解，為了便於描述，沒有重複立體記憶體元件255和立體記憶體元件200兩者中的其它相同結構的細節。
FIG. 2B shows a cross-sectional side view of yet another exemplary three-dimensional memory element 255 according to some embodiments of the present disclosure. The three-dimensional memory device 255 is similar to the three-dimensional memory device 200, except that the conductive layer 222 and the upper end of the channel structure 224 have different structures. It should be understood that, for ease of description, other details of the same structure in both the three-dimensional memory element 255 and the three-dimensional memory element 200 are not repeated.
如圖2B所示，根據一些實施例，各個通道結構224還包括鄰接P型摻雜半導體層220的通道插塞225。在本發明的其中一些實施例中，各個通道插塞
225圍繞並且接觸半導體通道228的相應頂部部分229。通道插塞225的頂表面可以是與P型摻雜半導體層220的頂表面齊平。通道插塞225可以具有與半導體通道228的頂部部分229相同的材料(例如，摻雜多晶矽)，並且因此可以被視為通道結構224的半導體通道228的一部分。也就是說，在本發明內容中，被P型摻雜半導體層220圍繞的整個摻雜多晶矽結構，可以被視為通道結構224的上端。因此，根據一些實施例，立體記憶體元件200和立體記憶體元件255兩者中的導電層222(以及其中的金屬矽化物層219)是與通道結構224的上端接觸的。
As shown in FIG. 2B, according to some embodiments, each channel structure 224 further includes a channel plug 225 adjacent to the P-type doped semiconductor layer 220. In some of the embodiments of the present invention, each channel plug
225 surrounds and contacts the corresponding top portion 229 of the semiconductor channel 228. The top surface of the channel plug 225 may be flush with the top surface of the P-type doped semiconductor layer 220. The channel plug 225 may have the same material as the top portion 229 of the semiconductor channel 228 (for example, doped polysilicon), and therefore may be regarded as a part of the semiconductor channel 228 of the channel structure 224. In other words, in the context of the present invention, the entire doped polysilicon structure surrounded by the P-type doped semiconductor layer 220 can be regarded as the upper end of the channel structure 224. Therefore, according to some embodiments, the conductive layer 222 (and the metal silicide layer 219 therein) in both the three-dimensional memory device 200 and the three-dimensional memory device 255 are in contact with the upper end of the channel structure 224.
與立體記憶體元件200中的導電層222不同(如圖2A所示，在立體記憶體元件200中，導電層222的第二部分在P型摻雜半導體層220的頂表面下方，並且圍繞通道結構224的上端)，因為通道結構224的上端還包括圖2B中的通道插塞225，所以整個導電層222在P型摻雜半導體層220的頂表面上方。如圖2B所示，通道結構224的上端的頂表面是與P型摻雜半導體層220的頂表面齊平，並且導電層222被設置在P型摻雜半導體層220和通道結構224的上端上方。換句話說，立體記憶體元件200中的導電層222的、填充在P型摻雜半導體層220與半導體通道228的頂部部分229之間的凹部的一部分，可以被立體記憶體元件255中的通道插塞225代替，使得導電層222可以形成在P型摻雜半導體層220和通道結構224的頂表面上的相同平面中。
Unlike the conductive layer 222 in the three-dimensional memory device 200 (as shown in FIG. 2A, in the three-dimensional memory device 200, the second part of the conductive layer 222 is below the top surface of the P-type doped semiconductor layer 220 and surrounds the channel The upper end of the structure 224), because the upper end of the channel structure 224 also includes the channel plug 225 in FIG. 2B, the entire conductive layer 222 is above the top surface of the P-type doped semiconductor layer 220. As shown in FIG. 2B, the top surface of the upper end of the channel structure 224 is flush with the top surface of the P-type doped semiconductor layer 220, and the conductive layer 222 is disposed above the upper ends of the P-type doped semiconductor layer 220 and the channel structure 224 . In other words, a portion of the conductive layer 222 in the three-dimensional memory device 200 that fills the recess between the P-type doped semiconductor layer 220 and the top portion 229 of the semiconductor channel 228 can be used by the channel in the three-dimensional memory device 255. The plug 225 is replaced, so that the conductive layer 222 may be formed in the same plane on the top surface of the P-type doped semiconductor layer 220 and the channel structure 224.
圖2C示出了根據本發明內容的一些實施例的又一示例性立體記憶體元件260的橫截面的側視圖。立體記憶體元件260類似於立體記憶體元件200，不同之處在於導電層222的不同結構。應理解，為了便於描述，沒有重複立體記憶體元件260和立體記憶體200兩者中的其它相同結構的細節。
FIG. 2C shows a cross-sectional side view of yet another exemplary three-dimensional memory element 260 according to some embodiments of the present disclosure. The three-dimensional memory device 260 is similar to the three-dimensional memory device 200, and the difference lies in the different structure of the conductive layer 222. It should be understood that, for ease of description, other details of the same structure in both the three-dimensional memory element 260 and the three-dimensional memory 200 are not repeated.
如圖2C所示，根據一些實施例，導電層222的金屬層223是與半導體通道228接觸的，並且金屬層223的一部分在金屬矽化物層219上方並且與其接觸。與立體記憶體元件200中的導電層222不同(在立體記憶體元件200中，金屬矽化物層219的一部分在P型摻雜半導體層220的頂表面下方，並且圍繞半導體通道228的頂部部分229)，在立體記憶體元件260中，僅金屬層223在P型摻雜半導體層220的頂表面下方，並且圍繞半導體通道228的頂部部分229。然而，在立體記憶體元件200、立體記憶體元件255和立體記憶體元件260中，導電層222的第一部分具有相同的結構，即，具有在P型摻雜半導體層220上的金屬矽化物層219，以及在金屬矽化物層219上方並且與其接觸的金屬層223。至於導電層222的第二部分(在通道結構224的區域內)，立體記憶體元件200、立體記憶體元件255和立體記憶體元件260中的各種結構，可以是由以下關於製造製程詳細描述的用於形成導電層222的不同示例形成的，例如，如何填充在P型摻雜半導體層220與半導體通道228的頂部部分227之間的凹部的方式。
As shown in FIG. 2C, according to some embodiments, the metal layer 223 of the conductive layer 222 is in contact with the semiconductor channel 228, and a portion of the metal layer 223 is above and in contact with the metal silicide layer 219. Unlike the conductive layer 222 in the three-dimensional memory device 200 (in the three-dimensional memory device 200, a part of the metal silicide layer 219 is below the top surface of the P-type doped semiconductor layer 220 and surrounds the top portion 229 of the semiconductor channel 228 ), in the three-dimensional memory device 260, only the metal layer 223 is below the top surface of the P-type doped semiconductor layer 220 and surrounds the top portion 229 of the semiconductor channel 228. However, in the three-dimensional memory device 200, the three-dimensional memory device 255 and the three-dimensional memory device 260, the first portion of the conductive layer 222 has the same structure, that is, has a metal silicide layer on the P-type doped semiconductor layer 220 219, and a metal layer 223 above and in contact with the metal silicide layer 219. As for the second part of the conductive layer 222 (in the area of the channel structure 224), the various structures of the three-dimensional memory device 200, the three-dimensional memory device 255 and the three-dimensional memory device 260 can be described in detail below regarding the manufacturing process Different examples for forming the conductive layer 222 are formed, for example, how to fill the recesses between the P-type doped semiconductor layer 220 and the top portion 227 of the semiconductor channel 228.
例如，如以下詳細描述的，圖2C中的立體記憶體元件260的金屬矽化物層219可以是用於自動地停止通道結構224的通道孔的蝕刻的停止層的一部分。可以對停止層進行圖案化，以從P型摻雜半導體層220的背面曝露通道結構224的上端，並且停止層的剩餘部分可以作為金屬矽化物層219保留在立體記憶體元件260中。然後，金屬層223可以被形成以填充在P型摻雜半導體層220與半導體通道228的頂部部分229之間的凹部，以及被形成在金屬矽化物層219上。相比之下，在形成導電層222之前，可以去除立體記憶體元件200和立體記憶體元件255中的相同停止層。因此，在從P型摻雜半導體層220的背面去除停止層之後，可以形成立體記憶體元件200和立體記憶體元件255中的金屬矽化物層219，以與通道結構224的上端接觸，其中在立體記憶體元件200中沒有通道插塞225，
而在立體記憶體元件255中包含有通道插塞225，這與立體記憶體元件260中的導電層222相比，可以降低與通道結構224的接觸電阻，但是增加了製程的數量。
For example, as described in detail below, the metal silicide layer 219 of the three-dimensional memory device 260 in FIG. 2C may be a part of a stop layer for automatically stopping the etching of the channel hole of the channel structure 224. The stop layer can be patterned to expose the upper end of the channel structure 224 from the backside of the P-type doped semiconductor layer 220, and the remaining part of the stop layer can be retained in the three-dimensional memory device 260 as the metal silicide layer 219. Then, the metal layer 223 may be formed to fill the recess between the P-type doped semiconductor layer 220 and the top portion 229 of the semiconductor channel 228, and be formed on the metal silicide layer 219. In contrast, before forming the conductive layer 222, the same stop layer in the three-dimensional memory element 200 and the three-dimensional memory element 255 may be removed. Therefore, after removing the stop layer from the backside of the P-type doped semiconductor layer 220, the metal silicide layer 219 in the three-dimensional memory device 200 and the three-dimensional memory device 255 can be formed to contact the upper end of the channel structure 224, wherein There is no channel plug 225 in the three-dimensional memory device 200,
The three-dimensional memory device 255 includes the channel plug 225. Compared with the conductive layer 222 in the three-dimensional memory device 260, the contact resistance with the channel structure 224 can be reduced, but the number of manufacturing processes is increased.
圖3A-3P示出了根據本發明內容的一些實施例的用於形成示例性立體記憶體元件的製造過程。圖5A示出了根據本發明內容的一些實施例的用於形成示例性立體記憶體元件的方法500的流程圖。圖5B示出了根據本發明內容的一些實施例的用於形成示例性立體記憶體元件的另一方法501的流程圖。在圖3A-3P、5A和5B中所描繪的立體記憶體元件的示例包括在圖1A-1C中所描繪的立體記憶體元件100、立體記憶體元件155和立體記憶體元件160。將一起描述圖3A-3P、5A和5B。應理解，在方法500和方法501中所示的操作步驟不具有排他性，並且也可以在所示的操作步驟中的任何操作步驟之前、之後或之間執行其它操作步驟。此外，這些操作步驟中的一些操作步驟可以同時執行，或者以與圖5A和5B中所示的順序不同的循序執行。
3A-3P illustrate a manufacturing process for forming an exemplary three-dimensional memory element according to some embodiments of the present disclosure. FIG. 5A shows a flowchart of a method 500 for forming an exemplary three-dimensional memory element according to some embodiments of the present disclosure. FIG. 5B shows a flowchart of another method 501 for forming an exemplary three-dimensional memory element according to some embodiments of the present disclosure. Examples of the three-dimensional memory device depicted in FIGS. 3A-3P, 5A, and 5B include the three-dimensional memory device 100, the three-dimensional memory device 155, and the three-dimensional memory device 160 depicted in FIGS. 1A-1C. Figures 3A-3P, 5A, and 5B will be described together. It should be understood that the operation steps shown in method 500 and method 501 are not exclusive, and other operation steps may also be performed before, after, or during any operation step in the operation steps shown. In addition, some of these operation steps may be performed at the same time or in a sequential order different from the order shown in FIGS. 5A and 5B.
參考圖5A，方法500從操作步驟502開始，在操作步驟502中，在第一基底上形成週邊電路。第一基底可以是矽基底。如圖3G所示，使用多個製程在矽基底350上形成多個電晶體，多個製程包括但不限於微影、蝕刻、薄膜沉積、熱生長、注入、化學機械拋光(CMP)和任何其它合適的製程。在本發明的其中一些實施例中，透過離子注入和/或熱擴散在矽基底350中形成摻雜區(未示出)，其例如用作電晶體的源極區和/或汲極區。在本發明的其中一些實施例中，還透過濕式蝕刻和/或乾式蝕刻以及薄膜沉積在矽基底350中形成隔離區(例如，淺溝槽隔離(STI))。電晶體可以形成在矽基底350上的週邊電路352。
Referring to FIG. 5A, the method 500 starts from operation step 502. In operation step 502, a peripheral circuit is formed on the first substrate. The first substrate may be a silicon substrate. As shown in FIG. 3G, multiple processes are used to form multiple transistors on the silicon substrate 350. Multiple processes include, but are not limited to, lithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other processes. The right process. In some embodiments of the present invention, a doped region (not shown) is formed in the silicon substrate 350 through ion implantation and/or thermal diffusion, which is used as a source region and/or a drain region of a transistor, for example. In some embodiments of the present invention, an isolation region (for example, shallow trench isolation (STI)) is formed in the silicon substrate 350 through wet etching and/or dry etching and thin film deposition. The transistor may be formed on the peripheral circuit 352 on the silicon substrate 350.
如圖3G所示，在週邊電路352上方形成鍵合層348。鍵合層348包括電
性連接到週邊電路352的鍵合接觸。為了形成鍵合層348，使用一種或多種薄膜沉積製程來沉積層間介電層，例如，化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合；使用濕式蝕刻和/或乾式蝕刻(例如，反應離子蝕刻(RIE))，隨後使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，來形成穿過層間介電層的鍵合接觸。
As shown in FIG. 3G, a bonding layer 348 is formed on the peripheral circuit 352. Bonding layer 348 includes electrical
The bond contacts of the peripheral circuit 352 are connected to each other. In order to form the bonding layer 348, one or more thin film deposition processes are used to deposit the interlayer dielectric layer, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof; Use wet etching and/or dry etching (e.g., reactive ion etching (RIE)) followed by one or more thin film deposition processes (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition) (PVD), any other suitable process, or any combination thereof) to form bond contacts through the interlayer dielectric layer.
可以在第二基底上方，形成各自垂直地延伸穿過儲存堆疊層和N型摻雜半導體層的通道結構。如圖5A所示，方法500進行到操作步驟504，在操作步驟504中，依次形成在第二基底上的犧牲層、在犧牲層上的第一停止層、在第一停止層上的N型摻雜半導體層、以及在N型摻雜半導體層上的介電堆疊層。可以在第二基底的正面上形成犧牲層，在該第二基底上可以形成半導體元件。第二基底可以是矽基底。應理解，由於將從最終產品中去除第二基底，因此第二基底可以是虛設晶圓的一部分，例如，載體基底，其由任何合適的材料(僅舉幾例，例如玻璃、藍寶石、塑膠、矽)製成，以減少第二基底的成本。在本發明的其中一些實施例中，該基底是載體基底，N型摻雜半導體層包括多晶矽，並且介電堆疊層包括交錯的堆疊介電層和堆疊犧牲層。在本發明的其中一些實施例中，堆疊介電層和堆疊犧牲層被交替地沉積在N型摻雜半導體層上以形成介電堆疊層。在本發明的其中一些實施例中，犧牲層包括兩個襯墊氧化物層(也被稱為緩衝層)以及被夾在兩個襯墊氧化物層之間的第二停止層。在本發明的其中一些實施例中，第一停止層包括高k介電層，第二停止層包括氮化矽，並且兩個襯墊氧化物層中的每一個包括氧化矽。
A channel structure may be formed above the second substrate, each vertically extending through the storage stack layer and the N-type doped semiconductor layer. As shown in FIG. 5A, the method 500 proceeds to operation step 504. In operation step 504, a sacrificial layer on the second substrate, a first stop layer on the sacrificial layer, and an N-type stop layer on the first stop layer are sequentially formed. A doped semiconductor layer and a dielectric stack layer on the N-type doped semiconductor layer. A sacrificial layer may be formed on the front surface of the second substrate, and a semiconductor element may be formed on the second substrate. The second substrate may be a silicon substrate. It should be understood that since the second substrate will be removed from the final product, the second substrate may be part of a dummy wafer, such as a carrier substrate, which is made of any suitable material (to name a few, such as glass, sapphire, plastic, Silicon) to reduce the cost of the second substrate. In some embodiments of the present invention, the substrate is a carrier substrate, the N-type doped semiconductor layer includes polysilicon, and the dielectric stack includes interlaced stacked dielectric layers and stacked sacrificial layers. In some of the embodiments of the present invention, the stacked dielectric layer and the stacked sacrificial layer are alternately deposited on the N-type doped semiconductor layer to form a dielectric stack layer. In some embodiments of the present invention, the sacrificial layer includes two pad oxide layers (also referred to as buffer layers) and a second stop layer sandwiched between the two pad oxide layers. In some embodiments of the present invention, the first stop layer includes a high-k dielectric layer, the second stop layer includes silicon nitride, and each of the two pad oxide layers includes silicon oxide.
如圖3A所示，在載體基底302上形成犧牲層303，在犧牲層303上形成
停止層305，並且在停止層305上形成N型摻雜半導體層306。N型摻雜半導體層306可以包括摻雜有N型摻雜劑(例如，P、As或Sb)的多晶矽。犧牲層303可以包括任何合適的犧牲材料，其可以隨後被選擇性地去除，並且犧牲層303包含不同於N型摻雜半導體層306的材料。在本發明的其中一些實施例中，犧牲層303是具有被夾在兩個襯墊氧化物層之間的停止層304的複合介電層。如以下詳細描述的，當從背面去除載體基底302時，停止層304可以充當化學機械拋光(CMP)/蝕刻停止層，並且停止層304可以包括不同於載體基底302的材料的任何合適的材料，例如氮化矽。類似地，當從正面蝕刻通道孔時，停止層305可以充當蝕刻停止層，並且停止層305可以包括相對於多晶矽(在停止層305上的N型摻雜半導體層306的材料)而言具有高蝕刻選擇性(例如，大於大約5)的任何合適的材料。在一個示例中，停止層305可以在稍後製程中從最終產品中去除，並且可以包括高k介電層，僅舉幾例，例如氧化鋁、氧化鉿、氧化鋯或氧化鈦。在另一示例中，停止層305的至少部分可以保留在最終產品中，並且可以包括金屬矽化物，僅舉幾例，例如，矽化銅、矽化鈷、矽化鎳、矽化鈦、矽化鎢、矽化銀、矽化鋁、矽化金、矽化鉑。應理解，在一些示例中，可以在載體基底302和停止層304之間以及在停止層304和停止層305之間形成襯墊氧化物層(例如，氧化矽層)，以鬆弛不同層之間的應力並且避免剝離。
As shown in FIG. 3A, a sacrificial layer 303 is formed on the carrier substrate 302, and a sacrificial layer 303 is formed on the sacrificial layer 303.
A stop layer 305, and an N-type doped semiconductor layer 306 is formed on the stop layer 305. The N-type doped semiconductor layer 306 may include polysilicon doped with N-type dopants (for example, P, As, or Sb). The sacrificial layer 303 may include any suitable sacrificial material, which may be selectively removed later, and the sacrificial layer 303 includes a material different from the N-type doped semiconductor layer 306. In some embodiments of the present invention, the sacrificial layer 303 is a composite dielectric layer with a stop layer 304 sandwiched between two pad oxide layers. As described in detail below, when the carrier substrate 302 is removed from the backside, the stop layer 304 may act as a chemical mechanical polishing (CMP)/etch stop layer, and the stop layer 304 may include any suitable material different from the material of the carrier substrate 302, For example, silicon nitride. Similarly, when the via hole is etched from the front side, the stop layer 305 can serve as an etch stop layer, and the stop layer 305 can include a high level of polysilicon (the material of the N-type doped semiconductor layer 306 on the stop layer 305). Any suitable material with an etch selectivity (e.g., greater than about 5). In one example, the stop layer 305 may be removed from the final product in a later process, and may include a high-k dielectric layer, to name a few, such as aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide. In another example, at least part of the stop layer 305 may remain in the final product, and may include metal silicide, to name a few, for example, copper silicide, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, and silver silicide. , Aluminum silicide, gold silicide, platinum silicide. It should be understood that, in some examples, a pad oxide layer (for example, a silicon oxide layer) may be formed between the carrier substrate 302 and the stop layer 304 and between the stop layer 304 and the stop layer 305 to relax the gap between the different layers. The stress and avoid peeling.
根據一些實施例，為了形成犧牲層303，使用一種或多種薄膜沉積製程在載體基底302上依次沉積氧化矽、氮化矽和氧化矽，薄膜沉積製程包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合。根據一些實施例，為了形成停止層305，使用一種或多種薄膜沉積製程在犧牲層303上沉積高k介電層，薄膜沉積製程包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合。在本發
明的其中一些實施例中，為了形成N型摻雜半導體層306，使用一種或多種薄膜沉積製程(其包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)在停止層305上沉積多晶矽，隨後使用離子注入和/或熱擴散，利用N型摻雜劑(例如，P、As或Sb)摻雜所沉積的多晶矽。在本發明的其中一些實施例中，為了形成N型摻雜半導體層306，當在停止層305上沉積多晶矽時，執行對例如P、As或Sb之類的N型摻雜劑的原位摻雜。在其中停止層305包括金屬矽化物的一些實施例中，將金屬層沉積在犧牲層303上，隨後沉積多晶矽以在金屬層上形成N型摻雜半導體層306。然後，可以透過熱處理(例如，退火、燒結或任何其它合適的製程)在多晶矽和金屬層上執行矽化製程，以將金屬層轉換為金屬矽化物層，作為停止層305。
According to some embodiments, in order to form the sacrificial layer 303, one or more thin film deposition processes are used to sequentially deposit silicon oxide, silicon nitride, and silicon oxide on the carrier substrate 302. The thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), Physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. According to some embodiments, in order to form the stop layer 305, one or more thin film deposition processes are used to deposit a high-k dielectric layer on the sacrificial layer 303. The thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition ( PVD), atomic layer deposition (ALD), or any combination thereof. In this hair
In some of the embodiments mentioned, in order to form the N-type doped semiconductor layer 306, one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition) are used. (ALD) or any combination thereof) Deposit polysilicon on the stop layer 305, and then use ion implantation and/or thermal diffusion to dope the deposited polysilicon with an N-type dopant (for example, P, As, or Sb). In some embodiments of the present invention, in order to form the N-type doped semiconductor layer 306, when polysilicon is deposited on the stop layer 305, in-situ doping of N-type dopants such as P, As, or Sb is performed. miscellaneous. In some embodiments where the stop layer 305 includes a metal silicide, a metal layer is deposited on the sacrificial layer 303, and then polysilicon is deposited to form an N-type doped semiconductor layer 306 on the metal layer. Then, a silicidation process can be performed on the polysilicon and the metal layer through heat treatment (for example, annealing, sintering, or any other suitable process) to convert the metal layer into a metal silicide layer, which serves as the stop layer 305.
如圖3B所示，在N型摻雜半導體層306上形成包括多對的第一介電層(本文中被稱為“堆疊犧牲層”312)和第二介電層(本文中被稱為“堆疊介電層”310，本文一起被稱為“介電層對”)的介電堆疊層308。根據一些實施例，介電堆疊層308包括交錯的堆疊犧牲層312和堆疊介電層310。堆疊介電層310和堆疊犧牲層312可以被交替地沉積在載體基底302上方的N型摻雜半導體層306上，以形成介電堆疊層308。在本發明的其中一些實施例中，各個堆疊介電層310包括氧化矽層，並且各個堆疊犧牲層312包括氮化矽層。介電堆疊層308可以透過一種或多種薄膜沉積製程來形成，薄膜沉積製程包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合。如圖3B所示，可以在介電堆疊層308的邊緣上形成階梯結構。階梯結構可以透過朝向載體基底302對介電堆疊層308的介電層對執行多個所謂的“修整-蝕刻”迴圈來形成。由於施加到介電堆疊層308的介電層對的重複的修整-蝕刻迴圈，介電堆疊層308可以具有一個或多個傾斜的邊緣以及比底部介電層對要短的頂部介電層
對，如圖3B所示。
As shown in FIG. 3B, the N-type doped semiconductor layer 306 is formed on the N-type doped semiconductor layer 306 including a plurality of pairs of a first dielectric layer (referred to herein as a "stacked sacrificial layer" 312) and a second dielectric layer (referred to herein as The "stacked dielectric layer" 310, collectively referred to herein as the "dielectric layer pair") is the dielectric stack layer 308. According to some embodiments, the dielectric stack 308 includes a stacked sacrificial layer 312 and a stacked dielectric layer 310 that are staggered. The stacked dielectric layer 310 and the stacked sacrificial layer 312 may be alternately deposited on the N-type doped semiconductor layer 306 above the carrier substrate 302 to form the dielectric stacked layer 308. In some embodiments of the present invention, each stacked dielectric layer 310 includes a silicon oxide layer, and each stacked sacrificial layer 312 includes a silicon nitride layer. The dielectric stack 308 can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. As shown in FIG. 3B, a step structure may be formed on the edge of the dielectric stack 308. The stepped structure can be formed by performing a plurality of so-called “trimming-etching” loops on the dielectric layer pair of the dielectric stack layer 308 toward the carrier substrate 302. Due to the repeated trim-etch loops of the dielectric layer pair applied to the dielectric stack layer 308, the dielectric stack layer 308 may have one or more slanted edges and a top dielectric layer that is shorter than the bottom dielectric layer pair.
Yes, as shown in Figure 3B.
如圖5A所示，方法500進行到操作步驟506，在操作步驟506中，形成各自垂直地延伸穿過介電堆疊層和N型摻雜半導體層、在第一停止層處停止的多個通道結構。在本發明的其中一些實施例中，為了形成通道結構，蝕刻各自垂直地延伸穿過介電堆疊層和N型摻雜半導體層、在第一停止層處停止的通道孔，並且沿著各個通道孔的側壁依次沉積儲存膜和半導體通道。
As shown in FIG. 5A, the method 500 proceeds to operation step 506. In operation step 506, a plurality of channels each extending vertically through the dielectric stack layer and the N-type doped semiconductor layer and stopping at the first stop layer are formed. structure. In some of the embodiments of the present invention, in order to form the channel structure, the etching each extends vertically through the dielectric stack layer and the N-type doped semiconductor layer, and the channel hole stopped at the first stop layer, and along each channel A storage film and a semiconductor channel are sequentially deposited on the sidewall of the hole.
如圖3B所示，各個通道孔是垂直地延伸穿過介電堆疊層308和N型摻雜半導體層306、在停止層305處停止的開口。在本發明的其中一些實施例中，形成多個開口，使得各個開口成為用於在隨後的製程中生長單獨的通道結構314的位置。在本發明的其中一些實施例中，用於形成通道結構314的通道孔的製造製程，包括濕式蝕刻和/或乾式蝕刻，例如深RIE(DRIE)。根據一些實施例，由於在停止層305的材料(例如，氧化鋁或金屬矽化物)與N型摻雜半導體層306的材料(即，多晶矽)之間的蝕刻選擇性，所以對通道孔的蝕刻繼續直到被停止層305(例如，高k介電層(例如，氧化鋁層)或金屬矽化物層)停止為止。
在本發明的其中一些實施例中，可以控制蝕刻條件(例如，蝕刻速率和時間)，以確保各個通道孔已經到達停止層305並且被其停止，進而將通道孔和其中形成的通道結構314之間的開槽變化最小化。應理解，取決於特定的蝕刻選擇性，一個或多個通道孔可以在很小程度上延伸進入停止層305中，在本發明內容中仍將此視為被停止層305停止。
As shown in FIG. 3B, each via hole is an opening that extends vertically through the dielectric stack layer 308 and the N-type doped semiconductor layer 306 and stops at the stop layer 305. In some embodiments of the present invention, a plurality of openings are formed, so that each opening becomes a position for growing a separate channel structure 314 in a subsequent manufacturing process. In some embodiments of the present invention, the manufacturing process of the channel hole used to form the channel structure 314 includes wet etching and/or dry etching, such as deep RIE (DRIE). According to some embodiments, due to the etching selectivity between the material of the stop layer 305 (for example, aluminum oxide or metal silicide) and the material of the N-type doped semiconductor layer 306 (that is, polysilicon), the etching of the via hole Continue until stopped by the stopped layer 305 (for example, a high-k dielectric layer (for example, an aluminum oxide layer) or a metal silicide layer).
In some of the embodiments of the present invention, the etching conditions (for example, etching rate and time) can be controlled to ensure that each channel hole has reached the stop layer 305 and is stopped by it, and then the channel hole and the channel structure 314 formed therein Minimize the change in slotting between. It should be understood that depending on the specific etching selectivity, one or more via holes may extend into the stop layer 305 to a small extent, and this is still regarded as being stopped by the stop layer 305 in the context of the present invention.
如圖3B所示，包括阻擋層317、儲存層316和穿隧層315的儲存膜以及半導體通道318是沿著通道孔的側壁和底表面按該順序依次形成的。在本發明的
其中一些實施例中，首先使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，沿著通道孔的側壁和底表面按該順序沉積阻擋層317、儲存層316和穿隧層315，以形成儲存膜。然後，可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，在穿隧層315之上沉積例如多晶矽(例如，未摻雜的多晶矽)之類的半導體材料，來形成半導體通道318。在本發明的其中一些實施例中，依次沉積第一氧化矽層、氮化矽層、第二氧化矽層和多晶矽層(“SONO”結構)，以形成儲存膜的阻擋層317、儲存層316和穿隧層315以及半導體通道318。
As shown in FIG. 3B, the storage film including the barrier layer 317, the storage layer 316, and the tunnel layer 315, and the semiconductor channel 318 are sequentially formed in this order along the sidewall and bottom surface of the channel hole. In the present invention
In some of these embodiments, one or more thin film deposition processes (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD)), any other suitable processes, or any combination thereof are first used ), the barrier layer 317, the storage layer 316, and the tunnel layer 315 are deposited in this order along the sidewall and bottom surface of the channel hole to form a storage film. Then, by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof), A semiconductor material such as polysilicon (for example, undoped polysilicon) is deposited on the tunnel layer 315 to form the semiconductor channel 318. In some embodiments of the present invention, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure) are sequentially deposited to form the barrier layer 317 and the storage layer 316 of the storage film. And the tunneling layer 315 and the semiconductor channel 318.
如圖3B所示，在通道孔中並且在半導體通道318之上形成封蓋層以完全或部分地填充通道孔(例如，不具有或具有氣隙)。可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來沉積介電材料(例如，氧化矽)，進而形成封蓋層。然後，可以在通道孔的頂部部分中形成通道插塞。
在本發明的其中一些實施例中，透過化學機械拋光(CMP)、濕式蝕刻和/或乾式蝕刻來去除並且平坦化儲存膜、半導體通道318和封蓋層的在介電堆疊層308的頂表面上的一部分。然後，可以透過將半導體通道318和封蓋層的在通道孔的頂部部分中的一部分進行濕式蝕刻和/或乾式蝕刻，在通道孔的頂部部分中形成凹部。然後，可以透過經由一種或多種薄膜沉積製程(例如，化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)將例如多晶矽之類的半導體材料沉積到凹部中，來形成通道插塞。根據一些實施例，由此形成穿過介電堆疊層308和N型摻雜半導體層306、在停止層305處停止的通道結構314。
As shown in FIG. 3B, a capping layer is formed in the channel hole and over the semiconductor channel 318 to completely or partially fill the channel hole (for example, without or with an air gap). The dielectric can be deposited by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) Material (for example, silicon oxide) to form a capping layer. Then, a channel plug may be formed in the top part of the channel hole.
In some of the embodiments of the present invention, the storage film, the semiconductor channel 318, and the capping layer on the top of the dielectric stack 308 are removed and planarized by chemical mechanical polishing (CMP), wet etching and/or dry etching. The part on the surface. Then, by wet etching and/or dry etching a part of the semiconductor channel 318 and the capping layer in the top part of the channel hole, a recess can be formed in the top part of the channel hole. Then, semiconductor materials such as polysilicon can be deposited through one or more thin film deposition processes (for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof) Into the recess to form a channel plug. According to some embodiments, a channel structure 314 passing through the dielectric stack layer 308 and the N-type doped semiconductor layer 306 and stopping at the stop layer 305 is thereby formed.
如圖5A所示，方法500進行到操作步驟508，在操作步驟508中，例如使用所謂的“閘極替換”製程，利用儲存堆疊層替換介電堆疊層，使得通道結構垂直地延伸穿過儲存堆疊層和N型摻雜半導體層。在本發明的其中一些實施例中，為了利用儲存堆疊層替換介電堆疊層，蝕刻垂直地延伸穿過介電堆疊層、在N型摻雜半導體層處停止的開口，並且穿過開口、利用堆疊導電層替換堆疊犧牲層，以形成包括交錯的堆疊介電層和堆疊導電層的儲存堆疊層。
As shown in FIG. 5A, the method 500 proceeds to operation step 508. In operation step 508, for example, using a so-called "gate replacement" process, the storage stack layer is used to replace the dielectric stack layer so that the channel structure extends vertically through the storage layer. Stacked layers and N-type doped semiconductor layers. In some of the embodiments of the present invention, in order to replace the dielectric stack with a storage stack, the etching extends vertically through the dielectric stack, an opening that stops at the N-type doped semiconductor layer, and passes through the opening, using The stacked conductive layer replaces the stacked sacrificial layer to form a storage stacked layer including staggered stacked dielectric layers and stacked conductive layers.
如圖3C所示，縫隙320是垂直地延伸穿過介電堆疊層308並且在N型摻雜半導體層306處停止的開口。在本發明的其中一些實施例中，用於形成縫隙320的製造製程，包括濕式蝕刻和/或乾式蝕刻，例如DRIE。然後，可以穿過縫隙320執行閘極替換，以利用(在圖3E中所示的)儲存堆疊層330替換介電堆疊層308。
As shown in FIG. 3C, the slit 320 is an opening that extends vertically through the dielectric stack 308 and stops at the N-type doped semiconductor layer 306. In some embodiments of the present invention, the manufacturing process for forming the gap 320 includes wet etching and/or dry etching, such as DRIE. Then, gate replacement may be performed through the gap 320 to replace the dielectric stack layer 308 with the storage stack layer 330 (shown in FIG. 3E).
如圖3D所示，首先透過穿過縫隙320去除(在圖3C中所示的)堆疊犧牲層312來形成橫向凹部322。在本發明的其中一些實施例中，透過穿過縫隙320施加蝕刻劑來去除堆疊犧牲層312，進而產生在堆疊介電層310之間交錯的橫向凹部322。蝕刻劑可以包括對於堆疊介電層310選擇性地蝕刻堆疊犧牲層312的任何合適的蝕刻劑。
As shown in FIG. 3D, the lateral recesses 322 are first formed by removing the stacked sacrificial layer 312 (shown in FIG. 3C) through the gap 320. In some of the embodiments of the present invention, the stacked sacrificial layer 312 is removed by applying an etchant through the gap 320, thereby generating the lateral recesses 322 staggered between the stacked dielectric layers 310. The etchant may include any suitable etchant that selectively etches the stacked sacrificial layer 312 with respect to the stacked dielectric layer 310.
如圖3E所示，將堆疊導電層328(包括閘電極和黏合層)穿過縫隙320沉積到(在圖3D中所示的)橫向凹部322中。在本發明的其中一些實施例中，在堆疊導電層328之前，將閘極介電層332沉積到橫向凹部322中，使得堆疊導電層328被沉積在閘極介電層332上。可以使用一種或多種薄膜沉積製程(例如，原
子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適製程、或其任何組合)來沉積堆疊導電層328，例如金屬層。在本發明的其中一些實施例中，沿著縫隙320的側壁以及在其底部形成閘極介電層332，例如高k介電層。根據一些實施例，由此形成包括交錯的堆疊導電層328和堆疊介電層310的儲存堆疊層330，代替(在圖3D中所示的)介電堆疊層308。
As shown in FIG. 3E, the stacked conductive layer 328 (including the gate electrode and the adhesion layer) is deposited through the gap 320 into the lateral recess 322 (shown in FIG. 3D). In some embodiments of the present invention, before the conductive layer 328 is stacked, the gate dielectric layer 332 is deposited into the lateral recess 322 so that the stacked conductive layer 328 is deposited on the gate dielectric layer 332. One or more thin film deposition processes (for example, the original
Sublayer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, or any combination thereof) is used to deposit the stacked conductive layer 328, such as a metal layer. In some embodiments of the present invention, a gate dielectric layer 332, such as a high-k dielectric layer, is formed along the sidewall of the gap 320 and at the bottom thereof. According to some embodiments, a storage stack 330 including staggered stacked conductive layers 328 and stacked dielectric layers 310 is thereby formed instead of the dielectric stack 308 (shown in FIG. 3D).
如圖5A所示，方法500進行到操作步驟510，在操作步驟510中，形成垂直地延伸穿過儲存堆疊層的絕緣結構。在本發明的其中一些實施例中，為了形成絕緣結構，在形成儲存堆疊層之後，將一種或多種介電材料沉積到開口中以填充開口。如圖3E所示，形成垂直地延伸穿過儲存堆疊層330、在N型摻雜半導體層306的頂表面上停止的絕緣結構336。可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來將一種或多種介電材料(例如，氧化矽)沉積到縫隙320中以完全或部分地填充縫隙320(具有或不具有氣隙)，進而形成絕緣結構336。在本發明的其中一些實施例中，絕緣結構336包括閘極介電層332(例如，包括高k介電)和介電封蓋層334(例如，包括氧化矽)。
As shown in FIG. 5A, the method 500 proceeds to operation 510, in which an insulating structure extending vertically through the storage stack is formed. In some embodiments of the present invention, in order to form an insulating structure, after forming the storage stack layer, one or more dielectric materials are deposited into the opening to fill the opening. As shown in FIG. 3E, an insulating structure 336 extending vertically through the storage stack 330 and stopping on the top surface of the N-type doped semiconductor layer 306 is formed. One or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) can be used to combine one or more thin film deposition processes. Various dielectric materials (for example, silicon oxide) are deposited in the gap 320 to completely or partially fill the gap 320 (with or without an air gap), thereby forming the insulating structure 336. In some embodiments of the present invention, the insulating structure 336 includes a gate dielectric layer 332 (for example, including a high-k dielectric) and a dielectric capping layer 334 (for example, including silicon oxide).
如圖3F所示，在形成絕緣結構336之後，形成包括通道局部接觸344和字元線局部接觸342的局部接觸以及週邊接觸338和週邊接觸340。可以透過使用一種或多種薄膜沉積製程(例如，化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)來在儲存堆疊層330的頂部上沉積介電材料(例如，氧化矽或氮化矽)，進而在儲存堆疊層330上形成局部介電層。可以透過使用濕式蝕刻和/或乾式蝕刻(例如，RIE)來蝕刻穿過局部介電層(和任何其它層間介電層)的接觸開口，隨後使用一種或多種薄膜沉積製程(例
如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來用導電材料填充接觸開口，進而形成通道局部接觸344、字元線局部接觸342以及週邊接觸338和週邊接觸340。
As shown in FIG. 3F, after the insulating structure 336 is formed, a partial contact including a channel partial contact 344 and a word line partial contact 342, and a peripheral contact 338 and a peripheral contact 340 are formed. The medium can be deposited on top of the storage stack 330 by using one or more thin film deposition processes (for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof). An electrical material (for example, silicon oxide or silicon nitride) to form a local dielectric layer on the storage stack 330. The contact openings through the local dielectric layer (and any other interlayer dielectric layers) can be etched through the use of wet etching and/or dry etching (e.g., RIE), followed by one or more thin film deposition processes (e.g.
For example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, or any combination thereof) to fill the contact opening with a conductive material to form a channel local contact 344 , Character line local contact 342 and peripheral contact 338 and peripheral contact 340.
如圖3F所示，在通道局部接觸344、字元線局部接觸342以及週邊接觸338和週邊接觸340上方形成鍵合層346。鍵合層346包括電性連接到通道局部接觸344、字元線局部接觸342以及週邊接觸338和週邊接觸340的鍵合接觸。為了形成鍵合層346，使用一種或多種薄膜沉積製程(例如，化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)來沉積層間介電層，並且使用濕式蝕刻和/或乾式蝕刻(例如，RIE)，隨後使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，穿過層間介電層來形成鍵合接觸。
As shown in FIG. 3F, a bonding layer 346 is formed over the channel partial contact 344, the character line partial contact 342, and the peripheral contact 338 and the peripheral contact 340. The bonding layer 346 includes bonding contacts electrically connected to the channel partial contact 344, the character line partial contact 342, and the peripheral contact 338 and the peripheral contact 340. To form the bonding layer 346, one or more thin film deposition processes (for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof) are used to deposit the interlayer dielectric layer , And use wet etching and/or dry etching (e.g., RIE), followed by one or more thin film deposition processes (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD)) , Any other suitable process, or any combination thereof), through the interlayer dielectric layer to form bonding contacts.
如圖5A所示，方法500進行到操作步驟512，在操作步驟512中，將第一基底和第二基底以面對面的方式鍵合，使得儲存堆疊層在週邊電路上方。鍵合可以包括混合鍵合。如圖3G所示，載體基底302和形成於其上的部件(例如，儲存堆疊層330和穿過其形成的通道結構314)上下翻轉。根據一些實施例，將面朝下的鍵合層346與面朝上的鍵合層348鍵合，即以面對面的方式鍵合，進而在載體基底302和矽基底350之間形成鍵合介面354。在本發明的其中一些實施例中，在鍵合之前，對鍵合表面應用處理製程，例如電漿處理、濕處理和/或熱處理。在鍵合之後，將鍵合層346中的鍵合接觸與鍵合層348中的鍵合接觸彼此對齊並且接觸，使得儲存堆疊層330和穿過其形成的通道結構314可以電性連接到週邊電路352並且在週邊電路352上方。
As shown in FIG. 5A, the method 500 proceeds to operation step 512. In operation step 512, the first substrate and the second substrate are bonded in a face-to-face manner so that the storage stack layer is above the peripheral circuit. Bonding may include hybrid bonding. As shown in FIG. 3G, the carrier substrate 302 and the components formed thereon (for example, the storage stack 330 and the channel structure 314 formed therethrough) are turned upside down. According to some embodiments, the bonding layer 346 facing down and the bonding layer 348 facing up are bonded, that is, bonded in a face-to-face manner, thereby forming a bonding interface 354 between the carrier substrate 302 and the silicon substrate 350 . In some embodiments of the present invention, before bonding, a treatment process, such as plasma treatment, wet treatment, and/or heat treatment, is applied to the bonding surface. After bonding, the bonding contact in the bonding layer 346 and the bonding contact in the bonding layer 348 are aligned and contacted with each other, so that the storage stack 330 and the channel structure 314 formed therethrough can be electrically connected to the periphery The circuit 352 is above the peripheral circuit 352.
如圖5A所示，方法500進行到操作步驟514，在操作步驟514中，依次去除第二基底、犧牲層和第一停止層，以曝露多個通道結構中的每一個的端部。
可以從第二基底的背面執行去除。在本發明的其中一些實施例中，為了依次去除第二基底、犧牲層和第一停止層，去除第二基底，在犧牲層的第二停止層處停止，並且去除犧牲層的剩餘部分，在第一停止層處停止。
As shown in FIG. 5A, the method 500 proceeds to operation step 514. In operation step 514, the second substrate, the sacrificial layer, and the first stop layer are sequentially removed to expose the end of each of the plurality of channel structures.
The removal can be performed from the back of the second substrate. In some of the embodiments of the present invention, in order to sequentially remove the second substrate, the sacrificial layer and the first stop layer, remove the second substrate, stop at the second stop layer of the sacrificial layer, and remove the remaining part of the sacrificial layer. Stop at the first stop level.
如圖3H所示，從背面完全去除載體基底302(以及在圖3G中所示的在載體基底302和停止層304之間的襯墊氧化物層)，直到被停止層304(例如，氮化矽層)停止為止。可以使用化學機械拋光(CMP)、研磨、乾式蝕刻和/或濕式蝕刻來完全地去除載體基底302。在本發明的其中一些實施例中，將載體基底302剝離。在其中載體基底302包括矽並且停止層304包括氮化矽的一些實施例中，使用矽化學機械拋光(CMP)去除載體基底302，當到達具有不同於矽的材料的停止層304(即，充當背面化學機械拋光(CMP)停止層)時，其可以自動地停止。在本發明的其中一些實施例中，使用透過氫氧化四甲基銨(TMAH)的濕式蝕刻來去除基底302(矽基底)，當到達具有不同於矽的材料的停止層304(即，充當背面蝕刻停止層)時，其自動地停止。停止層304可以確保完全去除載體基底302，而無需顧慮在減薄之後的厚度均勻性。
As shown in FIG. 3H, the carrier substrate 302 (and the pad oxide layer between the carrier substrate 302 and the stop layer 304 shown in FIG. 3G) is completely removed from the backside until the stop layer 304 (for example, nitrided The silicon layer) stops. The carrier substrate 302 may be completely removed using chemical mechanical polishing (CMP), grinding, dry etching, and/or wet etching. In some embodiments of the present invention, the carrier substrate 302 is peeled off. In some embodiments where the carrier substrate 302 includes silicon and the stop layer 304 includes silicon nitride, silicon chemical mechanical polishing (CMP) is used to remove the carrier substrate 302, and when it reaches the stop layer 304 having a material other than silicon (ie, acts as It can automatically stop when the backside chemical mechanical polishing (CMP) stop layer). In some of the embodiments of the present invention, wet etching through tetramethylammonium hydroxide (TMAH) is used to remove the substrate 302 (silicon substrate), and when it reaches the stop layer 304 having a material different from silicon (ie, acts as When the backside etching stop layer), it stops automatically. The stop layer 304 can ensure that the carrier substrate 302 is completely removed without worrying about the thickness uniformity after thinning.
如圖3I所示，接下來也可以使用濕式蝕刻，利用例如磷酸和氫氟酸之類的適當蝕刻劑來完全地去除犧牲層303的剩餘部分(例如，在圖3H中所示的停止層304以及在停止層304與停止層305之間的另一襯墊氧化物層)，直到被具有不同材料(例如，高k介電)的停止層305停止為止。如上所述，由於各個通道結構314沒有延伸超過停止層305進入犧牲層303或載體基底302中，因此對載體基底302和犧牲層303的去除不影響通道結構314。如圖3J所示，在其中停止層
305包括高k介電層(與包括金屬矽化物的導電層相反)的一些實施例中，使用濕式蝕刻和/或乾式蝕刻來完全地去除(在圖3I中所示的)停止層305，以曝露通道結構314的上端。
As shown in FIG. 3I, wet etching can also be used next, using an appropriate etchant such as phosphoric acid and hydrofluoric acid to completely remove the remaining part of the sacrificial layer 303 (for example, the stop layer shown in FIG. 3H 304 and another pad oxide layer between the stop layer 304 and the stop layer 305) until it is stopped by the stop layer 305 having a different material (for example, a high-k dielectric). As described above, since each channel structure 314 does not extend beyond the stop layer 305 into the sacrificial layer 303 or the carrier substrate 302, the removal of the carrier substrate 302 and the sacrificial layer 303 does not affect the channel structure 314. As shown in Figure 3J, the stop layer
In some embodiments where 305 includes a high-k dielectric layer (as opposed to a conductive layer including a metal silicide), wet etching and/or dry etching are used to completely remove the stop layer 305 (shown in FIG. 3I), The upper end of the channel structure 314 is exposed.
如圖5A所示，方法500進行到操作步驟516，在操作步驟516中，形成與多個通道結構的端部接觸的導電層。在本發明的其中一些實施例中，導電層包括與多個通道結構的端部和N型摻雜半導體層接觸的金屬矽化物層、以及與金屬矽化物層接觸的金屬層。在本發明的其中一些實施例中，為了形成導電層，去除儲存膜的鄰接N型摻雜半導體層的一部分，以形成圍繞半導體通道的一部分的凹部，並且將半導體通道的該部分摻雜。在本發明的其中一些實施例中，為了形成導電層，將金屬矽化物層形成為在凹部中與半導體通道的摻雜部分接觸、並且在凹部的外部與N型摻雜半導體層接觸。
As shown in FIG. 5A, the method 500 proceeds to operation step 516. In operation step 516, a conductive layer in contact with the ends of a plurality of channel structures is formed. In some embodiments of the present invention, the conductive layer includes a metal silicide layer in contact with the ends of the plurality of channel structures and the N-type doped semiconductor layer, and a metal layer in contact with the metal silicide layer. In some embodiments of the present invention, in order to form the conductive layer, a part of the storage film adjacent to the N-type doped semiconductor layer is removed to form a recess surrounding a part of the semiconductor channel, and this part of the semiconductor channel is doped. In some of the embodiments of the present invention, in order to form the conductive layer, the metal silicide layer is formed to contact the doped portion of the semiconductor channel in the recess, and to contact the N-type doped semiconductor layer outside the recess.
如圖3J所示，去除(在圖3I中所示的)儲存層316、阻擋層317和穿隧層315的鄰接N型摻雜半導體層306的一部分，以形成圍繞半導體通道318的延伸進入N型摻雜半導體層306中的頂部部分的凹部357。在本發明的其中一些實施例中，依次執行兩個濕式蝕刻製程。例如，使用濕式蝕刻，利用例如磷酸之類的適當的蝕刻劑，選擇性地去除包括氮化矽的儲存層316，而不蝕刻包括多晶矽的N型摻雜半導體層306。可以透過控制蝕刻時間和/或蝕刻速率來控制對儲存層316的蝕刻，使得蝕刻不會繼續，而影響儲存層316的被儲存堆疊層330圍繞的其餘部分。然後，可以使用濕式蝕刻，利用例如氫氟酸之類的適當的蝕刻劑，選擇性地去除包括氧化矽的阻擋層317和穿隧層315，而不蝕刻包括多晶矽的N型摻雜半導體層306和半導體通道318。可以透過控制蝕刻時間和/或蝕刻速率來控制對阻擋層317和穿隧層315的蝕刻，使得蝕刻不會繼續而影響阻擋層317和穿隧層
315的被儲存堆疊層330圍繞的其餘部分。在本發明的其中一些實施例中，使用經圖案化的停止層305作為蝕刻遮罩，執行單個乾式蝕刻製程。例如，當執行乾式蝕刻時，可以不去除停止層305，而是替代地可以對其進行圖案化，以僅曝露在通道結構314的上端處的儲存層316、阻擋層317和穿隧層315，同時仍然作為蝕刻遮罩覆蓋其它區域。然後可以執行乾式蝕刻以蝕刻儲存層316、阻擋層317和穿隧層315的鄰接N型摻雜半導體層306的一部分。可以透過控制蝕刻時間和/或蝕刻速率來控制乾式蝕刻，使得蝕刻不會繼續而影響儲存層316、阻擋層317和穿隧層315的被儲存堆疊層330圍繞的其餘部分。一旦完成乾式蝕刻，就可以去除經圖案化的停止層305。
As shown in FIG. 3J, a portion of the storage layer 316, the barrier layer 317, and the tunneling layer 315 (shown in FIG. 3I) adjacent to the N-type doped semiconductor layer 306 is removed to form a portion of the N-type doped semiconductor layer 306 surrounding the semiconductor channel 318. Type doped semiconductor layer 306 at the top portion of the recess 357. In some embodiments of the present invention, two wet etching processes are performed sequentially. For example, wet etching is used to selectively remove the storage layer 316 including silicon nitride using an appropriate etchant such as phosphoric acid, without etching the N-type doped semiconductor layer 306 including polysilicon. The etching of the storage layer 316 can be controlled by controlling the etching time and/or the etching rate, so that the etching will not continue and affect the rest of the storage layer 316 surrounded by the storage stacked layer 330. Then, wet etching can be used to selectively remove the barrier layer 317 including silicon oxide and the tunnel layer 315 using an appropriate etchant such as hydrofluoric acid, without etching the N-type doped semiconductor layer including polysilicon 306 and semiconductor channel 318. The etching of the barrier layer 317 and the tunneling layer 315 can be controlled by controlling the etching time and/or the etching rate, so that the etching will not continue to affect the barrier layer 317 and the tunneling layer.
The remaining part of 315 surrounded by the storage stack 330. In some embodiments of the present invention, the patterned stop layer 305 is used as an etching mask to perform a single dry etching process. For example, when performing dry etching, the stop layer 305 may not be removed, but instead may be patterned to expose only the storage layer 316, the barrier layer 317, and the tunnel layer 315 at the upper end of the channel structure 314, At the same time, it is still used as an etching mask to cover other areas. Then, dry etching may be performed to etch a portion of the storage layer 316, the barrier layer 317, and the tunnel layer 315 adjacent to the N-type doped semiconductor layer 306. The dry etching can be controlled by controlling the etching time and/or the etching rate, so that the etching will not continue to affect the remaining parts of the storage layer 316, the barrier layer 317, and the tunnel layer 315 surrounded by the storage stack 330. Once the dry etching is completed, the patterned stop layer 305 can be removed.
然而，與經由具有高高寬比(例如，大於50)的穿過介電堆疊層308/儲存堆疊層330的開口(例如，圖3D中的縫隙320)、使用正面濕式蝕刻的已知解決方案相比，從背面去除儲存層316、阻擋層317和穿隧層315的鄰接N型摻雜半導體層306的一部分，具有簡單許多的製程難度並且具有更高的生產成品率。可避免由縫隙320的較大高寬比所導致的問題，可以降低製造複雜性和成本，並且可以增加成品率。此外，垂直可縮放性(例如，介電堆疊層308/儲存堆疊層330的增加的層級)也可以得到改進。
However, compared with the known solution of using front wet etching through the opening (for example, the gap 320 in FIG. 3D) through the dielectric stack 308/storage stack 330 with a high aspect ratio (for example, greater than 50) Compared with the solution, removing a part of the storage layer 316, the barrier layer 317, and the tunnel layer 315 adjacent to the N-type doped semiconductor layer 306 from the back surface has a much simpler process difficulty and a higher production yield. The problems caused by the larger aspect ratio of the gap 320 can be avoided, the manufacturing complexity and cost can be reduced, and the yield can be increased. In addition, vertical scalability (eg, increased levels of the dielectric stack 308/storage stack 330) can also be improved.
如圖3J所示，根據一些實施例，可以去除各個通道結構314的儲存膜(包括阻擋層317、儲存層316和穿隧層315)的鄰接N型摻雜半導體層306的頂部部分以形成凹部357，其曝露半導體通道318的頂部部分。在本發明的其中一些實施例中，對半導體通道318的被凹部357曝露的頂部部分進行摻雜，以增加其導電性。例如，可以執行傾斜離子注入製程，以利用任何合適的摻雜劑將半導體通道318(例如，包括多晶矽)的被凹部357曝露的頂部部分摻雜到期望的摻
雜濃度。
As shown in FIG. 3J, according to some embodiments, the top portion of the storage film (including the barrier layer 317, the storage layer 316, and the tunneling layer 315) of each channel structure 314 adjacent to the N-type doped semiconductor layer 306 may be removed to form a recess. 357, which exposes the top part of the semiconductor channel 318. In some embodiments of the present invention, the top portion of the semiconductor channel 318 exposed by the recess 357 is doped to increase its conductivity. For example, an inclined ion implantation process may be performed to dope the top portion of the semiconductor channel 318 (for example, including polysilicon) exposed by the recess 357 to the desired dopant with any suitable dopant.
Miscellaneous concentration.
如圖3K所示，在(圖3J中所示的)凹部357中形成圍繞並且接觸半導體通道318的摻雜頂部部分的導電層359，以及在凹部357的外部在N型摻雜半導體層306上形成導電層359。在本發明的其中一些實施例中，為了形成導電層359，將金屬矽化物層360形成為在凹部357中與半導體通道318的摻雜頂部部分接觸、並且在凹部357的外部與N型摻雜半導體層306接觸，並且在金屬矽化物層360上形成金屬層362。在一個示例中，可以使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，在凹部357的側壁和底表面上以及在N型摻雜半導體層306上沉積金屬膜(例如，Co、Ni或Ti)。金屬膜可以是與N型摻雜半導體層306的多晶矽和半導體通道318的摻雜頂部部分接觸的。然後，可以透過熱處理(例如，退火、燒結或任何其它合適的製程)在金屬膜和多晶矽上執行矽化製程，以沿著凹部357的側壁和底表面以及在N型摻雜半導體層306上形成金屬矽化物層360。然後，可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，在金屬矽化物層360上沉積另一金屬膜(例如，W、Al、Ti、TiN、Co和/或Ni)，以填充凹部357的剩餘空間，進而在金屬矽化物層360上形成金屬層362。在另一示例中，代替分別沉積兩個金屬膜，可以使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，將單個金屬膜(例如，Co、Ni或Ti)沉積到凹部357中，以填充凹部357並且沉積在N型摻雜半導體層306上。然後，可以透過熱處理(例如，退火、燒結或任何其它合適的製程)在金屬膜和多晶矽上執行矽化製程，使得金屬膜的一部分形成沿著凹部357的側壁和
底表面，以及形成在N型摻雜半導體層306上的金屬矽化物層360，而金屬膜的剩餘部分成為在金屬矽化物層360上的金屬層362。可以執行化學機械拋光(CMP)製程，以去除任何多餘的金屬層362。如圖3K所示，根據一些實施例，由此形成包括金屬矽化物層360和金屬層362的導電層359(作為圖1A中的立體記憶體元件100中的導電層122的一個示例)。在本發明的其中一些實施例中，對導電層359進行圖案化和蝕刻以便不覆蓋週邊區域。
As shown in FIG. 3K, a conductive layer 359 surrounding and contacting the doped top portion of the semiconductor channel 318 is formed in the recess 357 (shown in FIG. 3J), and on the N-type doped semiconductor layer 306 outside the recess 357 A conductive layer 359 is formed. In some of the embodiments of the present invention, in order to form the conductive layer 359, the metal silicide layer 360 is formed in the recess 357 to contact the doped top portion of the semiconductor channel 318, and to be N-doped outside the recess 357 The semiconductor layer 306 is in contact, and a metal layer 362 is formed on the metal silicide layer 360. In one example, one or more thin film deposition processes (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) can be used , A metal film (for example, Co, Ni, or Ti) is deposited on the sidewall and bottom surface of the recess 357 and on the N-type doped semiconductor layer 306. The metal film may be in contact with the polysilicon of the N-type doped semiconductor layer 306 and the doped top portion of the semiconductor channel 318. Then, a silicidation process can be performed on the metal film and polysilicon through heat treatment (for example, annealing, sintering, or any other suitable process) to form metal along the sidewall and bottom surface of the recess 357 and on the N-type doped semiconductor layer 306. Silicide layer 360. Then, by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof), Another metal film (for example, W, Al, Ti, TiN, Co, and/or Ni) is deposited on the metal silicide layer 360 to fill the remaining space of the recess 357 to form a metal layer 362 on the metal silicide layer 360. In another example, instead of depositing two metal films separately, one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other A suitable process, or any combination thereof), deposit a single metal film (for example, Co, Ni, or Ti) into the recess 357 to fill the recess 357 and be deposited on the N-type doped semiconductor layer 306. Then, a silicidation process can be performed on the metal film and polysilicon through heat treatment (for example, annealing, sintering, or any other suitable process), so that a part of the metal film is formed along the sidewalls of the recess 357 and
The bottom surface, and the metal silicide layer 360 formed on the N-type doped semiconductor layer 306, and the remaining part of the metal film becomes the metal layer 362 on the metal silicide layer 360. A chemical mechanical polishing (CMP) process can be performed to remove any excess metal layer 362. As shown in FIG. 3K, according to some embodiments, a conductive layer 359 including a metal silicide layer 360 and a metal layer 362 is thus formed (as an example of the conductive layer 122 in the three-dimensional memory device 100 in FIG. 1A). In some embodiments of the present invention, the conductive layer 359 is patterned and etched so as not to cover the peripheral area.
在本發明的其中一些實施例中，為了形成導電層，將摻雜多晶矽沉積到凹部中以與半導體通道的摻雜部分接觸，並且形成與摻雜多晶矽和N型摻雜半導體層接觸的金屬矽化物層。如圖3O所示，在(圖3J中所示的)凹部357中形成通道插塞365，其圍繞並且接觸半導體通道318的摻雜頂部部分。結果，根據一些實施例，由此用通道插塞365替換通道結構314的鄰接N型摻雜半導體層306的被去除的頂部部分(在圖3H中所示)。在本發明的其中一些實施例中，為了形成通道插塞365，使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來將多晶矽沉積到凹部357中以填充凹部357，隨後使用化學機械拋光(CMP)製程來去除在N型摻雜半導體層306的頂表面上方的任何多餘多晶矽。
在本發明的其中一些實施例中，在將多晶矽沉積到凹部357中時，執行對例如P、As或Sb之類的N型摻雜劑的原位摻雜，以摻雜通道插塞365。由於通道插塞365和半導體通道318的摻雜頂部部分可以包括相同的材料(例如，摻雜多晶矽)，所以可以將通道插塞365視為通道結構314的半導體通道318的一部分。
In some of the embodiments of the present invention, in order to form the conductive layer, doped polysilicon is deposited into the recess to contact the doped portion of the semiconductor channel, and a metal silicide is formed in contact with the doped polysilicon and the N-type doped semiconductor layer.物层。 The material layer. As shown in FIG. 3O, a channel plug 365 is formed in the recess 357 (shown in FIG. 3J), which surrounds and contacts the doped top portion of the semiconductor channel 318. As a result, according to some embodiments, the removed top portion of the channel structure 314 adjacent to the N-type doped semiconductor layer 306 (shown in FIG. 3H) is thereby replaced with the channel plug 365. In some embodiments of the present invention, in order to form the channel plug 365, one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), Any other suitable process, or any combination thereof) to deposit polysilicon into the recess 357 to fill the recess 357, and then use a chemical mechanical polishing (CMP) process to remove any excess on the top surface of the N-type doped semiconductor layer 306 Polysilicon.
In some embodiments of the present invention, when polysilicon is deposited into the recess 357, in-situ doping of N-type dopants such as P, As, or Sb is performed to dope the channel plug 365. Since the doped top portion of the channel plug 365 and the semiconductor channel 318 may include the same material (for example, doped polysilicon), the channel plug 365 may be regarded as a part of the semiconductor channel 318 of the channel structure 314.
如圖3O所示，在N型摻雜半導體層306和通道插塞365上形成包括金屬矽化物層360和金屬層362的導電層359。在本發明的其中一些實施例中，首先
在N型摻雜半導體層306和通道插塞365上沉積金屬膜，隨後進行矽化製程，以形成與通道插塞365和N型摻雜半導體層306接觸的金屬矽化物層360。然後，可以在金屬矽化物層360上沉積另一金屬膜以形成金屬層362。在本發明的其中一些實施例中，在N型摻雜半導體層306和通道插塞365上沉積金屬膜，隨後進行矽化製程，使得金屬膜的與N型摻雜半導體層306和通道插塞365接觸的一部分形成金屬矽化物層360，並且金屬膜的剩餘部分成為金屬層362。如圖3O所示，根據一些實施例，由此形成包括金屬矽化物層360和金屬層362的導電層359(作為圖1B中的立體記憶體元件155中的導電層122的一個示例)。在本發明的其中一些實施例中，對導電層359進行圖案化和蝕刻以便不覆蓋週邊區域。
As shown in FIG. 30, a conductive layer 359 including a metal silicide layer 360 and a metal layer 362 is formed on the N-type doped semiconductor layer 306 and the channel plug 365. In some of the embodiments of the present invention, first
A metal film is deposited on the N-type doped semiconductor layer 306 and the channel plug 365, and then a silicidation process is performed to form a metal silicide layer 360 in contact with the channel plug 365 and the N-type doped semiconductor layer 306. Then, another metal film can be deposited on the metal silicide layer 360 to form the metal layer 362. In some embodiments of the present invention, a metal film is deposited on the N-type doped semiconductor layer 306 and the channel plug 365, and then a silicidation process is performed, so that the metal film is combined with the N-type doped semiconductor layer 306 and the channel plug 365. A part of the contact forms the metal silicide layer 360, and the remaining part of the metal film becomes the metal layer 362. As shown in FIG. 30, according to some embodiments, a conductive layer 359 including a metal silicide layer 360 and a metal layer 362 is thereby formed (as an example of the conductive layer 122 in the three-dimensional memory element 155 in FIG. 1B). In some embodiments of the present invention, the conductive layer 359 is patterned and etched so as not to cover the peripheral area.
如圖5A所示，方法500進行到操作步驟518，在操作步驟518中，形成在儲存堆疊層上方並且與N型摻雜半導體層接觸的源極接觸。如圖3L所示，在N型摻雜半導體層306上形成一個或多個層間介電層356。可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它適合的製程、或其任何組合)來在N型摻雜半導體層306的頂表面上沉積介電材料，進而形成層間介電層356。可以形成穿過層間介電層356和導電層359進入N型摻雜半導體層306中的源極接觸開口358。在本發明的其中一些實施例中，使用濕式蝕刻和/或乾式蝕刻(例如，RIE)來形成源極接觸開口358。在本發明的其中一些實施例中，源極接觸開口358進一步延伸進入N型摻雜半導體層306的頂部部分中。穿過層間介電層356的蝕刻製程可以繼續蝕刻N型摻雜半導體層306的一部分。在本發明的其中一些實施例中，在蝕刻穿過層間介電層356和導電層359之後，使用單獨的蝕刻製程來蝕刻N型摻雜半導體層306的一部分。
As shown in FIG. 5A, the method 500 proceeds to operation step 518. In operation step 518, a source contact is formed above the storage stack layer and in contact with the N-type doped semiconductor layer. As shown in FIG. 3L, one or more interlayer dielectric layers 356 are formed on the N-type doped semiconductor layer 306. It is possible to use one or more thin film deposition processes (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, or any combination thereof) in the N-type A dielectric material is deposited on the top surface of the doped semiconductor layer 306 to form an interlayer dielectric layer 356. A source contact opening 358 passing through the interlayer dielectric layer 356 and the conductive layer 359 into the N-type doped semiconductor layer 306 may be formed. In some embodiments of the present invention, wet etching and/or dry etching (for example, RIE) are used to form the source contact opening 358. In some embodiments of the present invention, the source contact opening 358 further extends into the top portion of the N-type doped semiconductor layer 306. The etching process through the interlayer dielectric layer 356 can continue to etch a portion of the N-type doped semiconductor layer 306. In some embodiments of the present invention, after etching through the interlayer dielectric layer 356 and the conductive layer 359, a separate etching process is used to etch a portion of the N-type doped semiconductor layer 306.
如圖3M所示，在N型摻雜半導體層306的背面處的源極接觸開口358(在圖3L中所示)中形成源極接觸364。根據一些實施例，源極接觸364在儲存堆疊層330上方，並且與N型摻雜半導體層306接觸。在本發明的其中一些實施例中，使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，將一種或多種導電材料沉積到源極接觸開口358中，以利用黏合層(例如，TiN)和導體層(例如，W)填充源極接觸開口358。然後可以執行例如化學機械拋光(CMP)之類的平坦化製程以去除多餘的導電材料，使得源極接觸364的頂表面是與層間介電層356的頂表面齊平。
As shown in FIG. 3M, a source contact 364 is formed in the source contact opening 358 (shown in FIG. 3L) at the back surface of the N-type doped semiconductor layer 306. According to some embodiments, the source contact 364 is above the storage stack layer 330 and is in contact with the N-type doped semiconductor layer 306. In some embodiments of the present invention, one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD)), any other suitable process, or Any combination thereof), one or more conductive materials are deposited into the source contact opening 358 to fill the source contact opening 358 with an adhesion layer (for example, TiN) and a conductive layer (for example, W). Then, a planarization process such as chemical mechanical polishing (CMP) may be performed to remove excess conductive material, so that the top surface of the source contact 364 is flush with the top surface of the interlayer dielectric layer 356.
如圖5A所示，方法500進行到操作步驟520，在操作步驟520中，形成在源極接觸上方並且與源極接觸接觸的互連層。在本發明的其中一些實施例中，形成穿過N型摻雜半導體層並且與互連層接觸的接觸，使得N型摻雜半導體層透過源極接觸和互連層電性連接到該接觸。
As shown in FIG. 5A, the method 500 proceeds to operation step 520. In operation step 520, an interconnection layer above and in contact with the source contact is formed. In some embodiments of the present invention, a contact passing through the N-type doped semiconductor layer and in contact with the interconnection layer is formed, so that the N-type doped semiconductor layer is electrically connected to the contact through the source contact and the interconnection layer.
如圖3N所示，形成在源極接觸364上方並且與其接觸的重佈線層370。在本發明的其中一些實施例中，透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，在層間介電層356的頂表面和源極接觸364上沉積導電材料(例如，Al)，進而形成重佈線層370。可以在重佈線層370上形成鈍化層372。在本發明的其中一些實施例中，透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)沉積介電材料(例如，氮化矽)，進而形成鈍化層372。根據一些實施例，由此形成包括層間介電層356、重佈線層370和鈍化
層372的互連層376。
As shown in FIG. 3N, a rewiring layer 370 is formed above and in contact with the source contact 364. In some embodiments of the present invention, by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, Or any combination thereof), a conductive material (for example, Al) is deposited on the top surface of the interlayer dielectric layer 356 and the source contact 364, thereby forming the redistribution layer 370. A passivation layer 372 may be formed on the rewiring layer 370. In some embodiments of the present invention, by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, Or any combination thereof) to deposit a dielectric material (for example, silicon nitride) to form a passivation layer 372. According to some embodiments, the resulting formation includes interlayer dielectric layer 356, rewiring layer 370, and passivation
The interconnection layer 376 of the layer 372.
如圖3L所示，形成各自延伸穿過層間介電層356和N型摻雜半導體層306的接觸開口363和接觸開口361。在本發明的其中一些實施例中，使用濕式蝕刻和/或乾式蝕刻(例如，RIE)，穿過層間介電層356和N型摻雜半導體層306來形成接觸開口363和接觸開口361。在本發明的其中一些實施例中，使用微影來將接觸開口363和接觸開口361進行圖案化以分別與週邊接觸338和週邊接觸340對準。對接觸開口363和接觸開口361的蝕刻，可以在週邊接觸338和週邊接觸340的上端處停止以曝露週邊接觸338和週邊接觸340。如圖3L所示，使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，沿著接觸開口363和接觸開口361的側壁形成間隙壁367，以將N型摻雜半導體層306電性隔離。在本發明的其中一些實施例中，在形成間隙壁367之後，執行對源極接觸開口358的蝕刻，使得不沿著源極接觸開口358的側壁形成間隙壁367，以增加在源極接觸364和N型摻雜半導體層306之間的接觸面積。
As shown in FIG. 3L, contact openings 363 and contact openings 361 each extending through the interlayer dielectric layer 356 and the N-type doped semiconductor layer 306 are formed. In some embodiments of the present invention, wet etching and/or dry etching (eg, RIE) are used to form the contact opening 363 and the contact opening 361 through the interlayer dielectric layer 356 and the N-type doped semiconductor layer 306. In some embodiments of the present invention, lithography is used to pattern the contact opening 363 and the contact opening 361 to align with the peripheral contact 338 and the peripheral contact 340, respectively. The etching of the contact opening 363 and the contact opening 361 can be stopped at the upper ends of the peripheral contact 338 and the peripheral contact 340 to expose the peripheral contact 338 and the peripheral contact 340. As shown in FIG. 3L, one or more thin film deposition processes are used (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) A spacer 367 is formed along the sidewalls of the contact opening 363 and the contact opening 361 to electrically isolate the N-type doped semiconductor layer 306. In some of the embodiments of the present invention, after the spacer 367 is formed, the source contact opening 358 is etched so that the spacer 367 is not formed along the sidewall of the source contact opening 358 to increase the source contact 364. And the contact area between the N-type doped semiconductor layer 306.
如圖3M所示，分別在N型摻雜半導體層306的背面處的接觸開口363和接觸開口361(在圖3L中所示)中形成接觸366和接觸368。根據一些實施例，接觸366和368垂直地延伸穿過層間介電層356和N型摻雜半導體層306。可以使用相同的沉積製程來形成接觸366和368以及源極接觸364以減少沉積製程的數量。在本發明的其中一些實施例中，使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來將一種或多種導電材料沉積到接觸開口363和接觸開口361中，以利用黏合層(例如，TiN)和導體層(例如，W)填充接觸開口
363和接觸開口361。然後可以執行平坦化製程(例如，化學機械拋光(CMP))，以去除多餘的導電材料，使得接觸366和接觸368的頂表面(以及源極接觸364的頂表面)是與層間介電層356的頂表面齊平。在本發明的其中一些實施例中，由於接觸開口363和接觸開口361是分別與週邊接觸338和週邊接觸340對準的，因此接觸366和接368也分別在週邊接觸338和週邊接觸340上方並且與其接觸。
As shown in FIG. 3M, a contact 366 and a contact 368 are formed in the contact opening 363 and the contact opening 361 (shown in FIG. 3L) at the back surface of the N-type doped semiconductor layer 306, respectively. According to some embodiments, the contacts 366 and 368 extend vertically through the interlayer dielectric layer 356 and the N-type doped semiconductor layer 306. The same deposition process can be used to form the contacts 366 and 368 and the source contact 364 to reduce the number of deposition processes. In some embodiments of the present invention, one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD)), any other suitable process, or Any combination thereof) to deposit one or more conductive materials into the contact opening 363 and the contact opening 361 to fill the contact opening with an adhesion layer (for example, TiN) and a conductive layer (for example, W)
363 and contact opening 361. A planarization process (for example, chemical mechanical polishing (CMP)) can then be performed to remove excess conductive material so that the top surfaces of contacts 366 and 368 (and the top surface of source contact 364) are in contact with the interlayer dielectric layer 356 The top surface is flush. In some of the embodiments of the present invention, since the contact opening 363 and the contact opening 361 are aligned with the peripheral contact 338 and the peripheral contact 340, respectively, the contact 366 and the contact 368 are also above the peripheral contact 338 and the peripheral contact 340, respectively. Contact with it.
如圖3N所示，還形成在接觸366上方並且與其接觸的重佈線層370。
結果，N型摻雜半導體層306可以透過源極接觸364、互連層376的重佈線層370和接觸366電性連接到週邊接觸338。在本發明的其中一些實施例中，N型摻雜半導體層306透過源極接觸364、互連層376、接觸366、週邊接觸338以及鍵合層346和鍵合層348電性連接到週邊電路352。
As shown in FIG. 3N, a rewiring layer 370 above and in contact with the contact 366 is also formed.
As a result, the N-type doped semiconductor layer 306 can be electrically connected to the peripheral contact 338 through the source contact 364, the rewiring layer 370 of the interconnection layer 376, and the contact 366. In some embodiments of the present invention, the N-type doped semiconductor layer 306 is electrically connected to the peripheral circuit through the source contact 364, the interconnection layer 376, the contact 366, the peripheral contact 338, the bonding layer 346 and the bonding layer 348. 352.
如圖3N所示，形成在接觸368上方並且與其接觸的接觸襯墊374。在本發明的其中一些實施例中，透過濕式蝕刻和/或乾式蝕刻來去除鈍化層372的覆蓋接觸368的一部分，以曝露下面的重佈線層370的一部分，進而形成接觸襯墊374。結果，用於襯墊輸出的接觸襯墊374可以透過接觸368、週邊接觸340以及鍵合層346和鍵合層348電性連接到週邊電路352。
As shown in FIG. 3N, a contact pad 374 above and in contact with the contact 368 is formed. In some embodiments of the present invention, a part of the passivation layer 372 covering the contact 368 is removed by wet etching and/or dry etching to expose a part of the underlying redistribution layer 370 to form a contact pad 374. As a result, the contact pad 374 for pad output can be electrically connected to the peripheral circuit 352 through the contact 368, the peripheral contact 340, and the bonding layer 346 and the bonding layer 348.
應理解，方法500中的第一停止層可以是第一導電層(例如，金屬矽化物層)，其部分保留在最終產品中的導電層中，如下文關於方法501描述的。
為了便於描述，可能沒有重複在方法500和501之間的類似操作步驟的細節。參考圖5B，方法501從操作步驟502開始，在操作步驟502中，在第一基底上形成週邊電路。第一基底可以是矽基底。
It should be understood that the first stop layer in the method 500 may be a first conductive layer (for example, a metal silicide layer), part of which remains in the conductive layer in the final product, as described below with respect to the method 501.
For ease of description, the details of similar operation steps between methods 500 and 501 may not be repeated. Referring to FIG. 5B, the method 501 starts from operation step 502. In operation step 502, a peripheral circuit is formed on the first substrate. The first substrate may be a silicon substrate.
如圖5B所示，方法501進行到操作步驟505，在操作步驟505中，依次形成在第二基底上的犧牲層、在犧牲層上的第一導電層、在第一導電層上的N型摻雜半導體層、以及在N型摻雜半導體層上的介電堆疊層。在本發明的其中一些實施例中，第一導電層包括金屬矽化物。如圖3A所示，停止層305可以是包括金屬矽化物的導電層，即金屬矽化物層。應理解，以上與形成載體基底302、犧牲層303和N型摻雜半導體層306相關的描述可以類似地應用於方法501，並且因此，為了便於描述不再重複。
As shown in FIG. 5B, the method 501 proceeds to operation step 505. In operation step 505, a sacrificial layer on the second substrate, a first conductive layer on the sacrificial layer, and an N-type conductive layer on the first conductive layer are sequentially formed. A doped semiconductor layer and a dielectric stack layer on the N-type doped semiconductor layer. In some embodiments of the present invention, the first conductive layer includes metal silicide. As shown in FIG. 3A, the stop layer 305 may be a conductive layer including metal silicide, that is, a metal silicide layer. It should be understood that the above description related to forming the carrier substrate 302, the sacrificial layer 303, and the N-type doped semiconductor layer 306 can be similarly applied to the method 501, and therefore, for convenience of description, it will not be repeated.
如圖5B所示，方法501進行到操作步驟507，在操作步驟507中，形成各自垂直地延伸穿過介電堆疊層和N型摻雜半導體層、在第一導電層處停止的多個通道結構。在本發明的其中一些實施例中，為了形成通道結構，形成各自垂直地延伸穿過介電堆疊層和摻雜元件層、在第一導電層處停止的多個通道孔，並且隨後沿著各個通道孔的側壁沉積儲存膜和半導體通道。
As shown in FIG. 5B, the method 501 proceeds to operation step 507. In operation step 507, a plurality of channels each extending vertically through the dielectric stack layer and the N-type doped semiconductor layer and stopping at the first conductive layer are formed. structure. In some of the embodiments of the present invention, in order to form a channel structure, a plurality of channel holes each extending vertically through the dielectric stack layer and the doped element layer and stopping at the first conductive layer are formed, and then along each A storage film and a semiconductor channel are deposited on the sidewall of the channel hole.
如圖5B所示，方法501進行到操作步驟508，在操作步驟508中，利用儲存堆疊層替換介電堆疊層，使得各個通道結構垂直地延伸穿過儲存堆疊層和N型摻雜半導體層。在本發明的其中一些實施例中，為了利用儲存堆疊層替換介電堆疊層，蝕刻垂直地延伸穿過介電堆疊層、在N型摻雜半導體層處停止的開口，並且穿過開口，利用堆疊導電層替換堆疊犧牲層以形成包括交錯的堆疊介電層和堆疊導電層的儲存堆疊層。
As shown in FIG. 5B, the method 501 proceeds to operation step 508. In operation step 508, the storage stack layer is used to replace the dielectric stack layer so that each channel structure extends vertically through the storage stack layer and the N-type doped semiconductor layer. In some of the embodiments of the present invention, in order to replace the dielectric stack with a storage stack, the etching extends vertically through the dielectric stack, an opening that stops at the N-type doped semiconductor layer, and passes through the opening, using The stacked conductive layer replaces the stacked sacrificial layer to form a storage stacked layer including staggered stacked dielectric layers and stacked conductive layers.
如圖5B所示，方法501進行到操作步驟510，在操作步驟510中，形成垂直地延伸穿過儲存堆疊層的絕緣結構。在本發明的其中一些實施例中，為了形成絕緣結構，在形成儲存堆疊層之後，將一種或多種介電材料沉積到開口中
以填充開口。如圖5B所示，方法501進行到操作步驟512，在操作步驟512中，將第一基底和第二基底晶圓以面對面的方式鍵合，使得儲存堆疊層在週邊電路上方。鍵合可以包括混合鍵合。
As shown in FIG. 5B, the method 501 proceeds to operation 510, in which an insulating structure extending vertically through the storage stack is formed. In some of the embodiments of the present invention, in order to form an insulating structure, after forming the storage stack layer, one or more dielectric materials are deposited into the opening
To fill the opening. As shown in FIG. 5B, the method 501 proceeds to operation step 512. In operation step 512, the first substrate and the second substrate wafer are bonded in a face-to-face manner such that the storage stack layer is above the peripheral circuit. Bonding may include hybrid bonding.
如圖5B所示，方法501進行到操作步驟515，在操作步驟515中，依次去除第二基底、犧牲層、以及第一導電層的一部分，以曝露多個通道結構中的每一個的端部。可以從第二基底的背面執行去除。在本發明的其中一些實施例中，為了依次去除第二基底、犧牲層、以及第一導電層的一部分，去除第二基底，在停止層處停止，去除犧牲層的剩餘部分，在第一導電層處停止，並且去除第一導電層的一部分以曝露多個通道結構中的每一個的端部。
As shown in FIG. 5B, the method 501 proceeds to operation step 515. In operation step 515, the second substrate, the sacrificial layer, and a part of the first conductive layer are sequentially removed to expose the end of each of the plurality of channel structures. . The removal can be performed from the back of the second substrate. In some embodiments of the present invention, in order to sequentially remove the second substrate, the sacrificial layer, and a part of the first conductive layer, the second substrate is removed, stopping at the stop layer, and the remaining part of the sacrificial layer is removed. Stop at the layer, and remove a portion of the first conductive layer to expose the end of each of the plurality of channel structures.
應理解，以上與去除載體基底302和犧牲層303相關的描述可以類似地應用於方法501，並且因此為了便於描述不再重複。如圖3P所示，在去除(圖3G中所示的)犧牲層303之後，去除導電層305(例如，金屬矽化物層)的一部分以曝露通道結構314的上端。可以將導電層305進行圖案化，使得可以使用例如微影、濕式蝕刻和/或乾式蝕刻來去除在各個通道結構314正上方的一部分以曝露各個通道結構314。根據一些實施例，導電層305的剩餘部分保留在N型摻雜半導體層306上。
It should be understood that the above description related to the removal of the carrier substrate 302 and the sacrificial layer 303 can be similarly applied to the method 501, and therefore will not be repeated for ease of description. As shown in FIG. 3P, after the sacrificial layer 303 (shown in FIG. 3G) is removed, a portion of the conductive layer 305 (for example, a metal silicide layer) is removed to expose the upper end of the channel structure 314. The conductive layer 305 may be patterned so that, for example, lithography, wet etching, and/or dry etching may be used to remove a portion directly above each channel structure 314 to expose each channel structure 314. According to some embodiments, the remaining part of the conductive layer 305 remains on the N-type doped semiconductor layer 306.
如圖5B所示，方法501進行到操作步驟517，在操作步驟517中，形成與多個通道結構的端部和第一導電層接觸的第二導電層。第二導電層可以包括金屬。在本發明的其中一些實施例中，為了形成第二導電層，蝕刻儲存膜的鄰接N型摻雜半導體層的一部分以形成圍繞半導體通道的一部分的凹部，對半導體通道的該部分進行摻雜，並且將金屬沉積到凹部中以與半導體通道的摻雜部分
接觸，並且沉積到凹部的外部以與第一導電層接觸。
As shown in FIG. 5B, the method 501 proceeds to operation step 517. In operation step 517, a second conductive layer in contact with the ends of the plurality of channel structures and the first conductive layer is formed. The second conductive layer may include metal. In some embodiments of the present invention, in order to form the second conductive layer, a part of the storage film adjacent to the N-type doped semiconductor layer is etched to form a recess surrounding a part of the semiconductor channel, and this part of the semiconductor channel is doped, And deposit the metal into the recess to interact with the doped part of the semiconductor channel
Contact, and deposit to the outside of the recess to contact the first conductive layer.
應理解，以上與去除儲存層316、阻擋層317和穿隧層315的鄰接N型摻雜半導體層306的一部分，以形成凹部357相關的描述可以類似地應用於方法501，並且因此為了便於描述，不再重複。如圖3P所示，在(圖3J中所示的)凹部357中形成金屬層362，其圍繞並且接觸半導體通道318的摻雜頂部部分，以及在凹部357的外部在導電層305(例如，金屬矽化物層)上形成金屬層362。金屬層362可以圍繞並且接觸通道結構314的在凹部357中的端部(例如，半導體通道318的摻雜部分)。金屬層362也可以在凹部357的外部的導電層305上方並且與其接觸。可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，來沉積金屬膜(例如，W、Al、Ti、TiN、Co和/或Ni)以填充凹部357，並且在凹部357的外部沉積在導電層305上，進而形成金屬層362。可以執行化學機械拋光(CMP)製程以去除任何多餘的金屬層362。根據一些實施例，由此形成包括金屬層362和導電層305的導電層359(作為圖1C中的立體記憶體元件160中的導電層122的一個示例)。在本發明的其中一些實施例中，將導電層359進行圖案化和蝕刻以便不覆蓋週邊區域。與方法500相比，可以透過在最終產品中保留導電層的第一停止層(例如，金屬矽化物層)部分來減少方法501中的製造製程的數量。
It should be understood that the above description related to removing a portion of the storage layer 316, the barrier layer 317, and the tunnel layer 315 adjacent to the N-type doped semiconductor layer 306 to form the recess 357 can be similarly applied to the method 501, and therefore for ease of description , Do not repeat. As shown in FIG. 3P, a metal layer 362 is formed in the recess 357 (shown in FIG. 3J), which surrounds and contacts the doped top portion of the semiconductor channel 318, and a conductive layer 305 (e.g., metal A metal layer 362 is formed on the silicide layer. The metal layer 362 may surround and contact the end portion of the channel structure 314 in the recess 357 (for example, the doped portion of the semiconductor channel 318). The metal layer 362 may also be over and in contact with the conductive layer 305 outside the recess 357. The metal can be deposited by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) A film (for example, W, Al, Ti, TiN, Co, and/or Ni) is used to fill the recess 357 and is deposited on the conductive layer 305 outside the recess 357 to form a metal layer 362. A chemical mechanical polishing (CMP) process can be performed to remove any excess metal layer 362. According to some embodiments, a conductive layer 359 including a metal layer 362 and a conductive layer 305 is thus formed (as an example of the conductive layer 122 in the three-dimensional memory element 160 in FIG. 1C). In some embodiments of the present invention, the conductive layer 359 is patterned and etched so as not to cover the peripheral area. Compared with the method 500, the number of manufacturing processes in the method 501 can be reduced by retaining the first stop layer (for example, the metal silicide layer) portion of the conductive layer in the final product.
如圖5B所示，方法501進行到操作步驟518，在操作步驟518中，形成在儲存堆疊層上方，並且與N型摻雜半導體層接觸的源極接觸。如圖5B所示，方法501進行到操作步驟520，在操作步驟520中，形成在源極接觸上方並且與源極接觸接觸的互連層。在本發明的其中一些實施例中，形成穿過N型摻雜半導體
層，並且與互連層接觸的接觸，使得N型摻雜半導體層透過源極接觸和互連層電性連接到該接觸。
As shown in FIG. 5B, the method 501 proceeds to operation step 518. In operation step 518, the source electrode that is formed above the storage stack layer and is in contact with the N-type doped semiconductor layer is in contact. As shown in FIG. 5B, the method 501 proceeds to operation step 520. In operation step 520, an interconnection layer above and in contact with the source contact is formed. In some of the embodiments of the present invention, a through N-type doped semiconductor is formed
Layer and the contact contact with the interconnection layer, so that the N-type doped semiconductor layer is electrically connected to the contact through the source contact and the interconnection layer.
圖4A-4Q示出了根據本發明內容的一些實施例的用於形成另一示例性立體記憶體元件的製造過程。圖6A示出了根據本發明內容的一些實施例的用於形成另一示例性立體記憶體元件的方法600的流程圖。圖6B示出了根據本發明內容的一些實施例的用於形成另一示例性立體記憶體元件的另一方法601的流程圖。在圖4A-4Q、6A和6B中所描繪的立體記憶體元件的示例包括在圖2A-2C中所描繪的立體記憶體元件200、255和260。將一起描述圖4A-4Q、6A和6B。應理解，在方法600和方法601中所示的操作步驟不具有排他性，並且也可以在所示的操作步驟中的任何操作步驟之前、之後或之間執行其它操作步驟。此外，這些操作步驟中的一些操作步驟可以同時執行，或者以與圖6A和6B中所示的順序不同的循序執行。
4A-4Q illustrate a manufacturing process for forming another exemplary three-dimensional memory element according to some embodiments of the present disclosure. FIG. 6A shows a flowchart of a method 600 for forming another exemplary three-dimensional memory device according to some embodiments of the present disclosure. FIG. 6B shows a flowchart of another method 601 for forming another exemplary three-dimensional memory element according to some embodiments of the present invention. Examples of the three-dimensional memory devices depicted in FIGS. 4A-4Q, 6A, and 6B include the three-dimensional memory devices 200, 255, and 260 depicted in FIGS. 2A-2C. 4A-4Q, 6A, and 6B will be described together. It should be understood that the operation steps shown in method 600 and method 601 are not exclusive, and other operation steps may also be performed before, after, or during any operation step in the operation steps shown. In addition, some of these operation steps may be performed at the same time or in a sequential order different from the order shown in FIGS. 6A and 6B.
參考圖6A，方法600從操作步驟602開始，在操作步驟602中，在第一基底上形成週邊電路。第一基底可以是矽基底。如圖4G所示，使用多個製程在矽基底450上形成多個電晶體，這些製程包括但不限於微影、蝕刻、薄膜沉積、熱生長、注入、化學機械拋光(CMP)和任何其它合適的製程。在本發明的其中一些實施例中，透過離子注入和/或熱擴散來在矽基底450中形成摻雜區(未示出)，其例如用作電晶體的源極區和/或汲極區。在本發明的其中一些實施例中，還透過濕式蝕刻和/或乾式蝕刻以及薄膜沉積來在矽基底450中形成隔離區(例如，淺溝槽隔離(STI))。電晶體可以形成在矽基底450上的週邊電路452。
Referring to FIG. 6A, the method 600 starts from operation step 602. In operation step 602, a peripheral circuit is formed on the first substrate. The first substrate may be a silicon substrate. As shown in FIG. 4G, multiple processes are used to form multiple transistors on the silicon substrate 450. These processes include, but are not limited to, lithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. The manufacturing process. In some of the embodiments of the present invention, a doped region (not shown) is formed in the silicon substrate 450 by ion implantation and/or thermal diffusion, which, for example, serves as the source region and/or drain region of the transistor . In some embodiments of the present invention, an isolation region (for example, shallow trench isolation (STI)) is also formed in the silicon substrate 450 through wet etching and/or dry etching and thin film deposition. The transistor may be formed on the peripheral circuit 452 on the silicon substrate 450.
如圖4G所示，在週邊電路452上方形成鍵合層448。鍵合層448包括電
性連接到週邊電路452的鍵合接觸。為了形成鍵合層448，使用一種或多種薄膜沉積製程(例如，化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)來沉積層間介電層；使用濕式蝕刻和/或乾式蝕刻(例如，RIE)，隨後使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來形成穿過層間介電層的鍵合接觸。
As shown in FIG. 4G, a bonding layer 448 is formed above the peripheral circuit 452. Bonding layer 448 includes electrical
The bond contacts of the peripheral circuit 452 are connected to each other. In order to form the bonding layer 448, one or more thin film deposition processes (for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof) are used to deposit the interlayer dielectric layer ; Use wet etching and/or dry etching (for example, RIE), followed by one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), Any other suitable process, or any combination thereof) to form bonding contacts through the interlayer dielectric layer.
可以在第二基底上方形成各自垂直地延伸穿過儲存堆疊層以及具有N阱的P型摻雜半導體層的通道結構。如圖6A所示，方法600進行到操作步驟604，在操作步驟604中，依次形成在基底上的犧牲層、在犧牲層上的第一停止層、在第一停止層上的具有N阱的P型摻雜半導體層以及在P型摻雜半導體層上的介電堆疊層。可以在第二基底的正面上形成犧牲層，在該第二基底上可以形成半導體元件。第二基底可以是矽基底。應理解，由於將從最終產品中去除第二基底，因此第二基底可以是虛設晶圓的一部分，例如，載體基底，其由任何合適的材料(僅舉幾例，例如玻璃、藍寶石、塑膠、矽)製成，以減少第二基底的成本。在本發明的其中一些實施例中，該基底是載體基底，P型摻雜半導體層包括多晶矽，並且介電堆疊層包括交錯的堆疊介電層和堆疊犧牲層。在本發明的其中一些實施例中，堆疊介電層和堆疊犧牲層被交替地沉積在P型摻雜半導體層上以形成介電堆疊層。在本發明的其中一些實施例中，犧牲層包括兩個襯墊氧化物層(也被稱為緩衝層)和被夾在兩個襯墊氧化物層之間的第二停止層。
在本發明的其中一些實施例中，第一停止層包括高k介電材料，第二停止層包括氮化矽，並且兩個襯墊氧化物層中的每一個包括氧化矽。在本發明的其中一些實施例中，在形成介電堆疊層之前，利用N型摻雜劑來摻雜P型摻雜半導體層的一部分以形成N阱。
A channel structure each vertically extending through the storage stack layer and a P-type doped semiconductor layer with an N well may be formed above the second substrate. As shown in FIG. 6A, the method 600 proceeds to operation step 604. In operation step 604, a sacrificial layer on the substrate, a first stop layer on the sacrificial layer, and an N-well on the first stop layer are sequentially formed. A P-type doped semiconductor layer and a dielectric stack layer on the P-type doped semiconductor layer. A sacrificial layer may be formed on the front surface of the second substrate, and a semiconductor element may be formed on the second substrate. The second substrate may be a silicon substrate. It should be understood that since the second substrate will be removed from the final product, the second substrate may be part of a dummy wafer, such as a carrier substrate, which is made of any suitable material (to name a few, such as glass, sapphire, plastic, Silicon) to reduce the cost of the second substrate. In some embodiments of the present invention, the substrate is a carrier substrate, the P-type doped semiconductor layer includes polysilicon, and the dielectric stack includes alternate stacked dielectric layers and stacked sacrificial layers. In some of the embodiments of the present invention, the stacked dielectric layer and the stacked sacrificial layer are alternately deposited on the P-type doped semiconductor layer to form the dielectric stack layer. In some embodiments of the present invention, the sacrificial layer includes two pad oxide layers (also referred to as buffer layers) and a second stop layer sandwiched between the two pad oxide layers.
In some embodiments of the present invention, the first stop layer includes a high-k dielectric material, the second stop layer includes silicon nitride, and each of the two pad oxide layers includes silicon oxide. In some embodiments of the present invention, before forming the dielectric stack layer, an N-type dopant is used to dope a part of the P-type doped semiconductor layer to form an N-well.
如圖4A所示，在載體基底402上形成犧牲層403，在犧牲層403上形成停止層405，並且在停止層405上形成P型摻雜半導體層406。P型摻雜半導體層406可以包括摻雜有P型摻雜劑(例如，B、Ga或Al)的多晶矽。犧牲層403可以包括任何合適的犧牲材料，其可以隨後被選擇性地去除並且不同於P型摻雜半導體層406的材料。在本發明的其中一些實施例中，犧牲層403是具有被夾在兩個襯墊氧化物層之間的停止層404的複合介電層。如以下詳細描述的，當從背面去除載體基底402時，停止層404可以充當化學機械拋光(CMP)/蝕刻停止層，並且因此可以包括不同於載體基底402的材料的任何合適的材料，例如氮化矽。類似地，當從正面蝕刻通道孔時，停止層405可以充當蝕刻停止層，並且因此可以包括相對於多晶矽(在停止層405上的P型摻雜半導體層406的材料)而言具有高蝕刻選擇性(例如，大於大約5)的任何合適的材料。在一個示例中，停止層405可以在稍後製程中從最終產品中去除，並且可以包括高k介電，僅舉幾例，例如氧化鋁、氧化鉿、氧化鋯或氧化鈦。在另一示例中，停止層405的至少部分可以保留在最終產品中，並且可以包括金屬矽化物，僅舉幾例，例如矽化銅、矽化鈷、矽化鎳、矽化鈦、矽化鎢、矽化銀、矽化鋁、矽化金、矽化鉑。應理解，在一些示例中，可以在載體基底402和停止層404之間以及在停止層404和停止層405之間形成襯墊氧化物層(例如，氧化矽層)，以放鬆不同層之間的應力，並且避免剝離。
As shown in FIG. 4A, a sacrificial layer 403 is formed on the carrier substrate 402, a stop layer 405 is formed on the sacrificial layer 403, and a P-type doped semiconductor layer 406 is formed on the stop layer 405. The P-type doped semiconductor layer 406 may include polysilicon doped with P-type dopants (for example, B, Ga, or Al). The sacrificial layer 403 may include any suitable sacrificial material, which may be selectively removed later and is different from the material of the P-type doped semiconductor layer 406. In some of the embodiments of the present invention, the sacrificial layer 403 is a composite dielectric layer with a stop layer 404 sandwiched between two pad oxide layers. As described in detail below, when the carrier substrate 402 is removed from the backside, the stop layer 404 may act as a chemical mechanical polishing (CMP)/etch stop layer, and therefore may include any suitable material other than the material of the carrier substrate 402, such as nitrogen. Silica. Similarly, when the via hole is etched from the front side, the stop layer 405 can act as an etch stop layer, and therefore can include a high etching option relative to polysilicon (the material of the P-type doped semiconductor layer 406 on the stop layer 405). Any suitable material that is resistant (e.g., greater than about 5). In one example, the stop layer 405 may be removed from the final product in a later process, and may include a high-k dielectric, to name a few, such as aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide. In another example, at least part of the stop layer 405 may remain in the final product, and may include metal silicide, to name a few, such as copper silicide, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, silver silicide, Aluminum silicide, gold silicide, platinum silicide. It should be understood that, in some examples, a pad oxide layer (for example, a silicon oxide layer) may be formed between the carrier substrate 402 and the stop layer 404 and between the stop layer 404 and the stop layer 405 to relax the gap between different layers. The stress, and avoid peeling.
根據一些實施例，為了形成犧牲層403，使用一種或多種薄膜沉積製程來在載體基底402上依次沉積氧化矽、氮化矽和氧化矽，薄膜沉積製程包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合。根據一些實施例，為了形成停止層405，使用一種或多種薄膜沉積
製程來在犧牲層403上沉積高k介電，薄膜沉積製程包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合。在本發明的其中一些實施例中，為了形成P型摻雜半導體層406，使用一種或多種薄膜沉積製程(其包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)來在停止層405上沉積多晶矽，隨後使用離子注入和/或熱擴散來利用P型摻雜劑(例如，B、Ga或Al)摻雜所沉積的多晶矽。
在本發明的其中一些實施例中，為了形成P型摻雜半導體層406，當在停止層405上沉積多晶矽時，執行對例如B、Ga或Al之類的P型摻雜劑的原位摻雜。在其中停止層405包括金屬矽化物的一些實施例中，將金屬層沉積在犧牲層403上，隨後沉積多晶矽以在金屬層上形成P型摻雜半導體層406。然後，透過熱處理(例如，退火、燒結或任何其它合適的製程)在多晶矽和金屬層上執行矽化製程，以將金屬層轉換為金屬矽化物層，作為停止層405。
According to some embodiments, in order to form the sacrificial layer 403, one or more thin film deposition processes are used to sequentially deposit silicon oxide, silicon nitride, and silicon oxide on the carrier substrate 402. The thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD) , Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) or any combination thereof. According to some embodiments, in order to form the stop layer 405, one or more thin film deposits are used
The process is to deposit a high-k dielectric on the sacrificial layer 403. The thin film deposition process includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments of the present invention, in order to form the P-type doped semiconductor layer 406, one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic Layer deposition (ALD) or any combination thereof) to deposit polysilicon on the stop layer 405, followed by ion implantation and/or thermal diffusion to dope the deposited polysilicon with P-type dopants (eg, B, Ga, or Al) .
In some embodiments of the present invention, in order to form the P-type doped semiconductor layer 406, when polysilicon is deposited on the stop layer 405, in-situ doping of P-type dopants such as B, Ga, or Al is performed. miscellaneous. In some embodiments where the stop layer 405 includes a metal silicide, a metal layer is deposited on the sacrificial layer 403, and then polysilicon is deposited to form a P-type doped semiconductor layer 406 on the metal layer. Then, a silicidation process is performed on the polysilicon and metal layer through heat treatment (for example, annealing, sintering, or any other suitable process) to convert the metal layer into a metal silicide layer as the stop layer 405.
如圖4A所示，P型摻雜半導體層406的一部分摻雜有N型摻雜劑(例如，P、As或Sb)，以在P型摻雜半導體層406中形成N阱407。在本發明的其中一些實施例中，使用離子注入和/或熱擴散來形成N阱407。可以控制離子注入和/或熱擴散製程以控制N阱407的厚度(穿過P型摻雜半導體層406的整個厚度或者穿過其部分)。
As shown in FIG. 4A, a portion of the P-type doped semiconductor layer 406 is doped with N-type dopants (for example, P, As, or Sb) to form an N well 407 in the P-type doped semiconductor layer 406. In some of the embodiments of the present invention, ion implantation and/or thermal diffusion are used to form the N-well 407. The ion implantation and/or thermal diffusion process can be controlled to control the thickness of the N well 407 (through the entire thickness of the P-type doped semiconductor layer 406 or through a portion thereof).
如圖4B所示，在P型摻雜半導體層406上形成包括多對的第一介電層(本文中被稱為“堆疊犧牲層”412)和第二介電層(本文中被稱為“堆疊介電層”410，本文中一起被稱為“介電層對”)的介電堆疊層408。根據一些實施例，介電堆疊層408包括交錯的堆疊犧牲層412和堆疊介電層410。堆疊介電層410和堆疊犧牲層412可以被交替地沉積在載體基底402上方的P型摻雜半導體層406
上，以形成介電堆疊層408。在本發明的其中一些實施例中，各個堆疊介電層410包括氧化矽層，並且各個堆疊犧牲層412包括氮化矽層。介電堆疊層408可以是透過一種或多種薄膜沉積製程來形成的，薄膜沉積製程包括但不限於化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合。如圖4B所示，可以在介電堆疊層408的邊緣上形成階梯結構。階梯結構可以透過朝向載體基底402對介電堆疊層408的介電層對執行多個所謂的“修整-蝕刻”迴圈來形成。由於被施加到介電堆疊層408的介電層對的重複的修整-蝕刻迴圈，介電堆疊層408可以具有一個或多個傾斜的邊緣以及比底部介電層對要短的頂部介電層對，如圖4B所示。
As shown in FIG. 4B, the P-type doped semiconductor layer 406 is formed on the P-type doped semiconductor layer 406 including a plurality of pairs of a first dielectric layer (referred to herein as "stacked sacrificial layer" 412) and a second dielectric layer (referred to herein as The "stacked dielectric layer" 410, collectively referred to herein as the "dielectric layer pair") is the dielectric stack layer 408. According to some embodiments, the dielectric stack layer 408 includes a stacked sacrificial layer 412 and a stacked dielectric layer 410 that are staggered. The stacked dielectric layer 410 and the stacked sacrificial layer 412 may be alternately deposited on the P-type doped semiconductor layer 406 above the carrier substrate 402
上, to form a dielectric stack layer 408. In some embodiments of the present invention, each stacked dielectric layer 410 includes a silicon oxide layer, and each stacked sacrificial layer 412 includes a silicon nitride layer. The dielectric stack layer 408 can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any of them combination. As shown in FIG. 4B, a stepped structure may be formed on the edge of the dielectric stack 408. The stepped structure can be formed by performing a plurality of so-called “trim-etch” loops on the dielectric layer pair of the dielectric stack layer 408 toward the carrier substrate 402. Due to the repeated trim-etch loops of the dielectric layer pair applied to the dielectric stack layer 408, the dielectric stack layer 408 may have one or more slanted edges and a top dielectric that is shorter than the bottom dielectric layer pair. Layer pair, as shown in Figure 4B.
如圖6A所示，方法600進行到操作步驟606，在操作步驟606中，形成各自垂直地延伸穿過介電堆疊層和P型摻雜半導體層、在第一停止層處停止的通道結構。在本發明的其中一些實施例中，為了形成通道結構，蝕刻各自垂直地延伸穿過介電堆疊層和P型摻雜半導體層、在第一停止層處停止的通道孔，並且沿著各個通道孔的側壁依次沉積儲存膜和半導體通道。
As shown in FIG. 6A, the method 600 proceeds to operation step 606. In operation step 606, channel structures each vertically extending through the dielectric stack layer and the P-type doped semiconductor layer and stopping at the first stop layer are formed. In some of the embodiments of the present invention, in order to form the channel structure, the etching each extends vertically through the dielectric stack layer and the P-type doped semiconductor layer, the channel hole stopped at the first stop layer, and along each channel A storage film and a semiconductor channel are sequentially deposited on the sidewall of the hole.
如圖4B所示，各個通道孔是垂直地延伸穿過介電堆疊層408和P型摻雜半導體層406、在停止層405處停止的開口。在本發明的其中一些實施例中，形成多個開口，使得各個開口成為用於在稍後的製程中生長單獨的通道結構414的位置。在本發明的其中一些實施例中，用於形成通道結構414的通道孔的製造製程包括濕式蝕刻和/或乾式蝕刻，例如DRIE。根據一些實施例，由於在停止層405的材料(例如，氧化鋁或金屬矽化物)與P型摻雜半導體層406的材料(即，多晶矽)之間的蝕刻選擇性，所以對通道孔的蝕刻繼續直到被停止層405(例如，高k介電層(例如，氧化鋁層)或金屬矽化物層)停止為止。在本發明的其中一
些實施例中，可以控制蝕刻條件(例如，蝕刻速率和時間)，以確保各個通道孔已經到達停止層405並且被其停止，進而將通道孔和在其中形成的通道結構414之間的開槽變化最小化。應理解，取決於特定的蝕刻選擇性，一個或多個通道孔可以在很小程度上延伸進入停止層405中，在本發明內容中仍然將此視為被停止層405停止。
As shown in FIG. 4B, each via hole is an opening that extends vertically through the dielectric stack layer 408 and the P-type doped semiconductor layer 406, and stops at the stop layer 405. In some embodiments of the present invention, multiple openings are formed, so that each opening becomes a location for growing a separate channel structure 414 in a later process. In some embodiments of the present invention, the manufacturing process for forming the channel hole of the channel structure 414 includes wet etching and/or dry etching, such as DRIE. According to some embodiments, due to the etching selectivity between the material of the stop layer 405 (for example, aluminum oxide or metal silicide) and the material of the P-type doped semiconductor layer 406 (that is, polysilicon), the etching of the via hole Continue until stopped by the stopped layer 405 (for example, a high-k dielectric layer (for example, an aluminum oxide layer) or a metal silicide layer). In one of the present invention
In some embodiments, the etching conditions (e.g., etching rate and time) can be controlled to ensure that each channel hole has reached the stop layer 405 and is stopped by it, so as to slot the channel hole and the channel structure 414 formed therein. Change is minimized. It should be understood that, depending on the specific etching selectivity, one or more via holes may extend into the stop layer 405 to a small extent, and this is still regarded as being stopped by the stop layer 405 in the context of the present invention.
如圖4B所示，包括阻擋層417、儲存層416和穿隧層415的儲存膜以及半導體通道418是沿著通道孔的側壁和底表面按該順序依次形成的。在本發明的其中一些實施例中，首先使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，沿著通道孔的側壁和底表面按該順序沉積阻擋層417、儲存層416和穿隧層415，以形成儲存膜。然後，可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來在穿隧層415之上沉積半導體材料(例如，多晶矽(例如，未摻雜的多晶矽))，進而形成半導體通道418。在本發明的其中一些實施例中，依次沉積第一氧化矽層、氮化矽層、第二氧化矽層和多晶矽層(“SONO”結構)，以形成儲存膜的阻擋層417、儲存層416和穿隧層415以及半導體通道418。
As shown in FIG. 4B, the storage film including the barrier layer 417, the storage layer 416, and the tunnel layer 415, and the semiconductor channel 418 are sequentially formed in this order along the sidewall and bottom surface of the channel hole. In some embodiments of the present invention, one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, Or any combination thereof), the barrier layer 417, the storage layer 416, and the tunnel layer 415 are deposited in this order along the sidewall and bottom surface of the via hole to form a storage film. Then, you can use one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) A semiconductor material (for example, polysilicon (for example, undoped polysilicon)) is deposited on the tunnel layer 415 to form a semiconductor channel 418. In some embodiments of the present invention, the first silicon oxide layer, the silicon nitride layer, the second silicon oxide layer, and the polysilicon layer ("SONO" structure) are sequentially deposited to form the barrier layer 417 and the storage layer 416 of the storage film. And the tunneling layer 415 and the semiconductor channel 418.
如圖4B所示，在通道孔中並且在半導體通道418之上形成封蓋層以完全或部分地填充通道孔(例如，不具有或具有氣隙)。可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來沉積介電材料(例如，氧化矽)，進而形成封蓋層。然後，在通道孔的頂部部分中形成通道插塞。在本
發明的其中一些實施例中，透過化學機械拋光(CMP)、濕式蝕刻和/或乾式蝕刻來將儲存膜、半導體通道418和封蓋層的在介電堆疊層408的頂表面上的一部分去除並且平坦化。然後，可以透過對半導體通道418和封蓋層的在通道孔的頂部部分中的一部分進行濕式蝕刻和/或乾式蝕刻，進而在通道孔的頂部部分中形成凹部。然後，可以透過經由一種或多種薄膜沉積製程(例如，化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)來將例如多晶矽之類的半導體材料沉積到凹部中，進而形成通道插塞。根據一些實施例，由此形成穿過介電堆疊層408和P型摻雜半導體層406、在停止層405處停止的通道結構414。
As shown in FIG. 4B, a capping layer is formed in the channel hole and over the semiconductor channel 418 to completely or partially fill the channel hole (for example, without or with an air gap). The dielectric can be deposited by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) Material (for example, silicon oxide) to form a capping layer. Then, a channel plug is formed in the top part of the channel hole. In this
In some of the embodiments of the invention, a portion of the storage film, the semiconductor channel 418, and the capping layer on the top surface of the dielectric stack 408 are removed by chemical mechanical polishing (CMP), wet etching, and/or dry etching And flattened. Then, a part of the semiconductor channel 418 and the capping layer in the top part of the channel hole may be wet-etched and/or dry-etched to form a recess in the top part of the channel hole. Then, semiconductor materials such as polysilicon can be deposited through one or more thin film deposition processes (for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof) Deposited in the recess, thereby forming a channel plug. According to some embodiments, a channel structure 414 passing through the dielectric stack layer 408 and the P-type doped semiconductor layer 406 and stopping at the stop layer 405 is thereby formed.
如圖6A所示，方法600進行到操作步驟608，在操作步驟608中，例如使用所謂的“閘極替換”製程來利用儲存堆疊層替換介電堆疊層，使得通道結構垂直地延伸穿過儲存堆疊層和P型摻雜半導體層。在本發明的其中一些實施例中，為了利用儲存堆疊層替換介電堆疊層，蝕刻垂直地延伸穿過介電堆疊層、在P型摻雜半導體層處停止的開口，並且穿過開口，利用堆疊導電層替換堆疊犧牲層以形成包括交錯的堆疊介電層和堆疊導電層的儲存堆疊層。
As shown in FIG. 6A, the method 600 proceeds to operation step 608. In operation step 608, for example, a so-called "gate replacement" process is used to replace the dielectric stack with the storage stack, so that the channel structure extends vertically through the storage. Stacked layers and P-type doped semiconductor layers. In some of the embodiments of the present invention, in order to replace the dielectric stack with a storage stack, the etching extends vertically through the dielectric stack, an opening that stops at the P-type doped semiconductor layer, and passes through the opening, using The stacked conductive layer replaces the stacked sacrificial layer to form a storage stacked layer including staggered stacked dielectric layers and stacked conductive layers.
如圖4C所示，縫隙420是垂直地延伸穿過介電堆疊層408並且在P型摻雜半導體層406處停止的開口。在本發明的其中一些實施例中，用於形成縫隙420的製造製程包括濕式蝕刻和/或乾式蝕刻，例如DRIE。雖然如圖4C所示，縫隙420是與N阱407橫向地對準的，但是應理解，在其它示例中，縫隙420可以不是與N阱407橫向地對準的。然後，可以穿過縫隙420執行閘極替換，以利用(在圖4E中所示的)儲存堆疊層430替換介電堆疊層408。
As shown in FIG. 4C, the slit 420 is an opening that extends vertically through the dielectric stack layer 408 and stops at the P-type doped semiconductor layer 406. In some embodiments of the present invention, the manufacturing process for forming the gap 420 includes wet etching and/or dry etching, such as DRIE. Although the slit 420 is laterally aligned with the N-well 407 as shown in FIG. 4C, it should be understood that in other examples, the slit 420 may not be laterally aligned with the N-well 407. Then, gate replacement may be performed through the gap 420 to replace the dielectric stack layer 408 with the storage stack layer 430 (shown in FIG. 4E).
如圖4D所示，首先透過穿過縫隙420去除(在圖4C中所示的)堆疊犧牲層412來形成橫向凹部422。在本發明的其中一些實施例中，透過穿過縫隙420施加蝕刻劑來去除堆疊犧牲層412，進而產生在堆疊介電層410之間交錯的橫向凹部422。蝕刻劑可以包括對於堆疊介電層410選擇性地蝕刻堆疊犧牲層412的任何合適的蝕刻劑。
As shown in FIG. 4D, the lateral recesses 422 are first formed by removing the stacked sacrificial layer 412 (shown in FIG. 4C) through the gap 420. In some of the embodiments of the present invention, the stacked sacrificial layer 412 is removed by applying an etchant through the gap 420, thereby generating the lateral recesses 422 staggered between the stacked dielectric layers 410. The etchant may include any suitable etchant that selectively etches the stacked sacrificial layer 412 with respect to the stacked dielectric layer 410.
如圖4E所示，穿過縫隙420將堆疊導電層428(包括閘電極和黏合層)沉積到(在圖4D中所示的)橫向凹部422中。在本發明的其中一些實施例中，在堆疊導電層428之前，將閘極介電層432沉積到橫向凹部422中，使得堆疊導電層428被沉積在閘極介電層432上。可以使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適製程、或其任何組合)，來沉積堆疊導電層428(例如，金屬層)。在本發明的其中一些實施例中，還沿著縫隙420的側壁以及在底部形成閘極介電層432，例如高k介電層。根據一些實施例，由此形成包括交錯的堆疊導電層428和堆疊介電層410的儲存堆疊層430，其替換(在圖4D中所示的)介電堆疊層408。
As shown in FIG. 4E, the stacked conductive layer 428 (including the gate electrode and the adhesion layer) is deposited into the lateral recess 422 (shown in FIG. 4D) through the gap 420. In some embodiments of the present invention, before the conductive layer 428 is stacked, the gate dielectric layer 432 is deposited into the lateral recess 422 so that the stacked conductive layer 428 is deposited on the gate dielectric layer 432. One or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, or any combination thereof) can be used to deposit the stacked conductive layer 428 (e.g., metal layer). In some embodiments of the present invention, a gate dielectric layer 432, such as a high-k dielectric layer, is also formed along the sidewall of the gap 420 and at the bottom. According to some embodiments, a storage stack 430 including staggered stacked conductive layers 428 and stacked dielectric layers 410 is thus formed, which replaces the dielectric stack layer 408 (shown in FIG. 4D).
如圖6A所示，方法600進行到操作步驟610，在操作步驟610中，形成垂直地延伸穿過儲存堆疊層的絕緣結構。在本發明的其中一些實施例中，為了形成絕緣結構，在形成儲存堆疊層之後，將一種或多種介電材料沉積到開口中以填充開口。如圖4E所示，形成垂直地延伸穿過儲存堆疊層430、在P型摻雜半導體層406的頂表面上停止的絕緣結構436。可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來將一種或多種介電材料(例如，氧化矽)沉積到縫隙420中，以完全或部分地填充縫隙420(具有或不具有氣隙)，進
而形成絕緣結構436。在本發明的其中一些實施例中，絕緣結構436包括閘極介電層432(例如，包括高k介電)和介電封蓋層434(例如，包括氧化矽)。
As shown in FIG. 6A, the method 600 proceeds to operation 610, in which an insulating structure extending vertically through the storage stack is formed. In some embodiments of the present invention, in order to form an insulating structure, after forming the storage stack layer, one or more dielectric materials are deposited into the opening to fill the opening. As shown in FIG. 4E, an insulating structure 436 that extends vertically through the storage stack layer 430 and stops on the top surface of the P-type doped semiconductor layer 406 is formed. One or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) can be used to combine one or more thin film deposition processes. A variety of dielectric materials (for example, silicon oxide) are deposited in the gap 420 to completely or partially fill the gap 420 (with or without an air gap), and
An insulating structure 436 is formed. In some embodiments of the present invention, the insulating structure 436 includes a gate dielectric layer 432 (for example, including a high-k dielectric) and a dielectric capping layer 434 (for example, including silicon oxide).
如圖4F所示，在形成絕緣結構436之後，形成包括通道局部接觸444和字元線局部接觸442的局部接觸以及週邊接觸438、週邊接觸439和週邊接觸440。可以透過使用一種或多種薄膜沉積製程(例如，化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)來在儲存堆疊層430的頂部上沉積介電材料(例如，氧化矽或氮化矽)，進而在儲存堆疊層430上形成局部介電層。可以透過使用濕式蝕刻和/或乾式蝕刻(例如，RIE)來蝕刻穿過局部介電層(和任何其它層間介電層)的接觸開口，隨後使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來利用導電材料填充接觸開口，進而形成通道局部接觸444、字元線局部接觸442以及週邊接觸438、週邊接觸439和週邊接觸440。
As shown in FIG. 4F, after the insulating structure 436 is formed, a partial contact including a channel partial contact 444 and a word line partial contact 442, as well as a peripheral contact 438, a peripheral contact 439, and a peripheral contact 440 are formed. The medium can be deposited on top of the storage stack 430 by using one or more thin film deposition processes (for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof). An electrical material (for example, silicon oxide or silicon nitride) is used to form a local dielectric layer on the storage stack 430. The contact openings through the local dielectric layer (and any other interlayer dielectric layers) can be etched through the use of wet etching and/or dry etching (e.g., RIE), followed by one or more thin film deposition processes (e.g., atomic layer). Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), any other suitable process, or any combination thereof) to fill the contact openings with conductive materials, thereby forming channel local contacts 444, character lines The local contact 442 and the peripheral contact 438, the peripheral contact 439 and the peripheral contact 440.
如圖4F所示，在通道局部接觸444、字元線局部接觸442以及週邊接觸438、週邊接觸439和週邊接觸440上方形成鍵合層446。鍵合層446包括電性連接到通道局部接觸444、字元線局部接觸442以及週邊接觸438、週邊接觸439和週邊接觸440的鍵合接觸。為了形成鍵合層446，使用一種或多種薄膜沉積製程(例如，化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其任何組合)來沉積層間介電層，並且使用濕式蝕刻和/或乾式蝕刻(例如，RIE)，隨後使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，穿過層間介電層來形成鍵合接觸。
As shown in FIG. 4F, a bonding layer 446 is formed over the channel partial contact 444, the character line partial contact 442, and the peripheral contact 438, the peripheral contact 439, and the peripheral contact 440. The bonding layer 446 includes bonding contacts electrically connected to the channel partial contact 444, the character line partial contact 442, and the peripheral contact 438, the peripheral contact 439, and the peripheral contact 440. To form the bonding layer 446, one or more thin film deposition processes (for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof) are used to deposit the interlayer dielectric layer , And use wet etching and/or dry etching (e.g., RIE), followed by one or more thin film deposition processes (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD)) , Any other suitable process, or any combination thereof), through the interlayer dielectric layer to form bonding contacts.
如圖6A所示，方法600進行到操作步驟612，在操作步驟612中，將第一基底和第二基底以面對面的方式鍵合，使得儲存堆疊層在週邊電路上方。鍵合可以包括混合鍵合。如圖4G所示，載體基底402和形成於其上的部件(例如，儲存堆疊層430和穿過其形成的通道結構414)上下翻轉。根據一些實施例，將面朝下的鍵合層446與面朝上的鍵合層448鍵合，即以面對面的方式鍵合，進而在載體基底402和矽基底450之間形成鍵合介面454。在本發明的其中一些實施例中，在鍵合之前，對鍵合表面應用處理製程，例如電漿處理、濕處理和/或熱處理。在鍵合之後，將鍵合層446中的鍵合接觸與鍵合層448中的鍵合接觸彼此對準並且接觸，使得儲存堆疊層430和穿過其形成的通道結構414可以電性連接到週邊電路452並且在週邊電路452上方。
As shown in FIG. 6A, the method 600 proceeds to operation step 612. In operation step 612, the first substrate and the second substrate are bonded in a face-to-face manner so that the storage stack layer is above the peripheral circuit. Bonding may include hybrid bonding. As shown in FIG. 4G, the carrier substrate 402 and the components formed thereon (for example, the storage stack 430 and the channel structure 414 formed therethrough) are turned upside down. According to some embodiments, the bonding layer 446 facing down is bonded to the bonding layer 448 facing up, that is, bonded in a face-to-face manner, thereby forming a bonding interface 454 between the carrier substrate 402 and the silicon substrate 450 . In some embodiments of the present invention, before bonding, a treatment process, such as plasma treatment, wet treatment, and/or heat treatment, is applied to the bonding surface. After bonding, the bonding contact in the bonding layer 446 and the bonding contact in the bonding layer 448 are aligned and contacted with each other, so that the storage stack 430 and the channel structure 414 formed therethrough can be electrically connected to The peripheral circuit 452 is and above the peripheral circuit 452.
如圖6A所示，方法600進行到操作步驟614，在操作步驟614中，依次去除第二基底、犧牲層和第一停止層，以曝露多個通道結構中的每一個的端部。
可以從第二基底的背面執行去除。在本發明的其中一些實施例中，為了依次去除第二基底、犧牲層和第一停止層，去除第二基底，在犧牲層的第二停止層處停止，並且去除犧牲層的剩餘部分，在第一停止層處停止。
As shown in FIG. 6A, the method 600 proceeds to operation step 614. In operation step 614, the second substrate, the sacrificial layer, and the first stop layer are sequentially removed to expose the end of each of the plurality of channel structures.
The removal can be performed from the back of the second substrate. In some of the embodiments of the present invention, in order to sequentially remove the second substrate, the sacrificial layer and the first stop layer, remove the second substrate, stop at the second stop layer of the sacrificial layer, and remove the remaining part of the sacrificial layer. Stop at the first stop level.
如圖4H所示，從背面完全地去除載體基底402(以及在圖4G中所示的在載體基底402和停止層404之間的襯墊氧化物層)，直到被停止層404(例如，氮化矽層)停止為止。可以使用化學機械拋光(CMP)、研磨、乾式蝕刻和/或濕式蝕刻來完全地去除載體基底402。在本發明的其中一些實施例中，將載體基底402剝離。在其中載體基底402包括矽並且停止層404包括氮化矽的一些實施例中，使用矽化學機械拋光(CMP)去除載體基底402，當到達具有不同於矽的材
料的停止層404(即，充當背面化學機械拋光(CMP)停止層)時，其可以自動地停止。在本發明的其中一些實施例中，使用透過TMAH的濕式蝕刻來去除基底402(矽基底)，當到達具有不同於矽的材料的停止層404(即，充當背面蝕刻停止層)時，其自動地停止。停止層404可以確保完全去除載體基底402，而無需顧慮在減薄之後的厚度均勻性。
As shown in FIG. 4H, the carrier substrate 402 (and the pad oxide layer between the carrier substrate 402 and the stop layer 404 shown in FIG. 4G) is completely removed from the backside until the stopped layer 404 (for example, nitrogen Silicide layer) until it stops. The carrier substrate 402 may be completely removed using chemical mechanical polishing (CMP), grinding, dry etching, and/or wet etching. In some of the embodiments of the present invention, the carrier substrate 402 is peeled off. In some embodiments where the carrier substrate 402 includes silicon and the stop layer 404 includes silicon nitride, silicon chemical mechanical polishing (CMP) is used to remove the carrier substrate 402.
When the stop layer 404 of the material (ie, acts as a backside chemical mechanical polishing (CMP) stop layer), it can be automatically stopped. In some of the embodiments of the present invention, wet etching through TMAH is used to remove the substrate 402 (silicon substrate). When it reaches the stop layer 404 (that is, acts as a backside etch stop layer) with a material different from silicon, it Stop automatically. The stop layer 404 can ensure that the carrier substrate 402 is completely removed without worrying about the thickness uniformity after thinning.
如圖4I所示，然後同樣可以使用濕式蝕刻，利用例如磷酸和氫氟酸之類的適當蝕刻劑來完全地去除犧牲層403的剩餘部分(例如，在圖4H中所示的停止層404以及在停止層404與停止層405之間的另一襯墊氧化物層)，直到被具有不同材料(例如，高k介電)的停止層405停止為止。如上所述，由於各個通道結構414沒有延伸超過停止層405進入犧牲層403或載體基底402中，因此對載體基底402和犧牲層403的去除不影響通道結構414。如圖4J所示，在其中停止層405包括高k介電(與包括金屬矽化物的導電層相反)的一些實施例中，使用濕式蝕刻和/或乾式蝕刻來完全地去除(在圖4I所示的)停止層405，以曝露通道結構414的上端。
As shown in FIG. 4I, then wet etching can also be used, using a suitable etchant such as phosphoric acid and hydrofluoric acid to completely remove the remaining part of the sacrificial layer 403 (for example, the stop layer 404 shown in FIG. 4H). And another pad oxide layer between the stop layer 404 and the stop layer 405) until it is stopped by the stop layer 405 having a different material (for example, a high-k dielectric). As described above, since each channel structure 414 does not extend beyond the stop layer 405 into the sacrificial layer 403 or the carrier substrate 402, the removal of the carrier substrate 402 and the sacrificial layer 403 does not affect the channel structure 414. As shown in FIG. 4J, in some embodiments where the stop layer 405 includes a high-k dielectric (as opposed to a conductive layer including a metal silicide), wet etching and/or dry etching are used to completely remove (in FIG. 4I (Shown) a stop layer 405 to expose the upper end of the channel structure 414.
如圖6A所示，方法600進行到操作步驟616，在操作步驟616中，形成與多個通道結構的端部接觸的導電層。在本發明的其中一些實施例中，導電層包括與多個通道結構的端部和P型摻雜半導體層接觸的金屬矽化物層、以及與金屬矽化物層接觸的金屬層。在本發明的其中一些實施例中，為了形成導電層，去除儲存膜的鄰接P型摻雜半導體層的一部分以形成圍繞半導體通道的一部分的凹部，並且對半導體通道的該部分進行摻雜。在本發明的其中一些實施例中，為了形成導電層，將金屬矽化物層形成為在凹部中與半導體通道的摻雜部分接觸、並且在凹部的外部與P型摻雜半導體層接觸。
As shown in FIG. 6A, the method 600 proceeds to operation 616, in which a conductive layer is formed in contact with the ends of the plurality of channel structures. In some embodiments of the present invention, the conductive layer includes a metal silicide layer in contact with the ends of the plurality of channel structures and the P-type doped semiconductor layer, and a metal layer in contact with the metal silicide layer. In some embodiments of the present invention, in order to form the conductive layer, a part of the storage film adjacent to the P-type doped semiconductor layer is removed to form a recess surrounding a part of the semiconductor channel, and the part of the semiconductor channel is doped. In some of the embodiments of the present invention, in order to form the conductive layer, the metal silicide layer is formed to contact the doped portion of the semiconductor channel in the recess, and to contact the P-type doped semiconductor layer outside the recess.
如圖4J所示，去除(在圖4I中所示的)儲存層416、阻擋層417和穿隧層415的鄰接P型摻雜半導體層406的一部分，以形成圍繞半導體通道418的延伸進入P型摻雜半導體層406中的頂部部分的凹部457。在本發明的其中一些實施例中，依次執行兩個濕式蝕刻製程。例如，使用濕式蝕刻，利用例如磷酸之類的適當蝕刻劑，來選擇性地去除包括氮化矽的儲存層416，而不蝕刻包括多晶矽的P型摻雜半導體層406。可以透過控制蝕刻時間和/或蝕刻速率來控制對儲存層416的蝕刻，使得蝕刻不會繼續而影響儲存層416的被儲存堆疊層430圍繞的其餘部分。然後，可以使用濕式蝕刻，利用例如氫氟酸之類的適當蝕刻劑，來選擇性地去除包括氧化矽的阻擋層417和穿隧層415，而不蝕刻包括多晶矽的P型摻雜半導體層406和半導體通道418。可以透過控制蝕刻時間和/或蝕刻速率來控制對阻擋層417和穿隧層415的蝕刻，使得蝕刻不會繼續而影響阻擋層417和穿隧層415的被儲存堆疊層430圍繞的其餘部分。在本發明的其中一些實施例中，使用經圖案化的停止層405作為蝕刻遮罩，來執行單個乾式蝕刻製程。例如，當執行乾式蝕刻時，可以不去除停止層405，而是替代地可以對其進行圖案化，以僅曝露在通道結構414的上端處的儲存層416、阻擋層417和穿隧層415，同時仍然作為蝕刻遮罩覆蓋其它區域。然後可以執行乾式蝕刻以蝕刻儲存層416、阻擋層417和穿隧層415的鄰接P型摻雜半導體層406的一部分。可以透過控制蝕刻時間和/或蝕刻速率來控制乾式蝕刻，使得蝕刻不會繼續而影響儲存層416、阻擋層417和穿隧層415的被儲存堆疊層430圍繞的其餘部分。一旦完成乾式蝕刻，就可以去除經圖案化的停止層405。
As shown in FIG. 4J, a portion of the storage layer 416, the barrier layer 417, and the tunneling layer 415 (shown in FIG. 4I) adjacent to the P-type doped semiconductor layer 406 is removed to form an extension into the P type surrounding the semiconductor channel 418 Type doped semiconductor layer 406 at the top portion of the recess 457. In some embodiments of the present invention, two wet etching processes are performed sequentially. For example, wet etching is used to selectively remove the storage layer 416 including silicon nitride using an appropriate etchant such as phosphoric acid, and the P-type doped semiconductor layer 406 including polysilicon is not etched. The etching of the storage layer 416 can be controlled by controlling the etching time and/or the etching rate, so that the etching will not continue to affect the rest of the storage layer 416 surrounded by the storage stack layer 430. Then, wet etching can be used, using an appropriate etchant such as hydrofluoric acid, to selectively remove the barrier layer 417 including silicon oxide and the tunneling layer 415 without etching the P-type doped semiconductor layer including polysilicon 406 and semiconductor channel 418. The etching of the barrier layer 417 and the tunneling layer 415 can be controlled by controlling the etching time and/or the etching rate, so that the etching will not continue to affect the remaining parts of the barrier layer 417 and the tunneling layer 415 surrounded by the storage stack layer 430. In some embodiments of the present invention, the patterned stop layer 405 is used as an etching mask to perform a single dry etching process. For example, when performing dry etching, the stop layer 405 may not be removed, but instead may be patterned to expose only the storage layer 416, the barrier layer 417, and the tunnel layer 415 at the upper end of the channel structure 414, At the same time, it is still used as an etching mask to cover other areas. Then, dry etching may be performed to etch a portion of the storage layer 416, the barrier layer 417, and the tunnel layer 415 adjacent to the P-type doped semiconductor layer 406. The dry etching can be controlled by controlling the etching time and/or the etching rate so that the etching will not continue to affect the remaining parts of the storage layer 416, the barrier layer 417, and the tunnel layer 415 surrounded by the storage stack layer 430. Once the dry etching is completed, the patterned stop layer 405 can be removed.
然而，與經由具有較大高寬比(例如，大於50)的穿過介電堆疊層408/儲存堆疊層430的開口(例如，圖4D中的縫隙420)、使用正面濕式蝕刻的已
知解決方案相比，從背面去除儲存層416、阻擋層417和穿隧層415的鄰接P型摻雜半導體層406的一部分具有小得多的挑戰性並且具有更高的生產成品率。透過避免由縫隙420的高高寬比所引入的問題，可以降低製造複雜性和成本，並且可以增加成品率。此外，垂直可縮放性(例如，介電堆疊層408/儲存堆疊層430的增加的層級)也可以得到改善。
However, it is different from using a front wet etching through an opening (for example, the gap 420 in FIG. 4D) through the dielectric stack 408/storage stack 430 with a larger aspect ratio (for example, greater than 50).
Compared with known solutions, removing a part of the storage layer 416, the barrier layer 417, and the tunnel layer 415 adjacent to the P-type doped semiconductor layer 406 from the backside is much less challenging and has a higher production yield. By avoiding the problems introduced by the high aspect ratio of the gap 420, the manufacturing complexity and cost can be reduced, and the yield can be increased. In addition, vertical scalability (eg, increased levels of dielectric stack 408/storage stack 430) can also be improved.
如圖4J所示，根據一些實施例，可以去除各個通道結構414的儲存膜(包括阻擋層417、儲存層416和穿隧層415)的鄰接P型摻雜半導體層406的頂部部分，以形成凹部457，其曝露半導體通道418的頂部部分。在本發明的其中一些實施例中，對半導體通道418的被凹部457曝露的頂部部分進行摻雜，以增加其導電性。例如，可以執行傾斜離子注入製程，以利用任何合適的摻雜劑將半導體通道418(例如，包括多晶矽)的被凹部457曝露的頂部部分摻雜到期望的摻雜濃度。
As shown in FIG. 4J, according to some embodiments, the top portion of the storage film (including the barrier layer 417, the storage layer 416, and the tunneling layer 415) of each channel structure 414 adjacent to the P-type doped semiconductor layer 406 may be removed to form The recess 457 exposes the top part of the semiconductor channel 418. In some embodiments of the present invention, the top portion of the semiconductor channel 418 exposed by the recess 457 is doped to increase its conductivity. For example, an inclined ion implantation process may be performed to dope the top portion of the semiconductor channel 418 (for example, including polysilicon) exposed by the recess 457 to a desired doping concentration with any suitable dopant.
如圖4K所示，在(圖4J中所示的)凹部457中形成導電層459，其圍繞並且接觸半導體通道418的摻雜頂部部分，並且在凹部457的外部在P型摻雜半導體層406上形成導電層459。在本發明的其中一些實施例中，為了形成導電層459，將金屬矽化物層476形成為在凹部457中與半導體通道418的摻雜頂部部分接觸、並且在凹部457的外部與P型摻雜半導體層406接觸，並且在金屬矽化物層476上形成金屬層478。在一個示例中，可以使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，來在凹部457的側壁和底表面上以及在P型摻雜半導體層406上沉積金屬膜(例如，Co、Ni或Ti)。金屬膜可以是與P型摻雜半導體層406的多晶矽和半導體通道418的摻雜頂部部分接觸的。然後，可以透過
熱處理(例如，退火、燒結或任何其它合適的製程)在金屬膜和多晶矽上執行矽化製程，以沿著凹部457的側壁和底表面以及在P型摻雜半導體層406上形成金屬矽化物層476。然後，可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來在金屬矽化物層476上沉積另一金屬膜(例如，W、Al、Ti、TiN、Co和/或Ni)，以填充凹部457的剩餘空間，進而在金屬矽化物層476上形成金屬層478。在另一示例中，代替分別沉積兩個金屬膜，可以使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，將單個金屬膜(例如，Co、Ni或Ti)沉積到凹部457中以填充凹部457並且沉積在P型摻雜半導體層406上。然後，可以透過熱處理(例如，退火、燒結或任何其它合適的製程)在金屬膜和多晶矽上執行矽化製程，使得金屬膜的一部分形成沿著凹部457的側壁和底表面以及在P型摻雜半導體層406上的金屬矽化物層476，而金屬膜的剩餘部分成為金屬矽化物層476上的金屬層478。可以執行化學機械拋光(CMP)製程以去除任何多餘的金屬層478。如圖4K所示，根據一些實施例，由此形成包括金屬矽化物層476和金屬層478的導電層459(作為圖2A中的立體記憶體元件200中的導電層222的一個示例)。在本發明的其中一些實施例中，對導電層459進行圖案化和蝕刻，以便不覆蓋週邊區域。
As shown in FIG. 4K, a conductive layer 459 is formed in the recessed portion 457 (shown in FIG. 4J), which surrounds and contacts the doped top portion of the semiconductor channel 418, and forms a P-type doped semiconductor layer 406 on the outside of the recessed portion 457. A conductive layer 459 is formed thereon. In some embodiments of the present invention, in order to form the conductive layer 459, the metal silicide layer 476 is formed in the recess 457 in contact with the doped top portion of the semiconductor channel 418, and is doped with P-type outside the recess 457. The semiconductor layer 406 is in contact, and a metal layer 478 is formed on the metal silicide layer 476. In one example, one or more thin film deposition processes (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) can be used , To deposit a metal film (for example, Co, Ni, or Ti) on the sidewall and bottom surface of the recess 457 and on the P-type doped semiconductor layer 406. The metal film may be in contact with the polysilicon of the P-type doped semiconductor layer 406 and the doped top portion of the semiconductor channel 418. Then, through
Heat treatment (for example, annealing, sintering or any other suitable process) performs a silicidation process on the metal film and polysilicon to form a metal silicide layer 476 along the sidewall and bottom surface of the recess 457 and on the P-type doped semiconductor layer 406 . Then, you can use one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof) Another metal film (for example, W, Al, Ti, TiN, Co, and/or Ni) is deposited on the metal silicide layer 476 to fill the remaining space of the recess 457 to form a metal layer 478 on the metal silicide layer 476. In another example, instead of depositing two metal films separately, one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other In a suitable process, or any combination thereof), a single metal film (for example, Co, Ni, or Ti) is deposited into the recess 457 to fill the recess 457 and deposited on the P-type doped semiconductor layer 406. Then, a silicidation process can be performed on the metal film and polysilicon through heat treatment (for example, annealing, sintering or any other suitable process), so that a part of the metal film is formed along the sidewall and bottom surface of the recess 457 and on the P-type doped semiconductor. The metal silicide layer 476 on the layer 406, and the remaining part of the metal film becomes the metal layer 478 on the metal silicide layer 476. A chemical mechanical polishing (CMP) process can be performed to remove any excess metal layer 478. As shown in FIG. 4K, according to some embodiments, a conductive layer 459 including a metal silicide layer 476 and a metal layer 478 is thus formed (as an example of the conductive layer 222 in the three-dimensional memory device 200 in FIG. 2A). In some embodiments of the present invention, the conductive layer 459 is patterned and etched so as not to cover the peripheral area.
在本發明的其中一些實施例中，為了形成導電層，將摻雜多晶矽沉積到凹部中以與半導體通道的摻雜部分接觸，並且形成與摻雜多晶矽和P型摻雜半導體層接觸的金屬矽化物層。如圖4P所示，在(圖4J中所示的)凹部457中形成通道插塞480，其圍繞並且接觸半導體通道418的摻雜頂部部分。結果，根據一些實施例，由此利用通道插塞480替換(在圖4H中所示的)通道結構414的鄰
接P型摻雜半導體層406的被去除的頂部部分。在本發明的其中一些實施例中，為了形成通道插塞480，使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)，將多晶矽沉積到凹部457中以填充凹部457，隨後使用化學機械拋光(CMP)製程來去除在P型摻雜半導體層406的頂表面上方的任何多餘的多晶矽。在本發明的其中一些實施例中，在將多晶矽沉積到凹部457中時，執行對例如B、Ga或Al之類的P型摻雜劑的原位摻雜，以對通道插塞480進行摻雜。由於通道插塞480和半導體通道418的摻雜頂部部分可以包括相同的材料(例如，摻雜多晶矽)，所以可以將通道插塞480視為通道結構414的半導體通道418的一部分。
In some of the embodiments of the present invention, in order to form the conductive layer, doped polysilicon is deposited into the recess to contact the doped portion of the semiconductor channel, and a metal silicide is formed in contact with the doped polysilicon and the P-type doped semiconductor layer物层。 The material layer. As shown in FIG. 4P, a channel plug 480 is formed in the recess 457 (shown in FIG. 4J), which surrounds and contacts the doped top portion of the semiconductor channel 418. As a result, according to some embodiments, the adjacent channel structure 414 (shown in FIG. 4H) is thereby replaced with a channel plug 480.
The removed top portion of the P-type doped semiconductor layer 406 is connected. In some embodiments of the present invention, in order to form the channel plug 480, one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), Any other suitable process, or any combination thereof), deposit polysilicon into the recess 457 to fill the recess 457, and then use a chemical mechanical polishing (CMP) process to remove any excess on the top surface of the P-type doped semiconductor layer 406 Of polysilicon. In some embodiments of the present invention, when polysilicon is deposited into the recess 457, in-situ doping of P-type dopants such as B, Ga, or Al is performed to dope the channel plug 480. miscellaneous. Since the doped top portion of the channel plug 480 and the semiconductor channel 418 may include the same material (for example, doped polysilicon), the channel plug 480 may be regarded as a part of the semiconductor channel 418 of the channel structure 414.
如圖4P所示，在P型摻雜半導體層406和通道插塞480上形成包括金屬矽化物層476和金屬層478的導電層459。在本發明的其中一些實施例中，首先在P型摻雜半導體層406和通道插塞480上沉積金屬膜，隨後進行矽化製程以形成與通道插塞480和P型摻雜半導體層406接觸的金屬矽化物層476。然後，可以在金屬矽化物層476上沉積另一金屬膜以形成金屬層478。在本發明的其中一些實施例中，在P型摻雜半導體層406和通道插塞480上沉積金屬膜，隨後進行矽化製程，使得金屬膜的與P型摻雜半導體層406和通道插塞480接觸的一部分形成金屬矽化物層476，並且金屬膜的剩餘部分成為金屬層478。如圖4P所示，根據一些實施例，由此形成包括金屬矽化物層476和金屬層478的導電層459(作為圖2B中的立體記憶體元件255中的導電層222的一個示例)。在本發明的其中一些實施例中，對導電層459進行圖案化和蝕刻，以便不覆蓋週邊區域。
As shown in FIG. 4P, a conductive layer 459 including a metal silicide layer 476 and a metal layer 478 is formed on the P-type doped semiconductor layer 406 and the channel plug 480. In some embodiments of the present invention, a metal film is first deposited on the P-type doped semiconductor layer 406 and the channel plug 480, and then a silicidation process is performed to form contact with the channel plug 480 and the P-type doped semiconductor layer 406 Metal silicide layer 476. Then, another metal film may be deposited on the metal silicide layer 476 to form a metal layer 478. In some embodiments of the present invention, a metal film is deposited on the P-type doped semiconductor layer 406 and the channel plug 480, and then a silicidation process is performed, so that the metal film is combined with the P-type doped semiconductor layer 406 and the channel plug 480. A part of the contact forms a metal silicide layer 476, and the remaining part of the metal film becomes a metal layer 478. As shown in FIG. 4P, according to some embodiments, a conductive layer 459 including a metal silicide layer 476 and a metal layer 478 is thus formed (as an example of the conductive layer 222 in the three-dimensional memory element 255 in FIG. 2B). In some embodiments of the present invention, the conductive layer 459 is patterned and etched so as not to cover the peripheral area.
如圖6A所示，方法600進行到操作步驟618，在操作步驟618中，形成
在儲存堆疊層上方，並且與P型摻雜半導體層接觸的第一源極接觸，並且形成在儲存堆疊層上方並且與N阱接觸的第二源極接觸。如圖4L所示，在P型摻雜半導體層406上形成一個或多個層間介電層456。可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它適合的製程、或其任何組合)，來在P型摻雜半導體層406的頂表面上沉積介電材料，進而形成層間介電層456。
As shown in FIG. 6A, the method 600 proceeds to operation step 618. In operation step 618, a
A first source contact is formed above the storage stack layer and in contact with the P-type doped semiconductor layer, and a second source contact is formed above the storage stack layer and in contact with the N well. As shown in FIG. 4L, one or more interlayer dielectric layers 456 are formed on the P-type doped semiconductor layer 406. You can use one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes, or any combination thereof), to A dielectric material is deposited on the top surface of the type doped semiconductor layer 406 to form an interlayer dielectric layer 456.
如圖4M所示，可以形成穿過層間介電層456和導電層459進入P型摻雜半導體層406中的源極接觸開口458。在本發明的其中一些實施例中，使用濕式蝕刻和/或乾式蝕刻(例如，RIE)來形成源極接觸開口458。在本發明的其中一些實施例中，源極接觸開口458進一步延伸進入P型摻雜半導體層406的頂部部分中。穿過層間介電層456和導電層459的蝕刻製程可以繼續蝕刻P型摻雜半導體層406的一部分。在本發明的其中一些實施例中，在蝕刻穿過層間介電層456和導電層459之後，使用單獨的蝕刻製程來蝕刻P型摻雜半導體層406的一部分。
As shown in FIG. 4M, a source contact opening 458 may be formed through the interlayer dielectric layer 456 and the conductive layer 459 into the P-type doped semiconductor layer 406. In some embodiments of the present invention, wet etching and/or dry etching (for example, RIE) are used to form the source contact opening 458. In some embodiments of the present invention, the source contact opening 458 further extends into the top portion of the P-type doped semiconductor layer 406. The etching process through the interlayer dielectric layer 456 and the conductive layer 459 can continue to etch a part of the P-type doped semiconductor layer 406. In some embodiments of the present invention, after etching through the interlayer dielectric layer 456 and the conductive layer 459, a separate etching process is used to etch a portion of the P-type doped semiconductor layer 406.
如圖4M所示，可以形成穿過層間介電層456和導電層459進入N阱407中的源極接觸開口465。在本發明的其中一些實施例中，使用濕式蝕刻和/或乾式蝕刻(例如，RIE)來形成源極接觸開口465。在本發明的其中一些實施例中，源極接觸開口465進一步延伸進入N阱407的頂部部分中。穿過層間介電層456和導電層459的蝕刻製程可以繼續蝕刻N阱407的一部分。在本發明的其中一些實施例中，在蝕刻穿過層間介電層456和導電層459之後，使用單獨的蝕刻製程來蝕刻N阱407的一部分。可以在源極接觸開口465的蝕刻之後執行對源極接觸開口458的蝕刻，反之亦然。應理解，在一些示例中，可以透過相同的蝕刻製程來蝕刻源極接觸開口458和源極接觸開口465以減少蝕刻製程的數量。
As shown in FIG. 4M, a source contact opening 465 passing through the interlayer dielectric layer 456 and the conductive layer 459 into the N well 407 may be formed. In some embodiments of the present invention, wet etching and/or dry etching (for example, RIE) are used to form the source contact opening 465. In some embodiments of the present invention, the source contact opening 465 further extends into the top portion of the N well 407. The etching process through the interlayer dielectric layer 456 and the conductive layer 459 can continue to etch a part of the N well 407. In some embodiments of the present invention, after etching through the interlayer dielectric layer 456 and the conductive layer 459, a separate etching process is used to etch a portion of the N well 407. The etching of the source contact opening 458 may be performed after the etching of the source contact opening 465, and vice versa. It should be understood that, in some examples, the source contact opening 458 and the source contact opening 465 may be etched through the same etching process to reduce the number of etching processes.
如圖4N所示，在P型摻雜半導體層406的背面處的源極接觸開口458和465(圖4M中所示)中分別形成源極接觸464和源極接觸開口478。根據一些實施例，源極接觸464在儲存堆疊層430上方，並且與P型摻雜半導體層406接觸。
根據一些實施例，源極接觸479在儲存堆疊層430上方並且與N阱407接觸。在本發明的其中一些實施例中，使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來將一種或多種導電材料沉積到源極接觸開口458和465中，以利用黏合層(例如，TiN)和導體層(例如，W)填充源極接觸開口458和465。
然後，可以執行例如化學機械拋光(CMP)之類的平坦化製程以去除多餘的導電材料，使得源極接觸464和源極接觸478的頂表面是彼此齊平，以及與層間介電層456的頂表面齊平。應理解，在一些示例中，可以透過相同的沉積和化學機械拋光(CMP)製程來形成源極接觸464和源極接觸478以減少製造製程的步驟。
As shown in FIG. 4N, a source contact 464 and a source contact opening 478 are formed in the source contact openings 458 and 465 (shown in FIG. 4M) at the back surface of the P-type doped semiconductor layer 406, respectively. According to some embodiments, the source contact 464 is above the storage stack layer 430 and is in contact with the P-type doped semiconductor layer 406.
According to some embodiments, the source contact 479 is above the storage stack 430 and is in contact with the N well 407. In some embodiments of the present invention, one or more thin film deposition processes (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD)), any other suitable process, or Any combination thereof) to deposit one or more conductive materials into the source contact openings 458 and 465 to fill the source contact openings 458 and 465 with an adhesion layer (for example, TiN) and a conductive layer (for example, W).
Then, a planarization process such as chemical mechanical polishing (CMP) can be performed to remove excess conductive material, so that the top surfaces of the source contact 464 and the source contact 478 are flush with each other and are in contact with the interlayer dielectric layer 456. The top surface is flush. It should be understood that, in some examples, the source contact 464 and the source contact 478 may be formed through the same deposition and chemical mechanical polishing (CMP) process to reduce the number of manufacturing process steps.
如圖6A所示，方法600進行到操作步驟620，在操作步驟620中，形成在第一源極接觸和第二源極接觸上方，並且與其接觸的互連層。在本發明的其中一些實施例中，互連層包括分別在第一源極接觸和第二源極接觸上方並且與第一源極接觸和第二源極接觸接觸的第一互連和第二互連。
As shown in FIG. 6A, the method 600 proceeds to operation 620. In operation 620, an interconnection layer is formed over and in contact with the first source contact and the second source contact. In some of the embodiments of the present invention, the interconnection layer includes a first interconnection and a second interconnection respectively above the first source contact and the second source contact and in contact with the first source contact and the second source contact. interconnection.
如圖4O所示，形成在源極接觸464和源極接觸478上方並且與其接觸的重佈線層470。在本發明的其中一些實施例中，透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來在層間介電層456和源極接觸364的頂表面上沉積導電材料(例如，Al)，進而形成重佈線層470。在本發明的其中一
些實施例中，透過微影和蝕刻製程來將重佈線層470圖案化，以形成在源極接觸464上方並且與其接觸的第一互連470-1以及在源極接觸479上方並且與其接觸的第二互連470-2。第一互連470-1和第二互連470-2可以彼此電性隔離。可以在重佈線層470上形成鈍化層472。在本發明的其中一些實施例中，透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來沉積介電材料(例如，氮化矽)，進而形成鈍化層472。根據一些實施例，由此形成包括層間介電層456、重佈線層470和鈍化層472的互連層477。
As shown in FIG. 4O, a rewiring layer 470 is formed over and in contact with the source contact 464 and the source contact 478. In some of the embodiments of the present invention, by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, Or any combination thereof) to deposit a conductive material (for example, Al) on the top surfaces of the interlayer dielectric layer 456 and the source contact 364, thereby forming the redistribution layer 470. In one of the present invention
In some embodiments, the rewiring layer 470 is patterned through lithography and etching processes to form a first interconnect 470-1 above and in contact with the source contact 464, and a first interconnect 470-1 above and in contact with the source contact 479. The second interconnection 470-2. The first interconnect 470-1 and the second interconnect 470-2 may be electrically isolated from each other. A passivation layer 472 may be formed on the rewiring layer 470. In some of the embodiments of the present invention, by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, Or any combination thereof) to deposit a dielectric material (for example, silicon nitride) to form a passivation layer 472. According to some embodiments, the interconnection layer 477 including the interlayer dielectric layer 456, the rewiring layer 470, and the passivation layer 472 is thereby formed.
如圖4L所示，形成各自延伸穿過層間介電層456和P型摻雜半導體層406的接觸開口460、接觸開口461和接觸開口463。在本發明的其中一些實施例中，使用濕式蝕刻和/或乾式蝕刻(例如，RIE)，穿過層間介電層456和P型摻雜半導體層406來形成接觸開口460、接觸開口461和接觸開口463。在本發明的其中一些實施例中，使用微影來將接觸開口460、接觸開口461和接觸開口463圖案化，以分別與週邊接觸438、週邊接觸440和週邊接觸439對準。對接觸開口460、接觸開口461和接觸開口463的蝕刻可以在週邊接觸438、週邊接觸440和週邊接觸439的上端處停止，以曝露週邊接觸438、週邊接觸440和週邊接觸439。對接觸開口460、接觸開口461和接觸開口463的蝕刻可以透過相同的蝕刻製程來執行，以減少蝕刻製程的數量。應理解，由於不同的蝕刻深度，可以在對源極接觸開口465的蝕刻之前執行對接觸開口460、接觸開口461和接觸開口463的蝕刻(但不是同時)，反之亦然。
As shown in FIG. 4L, contact openings 460, contact openings 461, and contact openings 463, each extending through the interlayer dielectric layer 456 and the P-type doped semiconductor layer 406, are formed. In some embodiments of the present invention, wet etching and/or dry etching (for example, RIE) are used to form the contact opening 460, the contact opening 461, and the contact opening 460 through the interlayer dielectric layer 456 and the P-type doped semiconductor layer 406. Contact opening 463. In some embodiments of the present invention, lithography is used to pattern the contact opening 460, the contact opening 461, and the contact opening 463 to align with the peripheral contact 438, the peripheral contact 440, and the peripheral contact 439, respectively. The etching of the contact opening 460, the contact opening 461, and the contact opening 463 may be stopped at the upper ends of the peripheral contact 438, the peripheral contact 440, and the peripheral contact 439 to expose the peripheral contact 438, the peripheral contact 440, and the peripheral contact 439. The etching of the contact opening 460, the contact opening 461, and the contact opening 463 can be performed through the same etching process to reduce the number of etching processes. It should be understood that due to the different etching depths, the etching of the contact opening 460, the contact opening 461, and the contact opening 463 may be performed before the etching of the source contact opening 465 (but not at the same time), and vice versa.
如圖4M所示，使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、
或其任何組合)，沿著接觸開口460、接觸開口461和接觸開口463以及源極接觸開口465的側壁形成間隙壁462，以將P型摻雜半導體層406電性隔離。在本發明的其中一些實施例中，透過相同的沉積製程，沿著接觸開口460、接觸開口461和接觸開口463以及源極接觸開口465的側壁形成間隙壁462，以減少製造製程的數量。在本發明的其中一些實施例中，在形成間隙壁462之後執行對源極接觸開口458的蝕刻，使得不沿著源極接觸開口458的側壁形成間隙壁462，以增加在源極接觸464和P型摻雜半導體層406之間的接觸面積。
As shown in FIG. 4M, one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable processes,
Or any combination thereof), a spacer 462 is formed along the sidewalls of the contact opening 460, the contact opening 461, the contact opening 463, and the source contact opening 465 to electrically isolate the P-type doped semiconductor layer 406. In some embodiments of the present invention, through the same deposition process, spacers 462 are formed along the sidewalls of the contact opening 460, the contact opening 461, the contact opening 463, and the source contact opening 465 to reduce the number of manufacturing processes. In some embodiments of the present invention, the source contact opening 458 is etched after the spacer 462 is formed, so that the spacer 462 is not formed along the sidewall of the source contact opening 458, so as to increase the gap between the source contact 464 and the source contact opening 458. The contact area between the P-type doped semiconductor layers 406.
如圖4N所示，分別在P型摻雜半導體層406的背面處的接觸開口460、接觸開口461和接觸開口463(在圖4M中所示)中形成接觸466、接觸468和接觸469。根據一些實施例，接觸466、接觸468和接觸469垂直地延伸穿過層間介電層456和P型摻雜半導體層406。可以使用相同的沉積製程來形成接觸466、接觸468和接觸469以及源極接觸464和源極接觸478，以減少沉積製程的數量。在本發明的其中一些實施例中，使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來將一種或多種導電材料沉積到接觸開口460、接觸開口461和接觸開口463中，以利用黏合層(例如，TiN)和導體層(例如，W)填充接觸開口460、接觸開口461和接觸開口463。然後，可以執行平坦化製程(例如，化學機械拋光(CMP))，以去除多餘的導電材料，使得接觸466、接觸468和接觸469的頂表面(以及源極接觸464和源極接觸478的頂表面)是與層間介電層456的頂表面齊平。在本發明的其中一些實施例中，由於接觸開口460、接觸開口461和接觸開口463是分別與週邊接觸438、週邊接觸440和週邊接觸439對準的，因此接觸466、接觸468和接觸469也分別在週邊接觸438、週邊接觸440和週邊接觸439上方並且與其接觸。
As shown in FIG. 4N, a contact 466, a contact 468, and a contact 469 are formed in the contact opening 460, the contact opening 461, and the contact opening 463 (shown in FIG. 4M) at the back surface of the P-type doped semiconductor layer 406, respectively. According to some embodiments, the contact 466, the contact 468, and the contact 469 extend vertically through the interlayer dielectric layer 456 and the P-type doped semiconductor layer 406. The same deposition process can be used to form the contact 466, the contact 468 and the contact 469, and the source contact 464 and the source contact 478 to reduce the number of deposition processes. In some embodiments of the present invention, one or more thin film deposition processes (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD)), any other suitable process, or Any combination thereof) to deposit one or more conductive materials into the contact opening 460, the contact opening 461, and the contact opening 463 to fill the contact opening 460, the contact opening with an adhesive layer (for example, TiN) and a conductor layer (for example, W) 461 and contact opening 463. Then, a planarization process (for example, chemical mechanical polishing (CMP)) can be performed to remove excess conductive material so that the top surfaces of contacts 466, 468, and 469 (and the top surfaces of source contacts 464 and source contacts 478) The surface) is flush with the top surface of the interlayer dielectric layer 456. In some embodiments of the present invention, since the contact opening 460, the contact opening 461, and the contact opening 463 are aligned with the peripheral contact 438, the peripheral contact 440, and the peripheral contact 439, respectively, the contact 466, the contact 468, and the contact 469 are also aligned. Above and in contact with peripheral contact 438, peripheral contact 440, and peripheral contact 439, respectively.
如圖4O所示，形成在接觸466上方並且與其接觸的、重佈線層470的第一互連470-1。結果，P型摻雜半導體層406可以透過源極接觸464、互連層477的第一互連470-1和接觸466電性連接到週邊接觸438。在本發明的其中一些實施例中，P型摻雜半導體層406透過源極接觸464、互連層477的第一互連470-1、接觸466、週邊接觸438、以及鍵合層446和鍵合層448電性連接到週邊電路452。類似地，形成在接觸469上方並且與其接觸的、重佈線層470的第二互連470-2。結果，N阱407可以透過源極接觸479、互連層477的第二互連470-2和接觸469電性連接到週邊接觸438。在本發明的其中一些實施例中，N阱407透過源極接觸479、互連層477的第二互連470-2、接觸469、週邊接觸439以及鍵合層446和鍵合層448電性連接到週邊電路452。
As shown in FIG. 40, the first interconnection 470-1 of the rewiring layer 470 is formed above and in contact with the contact 466. As a result, the P-type doped semiconductor layer 406 can be electrically connected to the peripheral contact 438 through the source contact 464, the first interconnection 470-1 and the contact 466 of the interconnection layer 477. In some embodiments of the present invention, the P-type doped semiconductor layer 406 penetrates the source contact 464, the first interconnect 470-1 of the interconnect layer 477, the contact 466, the peripheral contact 438, and the bonding layer 446 and the bond The bonding layer 448 is electrically connected to the peripheral circuit 452. Similarly, a second interconnection 470-2 of the rewiring layer 470 is formed over and in contact with the contact 469. As a result, the N well 407 can be electrically connected to the peripheral contact 438 through the source contact 479, the second interconnection 470-2 of the interconnection layer 477, and the contact 469. In some embodiments of the present invention, the N well 407 is electrically conductive through the source contact 479, the second interconnection 470-2 of the interconnection layer 477, the contact 469, the peripheral contact 439, and the bonding layer 446 and the bonding layer 448. Connect to the peripheral circuit 452.
如圖4O所示，形成在接觸468上方並且與其接觸的接觸襯墊474。在本發明的其中一些實施例中，透過濕式蝕刻和/或乾式蝕刻來去除鈍化層472的覆蓋接觸468的一部分，以曝露下面的重佈線層470的一部分，進而形成接觸襯墊474。結果，用於襯墊輸出的接觸襯墊474可以透過接觸468、週邊接觸440以及鍵合層446和鍵合層448電性連接到週邊電路452。
As shown in FIG. 40, a contact pad 474 is formed above and in contact with the contact 468. In some embodiments of the present invention, a part of the passivation layer 472 covering the contact 468 is removed by wet etching and/or dry etching to expose a part of the underlying redistribution layer 470 to form a contact pad 474. As a result, the contact pad 474 for pad output can be electrically connected to the peripheral circuit 452 through the contact 468, the peripheral contact 440, and the bonding layer 446 and the bonding layer 448.
應理解，方法600中的第一停止層可以是第一導電層(例如，金屬矽化物層)，其部分保留在最終產品中的導電層中，如以下關於方法601描述的。
為了便於描述，可以不再重複方法600和601之間的類似操作步驟的細節。參考圖6B，方法601從操作步驟602開始，在操作步驟602中，在第一基底上形成週邊電路。第一基底可以是矽基底。
It should be understood that the first stop layer in the method 600 may be a first conductive layer (for example, a metal silicide layer), part of which remains in the conductive layer in the final product, as described below with respect to the method 601.
For ease of description, the details of similar operation steps between methods 600 and 601 may not be repeated. Referring to FIG. 6B, the method 601 starts from operation step 602. In operation step 602, a peripheral circuit is formed on the first substrate. The first substrate may be a silicon substrate.
如圖6B所示，方法601進行到操作步驟605，在操作步驟605中，依次形成在第二基底上的犧牲層、在犧牲層上的第一導電層、在第一導電層上的具有N阱的P型摻雜半導體層、以及在P型摻雜半導體層上的介電堆疊層。在本發明的其中一些實施例中，第一導電層包括金屬矽化物。如圖4A所示，停止層405可以是包括金屬矽化物的導電層，即金屬矽化物層。應理解，以上與形成載體基底402、犧牲層403和P型摻雜半導體層406相關的描述可以類似地應用於方法601，並且因此，為了便於描述不再重複。
As shown in FIG. 6B, the method 601 proceeds to operation step 605. In operation step 605, the sacrificial layer on the second substrate, the first conductive layer on the sacrificial layer, and the first conductive layer with N The P-type doped semiconductor layer of the well and the dielectric stack layer on the P-type doped semiconductor layer. In some embodiments of the present invention, the first conductive layer includes metal silicide. As shown in FIG. 4A, the stop layer 405 may be a conductive layer including metal silicide, that is, a metal silicide layer. It should be understood that the above description related to the formation of the carrier substrate 402, the sacrificial layer 403, and the P-type doped semiconductor layer 406 can be similarly applied to the method 601, and therefore, for convenience of description, it will not be repeated.
如圖6B所示，方法601進行到操作步驟607，在操作步驟607中，形成各自垂直地延伸穿過介電堆疊層和P型摻雜半導體層、在第一導電層處停止的多個通道結構。在本發明的其中一些實施例中，為了形成通道結構，形成各自垂直地延伸穿過介電堆疊層和摻雜元件層、在第一導電層處停止的多個通道孔，並且沿著各個通道孔的側壁來依次沉積儲存膜和半導體通道。
As shown in FIG. 6B, the method 601 proceeds to operation step 607. In operation step 607, a plurality of channels each extending vertically through the dielectric stack layer and the P-type doped semiconductor layer and stopping at the first conductive layer are formed. structure. In some of the embodiments of the present invention, in order to form a channel structure, a plurality of channel holes each extending vertically through the dielectric stack layer and the doped element layer and stopping at the first conductive layer are formed, and along each channel The sidewall of the hole is used to sequentially deposit the storage film and the semiconductor channel.
如圖6B所示，方法601進行到操作步驟608，在操作步驟608中，利用儲存堆疊層替換介電堆疊層，使得各個通道結構垂直地延伸穿過儲存堆疊層和P型摻雜半導體層。在本發明的其中一些實施例中，為了利用儲存堆疊層替換介電堆疊層，蝕刻垂直地延伸穿過介電堆疊層、在P型摻雜半導體層處停止的開口，並且穿過開口，利用堆疊導電層替換堆疊犧牲層，以形成包括交錯的堆疊介電層和堆疊導電層的儲存堆疊層。
As shown in FIG. 6B, the method 601 proceeds to operation step 608. In operation step 608, the storage stack layer is used to replace the dielectric stack layer so that each channel structure vertically extends through the storage stack layer and the P-type doped semiconductor layer. In some of the embodiments of the present invention, in order to replace the dielectric stack with the storage stack, the etching extends vertically through the dielectric stack, the opening that stops at the P-type doped semiconductor layer, and passes through the opening, using The stacked conductive layer replaces the stacked sacrificial layer to form a storage stacked layer including staggered stacked dielectric layers and stacked conductive layers.
如圖6B所示，方法601進行到操作步驟610，在操作步驟610中，形成垂直地延伸穿過儲存堆疊層的絕緣結構。在本發明的其中一些實施例中，為了形成絕緣結構，在形成儲存堆疊層之後，將一種或多種介電材料沉積到開口中
以填充開口。如圖6B所示，方法601進行到操作步驟612，在操作步驟612中，將第一基底和第二基底晶圓以面對面的方式鍵合，使得儲存堆疊層在週邊電路上方。鍵合可以包括混合鍵合。
As shown in FIG. 6B, the method 601 proceeds to operation 610, in which an insulating structure extending vertically through the storage stack is formed. In some of the embodiments of the present invention, in order to form an insulating structure, after forming the storage stack layer, one or more dielectric materials are deposited into the opening
To fill the opening. As shown in FIG. 6B, the method 601 proceeds to operation step 612. In operation step 612, the first substrate and the second substrate wafer are bonded in a face-to-face manner, so that the storage stack layer is above the peripheral circuit. Bonding may include hybrid bonding.
如圖6B所示，方法601進行到操作步驟615，在操作步驟615中，依次去除第二基底、犧牲層、以及第一導電層的一部分，以曝露多個通道結構中的每一個的端部。可以從第二基底的背面執行去除。在本發明的其中一些實施例中，為了依次去除第二基底、犧牲層、以及第一導電層的一部分，去除第二基底，在停止層處停止，去除犧牲層的剩餘部分，在第一導電層處停止，並且去除第一導電層的一部分以曝露多個通道結構中的每一個的端部。
As shown in FIG. 6B, the method 601 proceeds to operation step 615. In operation step 615, the second substrate, the sacrificial layer, and a part of the first conductive layer are sequentially removed to expose the end of each of the plurality of channel structures. . The removal can be performed from the back of the second substrate. In some embodiments of the present invention, in order to sequentially remove the second substrate, the sacrificial layer, and a part of the first conductive layer, the second substrate is removed, stopping at the stop layer, and the remaining part of the sacrificial layer is removed. Stop at the layer, and remove a portion of the first conductive layer to expose the end of each of the plurality of channel structures.
應理解，以上與去除載體基底402和犧牲層403相關的描述可以類似地應用於方法601，並且因此為了便於描述不再重複。如圖4Q所示，在去除(在圖4G中所示的)犧牲層403之後，去除導電層405(例如，金屬矽化物層)的一部分以曝露通道結構414的上端。可以將導電層405進行圖案化，使得可以使用例如微影、濕式蝕刻和/或乾式蝕刻來去除在各個通道結構414正上方的一部分以曝露各個通道結構414。根據一些實施例，導電層405的剩餘部分保留在P型摻雜半導體層406上。
It should be understood that the above description related to the removal of the carrier substrate 402 and the sacrificial layer 403 can be similarly applied to the method 601, and therefore will not be repeated for ease of description. As shown in FIG. 4Q, after the sacrificial layer 403 (shown in FIG. 4G) is removed, a portion of the conductive layer 405 (for example, a metal silicide layer) is removed to expose the upper end of the channel structure 414. The conductive layer 405 may be patterned so that, for example, lithography, wet etching, and/or dry etching may be used to remove a portion directly above each channel structure 414 to expose each channel structure 414. According to some embodiments, the remaining part of the conductive layer 405 remains on the P-type doped semiconductor layer 406.
如圖6B所示，方法601進行到操作步驟617，在操作步驟617中，形成與多個通道結構的端部和第一導電層接觸的第二導電層。第二導電層可以包括金屬。在本發明的其中一些實施例中，為了形成第二導電層，蝕刻儲存膜的鄰接P型摻雜半導體層的一部分以形成圍繞半導體通道的一部分的凹部，對半導體通道的該部分進行摻雜，並且將金屬沉積到凹部中以與半導體通道的摻雜部分
接觸，並且沉積到凹部的外部以與第一導電層接觸。
As shown in FIG. 6B, the method 601 proceeds to operation step 617. In operation step 617, a second conductive layer in contact with the ends of the plurality of channel structures and the first conductive layer is formed. The second conductive layer may include metal. In some embodiments of the present invention, in order to form the second conductive layer, a part of the storage film adjacent to the P-type doped semiconductor layer is etched to form a recess surrounding a part of the semiconductor channel, and this part of the semiconductor channel is doped, And deposit the metal into the recess to interact with the doped part of the semiconductor channel
Contact, and deposit to the outside of the recess to contact the first conductive layer.
應理解，以上與去除儲存層416、阻擋層417和穿隧層415的鄰接P型摻雜半導體層406的一部分以形成凹部457相關的描述可以類似地應用於方法601，並且因此為了便於描述不再重複。如圖4Q所示，在(圖4J中所示的)凹部457中形成圍繞並且接觸半導體通道418的摻雜頂部部分的金屬層478，以及在凹部457的外部在導電層405(例如，金屬矽化物層)上形成金屬層478。金屬層478可以圍繞並且接觸通道結構414的在凹部457中的端部(例如，半導體通道418的摻雜部分)。金屬層478也可以在凹部457的外部的導電層405上方並且與其接觸。可以透過使用一種或多種薄膜沉積製程(例如，原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、任何其它合適的製程、或其任何組合)來沉積金屬膜(例如，W、Al、Ti、TiN、Co和/或Ni)以填充凹部457並且在凹部457的外部沉積在導電層405上，進而形成金屬層478。可以執行化學機械拋光(CMP)製程以去除任何多餘的金屬層478。根據一些實施例，由此形成包括金屬層478和導電層405的導電層459(作為圖2C中的立體記憶體元件260中的導電層222的一個示例)。在本發明的其中一些實施例中，將導電層459圖案化和蝕刻以便不覆蓋週邊區域。與方法600相比，可以透過在最終產品中保留導電層的第一停止層(例如，金屬矽化物層)部分來減少方法601中的製造製程的數量。
It should be understood that the above description related to removing a portion of the storage layer 416, the barrier layer 417, and the tunneling layer 415 adjacent to the P-type doped semiconductor layer 406 to form the recess 457 can be similarly applied to the method 601, and therefore, for ease of description, Repeat again. As shown in FIG. 4Q, a metal layer 478 surrounding and contacting the doped top portion of the semiconductor channel 418 is formed in the recess 457 (shown in FIG. 4J), and a conductive layer 405 (e.g., metal silicide A metal layer 478 is formed on the object layer). The metal layer 478 may surround and contact the end portion of the channel structure 414 in the recess 457 (for example, the doped portion of the semiconductor channel 418). The metal layer 478 may also be over and in contact with the conductive layer 405 outside the recess 457. The metal film can be deposited by using one or more thin film deposition processes (for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, or any combination thereof) (For example, W, Al, Ti, TiN, Co, and/or Ni) to fill the recess 457 and deposit on the conductive layer 405 outside the recess 457, thereby forming a metal layer 478. A chemical mechanical polishing (CMP) process can be performed to remove any excess metal layer 478. According to some embodiments, a conductive layer 459 including a metal layer 478 and a conductive layer 405 is thus formed (as an example of the conductive layer 222 in the three-dimensional memory element 260 in FIG. 2C). In some embodiments of the present invention, the conductive layer 459 is patterned and etched so as not to cover the peripheral area. Compared with the method 600, the number of manufacturing processes in the method 601 can be reduced by retaining the first stop layer (for example, the metal silicide layer) portion of the conductive layer in the final product.
如圖6B所示，方法601進行到操作步驟618，在操作步驟618中，形成在儲存堆疊層上方並且與P型摻雜半導體層接觸的第一源極接觸，以及形成在儲存堆疊層上方並且與N阱接觸的第二源極接觸。如圖6B所示，方法601進行到操作步驟620，在操作步驟620中，形成在第一源極接觸和第二源極接觸上方並且與其接觸的互連層。在本發明的其中一些實施例中，互連層包括在第一源極接
觸上方並且與其接觸的第一互連、以及在第二源極接觸上方並且與其接觸的第二互連。在本發明的其中一些實施例中，形成穿過P型摻雜半導體層並且與第一互連接觸的第一接觸，使得P型摻雜半導體層透過第一源極接觸和第一互連電性連接到第一接觸。在本發明的其中一些實施例中，形成穿過P型摻雜半導體層並且與第二互連接觸的第二接觸，使得N阱透過第二源極接觸和第二互連電性連接到第二接觸。
As shown in FIG. 6B, the method 601 proceeds to operation step 618. In operation step 618, a first source contact formed above the storage stack layer and in contact with the P-type doped semiconductor layer, and formed above the storage stack layer and The second source contact is in contact with the N well. As shown in FIG. 6B, the method 601 proceeds to operation 620, in which an interconnection layer above and in contact with the first source contact and the second source contact is formed. In some of the embodiments of the present invention, the interconnection layer is included in the first source connection
A first interconnect that is above and in contact with, and a second interconnect that is above and in contact with the second source contact. In some of the embodiments of the present invention, a first contact is formed through the P-type doped semiconductor layer and in contact with the first interconnection, so that the P-type doped semiconductor layer passes through the first source contact and the first interconnection. Sexually connected to the first contact. In some of the embodiments of the present invention, a second contact is formed through the P-type doped semiconductor layer and in contact with the second interconnect, so that the N-well is electrically connected to the second through the second source contact and the second interconnect. Two contact.
根據本發明內容的一個方面，一種3D記憶體元件包括：基底；在基底上的週邊電路；在週邊電路上方的包括交錯的導電層和介電層的儲存堆疊層；在儲存堆疊層上方的N型摻雜半導體層；各自垂直地延伸穿過儲存堆疊層進入N型摻雜半導體層中的多個通道結構；與多個通道結構的上端接觸的導電層，導電層的至少部分在N型摻雜半導體層上；以及在儲存堆疊層上方並且與N型摻雜半導體層接觸的源極接觸。
According to one aspect of the present invention, a 3D memory device includes: a substrate; a peripheral circuit on the substrate; a storage stack layer including interlaced conductive layers and dielectric layers above the peripheral circuit; and N on the storage stack layer Type doped semiconductor layer; a plurality of channel structures each extending vertically through the storage stack layer into the N-type doped semiconductor layer; a conductive layer in contact with the upper ends of the plurality of channel structures, at least part of the conductive layer is in the N-type doped semiconductor layer On the hetero-semiconductor layer; and the source contact above the storage stack layer and in contact with the N-type doped semiconductor layer.
在本發明的其中一些實施例中，N型摻雜半導體層包括多晶矽。
In some embodiments of the present invention, the N-type doped semiconductor layer includes polysilicon.
在本發明的其中一些實施例中，3D記憶體元件被配置為：當執行擦除操作步驟時生成GIDL輔助體偏壓。
In some embodiments of the present invention, the 3D memory device is configured to generate a GIDL auxiliary body bias when the erase operation step is performed.
在本發明的其中一些實施例中，這些通道結構中的各個通道結構包括儲存膜和半導體通道，並且儲存膜的上端在半導體通道的上端下方。
In some embodiments of the present invention, each of these channel structures includes a storage film and a semiconductor channel, and the upper end of the storage film is below the upper end of the semiconductor channel.
在本發明的其中一些實施例中，導電層包括金屬矽化物層和金屬層。
In some embodiments of the present invention, the conductive layer includes a metal silicide layer and a metal layer.
在本發明的其中一些實施例中，金屬矽化物層與半導體通道接觸，並且金屬層在金屬矽化物層上方並且與金屬矽化物層接觸。
In some embodiments of the present invention, the metal silicide layer is in contact with the semiconductor channel, and the metal layer is above and in contact with the metal silicide layer.
在本發明的其中一些實施例中，半導體通道的延伸進入N型摻雜半導體層中的一部分包括摻雜多晶矽。
In some embodiments of the present invention, a portion of the semiconductor channel extending into the N-type doped semiconductor layer includes doped polysilicon.
在本發明的其中一些實施例中，N型摻雜半導體層的厚度小於大約50奈米。
In some embodiments of the present invention, the thickness of the N-type doped semiconductor layer is less than about 50 nanometers.
在本發明的其中一些實施例中，3D記憶體元件還包括：在源極接觸上方並且電性連接到源極接觸的互連層。
In some embodiments of the present invention, the 3D memory device further includes: an interconnection layer above the source contact and electrically connected to the source contact.
在本發明的其中一些實施例中，3D記憶體元件還包括穿過N型摻雜半導體層的第一接觸。根據一些實施例，N型摻雜半導體層至少透過源極接觸、互連層和第一接觸電性連接到週邊電路。
In some embodiments of the present invention, the 3D memory device further includes a first contact passing through the N-type doped semiconductor layer. According to some embodiments, the N-type doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact, the interconnection layer and the first contact.
在本發明的其中一些實施例中，3D記憶體元件還包括：絕緣結構，其垂直地延伸穿過儲存堆疊層並且橫向地延伸以將多個通道結構分成多個塊。
在本發明的其中一些實施例中，絕緣結構的頂表面是與N型摻雜半導體層的底表面齊平的。
In some embodiments of the present invention, the 3D memory device further includes an insulating structure that extends vertically through the storage stack layer and extends laterally to divide the plurality of channel structures into a plurality of blocks.
In some embodiments of the present invention, the top surface of the insulating structure is flush with the bottom surface of the N-type doped semiconductor layer.
在本發明的其中一些實施例中，3D記憶體元件還包括：在週邊電路與儲存堆疊層之間的鍵合介面。
In some embodiments of the present invention, the 3D memory device further includes a bonding interface between the peripheral circuit and the storage stack layer.
在本發明的其中一些實施例中，3D記憶體元件還包括：穿過N型摻雜半導體層的第二接觸。根據一些實施例，互連層包括電性連接到第二接觸的接觸襯墊。
In some embodiments of the present invention, the 3D memory device further includes: a second contact passing through the N-type doped semiconductor layer. According to some embodiments, the interconnection layer includes a contact pad electrically connected to the second contact.
在本發明的其中一些實施例中，多個通道結構中的各個通道結構的上端是與N型摻雜半導體層的頂表面齊平的或者在N型摻雜半導體層的頂表面下方。
In some embodiments of the present invention, the upper end of each of the plurality of channel structures is flush with or below the top surface of the N-type doped semiconductor layer.
根據本發明內容的另一方面，一種3D記憶體元件包括：基底；在基底上方的包括交錯的導電層和介電層的儲存堆疊層；在儲存堆疊層上方的N型摻雜半導體層；以及各自垂直地延伸穿過儲存堆疊層進入N型摻雜半導體層中的多個通道結構。多個通道結構中的各個通道結構包括儲存膜和半導體通道。儲存膜的上端在半導體通道的上端下方。3D記憶體元件還包括與多個通道結構的半導體通道接觸的導電層。導電層的至少部分在N型摻雜半導體層上。
According to another aspect of the present disclosure, a 3D memory device includes: a substrate; a storage stack layer including interlaced conductive layers and dielectric layers above the substrate; an N-type doped semiconductor layer above the storage stack layer; and A plurality of channel structures each extending vertically through the storage stack layer into the N-type doped semiconductor layer. Each of the plurality of channel structures includes a storage film and a semiconductor channel. The upper end of the storage film is below the upper end of the semiconductor channel. The 3D memory device also includes a conductive layer in contact with the semiconductor channels of the plurality of channel structures. At least part of the conductive layer is on the N-type doped semiconductor layer.
在本發明的其中一些實施例中，導電層包括金屬矽化物層和金屬層。
In some embodiments of the present invention, the conductive layer includes a metal silicide layer and a metal layer.
在本發明的其中一些實施例中，金屬矽化物層是與半導體通道接觸的，並且金屬層在金屬矽化物層上方並且與金屬矽化物層接觸。
In some embodiments of the present invention, the metal silicide layer is in contact with the semiconductor channel, and the metal layer is above and in contact with the metal silicide layer.
在本發明的其中一些實施例中，金屬層是與半導體通道接觸的，並且金屬層的一部分在金屬矽化物層上方並且與金屬矽化物層接觸。
In some embodiments of the present invention, the metal layer is in contact with the semiconductor channel, and a part of the metal layer is above the metal silicide layer and is in contact with the metal silicide layer.
在本發明的其中一些實施例中，N型摻雜半導體層的厚度小於大約50
奈米。
In some embodiments of the present invention, the thickness of the N-type doped semiconductor layer is less than about 50
Nano.
在本發明的其中一些實施例中，3D記憶體元件還包括：絕緣結構，其垂直地延伸穿過儲存堆疊層並且橫向地延伸以將多個通道結構分成多個塊。
在本發明的其中一些實施例中，絕緣結構的頂表面是與N型摻雜半導體層的底表面齊平的。
In some embodiments of the present invention, the 3D memory device further includes an insulating structure that extends vertically through the storage stack layer and extends laterally to divide the plurality of channel structures into a plurality of blocks.
In some embodiments of the present invention, the top surface of the insulating structure is flush with the bottom surface of the N-type doped semiconductor layer.
在本發明的其中一些實施例中，3D記憶體元件還包括：在儲存堆疊層上方並且與N型摻雜半導體層接觸的源極接觸。
In some embodiments of the present invention, the 3D memory device further includes: a source contact above the storage stack layer and in contact with the N-type doped semiconductor layer.
在本發明的其中一些實施例中，3D記憶體元件還包括：在基底上方的週邊電路；以及在週邊電路與儲存堆疊層之間的鍵合介面。
In some embodiments of the present invention, the 3D memory device further includes: a peripheral circuit above the substrate; and a bonding interface between the peripheral circuit and the storage stack layer.
在本發明的其中一些實施例中，3D記憶體元件還包括：在源極接觸上方並且電性連接到源極接觸的互連層。
In some embodiments of the present invention, the 3D memory device further includes: an interconnection layer above the source contact and electrically connected to the source contact.
在本發明的其中一些實施例中，N型摻雜半導體層至少透過源極接觸和互連層電性連接到週邊電路。
In some embodiments of the present invention, the N-type doped semiconductor layer is electrically connected to the peripheral circuit at least through the source contact and the interconnection layer.
根據本發明內容的又一方面，一種3D記憶體元件包括：第一半導體結構；第二半導體結構；以及在第一半導體結構與第二半導體結構之間的鍵合介面。第一半導體結構包括週邊電路。第二半導體結構包括：包括交錯的導電層和介電層的儲存堆疊層；N型摻雜半導體層；各自垂直地延伸穿過儲存堆疊層進入N型摻雜半導體層中並且電性連接到週邊電路的多個通道結構；以及將多個
通道結構電性連接的導電層，其包括金屬矽化物層和金屬層。
According to another aspect of the present disclosure, a 3D memory device includes: a first semiconductor structure; a second semiconductor structure; and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes peripheral circuits. The second semiconductor structure includes: a storage stack layer including interlaced conductive layers and dielectric layers; an N-type doped semiconductor layer; each vertically extends through the storage stack layer into the N-type doped semiconductor layer and is electrically connected to the periphery Multiple channel structure of the circuit; and multiple
The conductive layer electrically connected to the channel structure includes a metal silicide layer and a metal layer.
在本發明的其中一些實施例中，N型摻雜半導體層的厚度小於大約50奈米。
In some embodiments of the present invention, the thickness of the N-type doped semiconductor layer is less than about 50 nanometers.
在本發明的其中一些實施例中，這些通道結構中的各個通道結構包括儲存膜和半導體通道，並且金屬矽化物層與多個通道結構的半導體通道接觸。
In some embodiments of the present invention, each of the channel structures includes a storage film and a semiconductor channel, and the metal silicide layer is in contact with the semiconductor channels of the plurality of channel structures.
在本發明的其中一些實施例中，這些通道結構中的各個通道結構包括儲存膜和半導體通道，並且金屬層與多個通道結構的半導體通道接觸。
In some embodiments of the present invention, each of the channel structures includes a storage film and a semiconductor channel, and the metal layer is in contact with the semiconductor channels of the plurality of channel structures.
在本發明的其中一些實施例中，第二半導體結構還包括：絕緣結構，其垂直地延伸穿過儲存堆疊層並且橫向地延伸以將多個通道結構分成多個塊。
In some of the embodiments of the present invention, the second semiconductor structure further includes an insulating structure that extends vertically through the storage stack and extends laterally to divide the plurality of channel structures into a plurality of blocks.
在本發明的其中一些實施例中，絕緣結構不垂直地延伸進入N型摻雜半導體層中。
In some embodiments of the present invention, the insulating structure does not extend vertically into the N-type doped semiconductor layer.
在本發明的其中一些實施例中，第二半導體結構還包括與N型摻雜半導體層接觸的源極接觸。
In some embodiments of the present invention, the second semiconductor structure further includes a source contact in contact with the N-type doped semiconductor layer.
在本發明的其中一些實施例中，第二半導體結構還包括互連層，並且N型摻雜半導體層至少透過源極接觸和互連層電性連接到週邊電路。
In some embodiments of the present invention, the second semiconductor structure further includes an interconnection layer, and the N-type doped semiconductor layer is electrically connected to peripheral circuits at least through the source contact and the interconnection layer.
在本發明的其中一些實施例中，這些通道結構中的各個通道結構不
延伸超過N型摻雜半導體層。
In some of the embodiments of the present invention, each of these channel structures is not
Extends beyond the N-type doped semiconductor layer.
根據本發明內容的一方面，一種立體(3D)記憶體元件，包括：一基底，在所述基底上方的一週邊電路，在所述週邊電路上方的包括交錯的多個導電層和多個介電層的一儲存堆疊層，在所述儲存堆疊層上方的一N型摻雜半導體層，多個通道結構，其各自垂直地延伸穿過所述儲存堆疊層進入所述N型摻雜半導體層中，與所述多個通道結構的一上端接觸的一導電層，其中，所述導電層的至少一部分在所述N型摻雜半導體層上，以及一源極接觸，其在所述儲存堆疊層上方，並且與所述N型摻雜半導體層接觸。
According to one aspect of the present invention, a three-dimensional (3D) memory device includes: a substrate, a peripheral circuit above the substrate, and a plurality of interlaced conductive layers and a plurality of dielectrics above the peripheral circuit. A storage stack of the electrical layer, an N-type doped semiconductor layer above the storage stack, a plurality of channel structures, each of which extends vertically through the storage stack into the N-type doped semiconductor layer In, a conductive layer in contact with an upper end of the plurality of channel structures, wherein at least a part of the conductive layer is on the N-type doped semiconductor layer, and a source contact, which is in the storage stack Above the layer and in contact with the N-type doped semiconductor layer.
在本發明的其中一些實施例中，所述N型摻雜半導體層包括多晶矽。
In some embodiments of the present invention, the N-type doped semiconductor layer includes polysilicon.
在本發明的其中一些實施例中，所述立體記憶體元件被配置為：當執行一擦除操作步驟時，生成一閘極致汲極洩漏(GIDL)輔助體偏壓。
In some embodiments of the present invention, the three-dimensional memory device is configured to generate a gate-drain leakage (GIDL) auxiliary body bias when an erasing operation step is performed.
在本發明的其中一些實施例中，所述通道結構中的各個通道結構包括一儲存膜和一半導體通道，並且所述儲存膜的一上端在所述半導體通道的一上端下方。
In some embodiments of the present invention, each channel structure in the channel structure includes a storage film and a semiconductor channel, and an upper end of the storage film is below an upper end of the semiconductor channel.
在本發明的其中一些實施例中，所述導電層包括一金屬矽化物層和
金屬層。
In some embodiments of the present invention, the conductive layer includes a metal silicide layer and
Metal layer.
在本發明的其中一些實施例中，所述金屬矽化物層與所述半導體通道接觸，並且所述金屬層在所述金屬矽化物層上方，並且與所述金屬矽化物層
接觸。
In some embodiments of the present invention, the metal silicide layer is in contact with the semiconductor channel, and the metal layer is above the metal silicide layer and is in contact with the metal silicide layer.
get in touch with.
在本發明的其中一些實施例中，所述半導體通道中的延伸進入所述N型摻雜半導體層中的一部分包括摻雜多晶矽。
In some embodiments of the present invention, a part of the semiconductor channel extending into the N-type doped semiconductor layer includes doped polysilicon.
在本發明的其中一些實施例中，所述N型摻雜半導體層的厚度小於50奈米。
In some embodiments of the present invention, the thickness of the N-type doped semiconductor layer is less than 50 nm.
在本發明的其中一些實施例中，還包括：在所述源極接觸上方並且電性連接到所述源極接觸的一互連層。
In some embodiments of the present invention, it further includes: an interconnection layer above the source contact and electrically connected to the source contact.
在本發明的其中一些實施例中，還包括：穿過所述N型摻雜半導體層的一第一接觸，其中，所述N型摻雜半導體層至少透過所述源極接觸、所述互連層和所述第一接觸，來電性連接到所述週邊電路。
In some of the embodiments of the present invention, it further includes: a first contact passing through the N-type doped semiconductor layer, wherein the N-type doped semiconductor layer passes through at least the source contact and the mutual The connecting layer and the first contact are electrically connected to the peripheral circuit.
在本發明的其中一些實施例中，還包括：一絕緣結構，其垂直地延伸穿過所述儲存堆疊層，並且橫向地延伸以將所述多個通道結構分成多個塊，其中，所述絕緣結構的一頂表面是與所述N型摻雜半導體層的一底表面齊平。
In some of the embodiments of the present invention, it further includes: an insulating structure that extends vertically through the storage stack and extends laterally to divide the plurality of channel structures into a plurality of blocks, wherein the A top surface of the insulating structure is flush with a bottom surface of the N-type doped semiconductor layer.
在本發明的其中一些實施例中，還包括：在所述週邊電路與所述儲存堆疊層之間的一鍵合介面。
In some embodiments of the present invention, it further includes: a bonding interface between the peripheral circuit and the storage stack layer.
在本發明的其中一些實施例中，還包括：穿過所述N型摻雜半導體層的一第二接觸，其中，所述互連層包括電性連接到所述第二接觸的一接觸襯墊。
In some embodiments of the present invention, it further includes: a second contact passing through the N-type doped semiconductor layer, wherein the interconnection layer includes a contact liner electrically connected to the second contact pad.
在本發明的其中一些實施例中，所述多個通道結構中的各個通道結構的一上端是與所述N型摻雜半導體層的一頂表面齊平，或者在所述N型摻雜半導體層的一頂表面下方。
In some embodiments of the present invention, an upper end of each of the plurality of channel structures is flush with a top surface of the N-type doped semiconductor layer, or on the top surface of the N-type doped semiconductor layer. Below a top surface of the layer.
根據本發明內容的又一方面，一種立體(3D)記憶體元件，包括：一基底，在所述基底上方的包括交錯的多個導電層和多個介電層的一儲存堆疊層，在所述儲存堆疊層上方的一N型摻雜半導體層，多個通道結構，其各自垂直地延伸穿過所述儲存堆疊層進入所述N型摻雜半導體層中，其中，所述多個通道結構中的各個通道結構包括一儲存膜和一半導體通道，所述儲存膜的一上端在所述半導體通道的一上端下方，以及與所述多個通道結構的所述半導體通道接觸的一導電層，其中，所述導電層的至少一部分在所述N型摻雜半導體層上。
According to another aspect of the present invention, a three-dimensional (3D) memory device includes: a substrate, a storage stacked layer including a plurality of interlaced conductive layers and a plurality of dielectric layers above the substrate, and An N-type doped semiconductor layer above the storage stack layer, a plurality of channel structures, each of which extends vertically through the storage stack layer into the N-type doped semiconductor layer, wherein the plurality of channel structures Each channel structure in includes a storage film and a semiconductor channel, an upper end of the storage film is below an upper end of the semiconductor channel, and a conductive layer in contact with the semiconductor channels of the plurality of channel structures, Wherein, at least a part of the conductive layer is on the N-type doped semiconductor layer.
在本發明的其中一些實施例中，所述導電層包括一金屬矽化物層和一金屬層。
In some embodiments of the present invention, the conductive layer includes a metal silicide layer and a metal layer.
在本發明的其中一些實施例中，所述金屬矽化物層與所述半導體通道接觸，並且所述金屬層在所述金屬矽化物層上方，並且與所述金屬矽化物層接觸。
In some embodiments of the present invention, the metal silicide layer is in contact with the semiconductor channel, and the metal layer is above and in contact with the metal silicide layer.
在本發明的其中一些實施例中，所述金屬層與所述半導體通道接觸，並且所述金屬層的一部分在所述金屬矽化物層上方，並且與所述金屬矽化物層接觸。
In some embodiments of the present invention, the metal layer is in contact with the semiconductor channel, and a part of the metal layer is above and in contact with the metal silicide layer.
在本發明的其中一些實施例中，還包括：一絕緣結構，其垂直地延伸穿過所述儲存堆疊層，並且橫向地延伸以將所述多個通道結構分成多個塊，其中，所述絕緣結構的一頂表面與所述N型摻雜半導體層的一底表面齊平。
In some of the embodiments of the present invention, it further includes: an insulating structure that extends vertically through the storage stack and extends laterally to divide the plurality of channel structures into a plurality of blocks, wherein the A top surface of the insulating structure is flush with a bottom surface of the N-type doped semiconductor layer.
根據本發明內容的又一方面，一種立體(3D)記憶體元件，包括：一第一半導體結構，其包括一週邊電路，一第二半導體結構，其包括：一儲存堆疊層，其包括交錯的多個導電層和多個介電層，一N型摻雜半導體層，多個通道結構，其各自垂直地延伸穿過所述儲存堆疊層進入所述N型摻雜半導體層中，並且電性連接到所述週邊電路，以及將所述多個通道結構電性連接的一導電層，其包括一金屬矽化物層和一金屬層，以及在所述第一半導體結構與所述第二半導體結構之間的一鍵合介面。
According to another aspect of the present invention, a three-dimensional (3D) memory device includes: a first semiconductor structure including a peripheral circuit, and a second semiconductor structure including: a storage stack layer including interleaved A plurality of conductive layers and a plurality of dielectric layers, an N-type doped semiconductor layer, and a plurality of channel structures, each of which extends vertically through the storage stack layer into the N-type doped semiconductor layer, and is electrically conductive A conductive layer connected to the peripheral circuit and electrically connecting the plurality of channel structures includes a metal silicide layer and a metal layer, and is connected to the first semiconductor structure and the second semiconductor structure One-click interface between.
前面對具體實施例的描述將如此揭示本發明內容的總體性質，以使得其他人可以透過應用本領域技術內的知識，在無需過度實驗的情況下容易地修改和/或適應這些具體實施例的各種應用，而不脫離本發明內容的總體構思。
因此，基於本文給出的教導和指導，這樣的適應和修改旨在處於所公開的實施例的等效物的含義和範圍內。將理解的是，本文中的措辭或術語是出於描述的目的而非限制的目的，使得本說明書的術語或措辭將由本領域技術人員根據教導和指導來解釋。
The foregoing description of the specific embodiments will thus reveal the overall nature of the content of the present invention, so that others can easily modify and/or adapt these specific embodiments without undue experimentation by applying knowledge in the art. Various applications without departing from the general idea of the present invention.
Therefore, based on the teaching and guidance given herein, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It will be understood that the terms or terms herein are for descriptive purposes rather than for limitation purposes, so that the terms or terms in this specification will be interpreted by those skilled in the art according to teaching and guidance.
上面已經借助於功能構建塊描述了本發明內容的實施例，所述功能構建塊示出了特定功能以及其關係的實現方式。為了描述的方便，本文任意地定義了這些功能構建塊的邊界。只要適當地執行了特定功能和關係，就可以定義替代邊界。
The embodiments of the content of the present invention have been described above with the help of functional building blocks, which show the implementation of specific functions and their relationships. For the convenience of description, this article arbitrarily defines the boundaries of these functional building blocks. As long as specific functions and relationships are properly performed, alternative boundaries can be defined.
發明內容和摘要部分可以闡述由發明人設想的本發明內容的一個或多個示例性實施例，但不是全部的示例性實施例，並且因此，並不旨在以任何方式限制本發明內容和所附的申請專利範圍。
The Summary and Abstract section may illustrate one or more exemplary embodiments of the content of the present invention envisaged by the inventor, but not all exemplary embodiments, and therefore, are not intended to limit the content and the content of the present invention in any way. The attached scope of patent application.
本發明內容的廣度和範圍不應當受上述示例性實施例中的任何一者的限制，而應當僅根據隨後的申請專利範圍以及其等效物來限定。
The breadth and scope of the content of the present invention should not be limited by any one of the above exemplary embodiments, but should only be limited according to the scope of subsequent patent applications and their equivalents.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.
