TWI734339B - Synchronization circuit and cascaded synchronization circuit for converting asynchronous signal into synchronous signal - Google Patents

Abstract

A synchronization circuit and a cascaded synchronization circuit for converting an asynchronous signal into at least one synchronous signal are provided. The synchronization circuit includes a signal control circuit, a flip-flop circuit, a clock enable circuit and a clock control circuit. The flip-flop circuit is coupled to the signal control circuit, the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit, and the clock control circuit is coupled to the flip-flop circuit and the clock enable circuit. The signal control circuit and the clock control circuit can guarantee hold time and setup time is sufficient to allow the flip-flop circuit to output the synchronous signal without glitch regardless of the asynchronous signal.

Description

Synchronous circuit for converting non-synchronous signals into synchronous signals and overlapping synchronization Circuit

The present invention relates to electronic circuits, in particular to a synchronous circuit and a cascaded synchronous circuit for converting an asynchronous signal into a synchronous signal.

In some integrated circuit (IC) designs (such as a controller circuit used to control the operation of a memory device), asynchronous signals need to be converted into synchronous signals before being transmitted to the corresponding functional blocks. Based on a reference clock signal, a synchronization circuit can convert an asynchronous signal into an output signal synchronized with the reference clock signal. However, in practice, the output signal of the synchronization circuit may have glitches in some cases. For example, when the edge of the asynchronous signal, such as the rising edge or the falling edge, is very close to the trigger edge of the reference clock signal, or when the asynchronous signal has a narrow pulse at the time point of the trigger edge of the reference clock signal The output signal of the synchronous circuit will be affected due to the uncertainty of the state of the non-synchronous signal during the wave time, resulting in the generation of glitches.

Therefore, one object of the present invention is to provide a synchronous circuit and a cascaded synchronous circuit for converting an asynchronous signal into a synchronous signal, so as to ensure that it can be properly protected without any glitch. Generate the synchronization signal.

At least one embodiment of the present invention provides a synchronization circuit for converting an asynchronous signal into at least one synchronization signal, wherein the synchronization circuit may include a signal control circuit, a flip-flop circuit, and a clock enable Circuit and a clock control circuit. The signal control circuit is used for latching a logic value of an internal input signal and outputting the internal input signal when the difference between the asynchronous signal and the synchronous signal is detected. The flip-flop circuit is coupled to the signal control circuit, and is used to output the synchronization signal at a time point of a transition edge of a flip-flop clock signal according to the internal input signal. The clock activation circuit is coupled to the signal control circuit and the flip-flop circuit, and is used to activate an internal clock signal when the difference between the synchronization signal and the internal input signal is detected. The clock control circuit is coupled to the flip-flop circuit and the clock enabling circuit, and is used to output the flip-flop clock signal in response to a pulse width of the internal clock signal.

At least one embodiment of the present invention provides a spliced synchronization circuit for converting an initial asynchronous signal into a final synchronous signal. The overlapping synchronization circuit may include a first synchronization circuit and a second synchronization circuit connected in series with each other, and each synchronization circuit of the first synchronization circuit and the second synchronization circuit is used to convert the synchronization circuit based on a main clock signal An asynchronous signal is converted into at least one synchronous signal. In particular, the first synchronization circuit converts the initial asynchronous signal into a temporary synchronization signal based on the main clock signal, and the second synchronization circuit converts the temporary synchronization signal into the final synchronization signal based on the main clock signal. Each of the aforementioned synchronization circuits may include a signal control circuit, a flip-flop circuit, a clock enable circuit, and a clock control circuit. The signal control circuit is used for latching a logic value of an internal input signal and outputting the internal input signal when the difference between the asynchronous signal and the synchronous signal is detected. The flip-flop circuit is coupled to the signal control circuit, and is used to output the synchronization signal at a time point of a transition edge of a flip-flop clock signal according to the internal input signal. The clock activation circuit is coupled to the signal control circuit and the flip-flop circuit, and is used to activate an internal clock signal when the difference between the synchronization signal and the internal input signal is detected. The clock control circuit is coupled to the flip-flop circuit and the clock enable circuit, and is used to respond to a pulse of the internal clock signal The wave width outputs the clock signal of the flip-flop. According to the overlapping synchronization circuit, regardless of the initial asynchronous signal, the phase relationship between the main clock signal and the final synchronization signal is fixed.

The synchronization circuit of the present invention provides a stable operation mechanism, which can ensure that the synchronization signal generated by the synchronization circuit will not have glitches regardless of the asynchronous signal. In addition, the present invention also provides a stacking architecture based on a synchronization circuit to ensure that the phase relationship between the synchronization signal and the target timing is fixed.

10, 51, 52: synchronization circuit

120: signal control circuit

121: And logic circuit

122, 126, 164, 181, 184, 185: inverse logic circuit

123,124: Inverse OR logic circuit

125,144,146,182,183,186: reverser

140: flip-flop circuit

142: Flip-flop logic circuit

160: Clock enable circuit

162: Mutually Exclusive or Logic Circuit

180: clock control circuit

50: Overlap synchronization circuit

CLK, VPU, CKE_AS, CKE_I, CKE_SB, CKE_S, CKE_O, PDK, PDKb, DK, DKb, ENDK, N1, N2, CKE_AS_INITIAL, CKE_S_TEMP, CKE_S_FINAL, CKE_I1, ENDK1, PDK1, ENDbC2, DKPD: Signal

310,320,330,340,410,420,430,440,610,620,630,640: condition

310a, 310b, 310c, 320a, 320b, 320c, 330a, 330b, 340a, 340b, 410a, 410b, 420a, 420b, 430a, 430b, 430c, 430d, 440a, 440b, 440c, 440d, 610a, 610b, 610c, 620a, 620b, 620c, 630a, 630b, 630c, 640a, 640b, 640c: point in time

FIG. 1 is a block diagram of a synchronization circuit according to an embodiment of the invention.

Fig. 2 is a schematic circuit diagram of the synchronization circuit shown in Fig. 1 according to an embodiment of the present invention.

FIG. 3 is a timing diagram of a plurality of signals in the synchronization circuit shown in FIG. 2 according to an embodiment of the present invention.

FIG. 4 is a timing diagram of a plurality of signals in the synchronization circuit shown in FIG. 2 according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a stacked synchronization circuit according to an embodiment of the present invention.

FIG. 6 is a timing diagram of a plurality of signals in the overlapping synchronization circuit shown in FIG. 5 according to an embodiment of the present invention.

Figure 1 is a block diagram of a synchronization circuit 10 according to an embodiment of the present invention. The synchronization circuit 10 is used to convert an asynchronous signal (such as the signal CKE_AS) into at least one synchronization signal (such as one or more synchronization signals). , Which are collectively referred to as the synchronization signal). The synchronization circuit 10 may include a signal control circuit 120, a flip-flop circuit 140, a clock enable circuit 160, and a clock control circuit 180. The flip-flop circuit 140 is coupled to the signal control circuit 120, the clock enable circuit 160 is coupled to the signal control circuit 120 and the flip-flop circuit 140, and the clock control circuit 180 is coupled to the flip-flop circuit 140 and the clock is enabled Circuit 160.

In the operation of the signal control circuit 120, the signal control circuit 120 can be used to determine the difference between the asynchronous signal (for example, the signal CKE_AS) and the synchronous signal (for example, any of the one or more synchronous signals such as the signal CKE_S). When detected, a logic value of an internal input signal (such as the signal CKE_I) is latched, and the internal input signal is output. In particular, when the signal CKE_S has a first logic value, in response to the signal CKE_AS changing from the first logic value to a second logic value, the signal control circuit 120 can latch the logic value of the signal CKE_I and output the logic value of the signal CKE_I. The signal CKE_I, wherein the logical value of the signal CKE_I is equal to the second logical value. For example, when the logic value of the signal CKE_S is “0” and the logic value of the signal CKE_AS changes from “0” to “1”, the signal control circuit 120 may latch the logic value of the signal CKE_I to “1” and output the signal CKE_I. For another example, when the logical value of the signal CKE_S is "1" and the logical value of the signal CKE_AS changes from "1" to "0", the signal control circuit 120 can latch the logical value of the signal CKE_I in "0" and output the signal CKE_I .

In the operation of the clock enabling circuit 160, the clock enabling circuit 160 can enable an internal clock signal (such as the signal PDKb) when the difference between the signal CKE_S and the signal CKE_I is detected. For example, if the difference between the signal CKE_S and the signal CKE_I is not detected, the internal clock signal can be disabled to save the overall power consumption of the synchronization circuit 10. In particular, when the signal CKE_S and the signal CKE_I have different logic values, the clock enable circuit 160 can output the signal PDKb according to a main clock signal such as the signal CLK; and when the signal CKE_S and the signal CKE_I have the same logic value, the signal CKE_I It can have a fixed logical value. For example, when the logical values of the signal CKE_S and the signal CKE_I are "0" and "1" (or "1" and "0" respectively), the clock enable circuit 160 can output the signal PDKb according to the signal CLK, that is, the enable signal PDKb state switching (toggling). For another example, when the logical values of the signal CKE_S and the signal CKE_I are both "0" (or both are "1"), the clock enable circuit 160 The logic value of the signal PDKb can be fixed at "1", that is, the state switching of the signal PDKb is disabled.

In the operation of the clock control circuit 180, the clock control circuit 180 can output a flip-flop clock signal (such as the signal DKb) in response to a pulse width of the signal PDKb. In particular, when the pulse width of the signal PDKb is greater than a predetermined width, the signal DKb may have a pulse width greater than a minimum width; and when the pulse width of the signal PDKb is less than the predetermined width, the signal DKb may have a Fixed logic value. For example, when the pulse width of the signal PDKb is greater than the predetermined width, the clock control circuit 180 can control the signal DKb to ensure that the pulse width of the signal DKb is greater than the minimum width. For another example, when the logical values of the signals CKE_I and CKE_S become different (for example, they become different logical values from each other), the time point is very close to an edge (for example, a falling edge) of the signal CLK, the pulse of the signal PDKb The wave width may therefore be smaller than the predetermined width, and the clock control circuit 180 can fix the signal DKb at "1", that is, disable the state switching of the signal DKb.

In the operation of the flip-flop circuit 140, the flip-flop circuit 140 can output the synchronization signal (such as the signal CKE_S) according to the signal CKE_I at a time point of a transition edge of the signal DKb. Based on the above-mentioned control of the signals CKE_I and DKb, sufficient setup time and hold time can be provided, so regardless of the signal CKE_AS, the flip-flop circuit 140 can stably output the signal CKE_S without With glitch.

FIG. 2 is a schematic circuit diagram of the synchronization circuit 10 according to an embodiment of the present invention. It should be noted that the terminals marked with the same symbol can be regarded as directly connected to each other, and the connecting lines between these terminals are omitted and not shown here for the sake of brevity.

As shown in FIG. 2, the flip-flop 140 may include a flip-flop logic circuit 142 (labeled “FF” for brevity) and one or more inverters such as inverters 144 and 146. In this embodiment, the flip-flop logic circuit 142 may include a plurality of input terminals (such as terminals D, K, Kb, and PU) and an output terminal (such as terminal Q), where the terminals D, K, Kb, and PU are respectively Used to receive the signals CKE_I, DKb, DK and VPU, and the terminal Q is used to transmit a signal CKE_O to the flip-flop 144, where the signal DK is The reverse signal of the signal DKb. The signal VPU is used to provide initial values to certain nodes in the synchronization circuit 10, and the logic value of the signal VPU can be changed from "0" to "1" when the synchronization circuit 10 is powered on (or activated). It should be noted that when the logic value of the signal VPU is "0", regardless of the signals CKE_I, DKb, and DK, the flip-flop logic circuit 142 can fix the signal CKE_O at "0" (or "1"); When the logic value of the signal VPU is "1", the flip-flop logic circuit 142 can output and update the signal CKE_O according to the signal CKE_I at the rising edge of the signal DKb; however, the present invention is not limited to this. In addition, the flip-flop 144 can generate the reverse signal of the signal CKE_O (such as the signal CKE_SB) and transmit the signal CKE_SB to the flip-flop 146; and the flip-flop 146 can generate the reverse signal of the signal CKE_SB such as the signal CKE_S.

As shown in Figure 2, the signal control circuit 120 may include an AND logic circuit 121, a NAND logic circuit 122, a NOR logic circuit 123, a NOR logic circuit 124, and a The inverter 125, in which the signal control circuit 120 may further include an inverter and logic circuit 126 for power-on control. A first input terminal and a second input terminal of the logic circuit 121 are used to receive the signals CKE_AS and VPU, respectively. An output terminal of the negative logic circuit 122 is coupled to a third input terminal of the logic circuit 121, and a first input terminal of the negative logic circuit 122 is used to receive the signal CKE_S. A first input terminal of the inverting logic circuit 123 is coupled to an output terminal of the inverting logic circuit 126, wherein a first input terminal and a second input terminal of the inverting logic circuit 126 are used to receive the signals CKE_SB and VPU. For example, when the logic value of the signal VPU is “0”, regardless of the signal CKE_SB, the inverse logic circuit 126 can transmit the logic value “1” to the inverted logic circuit 123. When the logic value of the signal VPU is “1”, the inverting logic circuit 126 can act as an inverter to transmit the inverted signal of the signal CKE_SB to the inverting logic circuit 123. Therefore, the first input terminal of the inverting logic circuit 123 is used to receive the synchronization signal (for example, any one of the signals CKE_O and CKE_S) or its derivative (derivative) after the synchronization circuit 10 is powered on (or enabled). For example, the signal transmitted by the reflexive and logic circuit 126). An output terminal of the inverting logic circuit 124 is coupled to a second input terminal of the inverting logic circuit 123 and a second input terminal of the inverting logic circuit 122, and a first input terminal of the inverting logic circuit 124 The sub is coupled to an output terminal of the NOR logic circuit 123, and a second input terminal of the NOR logic circuit 124 is coupled to an output terminal of the AND logic circuit 121. An input terminal of the inverter 125 is coupled to the output terminal of the inverter logic circuit 124 to allow the inverter 125 to output the signal CKE_I. Based on this architecture, the signal control circuit 120 can detect the change (such as state transition) of the signal CKE_AS relative to the signal CKE_S, and latch the changed logic value of the signal CKE_AS to provide sufficient setup time and hold time for the flip-flop 140 .

As shown in FIG. 2, the clock enable circuit 160 may include an exclusive-OR (XOR) logic circuit 162 and an inverted logic circuit 164. A first input terminal and a second input terminal of the exclusive OR logic circuit 162 are used to receive the internal input signal and the synchronization signal, respectively, to generate a signal ENDK that can indicate whether the logic values of the signals CKE_I and CKE_S are different. It should be noted that the synchronization signal sent to the mutual exclusion or logic circuit 162 for detection may be the signal CKE_O in some embodiments, but the invention is not limited thereto. The inverting logic circuit 164 is used to output the signal PDKb, wherein a first input terminal of the inverting logic circuit 164 is used to receive the signal CLK, and a second input terminal of the inverting logic circuit 164 is coupled to the exclusive OR logic An output terminal of the circuit 162 receives the signal ENDK.

As shown in FIG. 2, the clock control circuit 180 may include inverter logic circuits 181, 184, and 185, and inverters 182, 183, and 186. A first input terminal of the inverter logic circuit 181 is used to receive the signal PDKb, wherein an input terminal of the inverter 182 is coupled to an output terminal of the inverter logic circuit 181 to output the signal DKb, and the inverter 183 An input terminal is coupled to an output terminal of the inverter 182 to output the signal DK. A first input terminal and a second input terminal of the inverting logic circuit 185 are used to receive the signals DKb and VPU, respectively, and an output terminal of the inverting logic circuit 185 is coupled to an input terminal of the inverter 186. A first input terminal of the inverse logic circuit 184 is coupled to the output terminal of the inverse logic circuit 181, and an output terminal of the inverse logic circuit 184 is coupled to a second input terminal of the inverse logic circuit 181. It should be noted that when the logic state of the signal VPU is "1", the signal N1 output from the inverter 186 can be equivalent to the signal DKb. Therefore, the second input terminal of the logic circuit 184 is reversed After the synchronization circuit 10 is powered on, it is used to receive the flip-flop clock signal (such as the signal DKb) or its derivative (such as the signal N1).

For the clock control circuit 180, the predetermined width and the minimum width can be determined by the above-mentioned logic circuits (such as inverters 182 and 186, and one or more of the inverter logic circuits 185, 181, and 184). In this embodiment, the proportional parameter of the inverter 182 is smaller than the proportional parameter of the inverse logic circuit 184. For any of the above-mentioned logic circuits, the proportional parameter (the ratio of any one of the above-mentioned logic circuits) Parameter) represents the channel width to channel length ratio of the N-type transistor in it (width-to-length ratio) (which can be called ``(W/L) <sub>N</sub> ``) and the channel width of the P-type transistor in it The ratio between the channel length ratios (which may be referred to as "(W/L) _{P ").} Based on this architecture, the pull-down capability of the inverter 182 is smaller than the pull-down capability of the inverter logic circuit 184. Therefore, when a falling edge of the signal PDKb is transmitted to the inverting logic circuit 181 and thereby the signal PDK is pulled up, the signal N2 output by the inverting logic circuit 184 can be pulled down earlier than the signal DKb output by the inverter 182. It should be noted that if the low pulse width of the signal PDKb is not wide enough to pull up the signal N2 before the signal PDK is pulled down again, the signal N2 will not be pulled down, which means that the transition of the signal PDKb is ignored in this operation If the low pulse width of the signal PDKb is wide enough to pull down the signal N2, the signal PDK will not be pulled down until the signal N2 is pulled up again (it needs to be triggered by the signal N1), so that the pulse width of the signal DKb is greater than the above The minimum width means that if the high pulse width of the signal PDK is wide enough to pull down the signal N2, the signal DKb will have the minimum low pulse width corresponding to the delay time of at least five gates (185-186-184-181-182) , And if the high pulse width of the signal PDK is not wide enough to pull down the signal N2, the signal DKb will not have a low pulse.

FIG. 3 is a timing diagram of a plurality of signals in the synchronization circuit 10 according to an embodiment of the present invention. This embodiment illustrates four conditions such as conditions 310, 320, 330, and 340. In the condition 310, the signal CKE_AS turns to low when the signal CLK is low (that is, it has a logic value of "0") (that is, its logic state changes from "1" to "0"); in the situation 320, the signal CKE_AS is in the signal When CLK is low, it turns to high (that is, its logic state changes from "0" to "1"); in the condition 330, the signal CKE_AS is high when the signal CLK is high (that is, it has When there is a logic value "1"), it turns low; in condition 340, the signal CKE_AS turns high when the signal CLK is high.

Please refer to the situation 310 shown in Fig. 3 and the synchronization circuit 10 shown in Fig. 2. After the signal CKE_AS turns low at a time point 310a (the signal CKE_S is high at this moment), the signal CKE_I turns low, and the signal ENDK turns high. After the signal CLK turns high at a time point 310b, the signal DKb turns low. After the signal CLK turns low at a time point 310c, the signal DKb turns high, the signals CKE_O and CKE_S turn low, and the signal ENDK turns low.

Please refer to the situation 320 shown in Fig. 3 and the synchronization circuit 10 shown in Fig. 2. After the signal CKE_AS turns high at a time point 320a (the signal CKE_S is low at this moment), the signal CKE_I turns high, and the signal ENDK turns high. After the signal CLK turns high at a time point 320b, the signal DKb turns low. After the signal CLK turns low at a time point 320c, the signal DKb turns high, the signals CKE_O and CKE_S turn high, and the signal ENDK turns low.

Please refer to the situation 330 shown in Fig. 3 and the synchronization circuit 10 shown in Fig. 2. After the signal CKE_AS turns low at a time point 330a (the signal CKE_S is high at this moment), the signal CKE_I turns low, the signal ENDK turns high, and the signal DKb turns low. After the signal CLK turns low at a time point 330b, the signal DKb turns high, the signals CKE_O and CKE_S turn low, and the signal ENDK turns low.

Please refer to the situation 340 shown in Fig. 3 and the synchronization circuit 10 shown in Fig. 2. After the signal CKE_AS turns high at a time point 340a (the signal CKE_S is low at this moment), the signal CKE_I turns high, the signal ENDK turns high, and the signal DKb turns low. After the signal CLK turns low at a time point 340b, the signal DKb turns high, the signals CKE_O and CKE_S turn high, and the signal ENDK turns low.

FIG. 4 is a timing diagram of a plurality of signals in the synchronization circuit 10 according to another embodiment of the present invention. This embodiment illustrates four conditions such as conditions 410, 420, 430, and 440. In conditions 410 and 430, the signal CKE_AS changes to low when the signal CLK is high; and in conditions 420 and 440, the signal CKE_AS changes to high when the signal CLK is high; it should be noted that the signal CKE_AS changes edge In these states In each case, they are respectively close to the falling edge of the signal CLK, as shown in Fig. 4.

Please refer to the situation 410 shown in Fig. 4 and the synchronization circuit 10 shown in Fig. 2. After the signal CKE_AS changes to low at a time point 410a (the signal CKE_S is high and the signal CLK is high), the signal CKE_I changes to low, the signal ENDK changes to high, and the signals PDKb and DKb change to low. After the signal CLK goes low at a time point 410b, the signal PDKb returns to high. The high pulse of the signal PDK (for example, the pulse with the logic value "1") is wide enough to pull down the signal N2 and compare with the signal PDKb. Low pulses (such as pulses with logic value "0") can be further widened. In particular, after the signal PDK turns high and the signal N2 turns low, the signal PDK will not immediately turn low due to the high signal PDKb, until the signal N2 passes through the inverter 182, the inverter logic circuit 185, and the inverter. The signal paths of the director 186, the inverter logic circuit 184, and the inverter logic circuit 181 are pulled up again, thereby widening the high pulse of the signal PDK (or the low pulse of the signal DKb). After that, the signals CKE_O and CKE_S turn low, and the signal ENDK turns low.

Please refer to the situation 420 shown in Fig. 4 and the synchronization circuit 10 shown in Fig. 2. After the signal CKE_AS turns high at a time point 420a (the signal CKE_S is low and the signal CLK is high), the signal CKE_I turns high, the signal ENDK turns high, and the signals PDKb and DKb turn low. After the signal CLK goes low at a time point 420b, the signal PDKb returns to high, where the high pulse of the signal PDK can be further broadened compared to the low pulse of the signal PDKb, and some details similar to the situation 410 The content is for brevity and will not be repeated here. After that, the signals CKE_O and CKE_S turn high, and the signal ENDK turns low.

Please refer to the situation 430 shown in Fig. 4 and the synchronization circuit 10 shown in Fig. 2. After the signal CKE_AS turns low at a time point 430a (the signal CKE_S is high and the signal CLK is high), the signal CKE_I turns to low, the signal ENDK turns to high, and the signal PDKb turns to low. After the signal CLK goes low at a time point 430b, the signal PDKb goes high, but the high pulse of the signal PDK is too narrow to pull down the signal N2 (and the signal DKb), so the signal DKb is maintained in its original logic state And the flip-flop logic circuit 142 will not be triggered. After the signal CLK turns high at a time point 430c, the signal DKb turns Is low. After the signal CLK turns low at a time point 430d, the signal DKb turns high, the signals CKE_O and CKE_S turn low, and the signal ENDK turns low.

Please refer to the situation 440 shown in Fig. 4 and the synchronization circuit 10 shown in Fig. 2. After the signal CKE_AS changes to high at a time point 440a (the signal CKE_S is low and the signal CLK is high), the signal CKE_I changes to high, the signal ENDK changes to high, and the signal PDKb changes to low. After the signal CLK goes low at a time point 440b, the signal PDKb goes high, but the high pulse of the signal PDK is too narrow to pull down the signal N2 (and the signal DKb), so the signal DKb is maintained in its original logic state And the flip-flop logic circuit 142 will not be triggered. After the signal CLK turns high at a time point 440c, the signal DKb turns low. After the signal CLK turns low at a time point 440d, the signal DKb turns high, the signals CKE_O and CKE_S turn high, and the signal ENDK turns low.

As shown in Figure 4, the above-mentioned mechanism of widening the high pulse of the signal PDK (and the low pulse of the signal DKb) may cause the falling edge of the signal CLK (the target timing of the synchronization signal) to interact with the synchronization signal (such as the signal). There is an additional delay between the transition edges of CKE_O and CKE_S). In some embodiments, two identical synchronization circuits can be connected in series to avoid the above-mentioned delay problem, as shown in Figure 5, where Figure 5 is a cascaded synchronization circuit 50 according to an embodiment of the present invention. Schematic diagram. As shown in FIG. 5, the overlapping synchronization circuit 50 can convert an initial asynchronous signal (such as the signal CKE_AS_INITIAL) into a final synchronization signal (such as the signal CKE_S_FINAL). The overlapping synchronization circuit 50 may include a first synchronization circuit (such as the synchronization circuit 51) and a second synchronization circuit (such as the synchronization circuit 52) connected in series, and each of the synchronization circuits 51 and 52 may be based on a master time. The pulse signal (such as the signal CLK) converts an asynchronous signal into at least one synchronous signal. In this embodiment, the synchronization circuit 51 can convert the initial asynchronous signal (such as the signal CKE_AS_INITIAL) into a temporary synchronization signal (such as the signal CKE_S_TEMP) based on the signal CLK, and the synchronization circuit 52 can convert the temporary synchronization signal (such as the signal CKE_S_TEMP) based on the signal CLK ( For example, the signal CKE_S_TEMP) is converted into the final synchronization signal (for example, the signal CKE_S_FINAL). In addition, each of the synchronization circuits 51 and 52 can be based on those shown in Fig. 1 and Fig. 2 The synchronization circuit 10 is implemented. For ease of understanding, a single synchronization circuit (such as each of the synchronization circuits 51 and 52) is used to receive an asynchronous signal (such as the signal CKE_AS), a reference clock signal (such as the signal CLK), and a power-on The input terminals of the control signal (such as the signal VPU) are respectively marked as "AS", "RCLK" and "PU" in the figure 5, and are used to output a synchronization signal (such as any of the signals CKE_O and CKE_S) An output terminal is marked as "S" in Figure 5.

For ease of understanding, please refer to FIG. 6 together with FIG. 2 and FIG. 5, where FIG. 6 is a timing diagram of a plurality of signals in the cascading synchronization circuit 50 according to an embodiment of the present invention. In this embodiment, the signals CLK, CKE_AS, CKE_I, CKE_S, ENDK, PDKb, and DKb in the synchronization circuit 51 (first stage) can be represented by the signals CLK, CKE_AS_INITIAL, CKE_I1, CKE_S_TEMP, ENDK1, PDKb1, and DKb1, respectively. The signals CLK, CKE_AS, CKE_I, CKE_S, ENDK, PDKb, and DKb in the synchronization circuit 52 (second stage) can be represented by the signals CLK, CKE_S_TEMP, CKE_I2, CKE_S_FINAL, ENDK2, PDKb2, and DKb2, respectively.

For the first stage (synchronization circuit 51), please refer to conditions 610 and 620. In condition 610, after the signal CKE_AS_INITIAL turns low at a time point 610a (the signal CKE_S_TEMP is high and the signal CLK is high), the signal CKE_I1 turns to low, the signal ENDK1 turns to high, and the signals PDKb1 and DKb1 turn to low . After the signal CLK turns low at a time point 610b, the signal PDKb1 returns to high, and the high pulse of the signal PDK in the synchronization circuit 51 (for example, the pulse with the logic value "1") is wide enough to pull down the synchronization circuit 51 The signal N2 can be further broadened compared to the low pulse of the signal PDKb1 (for example, the pulse with the logic value "0"). In particular, after the signal N2 in the synchronization circuit 51 turns low in response to the signal PDK turning high, the signal PDK in the synchronization circuit 51 will not immediately turn low in response to the signal PDKb1 turning high, until the signal in the synchronization circuit 51 The signal N2 passes through the signal path of the inverter 182, the inverter logic circuit 185, the inverter 186, the inverter logic circuit 184, and the inverter logic circuit 181 in the synchronization circuit 51 until it is pulled up again, thereby widening the synchronization circuit The high pulse of signal PDK in 51 (or the low pulse of signal DKb1). After that, at a time point 610c, the signal CKE_S_TEMP turns low and the signal ENDK1 turns Low.

In condition 620, after the signal CKE_AS_INITIAL turns high at a time point 620a (the signal CKE_S_TEMP is low and the signal CLK is high), the signal CKE_I1 turns to high, the signal ENDK1 turns to high, and the signals PDKb1 and DKb1 turn to low . After the signal CLK goes low at a time point 620b, the signal PDKb1 returns to high, where the high pulse wave of the signal PDK in the synchronization circuit 51 can be broadened compared to the low pulse wave of the signal PDKb1, and is similar to the situation 610 Some of the details are not repeated here for the sake of brevity. After that, at a time point 620c, the signal CKE_S_TEMP turns high and the signal ENDK1 turns low.

For the second stage (synchronization circuit 52), please refer to conditions 630 and 640. In the condition 630, after the signal CKE_S_TEMP turns low at time 610c (the signal CKE_S_FINAL is high and the signal CLK is low at this moment), the signal CKE_I2 turns to low, and the signal ENDK2 turns to high. After the signal CLK turns high at a time point 630a, the signal PDKb2 turns low, and the signal DKb2 turns low. After the signal CLK turns low at a time point 630b, the signal DKb2 turns high, and at a time 630c, the signal CKE_S_FINAL turns low and the signal ENDK2 turns low.

In the condition 640, after the signal CKE_S_TEMP turns high at time 620c (the signal CKE_S_FINAL is low and the signal CLK is low at this moment), the signal CKE_I2 turns to high, and the signal ENDK2 turns to high. After the signal CLK turns high at a time point 640a, the signal PDKb2 turns low, and the signal DKb2 turns low. After the signal CLK turns low at a time point 640b, the signal DKb2 turns high, and at a time 640c, the signal CKE_S_FINAL turns high and the signal ENDK2 turns low.

For conditions 610 and 620 (similar to conditions 410 and 420) shown in Figure 6, the low pulse of signal DKb1 is widened, resulting in the synchronization at the falling edge of signal CLK (corresponding to time points 610b and 620b, respectively) There is an additional delay between the target timing of the signal and the transition edge of the signal CKE_S_TEMP (corresponding to time points 610c and 620c, respectively). Then, the synchronization circuit 52 can synchronize the signal CKE_S_TEMP based on the signal CLK. Please note that the synchronization circuit 51 has changed the transition edge of the signal CKE_S_TEMP The configuration is slightly after the falling edge of the signal CLK, so the target timing of the synchronization signal (for example, the signal CKE_S_FINAL) can be the next falling edge of the signal CLK (corresponding to time points 630a and 640a, respectively). For the conditions 630 and 640 shown in Figure 6, the time difference between time points 610c and 630b (or time points 620c and 640b) is sufficient (the time difference is long enough or the pulse width is wide enough), so the above pull The low pulse mechanism of the clock signal of the flip-flop (such as the signal DKb shown in Figure 2) will not be activated/activated. Therefore, the rising edge of the low pulse of the signal DKb2 can be determined by the signal CLK (or the signal CKE_I2) instead of the inverter 182, the inverter logic circuit 185, the inverter 186, the inverter logic circuit 184, and the inverter logic circuit 184. The signal path of the logic circuit 181 is determined, so compared to using a single-stage circuit (for example, only the synchronization circuit 51), the falling edge of the signal CLK (corresponding to the target timing of the synchronization signal at time points 630b and 640b, respectively) and The delay between the transition edges of the signal CKE_S_FINAL (corresponding to time points 630c and 640c, respectively) can be reduced and fixed.

According to the structure of the overlapping synchronization circuit 50 shown in Figure 5, regardless of the initial asynchronous signal (such as the signal CKE_AS_INITIAL), the main clock signal (such as the signal CLK) and the final synchronization signal (such as the signal CKE_S_FINAL) The phase relationship between them is fixed. For example, regardless of the initial asynchronous signal, each transition of the final synchronous signal will not have an additional delay relative to the corresponding falling edge of the main clock signal. For another example, regardless of the initial asynchronous signal, each transition of the final synchronization signal has a fixed delay relative to the corresponding falling edge of the main clock signal. Therefore, compared with a single synchronization circuit (such as the synchronization circuit 10), the overlapped synchronization circuit 50 can further improve the performance.

It should be noted that one or more of the signals in the synchronization circuit 10 (or the synchronization signals 51 and 52) can be regarded as equivalent, such as the signals CKE_O and CKE_S, so they are used to transmit these equivalent signals to certain nodes. One or more connections can be adjusted without affecting the overall operation of the synchronization circuit 10 (or the synchronization circuits 51 and 52) or less likely to affect the overall operation, but the present invention is not limited to this. In addition, the implementation of providing initial values to some nodes in the synchronization circuit 10 (or synchronization circuits 51 and 52) It is not limited to the embodiment shown in FIG. 2. In addition, the above embodiments provide a falling edge trigger synchronization circuit (for example, the generated synchronization signal is aligned with the falling edge of the reference clock signal), but the present invention is not limited to this. Those with ordinary knowledge in the art can modify one or more logic circuits in any one of the synchronization circuits 10 and 50 to implement, for example, modify the flip-flop circuit 140 (or the clock enable circuit 160) or its internal The logic circuit 142 of the flip-flop logic circuit 142, and the relevant details will not be repeated here for the sake of brevity.

In summary, the synchronization circuit of the present invention can respectively generate sufficient hold time and setup time for signal synchronization, and also provides a power saving mechanism. Therefore, regardless of the asynchronous signal, the synchronous circuit can ensure that the synchronous signal generated by the synchronous circuit has no glitches without greatly increasing the overall cost. In addition, the present invention further provides a stacking structure based on the synchronization circuit of the present invention to ensure that the phase relationship between the synchronization signal (such as the final synchronization signal) and the target clock (such as the main clock signal CLK) is fixed of. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Synchronization circuit

120: signal control circuit

140: flip-flop circuit

160: Clock enable circuit

180: clock control circuit

CKE_AS, CLK, CKE_S, CKE_I, PDKb, DKb: signal

Claims (14)

A synchronous circuit for converting an asynchronous signal into at least one synchronous signal includes: a signal control circuit for latching when the difference between the asynchronous signal and the synchronous signal is detected A logic value of the internal input signal and output the internal input signal; a flip-flop circuit, coupled to the signal control circuit, used for a transition edge of a flip-flop clock signal ) Output the synchronization signal according to the internal input signal; a clock enable circuit, coupled to the signal control circuit and the flip-flop circuit, is used to detect the difference between the synchronization signal and the internal input signal When it is detected, an internal clock signal is activated; and a clock control circuit, coupled to the flip-flop circuit and the clock activation circuit, is used to output the flip-flop according to a pulse width of the internal clock signal A pulse signal, wherein when the pulse width of the internal clock signal is greater than a predetermined width, the flip-flop clock signal has a pulse width greater than a minimum width, and when the pulse width of the internal clock signal When the width is less than the predetermined width, the flip-flop clock signal has a fixed logic value. For example, the synchronous circuit described in the first item of the scope of patent application, wherein when the synchronous signal has a first logic value, the signal control circuit locks because the asynchronous signal changes from the first logic value to a second logic value Storing the logical value of the internal input signal and outputting the internal input signal having the logical value, wherein the logical value of the internal input signal is equal to the second logical value. The synchronization circuit described in item 2 of the scope of patent application, wherein the signal control circuit includes: An AND logic circuit, wherein a first input terminal of the AND logic circuit is used to receive the asynchronous signal; a NAND logic circuit, wherein an output terminal of the NAND logic circuit is coupled to the And a second input terminal of the logic circuit, and a first input terminal of the logic circuit is used to receive the synchronization signal; a first NOR logic circuit, wherein the first NOR logic circuit A first input terminal is used to receive the synchronization signal or its derivative after the synchronization circuit is powered on; a second NOR logic circuit, wherein an output terminal of the second NOR logic circuit is coupled to A second input terminal of the first inverting logic circuit and a second input terminal of the inverting logic circuit, a first input terminal of the second inverting logic circuit is coupled to the first inverting logic circuit An output terminal, and a second input terminal of the second NOR logic circuit coupled to an output terminal of the AND logic circuit; and an inverter coupled to the output terminal of the second NOR logic circuit , Used to output the internal input signal. For example, the synchronization circuit described in item 1 of the scope of patent application, wherein when the synchronization signal and the internal input signal have different logic values, the clock enable circuit outputs the internal clock signal according to a main clock signal; and When the synchronization signal and the internal input signal have the same logic value, the internal clock signal has a fixed logic value. The synchronization circuit described in item 4 of the scope of patent application, wherein the clock enable circuit includes: an exclusive-OR (XOR) logic circuit, wherein a first input terminal of the exclusive-OR logic circuit and a The second input terminal is used to receive the internal input signal and the Synchronization signal; and an inverted logic circuit for outputting the internal clock signal, wherein a first input terminal of the inverted logic circuit is used to receive the main clock signal, and a first of the inverted logic circuit The two input terminals are coupled to an output terminal of the mutually exclusive OR logic circuit. For the synchronization circuit described in claim 1, wherein the clock control circuit includes: a first inverting logic circuit, wherein a first input terminal of the first inverting logic circuit is used to receive the internal time Pulse signal; an inverter for outputting the inverter clock signal, wherein an input terminal of the inverter is coupled to an output terminal of the first inverter logic circuit; and a second inverter logic circuit Circuit, wherein a first input terminal of the second inverter logic circuit is coupled to the output terminal of the first inverter logic circuit, and an output terminal of the second inverter logic circuit is coupled to the first inverter A second input terminal of the logic circuit and a second input terminal of the second inverter logic circuit are used to receive the flip-flop clock signal or its derivative after the synchronization circuit is powered on. For the synchronous circuit described in item 6 of the scope of patent application, the proportional parameter of the inverter is smaller than the proportional parameter of the second inverter logic circuit, and for any of the inverter and the second inverter logic circuit First, the ratio parameter represents the ratio between the width-to-length ratio of the N-type transistor and the ratio of the P-type transistor. A splicing used to convert an initial asynchronous signal into a final synchronous signal (cascaded) synchronization circuit, the cascaded synchronization circuit includes a first synchronization circuit and a second synchronization circuit connected in series with each other, and each synchronization circuit of the first synchronization circuit and the second synchronization circuit is used based on a master The clock signal converts an asynchronous signal into at least one synchronous signal, wherein the first synchronous circuit converts the initial asynchronous signal into a temporary synchronous signal based on the main clock signal, and the second synchronous circuit is based on the main clock signal The signal converts the temporary synchronization signal into the final synchronization signal, and each synchronization circuit includes: a signal control circuit for latching when the difference between the asynchronous signal and the synchronization signal is detected ) A logic value of an internal input signal and output the internal input signal; a flip-flop circuit, coupled to the signal control circuit, used for a transition edge of a flip-flop clock signal ( The time point of transition edge) outputs the synchronization signal according to the internal input signal; a clock enable circuit is coupled to the signal control circuit and the flip-flop circuit for the difference between the synchronization signal and the internal input signal When detected, an internal clock signal is activated; and a clock control circuit, coupled to the flip-flop circuit and the clock enabling circuit, is used to output the positive and negative signals in response to a pulse width of the internal clock signal When the pulse width of the internal clock signal is greater than a predetermined width, the flip-flop clock signal has a pulse width greater than a minimum width, and when the internal clock signal has a pulse width When the pulse width is less than the predetermined width, the flip-flop clock signal has a fixed logic value; wherein regardless of the initial asynchronous signal, the phase relationship between the main clock signal and the final synchronization signal is fixed. As for the overlapping synchronization circuit described in item 8 of the scope of patent application, when the synchronization signal has a first logic value, the asynchronous signal changes from the first logic value to a second logic value. Value, the signal control circuit latches the logic value of the internal input signal and outputs the internal input signal with the logic value, wherein the logic value of the internal input signal is equal to the second logic value. For example, the overlapped synchronous circuit described in item 9 of the scope of patent application, wherein the signal control circuit includes: an AND logic circuit, wherein a first input terminal of the AND logic circuit is used to receive the asynchronous signal; A NAND logic circuit, wherein an output terminal of the NAND logic circuit is coupled to a second input terminal of the NAND logic circuit, and a first input terminal of the NAND logic circuit is used to receive the synchronization Signal; a first NOR logic circuit, wherein a first input terminal of the first NOR logic circuit is used to receive the synchronization signal or its derivative (derivative) after the synchronization circuit is powered on; A second inverting logic circuit, wherein an output terminal of the second inverting logic circuit is coupled to a second input terminal of the first inverting logic circuit and a second input terminal of the inverting logic circuit, the first A first input terminal of the two inverted OR logic circuit is coupled to an output terminal of the first inverted OR logic circuit, and a second input terminal of the second inverted OR logic circuit is coupled to an output of the AND logic circuit Terminal; and an inverter, coupled to the output terminal of the second inverted OR logic circuit, for outputting the internal input signal. For example, the overlapped synchronization circuit described in item 8 of the scope of patent application, wherein when the synchronization signal and the internal input signal have different logic values, the clock enable circuit outputs the internal clock signal according to the main clock signal; And when the synchronization signal and the internal input signal have the same logic value, the internal clock signal has a fixed logic value. The overlapped synchronization circuit described in item 11 of the scope of patent application, wherein the clock enable circuit includes: an exclusive-OR (XOR) logic circuit, wherein a first input terminal of the exclusive-OR logic circuit And a second input terminal is used to receive the internal input signal and the synchronization signal respectively; and a reverse logic circuit is used to output the internal clock signal, wherein a first input terminal of the reverse logic circuit is used To receive the main clock signal, and a second input terminal of the inverse logic circuit is coupled to an output terminal of the mutual exclusion OR logic circuit. As described in the eighth item of the scope of patent application, the clock control circuit includes: a first inverter and logic circuit, wherein a first input terminal of the first inverter and logic circuit is used to receive the Internal clock signal; an inverter for outputting the inverter clock signal, wherein an input terminal of the inverter is coupled to an output terminal of the first inverter and the logic circuit; and a second inverter And logic circuit, wherein a first input terminal of the second inverter logic circuit is coupled to the output terminal of the first inverter logic circuit, and an output terminal of the second inverter logic circuit is coupled to the first A second input terminal of the inverse logic circuit, and a second input terminal of the second inverse logic circuit are used to receive the flip-flop clock signal or its derivative after the synchronization circuit is powered on . As described in item 13 of the scope of patent application, the proportional parameter of the inverter is smaller than the proportional parameter of the second inverter logic circuit. Contrary to any of the logic circuits, the ratio parameter indicates the ratio of the channel width to channel length of the N-type transistor in it (width-to-length ratio) and the channel width to channel length ratio of the P-type transistor in it The ratio between.

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