TWI734301B - Power circuit, gate driver and related operation control method for multi-source display system - Google Patents

Abstract

The present invention provides a protection circuit and related operation control method to enable the PFM circuit when the operating duration of the PFM circuit is not greater than a first threshold, and disables the PFM circuit when a rest duration of the PFM circuit is not greater than a second threshold. The present invention further provides a protection circuit and related operation control method to avoid starting excessive vertical scanning operations within one frame scanning period by masking one of the gate scanning start signal STV, the gate clock signal CKV and the gate discharge signal OEV. The present invention further provides a protection circuit and related operation control method to disable the gate scanning start signal STV when the number of clock cycles is not equal to a target number of clock cycles, which protects the gate driver from overload.

Description

Power supply circuit, gate driver and related operation control for multi-source display system method

The present invention refers to a power supply circuit, gate driver and related operation control method used in a multi-source display system.

More and more vehicles are equipped with car infotainment systems (which can be installed on a control panel or a rear mirror) to provide vehicle information or entertainment programs. For example, the car infotainment system can provide vehicle information, real-time reversing development, movie/music/video game and other services to users in the car based on the input signal. Therefore, in order to provide different services to users, one input signal must be switched from multiple input signals to the car infotainment system.

FIG. 1 is a functional block diagram of a multi-source display system 1 in the prior art. The multi-source display system 1 can be a control panel or a rear mirror of a vehicle, which is used to receive a first display signal SA from a multimedia signal source 16 under the control of a switching circuit 10, or from a reversing vehicle. The camera 17 receives a second display signal SB. A timing control circuit 11 is used to generate a plurality of gate control signals STV, CKV, OEV, and VSYNC to a gate driver 13 according to the first display signal SA or the second display signal SB, and to generate a plurality of sources Control signals CKH and HSYNC to a source driver 14. A power supply The circuit 12 is used to generate the gate power supplies VGH and VGL to the gate driver 13 and to generate a source power DDVDH to the source driver 14.

The applicant noticed that the first display signal SA and the second display signal SB will suffer noise interference during the switching operation of the switching circuit 10, which leads to (1) the timing control circuit 11 generates an erroneous control signal, and (2) ) The power circuit 12 may be damaged due to wrong control signals. In detail, the frequency of the first display signal SA and the second display signal SB is usually 60 Hz, and the frequency of the noise can reach 200 KHz. The gate control signal STV is a gate scan start signal, where a pulse of the gate scan start signal STV is used to indicate the start timing of the vertical alignment of the horizontal scan lines of an image frame . When the number of gate scanning start signals STV in one frame scanning period increases due to noise interference, it will cause the gate driver 13 to initiate excessive vertical scanning operations in one frame scanning period. As a result, the gate driver 13 will be overloaded (overloaded), and overcurrent may also be generated due to the overload to damage the gate driver 13.

FIG. 2 is a functional block diagram of the power supply circuit 12 in the prior art. A first pulse frequency modulation (Pulse Frequency Modulation, PFM) circuit 21 is used to convert a system power supply VCC into a first relay voltage VDDP, and a first charging pump 22 is used to convert the first relay voltage VDDP is converted to gate power VGH. A second pulse frequency modulation circuit 23 is used to convert the system power VCC into a second relay voltage VDDN, and a second charging pump 24 is used to convert the second relay voltage VDDN into a gate power VGL . Ideally, the gate power supply VGH or VGL will drive only one row of gate lines of the display panel at a time; however, when the number of gate scanning start signals STV in one frame scanning period increases due to noise interference , The current of the gate power supply VGH or VGL will leak to too many gate lines, causing the voltage level of the gate power supply VGH and VGL to drop. Therefore, the leakage currents of the gate power supplies VGH and VGL further cause the first charging pump 22 and the second charging pump 24 to fail to stop operating, which causes the power supply circuit 12 to be overloaded and generate heat. And damage.

Therefore, how to prevent the gate driver 13 and the power supply circuit 12 from being interfered by high-frequency noise during the switching operation of the input signal source has become one of the important issues in this field.

Therefore, the main purpose of the present invention is to provide a power supply circuit, gate driver and related operation control method for a multi-source display system to avoid starting too many vertical scanning operations in one frame scanning period.

The present invention discloses a power supply circuit for a display system, including a first pulse frequency modulation circuit for converting a system power supply into a first relay voltage; a first charging pump coupled to The first pulse frequency modulation circuit is used to convert the first relay voltage to a first grid power supply; a second pulse frequency modulation circuit is used to convert the system power supply to a first grid power supply; Two relay voltages; a second charging pump, coupled to the second pulse frequency modulation circuit, for converting the second relay voltage into a second grid power supply; and a protection circuit, coupled It is connected to the first pulse wave frequency modulation circuit, the first charging pump, the second pulse wave frequency modulation circuit and the second charging pump. The protection circuit is used to enable the first pulse frequency modulation circuit when an operation duration of the first pulse wave frequency modulation circuit and the second pulse wave frequency modulation circuit is not greater than a first threshold value A variable circuit and the second pulse wave frequency modulation circuit; and when a remaining duration of the first pulse wave frequency modulation circuit and the second pulse wave frequency modulation circuit is not greater than a second threshold At this time, the first pulse wave frequency modulation circuit and the second pulse wave frequency modulation circuit are disabled.

The present invention further discloses an operation control method for a protection circuit to protect a display A power circuit of the display system, wherein the power circuit includes a pulse frequency modulation circuit, a charging pump, and the protection circuit. The operation control method includes enabling the pulse frequency modulation circuit; When the frequency modulation circuit is enabled, an operation duration of the pulse frequency modulation circuit is accumulated; when a grid power source generated by the charging pump does not meet the standard, it is determined that the pulse frequency modulation circuit is Whether the operation duration is greater than a first threshold; when the operation duration of the pulse frequency modulation circuit is greater than the first threshold, the pulse frequency modulation circuit is disabled; when the pulse frequency When the modulation circuit has been disabled, accumulate a remaining duration of the pulse frequency modulation circuit; and when the remaining duration of the pulse frequency modulation circuit is greater than a second threshold, enable the Pulse frequency modulation circuit.

The present invention further discloses an operation control method for a protection circuit for protecting a gate driver of a display system. The operation control method includes detecting a pulse wave of a gate scanning start signal, wherein the pulse wave of the gate scanning start signal is used to indicate a start timing of a vertical scanning operation of a frame; After a first pulse of the gate control signal, mask the gate control signal and accumulate a mask duration of the gate control signal; and when the mask duration is greater than a threshold value, clear the mask duration And detect the pulse wave of the grid control signal.

The present invention further discloses a gate driver for a display system, including an input buffer for receiving a gate scan start signal, a shift clock signal and a plurality of gate mode signals, wherein the plurality of gates The polar mode signal is used to indicate the number of gate lines of a display panel of the display system; a bidirectional shift register is coupled to the input buffer; a potential converter is coupled to the bidirectional shift register Register; an output buffer, coupled to the potential converter, used to generate a plurality of grid conduction signals to the display panel according to the gate scanning start signal, the shift clock signal and the plurality of mode signals And a protection circuit, coupled to the bidirectional shift register and the potential converter, used to detect a first pulse of the gate scan start signal, when the shift clock signal When the number of a clock cycle is less than a target number, the gate scan start signal is disabled; and after a first pulse of the gate scan start signal is detected, when the shift clock signal is at that time When the number of pulse cycles is at the target number, the gate scanning start signal is enabled.

1, 5: Multi-source display system

10: Switching circuit

11.51: timing control circuit

12.3: Power supply circuit

122: input buffer

123: Bidirectional shift register

124: Potential converter

125: output buffer

13, 120: gate driver

14: Source driver

15: display panel

16: Multimedia source

17: Reversing camera

21, 31: First pulse frequency modulation circuit

22, 32: The first charging pump

23, 33: Second pulse frequency modulation circuit

30, 121, 501: protection circuit

24, 34: second charging pump

4, 7, 110, 140: Operation control process

401~409, 701~705, 901~907, 111~117, 141~148: steps

CKV, OEV, VSYNC, EVEN, DUAL, CPV, L/R, OEV, OEPSN, SEG, SGOFF, ODDCH: gate control signal

CKH, HSYNC: source control signal

N _CK : number of clock cycles

N _TA : target number of clock cycles

OUT0~OUT1080: grid conduction signal

SA: The first display signal

SB: Second display signal

STV, STV2: grid scanning start signal

T ₁ : the first threshold

T ₂ : The second threshold

T ₃ : preset duration

T _MA : Masking duration

T _OP : Operation duration

T _RS : remaining duration

Vbias: power signal

VCC: system power

VDDN: second relay voltage

VDDP: the first relay voltage

VGH, VGL: Gate power supply

DDVDH: source power

Figure 1 is a functional block diagram of a multi-source display system in the prior art.

Figure 2 is a functional block diagram of a power circuit in the prior art.

Figure 3 is a functional block diagram of a power supply circuit according to an embodiment of the present invention.

Figure 4 is a flowchart of an operation control process according to an embodiment of the present invention.

Figure 5 is a functional block diagram of a multi-source display system according to an embodiment of the present invention.

Figure 6 is a signal waveform diagram for implementing multiple control signals STV, CKV, VSYNC, and HSYNC according to the present invention.

Figure 7 is a flowchart of an operation control process according to an embodiment of the present invention.

Figure 8 is a signal waveform diagram of multiple control signals STV, CKV, VSYNC, and HSYNC according to an embodiment of the present invention.

Figure 9 is a flowchart of an operation control process according to an embodiment of the present invention.

Figure 10 is a signal waveform diagram of multiple control signals STV, CKV, OEV, VSYNC, and HSYNC according to an embodiment of the present invention.

Figure 11 is a flowchart of an operation control process according to an embodiment of the present invention.

FIG. 12 is a functional block diagram of a gate driver according to an embodiment of the present invention.

FIG. 13 is a signal waveform diagram of multiple gate control signals CPV, STV1, OUT0~OUT1081, STV2 according to an embodiment of the present invention.

Figure 14 is a flowchart of an operation control process according to an embodiment of the present invention.

FIG. 3 is a functional block diagram of a power supply circuit 3 according to an embodiment of the present invention. The power supply circuit 3 can be used in a multi-source display system, and includes a protection circuit 30, a first pulse frequency modulation (PFM) circuit 31, a first charging pump 32, and a second pulse frequency The modulation circuit 33 and a second charging pump 34.

The first pulse frequency modulation circuit 31 is coupled to the first charging pump 32 and the protection circuit 30, and is used to convert a system power supply VCC (usually 2.7~3.6 volts) into a first relay voltage VDDP, and The first charging pump 32 is used to convert the first relay voltage VDDP into a first gate power VGH. The second pulse frequency modulation circuit 33 is coupled to the second charging pump 34 and the protection circuit 30 for converting the system power VCC into a second relay voltage VDDN, and the second charging pump 34 is used for The second relay voltage VDDN is converted into a second gate power source VGL.

The protection circuit 30 is coupled to the first pulse wave frequency modulation circuit 31 and the first charging pump 32, and is used for the first operation duration and the first relay voltage of the first pulse wave frequency modulation circuit 31. VDDP and the first gate power supply VGH enable or disable the first pulse frequency modulation circuit 31. The protection circuit 30 is coupled to the second pulse frequency modulation circuit 33 and the second charging pump 34, and is used to perform a second operation duration and the second relay voltage of the second pulse frequency modulation circuit 33 VDDN and the second gate power supply VGL enable or disable the second pulse frequency modulation circuit 33.

Specifically, FIG. 4 is a flowchart of the operation control process 4 according to the first embodiment of the present invention. The operation control flow 4 can be executed by the protection circuit 30 and includes the following steps.

Step 401: Detect the relay voltage VDDP or VDDN generated by the pulse frequency modulation circuit.

Step 402: When the pulse wave frequency modulation circuit is enabled, the operation duration T _{OP of the} pulse wave frequency modulation circuit is accumulated.

Step 403: Determine whether the gate power VGH or VGL generated by the charging pump has reached the standard? If yes, proceed to step 404; if not, proceed to step 405.

Step 404: Clear the operation duration T _{OP of the} pulse wave frequency modulation circuit. Go back to step 401.

Step 405: Determine whether the operation duration T _{OP of the} pulse wave frequency modulation circuit is greater than the first threshold (T _OP > T ₁ )? If yes, go to step 406; if not, go to step 401.

Step 406: Disable the pulse wave frequency modulation circuit.

Step 407: When the pulse wave frequency modulation circuit is disabled, the remaining duration T _{RS of the} pulse wave frequency modulation circuit is accumulated.

Step 408: Determine whether the remaining duration T _{RS of the} pulse wave frequency modulation circuit is greater than the second threshold (T _RS > T ₂ )? If yes, go to step 409; if not, go to step 407.

Step 409: Clear the remaining duration T _{RS of the} pulse wave frequency modulation circuit. Go back to step 401.

Taking the operation of the protection circuit 30 controlling the first pulse frequency modulation circuit 31 as an example, in step 401, the protection circuit 30 detects the relay voltage VDDP generated by the first pulse frequency modulation circuit 31 to ensure the first The pulse frequency modulation circuit 31 has been enabled; in one embodiment, the protection circuit 30 detects any voltage generated inside the first pulse frequency modulation circuit 31. In step 402, when the first pulse wave frequency modulation circuit 31 is enabled, the protection circuit 30 accumulates the operation duration T _{OP of the} first pulse wave frequency modulation circuit 31. In step 403, the protection circuit 30 detects whether the first gate power supply VGH has reached the standard (for example, the first gate power supply VGH has reached a predetermined voltage level) to determine whether an operation cycle of the power supply circuit 3 has been completed. In step 404, when the first gate power supply VGH has reached the standard, the protection circuit 30 clears the operation duration T _OP ; then, the protection circuit 30 detects the relay voltage VDDP again in the next operation cycle of the power circuit 3. In step 405, when the first grid power source VGH does not meet the standard, the protection circuit 30 determines whether the operation duration T _{OP of the} first pulse frequency modulation circuit 31 is greater than the first threshold T ₁ (T _OP >T ₁ ) . In step 406, when the operation duration T _{OP of the} first pulse wave frequency modulation circuit 31 is greater than the first threshold value (T _OP > T ₁ ), the protection circuit 30 disables the first pulse wave frequency modulation circuit 31 At this time, it can be inferred that the first pulse wave frequency modulation circuit 31 has been overloaded for a predetermined period of time. In step 407, when the first pulse wave frequency modulation circuit 31 has been disabled, the protection circuit 30 accumulates the remaining duration T _{RS of the} first pulse wave frequency modulation circuit 31. In step 408, the protection circuit 30 determines whether the remaining duration T _{RS of the} first pulse frequency modulation circuit 31 is greater than the second threshold value T ₂ (T _RS > T ₂ ). In step 409, when the remaining duration T _{RS of the} pulse wave frequency modulation circuit is greater than the second threshold value, the protection circuit 30 clears the remaining duration T _{RS of the} first pulse wave frequency modulation circuit 31; then, the protection circuit 30 in the next operating cycle of the power supply circuit 3, the first pulse frequency modulation circuit 31 is enabled.

In other words, when the operation duration T _{OP is} not greater than the first threshold T ₁ , the protection circuit 30 enables the first pulse frequency modulation circuit 31 (and the second pulse frequency modulation circuit 33); and when the remaining When the duration T _{RS is} not greater than the second threshold value T ₂ , the protection circuit 30 disables the first pulse frequency modulation circuit 31 (and the second pulse frequency modulation circuit 33). By appropriately setting the first threshold value T ₁ and the second threshold value T ₂ , the first pulse wave frequency modulation circuit 31 (and the second pulse wave frequency modulation circuit 33) can be used in the switching circuit of a multi-source display system During the switching operation, it operates normally without interference from noise.

FIG. 5 is a functional block diagram of a multi-source display system 5 according to an embodiment of the present invention. The multi-source display system 5 can be a control panel or a rear mirror of a vehicle, which is used to receive a first display signal SA from a multimedia signal source 16 under the control of a switching circuit 10, or from a reversing vehicle. The camera 17 receives a second display signal SB. A timing control circuit 51 is used to generate a plurality of gate control signals STV, CKV, OEV, and VSYNC to a gate driver 13 according to the first display signal SA or the second display signal SB, and to generate a plurality of source control signals CKH , HSYNC to a source 14. A power circuit 12 is used to generate gate power VGH and VGL to the gate driver 13 and a voltage source DDVDH to the source 14. The timing control circuit 51 includes a protection circuit 501, where the protection circuit 501 is used to process at least one of the gate control signals STV, CKV, and OEV before the gate control signals STV, CKV, and OEV are input to the gate driver 13.

Figure 6 is a signal waveform diagram for implementing multiple control signals STV, CKV, VSYNC, and HSYNC according to the present invention. Whenever the first pulse of the gate scan start signal STV is detected, the protection circuit 501 is used to shield the gate scan start signal for a predetermined duration T3 (for example, a frame scan period) Any pulse of STV. Therefore, within the preset duration T ₃ , no vertical scanning operation will be initiated to avoid overload of the gate driver 13.

Specifically, FIG. 7 is a flowchart of the operation control process 7 according to the first embodiment of the present invention. The operation control flow 7 can be executed by the protection circuit 501 and includes the following steps.

Step 701: Detect the pulse wave of the gate scanning start signal STV, where the pulse wave of the gate scanning start signal STV is used to indicate the start timing of the vertical scanning operation of one frame.

Step 702: Determine whether the first pulse of the gate scan start signal STV has been detected? If yes, go to step 703; if not, go back to step 701.

Step 703: Shield the gate scanning start signal STV, and accumulate the shielding duration T _{MA of the} gate scanning start signal STV.

Step 704: Determine whether the masking duration T _MA is greater than the third threshold value T ₃ ? If yes, go to step 705; if not, go back to step 703.

Step 705: Clear the masking duration T _MA . Go back to step 701.

In step 701, the protection circuit 501 detects the pulse wave of the gate scanning start signal STV, where the pulse wave of the gate scanning start signal STV is used to indicate the start timing of the vertical scanning operation of one frame. In steps 702 to 703, when the first pulse of the gate scan start signal STV is detected, the protection circuit 501 shields the gate scan start signal STV and accumulates the masking duration T _{MA of the gate scan start signal STV} . In steps 704 to 705, when the shielding duration T _{MA is} greater than the third threshold value T ₃ (T _MA >T ₃ ), the protection circuit 501 clears the shielding duration T _MA . In one embodiment, within the third threshold value T ₃ , the protection circuit 501 forcibly sets the gate scan start signal STV to a logic zero state, but it is not limited to this. _{Therefore, during the masking duration T MA} (third threshold value T ₃ ) after the first pulse of the gate scan start signal STV is detected, the protection circuit 501 masks the pulse of the gate scan start signal STV . By appropriately setting the third threshold value T ₃ , it can be ensured that in one frame scan period, the gate driver 13 will not start excessive vertical due to noise interference caused by the switching operation of the switching circuit 10 of the multi-source display system 5 Scan operation.

Figure 8 is a signal waveform diagram of multiple control signals STV, CKV, VSYNC, and HSYNC according to an embodiment of the present invention. In this embodiment, when an abnormal pulse or an occasional pulse of the gate scan start signal STV is detected, the protection circuit 501 _{turns off the control within a predetermined duration T 3} (for example, a frame scan period) Signal CKV. The control signal CKV is a vertical scan line clock. When the rising edge of the control signal CKV is detected, the gate driver 13 will turn on a vertical scan line. Therefore, when the control signal CKV is turned off (or is forcibly set to a logic state), the gate driver 13 cannot _{turn on any vertical scanning lines within the predetermined duration T 3} , so that the gate driver 13 can be prevented from being overloaded.

Specifically, FIG. 9 is a flowchart of the operation control process 9 according to the first embodiment of the present invention. The operation control process 9 can be executed by the protection circuit 501 and includes the following steps.

Step 901: Detect the pulse wave of the gate scanning start signal STV, where the pulse wave of the gate scanning start signal STV is used to indicate the start timing of the vertical scanning operation of one frame.

Step 902: Determine whether the first pulse of the gate scan start signal STV has been detected? If yes, go to step 903; if no, go back to step 901.

Step 903: Accumulate the masking duration T _{MA of the} gate scan start signal STV.

Step 904: Determine whether the masking duration T _MA is greater than the third threshold value T ₃ ? If yes, go to step 905; if not, go to step 906.

Step 905: Clear the masking duration T _MA . Go back to step 901.

Step 906: Determine whether another pulse of the gate scan start signal STV is detected? If yes, go to step 907; if not, go back to step 903.

Step 907: Disable the gate control signal CKV, where the gate control signal CKV is used to indicate the turn-on timing of the vertical scan line. Go back to step 903.

In step 901, the protection circuit 501 detects the pulse wave of the gate scanning start signal STV, where the pulse wave of the gate scanning start signal STV is used to indicate the start timing of the vertical scanning operation of one frame. In steps 902 to 903, when the first pulse of the gate scanning start signal STV is detected, the protection circuit 501 accumulates the shielding duration T _{MA of the} gate scanning start signal STV. In steps 904 to 905, when the shielding duration T _{MA is} greater than the third threshold value T ₃ (T _MA >T ₃ ), the protection circuit 501 clears the shielding duration T _MA . In steps 904 to 906, when the masking duration T _{MA is} not greater than the third threshold T ₃ (T _MA <= T ₃ ), the protection circuit 501 determines whether another pulse of the gate scan start signal STV is detected . In steps 906 to 907, when another pulse of the gate scan start signal STV is detected, the protection circuit 501 disables the gate control signal CKV _{during the masking duration T MA} (the third threshold value T ₃₎ , Where the gate control signal CKV is used to indicate the turn-on timing of the vertical scan line. Therefore, when the control signal CKV is turned off (or is forcibly set to a logic state), the gate driver 13 cannot _{turn on any vertical scanning lines within the predetermined duration T 3} , so that the gate driver 13 can be prevented from being overloaded.

Figure 10 is a signal waveform diagram of multiple control signals STV, CKV, OEV, VSYNC, and HSYNC according to an embodiment of the present invention. In this embodiment, when an abnormal pulse or an occasional pulse of the gate scan start signal STV is detected, the protection circuit 501 _{turns off the control within a predetermined duration T 3} (for example, a frame scan period) Signal OEV. The gate control signal OEV is used to control the vertical scan line to discharge during the process of switching between two consecutive scan lines. For example, when detecting that the control signal OEV is in a logic zero state, the gate driver 13 discharges a vertical scan line. Therefore, when the control signal OEV _{is turned off (or is forcibly set to a logic state) within the preset duration T 3} , the gate driver 13 can control any vertical scan line to discharge, so as to avoid a large discharge current caused by overload Damage to the power supply circuit 12.

Specifically, FIG. 11 is a flowchart of an operation control process 110 according to an embodiment of the present invention. The operation control process 110 can be executed by the protection circuit 501 and includes the following steps.

Step 111: Detect the pulse wave of the gate scanning start signal STV, where the pulse wave of the gate scanning start signal STV is used to indicate the start timing of the vertical scanning operation of one frame.

Step 112: Determine whether the first pulse of the gate scan start signal STV has been detected? If yes, go to step 113; if not, go back to step 111.

Step 113: Accumulate the masking duration T _{MA of the} gate scan start signal STV.

Step 114: Determine whether the masking duration T _MA is greater than the third threshold value T ₃ ? If yes, go to step 115; if not, go to step 116.

Step 115: Clear the masking duration T _MA . Go back to step 111.

Step 116: Determine whether another pulse of the gate scan start signal STV is detected? If yes, go to step 117; if not, go back to step 113.

Step 117: Disable the gate control signal OEV, where the gate control signal OEV is used to indicate the discharge timing of the vertical scan line. Go back to step 113.

In step 111, the protection circuit 501 detects the pulse wave of the gate scanning start signal STV, where the pulse wave of the gate scanning start signal STV is used to indicate the start timing of the vertical scanning operation of one frame. In steps 112 to 113, when the pulse wave of the gate scanning start signal STV is detected, the protection circuit 501 accumulates the shielding duration T _{MA of the} gate scanning start signal STV. In steps 114 to 115, when the shielding duration T _{MA is} greater than the third threshold value T ₃ (T _MA >T ₃ ), the protection circuit 501 clears the shielding duration T _MA . In steps 114 to 116, when the masking duration T _{MA is} not greater than the third threshold T ₃ (T _MA <= T ₃ ), the protection circuit 501 determines whether another pulse of the gate scan start signal STV is detected . In steps 116 to 117, when another pulse of the gate scanning start signal STV is detected, the protection circuit 501 disables the gate control signal OEV _{during the masking duration T MA} (the third threshold value T ₃₎ , Where the gate control signal OEV is used to indicate the discharge timing of the vertical scan line. Therefore, the gate driver 13 cannot control too many vertical scan lines to discharge. When the control signal OEV is turned off (or forced to a logic state) within the _{preset duration T 3, the gate driver 13 can control any vertical} The scan lines are discharged, so that the large discharge current caused by overload can prevent the power circuit 12 from being damaged.

FIG. 12 is a functional block diagram of a gate driver 120 according to an embodiment of the present invention. The gate driver 120 can be used in the multi-source display system 5 of FIG. 5, and includes a protection circuit 121, an input buffer 122, a bidirectional shift register 123, a potential converter 124, and an output buffer 125.

The input buffer 122 is used to receive a plurality of gate control signals EVEN, DUAL, CPV, L/R, STV1, STV2, OEV, OEPSN, SEG, SGOFF, ODDCH, and gate mode signal modes 1 to 8. The power signals Vbias, VGH, VDD, VSS, and VGL generated by the power circuit 12 of the multi-source display system 5 are used to drive the level converter 124 and the output buffer 125. The output buffer 125 can periodically output a plurality of gate conduction signals OUT0 to OUT1081 to the display panel 15 to sequentially turn on the gate lines of the display panel 15.

The protection circuit 121 is coupled to the input buffer 122 and the bidirectional shift register 123, and is used to detect the first pulse of the gate scanning start signal STV1 (or STV2), and to count the gate control signal CPV The number of clock cycles N _{CK is used} to determine whether to disable the gate scan start signal STV1 (or STV2). Please note that the gate control signal CPV is used for the shift clock of the bidirectional shift register 123. After detecting the first pulse of the gate scan start signal STV1 (or STV2), when the number of clock cycles of the gate control signal CPV is less than a target number N _TA (for example, all gates included in the display panel) When the number of pole lines) (N _CK <N _TA ), the protection circuit 121 disables the gate scanning start signal STV1 (or STV2). When the number of clock cycles of the gate control signal CPV is equal to the target number N _TA (N _CK =N _TA ), it means that the vertical scanning operation of one frame has been completed, so the protection circuit 121 enables the gate scanning start signal STV2 (or STV1) to perform the vertical scanning operation frame of the next frame. Please note that the gate mode signal mode 1 to mode 8 are used to indicate the total number of gate lines of the display panel (therefore, the gate mode signal mode 1 to mode 8 can be used to infer the target number N _TA ).

FIG. 13 is a signal waveform diagram of multiple gate control signals CPV, STV1, OUT0~OUT1081, STV2 according to an embodiment of the present invention. In this embodiment, when the first pulse of the gate scan start signal STV1 is detected on the first rising edge of the gate control signal CPV (or within the first clock period), the protection circuit 121 The gate scanning start signal STV1 is disabled, so that the gate scanning start signal STV1 is maintained at a low logic level. Assuming that the display panel includes 1080 gate lines, by outputting the gate conduction signal OUT1 with a single pulse on the first clock cycle of the gate control signal CPV, and the gate control signal OUT1 on the second clock cycle of the gate control signal CPV. The gate conduction signal OUT2,..., and the gate conduction signal OUT1080 with a single pulse in the 1080th clock cycle of the gate control signal CPV, the gate driver 120 can sequentially turn on 1080 gates Wire. By analogy, the protection circuit 121 receives the first pulse wave of the gate scanning start signal STV2 by enabling the gate scanning start signal STV2 to perform the vertical scanning operation frame of the next frame.

Figure 14 is a flowchart of an operation control process 140 according to an embodiment of the present invention. The operation control process 140 can be executed by the protection circuit 120 and includes the following steps.

Step 141: Determine the target number of clock cycles N _TA .

Step 142: Detect the pulse wave of the gate scanning start signal STV, where the pulse wave of the gate scanning start signal STV is used to indicate the start timing of the vertical scanning operation of one frame.

Step 143: Determine whether the first pulse of the gate scan start signal STV has been detected? If yes, go to step 144; if no, go back to step 142.

Step 144: Disable the gate scan start signal STV.

Step 145: Accumulate the number of clock cycles N _CK .

Step 146: Determine whether the number of clock cycles N _CK is equal to the target number of clock cycles N _TA ? If yes, go to step 147; if no, go back to step 145.

Step 147: Clear the number of clock cycles N _CK .

Step 148: Enable the gate scan start signal STV. Go back to step 141.

In step 141, the protection circuit 120 determines the target number of clock cycles N _TA according to the gate mode signal mode 1 to mode 8. In step 142, the protection circuit 120 detects the pulse wave of the gate scanning start signal STV (for example, STV1 or STV2), where the pulse wave of the gate scanning start signal STV is used to indicate the start of the vertical scanning operation of one frame Timing. In steps 143 to 144, when the first pulse of the gate scanning start signal STV is detected, the protection circuit 120 disables the gate scanning start signal STV. In step 145, the protection circuit 120 accumulates the number of clock cycles N _CK . In steps 146 to 147, when the number of clock cycles N _CK is equal to the target number of clock cycles N _TA , the protection circuit 120 clears the number of clock cycles N _CK . In step 148, the protection circuit 120 enables the gate scanning start signal STV to perform the vertical scanning operation frame of the next frame. Therefore, the gate driver 13 cannot initiate too many vertical scanning operations in one frame scanning period, so that the gate driver 13 can be prevented from being overloaded.

In summary, the present invention provides a protection circuit and related operation control method for enabling the pulse wave frequency modulation circuit when the operation duration of the pulse wave frequency modulation circuit is not greater than the first threshold; and When the remaining duration of the pulse wave frequency modulation circuit is not greater than the second threshold value, the pulse wave frequency modulation circuit is disabled. The present invention further provides a protection circuit and related operation control method for shielding one of the gate scan start signal STV, the gate clock signal CKV, and the gate discharge signal OEV to avoid starting in one frame scan period. Start excessive vertical scanning operations, so as to avoid overloading of the power supply circuit and the gate driver. The present invention further provides a protection circuit and related operation control method for disabling the gate scanning start signal STV when the number of clock cycles is not equal to the target number, so as to avoid overloading of the gate driver.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

3: Power supply circuit

30: Protection circuit

31: The first pulse frequency modulation circuit

32: The first charging pump

33: Second pulse frequency modulation circuit

34: The second charging pump

VCC: system power

VDDP: the first relay voltage

VDDN: second relay voltage

VGL, VGH: Gate power supply

Claims (8)

A power supply circuit for a display system, comprising: a first pulse frequency modulation circuit for converting a system power supply into a first relay voltage; a first charging pump coupled to the first A pulse frequency modulation circuit is used to convert the first relay voltage to a first grid power supply; a second pulse frequency modulation circuit is used to convert the system power supply to a second grid power supply Relay voltage; a second charging pump, coupled to the second pulse frequency modulation circuit, used to convert the second relay voltage into a second grid power; and a protection circuit, coupled to The first pulse wave frequency modulation circuit, the first charging pump, the second pulse wave frequency modulation circuit, and the second charging pump are used as the first pulse wave frequency modulation circuit and When an operation duration of the second pulse wave frequency modulation circuit is not greater than a first threshold value, the first pulse wave frequency modulation circuit and the second pulse wave frequency modulation circuit are enabled; and when When a remaining duration of the first pulse frequency modulation circuit and the second pulse frequency modulation circuit is not greater than a second threshold, the first pulse frequency modulation circuit and the second pulse frequency modulation circuit are disabled Two-pulse frequency modulation circuit. The power supply circuit according to claim 1, wherein the protection circuit detects a first relay voltage generated by the first pulse frequency modulation circuit to determine whether the first pulse frequency modulation circuit has Yes, and the protection circuit detects a second relay voltage generated by the second pulse frequency modulation circuit to determine whether the second pulse frequency modulation circuit is enabled. The power supply circuit according to claim 1, wherein the protection circuit detects the first gate power generated by the first charging pump and the second gate power generated by the second charging pump to determine the power circuit Whether an operation cycle of the first charging pump has been completed; and when the first grid generated by the first charging pump When the pole power has reached the standard and the operation period of the power circuit has been completed, the protection circuit clears the operation duration of the first pulse frequency modulation circuit, and when the second grid generated by the second charging pump When the pole power has reached the standard and the operation period of the power circuit has been completed, the protection circuit clears the operation duration of the second pulse frequency modulation circuit. The power supply circuit of claim 1, wherein when the remaining duration of the first pulse frequency modulation circuit is greater than the second threshold, the protection circuit clears the first pulse frequency modulation circuit The remaining duration, and when the remaining duration of the second pulse frequency modulation circuit is greater than the second threshold, the protection circuit clears the remaining duration of the second pulse frequency modulation circuit. An operation control method for a display system to protect a power circuit of a display system, wherein the power circuit includes a pulse frequency modulation circuit, a charging pump and the protection circuit, and the operation control method includes : Enable the pulse frequency modulation circuit; when the pulse frequency modulation circuit is enabled, accumulate an operation duration of the pulse frequency modulation circuit; when the charging pump generates a grid When the pole power supply fails to meet the standard, it is determined whether the operation duration of the pulse frequency modulation circuit is greater than a first threshold; when the operation duration of the pulse frequency modulation circuit is greater than the first threshold, Disable the pulse frequency modulation circuit; when the pulse frequency modulation circuit has been disabled, accumulate a remaining duration of the pulse frequency modulation circuit; and when the pulse frequency modulation circuit When the remaining duration of is greater than a second threshold, the pulse wave is enabled Frequency modulation circuit. The operation control method of claim 5, wherein after the step of enabling the pulse frequency modulation circuit, the operation control method further comprises: detecting a relay voltage generated by the pulse frequency modulation circuit , To determine whether the pulse frequency modulation circuit has been enabled. The operation control method of claim 5, wherein after the step of accumulating the operation duration of the pulse wave frequency modulation circuit when the pulse wave frequency modulation circuit is enabled, the operation control method is further Including: detecting the grid power generated by the charging pump to determine whether an operation cycle of the power circuit has been completed; and when the grid power generated by the charging pump has reached the standard and the operation cycle of the power circuit When completed, the operation duration of the pulse frequency modulation circuit is cleared. The operation control method according to claim 5, wherein after the step of accumulating the remaining duration of the pulse wave frequency modulation circuit when the pulse wave frequency modulation circuit has been disabled, the operation control method is further The method includes: when the remaining duration of the pulse wave frequency modulation circuit is greater than the second threshold value, clearing the remaining duration of the pulse wave frequency modulation circuit.

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