CN113053278A - Power supply circuit, grid driver and related operation control method for multi-source display system - Google Patents

Power supply circuit, grid driver and related operation control method for multi-source display system Download PDF

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Publication number
CN113053278A
CN113053278A CN201911363463.3A CN201911363463A CN113053278A CN 113053278 A CN113053278 A CN 113053278A CN 201911363463 A CN201911363463 A CN 201911363463A CN 113053278 A CN113053278 A CN 113053278A
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China
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gate
frequency modulation
circuit
pulse frequency
modulation circuit
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CN201911363463.3A
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CN113053278B (en
Inventor
廖启宏
吴长隆
彭仁俊
廖焕森
许国栋
张维仁
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Himax Technologies Ltd
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Himax Technologies Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Abstract

The invention provides a protection circuit and a related operation control method, which are used for enabling a pulse frequency modulation circuit when the operation duration of the pulse frequency modulation circuit is not more than a first threshold value; and de-energizing the pulse frequency modulation circuit when the remaining duration of the pulse frequency modulation circuit is not greater than the second threshold. The present invention further provides a protection circuit and related operation control method for masking one of the gate scan start signal STV, the gate clock signal CKV and the gate discharge signal OEV to prevent the power circuit and the gate driver from being overloaded. The invention also provides a protection circuit and a related operation control method, which are used for de-energizing the grid scanning starting signal STV when the number of the clock cycles is not equal to the target number so as to avoid the overload phenomenon of the grid driver.

Description

Power supply circuit, grid driver and related operation control method for multi-source display system
[ technical field ] A method for producing a semiconductor device
The invention relates to a power supply circuit, a grid driver and a related operation control method for a multi-source display system.
[ background of the invention ]
More and more vehicles are equipped with in-vehicle infotainment systems (which may be mounted on the control panel or on the rear-view mirror) for providing vehicle information or entertainment. For example, the infotainment system for vehicles can provide services such as vehicle information, real-time reverse images, or movies/music/video games to users in the vehicle according to the input signals. Therefore, in order to provide different services to the user, one input signal must be switched from among a plurality of input signals to the infotainment system for the vehicle.
Fig. 1 is a functional block diagram of a multi-source display system 1 in the prior art. The multi-source display system 1 can be a control panel or a rear view mirror of a vehicle for receiving a first display signal SA from a multimedia signal source 16 or a second display signal SB from a back-up video camera 17 under the control of a switching circuit 10. A Timing control circuit 11 is used for generating a plurality of gate control signals STV, CKV, OEV, VSYNC to a gate driver 13 and a plurality of source control signals CKH, HSYNC to a source driver 14 according to the first display signal SA or the second display signal SB. A power supply circuit 12 is used to generate gate power sources VGH, VGL to the gate driver 13 and a source power source DDVDH to the source driver 14.
The applicant has noticed that the first display signal SA and the second display signal SB are subjected to noise during the switching operation of the switching circuit 10, which results in (1) the timing control circuit 11 generating an erroneous control signal, and (2) the power supply circuit 12 being damaged by the erroneous control signal. In detail, the frequency of the first display signal SA and the second display signal SB is usually 60Hz, and the frequency of the noise can reach 200 KHz. The gate control signal STV is a gate scan start signal, wherein a pulse of the gate scan start signal STV indicates a start timing at which a row scan line (row) of a frame is aligned in a vertical direction. When the number of the gate scan start signals STV in one frame scan period increases due to noise interference, the gate driver 13 may be caused to start excessive vertical scan operations in one frame scan period. As a result, the gate driver 13 is overloaded (overloaded), and the gate driver 13 may be damaged by an overcurrent due to the overload.
Fig. 2 is a functional block diagram of a power circuit 12 in the prior art. A first Pulse Frequency Modulation (PFM) circuit 21 is used to convert a system power VCC into a first relay voltage VDDP, and a first charge pump 22 is used to convert the first relay voltage VDDP into a gate power VGH. A second pulse frequency modulation circuit 23 is used to convert the system power VCC into a second intermediate voltage VDDN, and a second charge pump 24 is used to convert the second intermediate voltage VDDN into the gate power VGL. Ideally, the gate power VGH or VGL will drive only one row (row) gate line of the display panel at a time; however, when the number of the gate scan start signals STV within one frame scan period increases due to noise interference, the current of the gate power VGH or VGL may leak to an excessive gate line, resulting in a decrease in the voltage level of the gate power VGH, VGL. Therefore, the leakage current of the gate power sources VGH and VGL further causes the first charge pump 22 and the second charge pump 24 to stop operating, which causes the power source circuit 12 to be overloaded, heated and damaged.
Therefore, how to avoid the gate driver 13 and the power circuit 12 from being interfered by high frequency noise during the switching operation of the input signal source has become one of the important issues in the art.
[ summary of the invention ]
It is therefore a primary objective of the claimed invention to provide a power circuit, a gate driver and an associated operation control method for a multi-source display system, which can prevent excessive vertical scanning operations from being initiated within one frame period.
The invention discloses a power supply circuit, which is used for a display system and comprises a first pulse frequency modulation circuit, a second pulse frequency modulation circuit and a first relay circuit, wherein the first pulse frequency modulation circuit is used for converting a system power supply into a first relay voltage; a first charge pump, coupled to the first pulse frequency modulation circuit, for converting the first intermediate voltage into a first gate power; a second pulse frequency modulation circuit for converting the system power supply into a second relay voltage; a second charge pump, coupled to the second pulse frequency modulation circuit, for converting the second intermediate voltage into a second gate power; and a protection circuit coupled to the first PFM circuit, the first charge pump, the second PFM circuit and the second charge pump. The protection circuit is used for enabling (Enable) the first pulse frequency modulation circuit and the second pulse frequency modulation circuit when the operation duration of the first pulse frequency modulation circuit and the second pulse frequency modulation circuit is not more than a first threshold value; and when a remaining duration of the first and second PFM circuits is not greater than a second threshold, disabling (Disable) the first and second PFM circuits.
The invention also discloses an operation control method for a protection circuit, which is used for protecting a power supply circuit of a display system, wherein the power supply circuit comprises a pulse frequency modulation circuit, a charge pump and the protection circuit; accumulating an operation duration of the pulse frequency modulation circuit when the pulse frequency modulation circuit is enabled; when a grid power supply generated by the charge pump does not reach a standard, judging whether the operation duration of the pulse frequency modulation circuit is larger than a first threshold value or not; when the operation duration of the pulse frequency modulation circuit is greater than the first threshold value, disabling the pulse frequency modulation circuit; accumulating a remaining duration of the PFM circuit when the PFM circuit has been disabled; and enabling the pulse frequency modulation circuit when the residual duration of the pulse frequency modulation circuit is greater than a second threshold value.
The invention also discloses an operation control method for the protection circuit, which is used for protecting a grid driver of a display system. The operation control method comprises detecting a pulse of a gate scanning start signal, wherein the pulse of the gate scanning start signal is used for indicating a start timing of a vertical scanning operation of one frame; after detecting a first pulse of the grid control signal, shielding the grid control signal and accumulating a shielding duration of the grid control signal; and clearing the shielding duration and detecting the pulse of the grid control signal when the shielding duration is greater than a threshold value.
The invention also discloses a gate driver, which is used for a display system and comprises an input buffer, a shift clock pulse signal and a plurality of gate mode signals, wherein the input buffer is used for receiving a gate scanning starting signal, the shift clock pulse signal and the gate mode signals; a bi-directional shift register coupled to the input buffer; a level shifter coupled to the bidirectional shift register; an output buffer, coupled to the level shifter, for generating a plurality of gate-on signals to the display panel according to the gate scan start signal, the shift clock signal and the plurality of mode signals; and a protection circuit, coupled to the bidirectional shift register and the level shifter, for disabling the gate scan start signal when a number of clock cycles of the shift clock signal is less than a target number after detecting a first pulse of the gate scan start signal; and after detecting a first pulse of the gate scanning start signal, enabling the gate scanning start signal when the clock cycle number of the shift clock signal is equal to the target number.
[ description of the drawings ]
FIG. 1 is a functional block diagram of a multi-source display system in the prior art.
Fig. 2 is a functional block diagram of a power circuit in the prior art.
Fig. 3 is a functional block diagram of a power circuit according to an embodiment of the invention.
FIG. 4 is a flowchart illustrating an operation control flow according to an embodiment of the present invention.
FIG. 5 is a functional block diagram of a multi-source display system according to an embodiment of the present invention.
FIG. 6 is a signal waveform diagram of a plurality of control signals STV, CKV, VSYNC and HSYNC according to the present invention.
FIG. 7 is a flowchart illustrating an operation control procedure according to an embodiment of the present invention.
FIG. 8 is a signal waveform diagram of the control signals STV, CKV, VSYNC and HSYNC according to the embodiment of the invention.
FIG. 9 is a flowchart illustrating an operation control flow according to an embodiment of the present invention.
FIG. 10 is a signal waveform diagram of the control signals STV, CKV, OEV, VSYNC and HSYNC according to the embodiment of the present invention.
FIG. 11 is a flowchart illustrating an operation control flow according to an embodiment of the present invention.
Fig. 12 is a functional block diagram of a gate driver according to an embodiment of the invention.
FIG. 13 is a signal waveform diagram of a plurality of gate control signals CPV, STV1, OUT 0-OUT 1081, STV2 according to an embodiment of the present invention.
FIG. 14 is a flowchart illustrating an operation control procedure according to an embodiment of the present invention.
[ notation ] to show
1. 5 Multi-source display system
10 switching circuit
11. 51 sequential control circuit
12. 3 power supply circuit
122 input buffer
123 bidirectional shift register
124 electric potential converter
125 output buffer
13. 120 gate driver
14 source driver
15 display panel
16 multimedia signal source
17 backing image camera
21. 31 first pulse frequency modulation circuit
22. 32 first charge pump
23. 33 second pulse frequency modulation circuit
30. 121, 501 protection circuit
24. 34 second charge pump
4. 7, 110, 140 operation control flow
401 to 409, 701 to 705, 901 to 907, 111 to 117, 141 to 148
CKV, OEV, VSYNC, EVEN, DUAL, Gate control signals CPV, L/R, OEV, OEPSN, SEG, SGOFF, ODDCH
CKH, HSYNC source control signal
NCKNumber of clock cycles
NTATarget number of clock cycles
OUT 0-OUT 1080 Gate ON Signal
SA first display signal
SB second display signal
STV, STV2 grid scanning initial signal
T1First threshold value
T2Second threshold value
T3Preset duration
TMADuration of masking
TOPDuration of operation
TRSRemaining duration
Vbias power signal
VCC system power supply
VDDN second intermediate voltage
VDDP first relay voltage
VGH, VGL grid power
DDVDH source power supply
[ detailed description ] embodiments
Fig. 3 is a functional block diagram of a power circuit 3 according to an embodiment of the present invention. The power circuit 3 can be used in a multi-source display system and includes a protection circuit 30, a first Pulse Frequency Modulation (PFM) circuit 31, a first charge pump 32, a second Pulse Frequency Modulation circuit 33, and a second charge pump 34.
The first pulse frequency modulation circuit 31 is coupled to the first charge pump 32 and the protection circuit 30 for converting a system power source VCC (typically 2.7-3.6 v) into a first intermediate voltage VDDP, and the first charge pump 32 is used for converting the first intermediate voltage VDDP into a first gate power source VGH. The second pulse frequency modulation circuit 33 is coupled to the second charge pump 34 and the protection circuit 30 for converting the system power source VCC into a second intermediate voltage VDDN, and the second charge pump 34 is used for converting the second intermediate voltage VDDN into a second gate power source VGL.
The protection circuit 30 is coupled to the first pulse frequency modulation circuit 31 and the first charge pump 32, and is used for enabling (enabling) or disabling (disabling) the first pulse frequency modulation circuit 31 according to a first operation duration of the first pulse frequency modulation circuit 31, the first relay voltage VDDP and the first gate power source VGH. The protection circuit 30 is coupled to the second pulse frequency modulation circuit 33 and the second charge pump 34, and is used for enabling or disabling the second pulse frequency modulation circuit 33 according to a second operation duration of the second pulse frequency modulation circuit 33, the second relay voltage VDDN and the second gate power source VGL.
Specifically, fig. 4 is a flowchart of an operation control process 4 according to an embodiment of the present invention. The operation control flow 4 may be executed by the protection circuit 30 and includes the following steps.
Step 401: the relay voltage VDDP or VDDN generated by the pulse frequency modulation circuit is detected.
Step 402: when the pulse frequency modulation circuit is enabled, the operation duration T of the pulse frequency modulation circuit is accumulatedOP。
Step 403: is it determined whether the gate power VGH or VGL generated by the charge pump has reached the standard? If yes, go to step 404; if not, go to step 405.
Step 404: clearing the duration of operation T of the PFM circuitOP. Go back to step 401.
Step 405: determining the duration of operation T of a pulse frequency modulation circuitOPWhether or not it is greater than a first threshold value (T)OP>T1) Is there a If yes, go to step 406; if not, go to step 401.
Step 406: and de-energizing the pulse frequency modulation circuit.
Step 407: accumulating the remaining duration T of the PFM circuit when the PFM circuit has been disabledRS。
Step 408: determining the remaining duration T of the PFM circuitRSWhether or not it is greater than a second threshold value (T)RS>T2) Is there a If yes, go to step 409; if not, go to step 407.
Step 409: clearing the remaining duration T of the PFM circuitRS. Go back to step 401.
As an example of the operation of the protection circuit 30 controlling the first pulse frequency modulation circuit 31, in step 401, the protection circuit 30 detects the relay voltage VDDP generated by the first pulse frequency modulation circuit 31 to ensure that the first pulse frequency modulation circuit 31 is enabled; in one embodiment, the protection circuit 30 detects any voltage generated internally from the first pulse frequency modulation circuit 31. In step 402, when the first PFM 31 is enabled, the protection circuit 30 accumulates the operation duration T of the first PFM 31OP. In step 403, the protection circuit 30 detects whether the first gate power VGH has reached the standard (e.g., the first gate power VGH has reached a default value)The voltage level is asserted) to determine whether one operation cycle of the power supply circuit 3 has been completed. In step 404, when the first gate power VGH has reached the target, the protection circuit 30 clears the operation duration TOP(ii) a Next, the protection circuit 30 detects the relay voltage VDDP again in the next operation period of the power supply circuit 3. In step 405, when the first gate power VGH is not calibrated, the protection circuit 30 determines the operation duration T of the first pulse frequency modulation circuit 31OPWhether or not it is greater than the first threshold value T1(TOP>T1). In step 406, the operation duration T of the first pulse frequency modulation circuit 31 is measuredOPGreater than a first threshold value (T)OP>T1) At this time, the protection circuit 30 disables the first pfm 31, and at this time, it is inferred that the first pfm 31 has been overloaded for a predetermined time. In step 407, when the first PFM 31 is disabled, the protection circuit 30 accumulates the remaining duration T of the first PFM 31RS. In step 408, the protection circuit 30 determines the remaining duration T of the first pfm 31RSWhether or not it is greater than a second threshold value T2(TRS>T2). In step 409, the remaining duration T of the pulse frequency modulation circuit is measuredRSAbove the second threshold, the protection circuit 30 clears the remaining duration T of the first pfm 31RS(ii) a Then, the protection circuit 30 enables the first pulse frequency modulation circuit 31 in the next operation period of the power circuit 3.
In other words, when the operation duration T isOPIs not greater than a first threshold value T1At this time, the protection circuit 30 enables the first pulse frequency modulation circuit 31 (and the second pulse frequency modulation circuit 33); and when the remaining duration T isRSIs not greater than a second threshold value T2When the protection circuit 30 is turned off, the first pulse frequency modulation circuit 31 (and the second pulse frequency modulation circuit 33) is disabled. By setting the first threshold value T appropriately1And a second threshold value T2The first pulse frequency modulation circuit 31 (and the second pulse frequency modulation circuit 33) can normally operate without noise interference during the switching operation of the switching circuit of the multi-source display systemAnd (4) disturbing.
Fig. 5 is a functional block diagram of a multi-source display system 5 according to an embodiment of the invention. The multi-source display system 5 can be a control panel or a rear view mirror of a vehicle for receiving a first display signal SA from a multimedia signal source 16 or a second display signal SB from a reverse video camera 17 under the control of a switching circuit 10. A timing control circuit 51 is used for generating a plurality of gate control signals STV, CKV, OEV, VSYNC to a gate driver 13 and generating a plurality of source control signals CKH, HSYNC to a source driver 14 according to the first display signal SA or the second display signal SB. A power circuit 12 is used to generate the gate power VGH, VGL to the gate driver 13 and a voltage source DDVDH to the source driver 14. The timing control circuit 51 comprises a protection circuit 501, wherein the protection circuit 501 is used for processing at least one of the gate control signals STV, CKV, OEV before the gate control signals STV, CKV, OEV are inputted to the gate driver 13.
FIG. 6 is a signal waveform diagram of a plurality of control signals STV, CKV, VSYNC and HSYNC according to the present invention. The protection circuit 501 is used for a predetermined duration T each time the first pulse of the gate scan start signal STV is detected3(e.g., one frame scanning period), any pulse of the gate scan start signal STV is masked. Thus, for a preset duration T3In order to prevent the gate driver 13 from being overloaded, any vertical scanning operation is not initiated.
Specifically, fig. 7 is a flowchart of an operation control process 7 according to an embodiment of the present invention. The operation control flow 7 may be executed by the protection circuit 501 and includes the following steps.
Step 701: a pulse of the gate scan start signal STV is detected, wherein the pulse of the gate scan start signal STV is used to indicate a start timing of a vertical scan operation for one frame.
Step 702: determine whether the first pulse of the gate scan start signal STV has been detected? If yes, go to step 703; if not, go back to step 701.
Step 703: masking the gate scanning start signal STV and accumulating the gate scanning start signalsMasking duration T of STVMA。
Step 704: determining the occlusion duration TMAWhether or not it is greater than a third threshold value T3Is there a If yes, go to step 705; if not, go back to step 703.
Step 705: clear mask duration TMA. Go back to step 701.
In step 701, the protection circuit 501 detects a pulse of the gate scanning start signal STV, where the pulse of the gate scanning start signal STV is used to indicate a start timing of a vertical scanning operation for one frame. In steps 702 to 703, when detecting the first pulse of the gate scanning start signal STV, the protection circuit 501 masks the gate scanning start signal STV and accumulates the mask duration T of the gate scanning start signal STVMA. In steps 704 to 705, when the masking duration T isMAGreater than a third threshold value T3(TMA>T3) In time, the protection circuit 501 clears the masking duration TMA. In one embodiment, at the third threshold T3In the meantime, the protection circuit 501 forces the gate scan start signal STV to be in a Logic zero (Logic zero) state, but is not limited thereto. Accordingly, the shielding duration T after the first pulse of the gate scan start signal STV is detectedMA(third threshold value T)3) In the meantime, the protection circuit 501 shields the pulse of the gate scanning start signal STV. By setting the third threshold value T appropriately3It is ensured that the gate driver 13 does not initiate excessive vertical scanning operation due to noise disturbance caused by the switching operation of the switching circuit 10 of the multi-source display system 5 within one frame scanning period.
FIG. 8 is a signal waveform diagram of the control signals STV, CKV, VSYNC and HSYNC according to the embodiment of the invention. In this embodiment, when detecting an abnormal pulse or an accidental pulse of the gate scan start signal STV, the protection circuit 501 is in a default duration T3The control signal CKV is turned off (e.g., one frame scan period). The control signal CKV is a vertical scan line frequency, and when a rising edge of the control signal CKV is detected, the gate driver 13 turns on a vertical scan line. Therefore, when the control signal CKV is turned off (or forced to be set at one)Logic state), the gate driver 13 cannot be at the default duration T3Any vertical scanning line is turned on internally, so that the gate driver 13 is prevented from being overloaded.
Specifically, fig. 9 is a flowchart of an operation control process 9 according to an embodiment of the present invention. The operation control flow 9 may be executed by the protection circuit 501 and includes the following steps.
Step 901: a pulse of the gate scan start signal STV is detected, wherein the pulse of the gate scan start signal STV is used to indicate a start timing of a vertical scan operation for one frame.
Step 902: determine whether the first pulse of the gate scan start signal STV has been detected? If yes, go to step 903; if not, go back to step 901.
Step 903: accumulation of the masking duration T of the gate scan start signal STVMA。
Step 904: determining the occlusion duration TMAWhether or not it is greater than a third threshold value T3Is there a If yes, go to step 905; if not, go to step 906.
Step 905: clear mask duration TMA. Go back to step 901.
Step 906: is it determined whether another pulse of the gate scan start signal STV is detected? If yes, go to step 907; if not, go back to step 903.
Step 907: the gate control signal CKV is disabled, wherein the gate control signal CKV indicates the turn-on timing of the vertical scan line. Go back to step 903.
In step 901, the protection circuit 501 detects a pulse of the gate scanning start signal STV, where the pulse of the gate scanning start signal STV is used to indicate a start timing of a vertical scanning operation for one frame. In steps 902 to 903, when the first pulse of the gate scanning start signal STV is detected, the protection circuit 501 accumulates the shielding duration T of the gate scanning start signal STVMA. In steps 904 to 905, when the masking duration T isMAGreater than a third threshold value T3(TMA>T3) In time, the protection circuit 501 clears the masking duration TMA. In steps 904 to 906, when masking is performedDuration TMAIs not greater than a third threshold value T3(TMA≤T3) At this time, the protection circuit 501 determines whether another pulse of the gate scanning start signal STV is detected. In steps 906 to 907, when another pulse of the gate scan start signal STV is detected, the protection circuit 501 is in the masking duration TMA(third threshold value T)3) And de-energizing the gate control signal CKV, wherein the gate control signal CKV indicates the turn-on timing of the vertical scan line. Therefore, when the control signal CKV is turned off (or forced to a logic state), the gate driver 13 cannot be in the default duration T3Any vertical scanning line is turned on internally, so that the gate driver 13 is prevented from being overloaded.
FIG. 10 is a signal waveform diagram of the control signals STV, CKV, OEV, VSYNC and HSYNC according to the embodiment of the present invention. In this embodiment, when detecting an abnormal pulse or an accidental pulse of the gate scan start signal STV, the protection circuit 501 is in a default duration T3(e.g., one frame scan period) the control signal OEV is turned off. The gate control signal OEV is used to control the vertical scan lines to discharge during switching between two consecutive scan lines. For example, when the control signal OEV is detected to be in a logic zero state, the gate driver 13 discharges a vertical scan line. Therefore, when the control signal OEV is at the default duration T3When turned off (or forced to a logic state), the gate driver 13 controls any vertical scan line to discharge, so as to prevent the power circuit 12 from being damaged by a large discharge current caused by an overload.
Specifically, fig. 11 is a flowchart of an operation control process 110 according to an embodiment of the invention. The operation control flow 110 may be executed by the protection circuit 501 and includes the following steps.
Step 111: a pulse of the gate scan start signal STV is detected, wherein the pulse of the gate scan start signal STV is used to indicate a start timing of a vertical scan operation for one frame.
Step 112: determine whether the first pulse of the gate scan start signal STV has been detected? If yes, go to step 113; if not, go back to step 111.
Step 113: accumulation of the masking duration T of the gate scan start signal STVMA。
Step 114: determining the occlusion duration TMAWhether or not it is greater than a third threshold value T3Is there a If yes, go to step 115; if not, go to step 116.
Step 115: clear mask duration TMA. Go back to step 111.
Step 116: is it determined whether another pulse of the gate scan start signal STV is detected? If yes, go to step 117; if not, go back to step 113.
Step 117: the gate control signal OEV is disabled, wherein the gate control signal OEV is used to indicate the discharge timing of the vertical scan line. Returning to step 113.
In step 111, the protection circuit 501 detects a pulse of the gate scanning start signal STV, wherein the pulse of the gate scanning start signal STV is used to indicate a start timing of a vertical scanning operation for one frame. In steps 112 to 113, when the pulse of the gate scanning start signal STV is detected, the protection circuit 501 accumulates the shielding duration T of the gate scanning start signal STVMA. In steps 114 to 115, when the masking duration T isMAGreater than a third threshold value T3(TMA>T3) In time, the protection circuit 501 clears the masking duration TMA. In steps 114 to 116, when the masking duration T isMAIs not greater than a third threshold value T3(TMA≤T3) At this time, the protection circuit 501 determines whether another pulse of the gate scanning start signal STV is detected. When another pulse of the gate scan start signal STV is detected, the protection circuit 501 for the masking duration T in steps 116 to 117MA(third threshold value T)3) In turn, the gate control signal OEV is disabled, wherein the gate control signal OEV indicates the discharge timing of the vertical scan line. Therefore, the gate driver 13 cannot control excessive vertical scan lines to discharge when the control signal OEV is in the default duration T3When turned off (or forced to a logic state), the gate driver 13 can control any vertical scan line to discharge, thereby avoiding overloadThe large discharge current damages the power supply circuit 12.
Fig. 12 is a functional block diagram of a gate driver 120 according to an embodiment of the invention. The gate driver 120 can be used in the multi-source display system 5 of fig. 5, and includes a protection circuit 121, an input buffer 122, a bi-directional shift register 123, a level shifter 124, and an output buffer 125.
The input buffer 122 is used to receive a plurality of gate control signals EVEN, DUAL, CPV, L/R, STV1, STV2, OEV, OEPSN, SEG, SGOFF, ODDCH, and gate MODE signal MODEs (MODE)1 to (MODE) 8. The power signals Vbias, VGH, VDD, VSS, VGL generated by the power circuit 12 of the multi-source display system 5 are used to drive the level shifter 124 and the output buffer 125. The output buffer 125 can periodically output a plurality of gate-on signals OUT0 OUT1081 to the display panel 15 for sequentially turning on the gate lines of the display panel 15.
The protection circuit 121 is coupled to the input buffer 122 and the bidirectional shift register 123, and is used for detecting a first pulse of the gate scan start signal STV1 (or STV2) and calculating a count of the number N of clock cycles of the gate control signal CPVCKTo determine whether the gate scan start signal STV1 (or STV2) is disabled. Note that the gate control signal CPV is a Shift clock (Shift clock) for the bidirectional Shift register 123. After detecting the first pulse of the gate scan start signal STV1 (or STV2), the number of clock cycles of the gate control signal CPV is less than a target number NTA(e.g., the number of all gate lines included in the display panel) (N)CK<NTA) When this occurs, the protection circuit 121 disables the gate scan start signal STV1 (or STV 2). When the number of clock cycles of the gate control signal CPV is equal to the target number NTA(NCK＝NTA) At this time, it indicates that the vertical scanning operation for one frame is completed, and therefore the protection circuit 121 enables the gate scanning start signal STV2 (or STV1) to perform the vertical scanning operation for the next frame. Please note that the gate MODE signal MODEs (MODE) 1-8 are used to indicate the number of all gate lines of the display panel (therefore, the gate MODE signal MODEs 1-8 can be used to derive the target number NTA)。
FIG. 13 is a signal waveform diagram of a plurality of gate control signals CPV, STV1, OUT 0-OUT 1081, STV2 according to an embodiment of the present invention. In this embodiment, when the first pulse of the gate scan start signal STV1 is detected at the first rising edge of the gate control signal CPV (or during the first clock period), the protection circuit 121 disables the gate scan start signal STV1, so that the gate scan start signal STV1 is maintained at a low logic level. Assuming that the display panel includes 1080 gate lines, the gate driver 120 may sequentially turn on the 1080 gate lines by outputting the gate-on signal OUT1 having a single pulse at the first clock period of the gate control signal CPV, the gate-on signals OUT2, … having a single pulse at the second clock period of the gate control signal CPV, and the gate-on signal OUT1080 having a single pulse at the 1080 clock period of the gate control signal CPV. In this way, the protection circuit 121 receives the first pulse of the gate scan start signal STV2 by enabling the gate scan start signal STV2, so as to perform the vertical scan operation frame of the next frame.
FIG. 14 is a flowchart of an operation control process 140 according to an embodiment of the present invention. The operation control process 140 may be performed by the protection circuit 120 and includes the following steps.
Step 141: determining a target number N of clock cyclesTA。
Step 142: a pulse of the gate scan start signal STV is detected, wherein the pulse of the gate scan start signal STV is used to indicate a start timing of a vertical scan operation for one frame.
Step 143: determine whether the first pulse of the gate scan start signal STV has been detected? If yes, go to step 144; if not, go back to step 142.
Step 144: the gate scan start signal STV is disabled.
Step 145: accumulating the number of clock cycles NCK。
Step 146: determining the number of clock cycles NCKWhether it is equal to the target number of clock cycles NTAIs there a If yes, go to step 147; if not, go back to step 145.
Step 147: cleaning outNumber of clock cycles NCK。
Step 148: the gate scan start signal STV is enabled. Go back to step 141.
In step 141, the protection circuit 120 determines the target number N of clock cycles according to the gate mode signals mode 1 to mode 8TA. In step 142, the protection circuit 120 detects a pulse of the gate scan start signal STV (e.g., STV1 or STV2), wherein the pulse of the gate scan start signal STV is used to indicate a start timing of a vertical scan operation for one frame. In steps 143 to 144, the protection circuit 120 disables the gate scan start signal STV when the first pulse of the gate scan start signal STV is detected. In step 145, the protection circuit 120 increments the number of clock cycles NCK. At steps 146 to 147, the number of clock cycles NCKEqual to the target number N of clock cyclesTAIn time, the protection circuit 120 clears the number of clock cycles NCK. In step 148, the protection circuit 120 enables the gate scan start signal STV to perform the vertical scan operation frame of the next frame. Therefore, the gate driver 13 cannot initiate excessive vertical scanning operation within one frame period, so that the gate driver 13 is prevented from being overloaded.
In summary, the present invention provides a protection circuit and related operation control method, for enabling a pulse frequency modulation circuit when an operation duration of the pulse frequency modulation circuit is not greater than a first threshold; and de-energizing the pulse frequency modulation circuit when the remaining duration of the pulse frequency modulation circuit is not greater than the second threshold. The present invention also provides a protection circuit and related operation control method for masking one of the gate scan start signal STV, the gate clock signal CKV and the gate discharge signal OEV to prevent excessive vertical scan operations from being initiated within one frame scan period, thereby preventing the power circuit and the gate driver from being overloaded. The invention also provides a protection circuit and a related operation control method, which are used for de-energizing the grid scanning starting signal STV when the number of clock cycles is not equal to the target number, so that the phenomenon of overloading of a grid driver can be avoided.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims (12)

1. A power supply circuit for a display system, comprising:
the first pulse frequency modulation circuit is used for converting a system power supply into a first relay voltage;
a first charge pump, coupled to the first pulse frequency modulation circuit, for converting the first intermediate voltage into a first gate power;
the second pulse frequency modulation circuit is used for converting the system power supply into a second relay voltage;
a second charge pump, coupled to the second pulse frequency modulation circuit, for converting the second intermediate voltage into a second gate power; and
a protection circuit, coupled to the first PFM circuit, the first charge pump, the second PFM circuit, and the second charge pump, for enabling the first PFM circuit and the second PFM circuit when an operation duration of the first PFM circuit and the second PFM circuit is not greater than a first threshold; and when the remaining duration of the first pulse frequency modulation circuit and the second pulse frequency modulation circuit is not greater than a second threshold value, the first pulse frequency modulation circuit and the second pulse frequency modulation circuit are disabled.
2. The power supply circuit as claimed in claim 1, wherein the protection circuit detects a relay voltage generated by the pulse frequency modulation circuit to determine whether the pulse frequency modulation circuit is enabled.
3. The power supply circuit of claim 1, wherein the protection circuit detects the gate power generated by the charge pump to determine whether an operation cycle of the power supply circuit has been completed; and the protection circuit clears the operation duration of the pulse frequency modulation circuit when the gate power generated by the charge pump has reached a standard and the operation period of the power supply circuit has been completed.
4. The power supply circuit of claim 1, wherein the protection circuit clears the remaining duration of the pulse frequency modulation circuit when the remaining duration of the pulse frequency modulation circuit is greater than the second threshold.
5. An operation control method for a protection circuit for protecting a power supply circuit of a display system, wherein the power supply circuit includes a pulse frequency modulation circuit and a charge pump and the protection circuit, the operation control method comprising:
enabling the pulse frequency modulation circuit;
accumulating the operation duration of the pulse frequency modulation circuit when the pulse frequency modulation circuit is enabled;
when the grid power supply generated by the charge pump does not reach the standard, judging whether the operation duration of the pulse frequency modulation circuit is larger than a first threshold value or not;
de-energizing the pulse frequency modulation circuit when the operational duration of the pulse frequency modulation circuit is greater than the first threshold;
accumulating a remaining duration of the pulse frequency modulation circuit when the pulse frequency modulation circuit has been de-energized; and
enabling the pulse frequency modulation circuit when the remaining duration of the pulse frequency modulation circuit is greater than a second threshold.
6. The operation control method according to claim 5, wherein after the step of enabling the pulse frequency modulation circuit, the operation control method further comprises:
and detecting the relay voltage generated by the pulse frequency modulation circuit, and judging whether the pulse frequency modulation circuit is enabled.
7. The operation control method according to claim 5, wherein after the step of accumulating the operation duration of the pulse frequency modulation circuit when the pulse frequency modulation circuit has been enabled, the operation control method further comprises:
detecting the grid power generated by the charge pump to judge whether the operation period of the power circuit is finished; and
clearing the operating duration of the pulse frequency modulation circuit when the gate power generated by the charge pump has reached a standard and the operating cycle of the power circuit has completed.
8. The operation control method according to claim 5, wherein after the step of accumulating the remaining duration of the pulse frequency modulation circuit when the pulse frequency modulation circuit has been de-energized, the operation control method further comprises:
clearing the remaining duration of the pulse frequency modulation circuit when the remaining duration of the pulse frequency modulation circuit is greater than the second threshold.
9. An operation control method for a protection circuit for protecting a gate driver of a display system, the operation control method comprising:
detecting a pulse of a gate scan start signal, wherein the pulse of the gate scan start signal is used to indicate a start timing of a vertical scan operation for one frame;
after detecting a first pulse of the gate control signal, masking the gate control signal and accumulating a masking duration of the gate control signal; and
clearing the masking duration and detecting the pulse of the gate control signal when the masking duration is greater than a threshold.
10. The operation control method according to claim 9, further comprising:
accumulating a masking duration of the gate scan start signal after the step of detecting the pulse of the gate scan start signal and the step of detecting the first pulse of the gate control signal;
after the step of clearing the masking duration and detecting the pulse of the gate control signal when the masking duration is greater than the threshold, judging whether another pulse of the gate scanning start signal is detected when the masking duration is not greater than the threshold; and
when the other pulse of the gate scanning start signal is detected, a gate control frequency signal indicating a turn-on timing of a vertical scanning line is disabled.
11. The operation control method according to claim 9, further comprising:
after the step of detecting the pulse of the gate scan start signal, accumulating the masking duration of the gate scan start signal when a first pulse of the gate scan start signal is detected;
after the step of clearing the masking duration and detecting the pulse of the gate scanning start signal when the masking duration is greater than the threshold, judging whether another pulse of the gate scanning start signal is detected when the masking duration is not greater than the threshold; and
and de-energizing the gate control discharge signal, wherein the gate control discharge signal is used for indicating the discharge timing of the vertical scanning line.
12. A gate driver for a display system, comprising:
an input buffer for receiving a gate scan start signal, a shift clock signal, and a plurality of gate mode signals indicating the number of gate lines of a display panel of the display system;
a bidirectional shift register coupled to the input buffer;
a level shifter coupled to the bidirectional shift register;
an output buffer, coupled to the level shifter, for generating a plurality of gate-on signals to the display panel according to the gate scan start signal, the shift clock signal, and the plurality of mode signals; and
a protection circuit, coupled to the bidirectional shift register and the level shifter, for disabling the gate scan start signal when a number of clock cycles of the shift clock signal is less than a target number after detecting a first pulse of the gate scan start signal; and after detecting a first pulse of the gate scanning start signal, enabling the gate scanning start signal when the clock cycle number of the shift clock signal is equal to the target number.
CN201911363463.3A 2019-12-26 Power supply circuit for multi-source display system and related operation control method Active CN113053278B (en)

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