TWI729920B - Apparatus, method, and computer program product thereof for generating a cutting path for a printed circuit board - Google Patents
Apparatus, method, and computer program product thereof for generating a cutting path for a printed circuit board Download PDFInfo
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本發明係關於一種為一印刷電路板(Printed Circuit Board;PCB)產生一成型路徑之裝置、方法及其電腦程式產品。具體而言,本發明係關於一種根據控制端點為一印刷電路板產生一成型路徑之裝置、方法及其電腦程式產品。The present invention relates to a device, method and computer program product for generating a molding path for a printed circuit board (PCB). Specifically, the present invention relates to a device, method and computer program product for generating a molding path for a printed circuit board according to a control terminal.
印刷電路板是電子設備的基礎材料,各種電子設備都具有已佈線且已設置積體電路(Integrated Circuit;IC)及各種電子元件(例如:電容器、電阻器、電感器、二極體等)之印刷電路板。為了確保電子設備能正常地運作,需先設計出該電子設備的各項系統規格,於印刷電路板上規劃各個電子元件的位置與它們的連接細節,再依據設計在印刷電路板上佈設導線與放置積體電路與各種電子元件,並導通各個電子元件,以使電子設備得以順利運作。Printed circuit boards are the basic materials of electronic devices. All kinds of electronic devices have wired and installed integrated circuits (Integrated Circuit; IC) and various electronic components (such as capacitors, resistors, inductors, diodes, etc.). A printed circuit board. In order to ensure that the electronic equipment can operate normally, it is necessary to design the system specifications of the electronic equipment first, plan the position of each electronic component and their connection details on the printed circuit board, and then lay wires and wires on the printed circuit board according to the design. Place the integrated circuit and various electronic components, and conduct each electronic component, so that the electronic equipment can operate smoothly.
關於印刷電路板的設計,目前業界是由工程師透過電腦輔助設計(Computer-Aided Design;CAD)軟體描繪出該印刷電路板上的導線設計圖,再依據電子設備的功能與製程之需求進一步地編輯及修正。此外,工程師也需透過電腦輔助設計軟體在印刷電路板上描繪出成型路徑,使得印刷電路板切割機能根據成型路徑進行裁切,完成該印刷電路板的分板。然而,印刷電路板的導線設計圖相當的複雜,需要由具有豐富經驗的工程師仔細地描繪出整條成型路徑。此種描繪成型路徑之作法極度仰賴工程師的經驗,且需要耗費工程師大量的時間與精力進行處理。Regarding the design of printed circuit boards, the industry currently uses computer-aided design (Computer-Aided Design; CAD) software to draw the wire design diagrams on the printed circuit boards, and then further edit them according to the functions of the electronic equipment and the requirements of the process And correction. In addition, engineers also need to use computer-aided design software to draw a molding path on the printed circuit board, so that the printed circuit board cutting machine can cut according to the molding path to complete the PCB splitting. However, the wire design drawing of the printed circuit board is quite complicated, and the entire molding path needs to be carefully drawn by an engineer with rich experience. This method of drawing the forming path extremely relies on the experience of the engineer, and requires a lot of time and energy for the engineer to process.
有鑑於此,如何簡化產生印刷電路板之成型路徑的流程,提供一種大幅提高工程師調整及修正成型路徑之效率的技術,為本發明所屬技術領域亟待解決的問題。In view of this, how to simplify the process of generating the molding path of the printed circuit board and provide a technology that greatly improves the efficiency of the engineer to adjust and correct the molding path is a problem to be solved in the technical field of the present invention.
為解決前述為一印刷電路板產生一成型路徑之各種問題,本發明提供一種為一印刷電路板產生一成型路徑之裝置、方法及其電腦程式產品。In order to solve the aforementioned problems of generating a molding path for a printed circuit board, the present invention provides an apparatus, method and computer program product for generating a molding path for a printed circuit board.
本發明所提供之為一印刷電路板產生一成型路徑之裝置包含一儲存器、一處理器及一輸入介面,其中該處理器電性連接至該儲存器及該輸入介面。該儲存器儲存該印刷電路板之一電腦輔助設計(Computer-Aided Design;CAD)檔案,其中該電腦輔助設計檔案定義複數個初始幾何物件,且各該初始幾何物件具有一座標資訊。該處理器根據該等座標資訊及一門檻值對該等初始幾何物件進行一前處理以得到複數個已處理幾何物件,其中任二個已處理幾何物件間之一距離不小於該門檻值。該輸入介面接收複數個控制端點。該處理器還根據該等控制端點,從該等已處理幾何物件中決定複數個子路徑,該等子路徑涵蓋該等控制端點,該處理器還串連該等子路徑作為該成型路徑。The device provided by the present invention for generating a molding path for a printed circuit board includes a memory, a processor and an input interface, wherein the processor is electrically connected to the memory and the input interface. The storage stores a computer-aided design (CAD) file of the printed circuit board, wherein the computer-aided design file defines a plurality of initial geometric objects, and each of the initial geometric objects has a piece of standard information. The processor performs a pre-processing on the initial geometric objects according to the coordinate information and a threshold value to obtain a plurality of processed geometric objects, and a distance between any two processed geometric objects is not less than the threshold value. The input interface receives a plurality of control endpoints. The processor also determines a plurality of sub-paths from the processed geometric objects according to the control endpoints, and the sub-paths cover the control endpoints, and the processor also concatenates the sub-paths as the shaping path.
本發明所提供之為一印刷電路板產生一成型路徑之方法適用於一電子計算裝置。該電子計算裝置儲存該印刷電路板之一電腦輔助設計檔案,該電腦輔助設計檔案定義複數個初始幾何物件,各該初始幾何物件具有一座標資訊。該方法包含下列步驟:(a)根據該等座標資訊及一門檻值對該等初始幾何物件進行一前處理以得到複數個已處理幾何物件,其中任二個已處理幾何物件間之一距離不小於該門檻值,(b)接收複數個控制端點,(c)根據該等控制端點,從該等已處理幾何物件中決定複數個子路徑,其中該等子路徑涵蓋該等控制端點,以及(d)串連該等子路徑作為該成型路徑。The method for generating a molding path for a printed circuit board provided by the present invention is suitable for an electronic computing device. The electronic computing device stores a computer-aided design file of the printed circuit board. The computer-aided design file defines a plurality of initial geometric objects, and each of the initial geometric objects has a piece of standard information. The method includes the following steps: (a) Perform a pre-processing on the initial geometric objects according to the coordinate information and a threshold value to obtain a plurality of processed geometric objects, where one of the two processed geometric objects is not at a distance Less than the threshold value, (b) receive a plurality of control endpoints, (c) determine a plurality of sub-paths from the processed geometric objects according to the control endpoints, where the sub-paths cover the control endpoints, And (d) connecting the sub-paths in series as the forming path.
本發明所提供之電腦程式產品包含複數個程式指令。在一電子計算裝置載入該電腦程式產品後,該電子計算裝置執行該電腦程式產品所包含之該等程式指令,以實現一種為一印刷電路板產生一成型路徑之方法。該方法包含下列步驟:(a)根據該等座標資訊及一門檻值對該等初始幾何物件進行一前處理以得到複數個已處理幾何物件,其中任二個已處理幾何物件間之一距離不小於該門檻值,(b)接收複數個控制端點,(c)根據該等控制端點,從該等已處理幾何物件中決定複數個子路徑,其中該等子路徑涵蓋該等控制端點,以及(d)串連該等子路徑作為該成型路徑。The computer program product provided by the present invention includes a plurality of program instructions. After an electronic computing device loads the computer program product, the electronic computing device executes the program instructions included in the computer program product to realize a method of generating a molding path for a printed circuit board. The method includes the following steps: (a) Perform a pre-processing on the initial geometric objects according to the coordinate information and a threshold value to obtain a plurality of processed geometric objects, where one of the two processed geometric objects is not at a distance Less than the threshold value, (b) receive a plurality of control endpoints, (c) determine a plurality of sub-paths from the processed geometric objects according to the control endpoints, where the sub-paths cover the control endpoints, And (d) connecting the sub-paths in series as the forming path.
本發明所提供之為一印刷電路板產生一成型路徑之技術(至少包含裝置、方法及其電腦程式產品)係利用該印刷電路板之一電腦輔助設計檔案所定義之複數個初始幾何物件來決定出該成型路徑。具體而言,本發明所提供之技術先根據一門檻值及該等初始幾何物件之座標資訊對該等初始幾何物件進行一前處理,藉此整合那些彼此之間距離過小之初始幾何物件(亦即,距離小於該門檻值之初始幾何物件),並因此獲得任二者間的距離不小於該門檻值的複數個已處理幾何物件。接著,可由使用者根據該等已處理幾何物件標示出用以形成該成型路徑的複數個控制端點。基於該等控制端點,本發明所提供之技術決定出涵蓋該等控制端點的複數個子路徑,進而串連該等子路徑作為該成型路徑。藉由前述運作,本發明所提供之技術能根據複數個控制端點決定出複數個子路徑,再據以產生該印刷電路板之該成型路徑。依據本發明所提供之技術,使用者不需要耗費大量的時間描繪一印刷電路板的完整的成型路徑,僅需標示出複數個控制端點即可產生印刷電路板的完整的成型路徑。因此,可大幅地提高產生該成型路徑之效率,降低時間成本。The technology provided by the present invention for generating a molding path for a printed circuit board (including at least devices, methods and computer program products) is determined by using a plurality of initial geometric objects defined by a computer-aided design file of the printed circuit board Out of the molding path. Specifically, the technology provided by the present invention first performs a pre-processing on the initial geometric objects based on a threshold value and the coordinate information of the initial geometric objects, so as to integrate those initial geometric objects whose distances are too small (also That is, the initial geometric object whose distance is less than the threshold value), and therefore, a plurality of processed geometric objects whose distance between any two is not less than the threshold value is obtained. Then, the user can mark a plurality of control endpoints used to form the molding path based on the processed geometric objects. Based on the control endpoints, the technology provided by the present invention determines a plurality of sub-paths covering the control endpoints, and then concatenates the sub-paths as the shaping path. Through the foregoing operations, the technology provided by the present invention can determine a plurality of sub-paths based on a plurality of control endpoints, and then generate the molding path of the printed circuit board accordingly. According to the technology provided by the present invention, the user does not need to spend a lot of time drawing a complete molding path of a printed circuit board, and only needs to mark a plurality of control endpoints to generate a complete molding path of the printed circuit board. Therefore, the efficiency of generating the molding path can be greatly improved, and the time cost can be reduced.
以下結合圖式闡述本發明之詳細技術及實施方式,俾使本發明所屬技術領域中具有通常知識者能理解所請求保護之發明之技術特徵。The detailed technology and implementation of the present invention are described below in conjunction with the drawings, so that those with ordinary knowledge in the technical field to which the present invention belongs can understand the technical features of the claimed invention.
以下將透過實施方式來解釋本發明所提供之為一印刷電路板產生一成型路徑之裝置、方法及其電腦程式產品。然而,該等實施方式並非用以限制本發明需在如該等實施方式所述之任何環境、應用或方式方能實施。因此,關於以下實施方式之說明僅在於闡釋本發明之目的,而非用以限制本發明之範圍。應理解,在以下實施方式及圖式中,與本發明非直接相關之元件已省略而未繪示,且圖式中各元件之尺寸以及元件間之尺寸比例僅為便於繪示及說明,而非用以限制本發明之範圍。The following will explain the device, method and computer program product provided by the present invention for generating a molding path for a printed circuit board through embodiments. However, these embodiments are not intended to limit the implementation of the present invention in any environment, application or method as described in these embodiments. Therefore, the description of the following embodiments is only for explaining the purpose of the present invention, rather than limiting the scope of the present invention. It should be understood that in the following embodiments and drawings, elements that are not directly related to the present invention have been omitted and are not shown, and the size of each element and the size ratio between elements in the drawings are only for ease of illustration and description, and It is not intended to limit the scope of the present invention.
本發明之第一實施方式為針對一印刷電路板產生一成型路徑之裝置(下稱「成型路徑產生裝置」)1,其架構示意圖係描繪於第1圖。成型路徑產生裝置1包含一儲存器11、一處理器13及一輸入介面15,其中處理器13電性連接至儲存器11及輸入介面15。儲存器11可為一記憶體、一通用串列匯流排(Universal Serial Bus;USB)碟、一硬碟、一光碟(Compact Disk;CD)、一數位多工光碟(Digital Versatile Disc;DVD)、一隨身碟或本發明所屬技術領域中具有通常知識者所知之任何其他能儲存數位資料之非暫態儲存媒體或儲存電路。處理器13可為各種處理器、中央處理單元(Central Processing Unit;CPU)、微處理器(Microprocessor Unit;MPU)、數位訊號處理器(Digital Signal Processor;DSP)或本發明所屬技術領域中具有通常知識者所知悉之其他計算裝置。輸入介面15可為任何能與處理器13搭配使用,且能接收訊號的介面,例如:通用串列匯流排介面、網路介面卡,但不以此為限。The first embodiment of the present invention is a device for generating a molding path for a printed circuit board (hereinafter referred to as "molding path generating device") 1, and the schematic diagram of the structure is depicted in FIG. 1. The forming
於本實施方式中,成型路徑產生裝置1之儲存器11儲存一印刷電路板之一電腦輔助設計檔案CF,其中電腦輔助設計檔案CF記錄該印刷電路板之佈線資訊。具體而言,電腦輔助設計檔案CF定義複數個初始幾何物件O
1、O
2、……、O
n,且各初始幾何物件O
1、O
2、……、O
n具有一座標資訊(未繪示)。需說明者,初始幾何物件O
1、O
2、……、O
n各自之形狀、大小及位置係工程師根據電子設備的功能與製程之需求而設計。不同形狀之初始幾何物件對應至不同座標資訊。舉例而言,若一初始幾何物件為圓形,則該初始幾何物件之座標資訊可包含一圓心座標及一半徑長度。再舉例而言,若一初始幾何物件為一線段,則該初始幾何物件之座標資訊可包含該線段兩端點各自之座標。
In this embodiment, the
於本實施方式中,成型路徑產生裝置1所執行之運作可區分為二個階段,其中第一階段之運作在於對電腦輔助設計檔案CF進行一前處理(由初始幾何物件O
1、O
2、……、O
n所界定的大量端點中過濾不必要的端點,以形成複數個已處理幾何物件),而第二階段之運作則在於根據使用者所標示的控制端點決定複數個子路徑,進而產生該印刷電路板之成型路徑30。
In this embodiment, the operation performed by the forming
茲先說明成型路徑產生裝置1如何對電腦輔助設計檔案CF所定義之初始幾何物件O 1、O 2、……、O n進行前處理。概要而言,初始幾何物件O 1、O 2、……、O n係包含於一個二維空間。成型路徑產生裝置1的處理器13會根據初始幾何物件O 1、O 2、……、O n的座標資訊及一門檻值對初始幾何物件O 1、O 2、……、O n進行前處理,藉此得到複數個已處理幾何物件(未繪示),其中任二個已處理幾何物件間之一距離不小於該門檻值。 Hereby forming first described how a path generating means to the initial geometry types computer-aided design files CF of defined O 1, O 2, ......, O n pretreatment. Summary, the initial geometry of the object O 1, O 2, ......, O n contained in a two-dimensional space based. Based on initial geometry object O 1, O 2, ......, O n coordinate information and a threshold value processor path forming means 13 of generating initial geometric objects O 1, O 2, ......, O n pretreated , Thereby obtaining a plurality of processed geometric objects (not shown), and a distance between any two processed geometric objects is not less than the threshold value.
具體而言,成型路徑產生裝置1的處理器13所進行的前處理係整合那些彼此之間距離過小的初始幾何物件(亦即,彼此間距離小於該門檻值之初始幾何物件)。換言之,處理器13判斷初始幾何物件O
1、O
2、……、O
n中有哪些應該相連。若處理器13判斷初始幾何物件O
1、O
2、……、O
n中有哪兩個間的距離小於該門檻值,則處理器13將該二個初始幾何物件相連。若處理器13判斷二個初始幾何物件間的距離大於該門檻值,則不會相連該二個初始幾何物件。透過上述前處理後所得到的幾何物件稱之為已處理幾何物件(包含那些未與其他初始幾何物件相連的初始幾何物件與那些相連後的幾何物件)。為便於理解,請參第1B圖之具體範例,其描繪成型路徑產生裝置1進行前處理後所產生之複數個已處理幾何物件。
Specifically, the pre-processing performed by the
某些印刷電路板的佈線資訊較為複雜,而這類的印刷電路板的電腦輔助設計檔案所包含的初始幾何物件界定大量的端點,例如:數萬至數十萬個端點。為了降低前處理所需的時間及提升效能,於某些實施方式中,處理器13可先將該二維空間區分為複數個區域,再分別針對不同區域所包含的初始幾何物件進行前處理。前述的該等區域可完全不重疊,亦可部分重疊。在該等實施方式中,處理器13對初始幾何物件O
1、O
2、……、O
n進行前處理時,係判斷各該區域所包含的初始幾何物件是否應該相連,亦即處理器13會將各該區域所包含之初始幾何物件中兩兩間之一距離小於該門檻值者相連。透過將該二維空間區分為複數個區域,處理器13在執行前處理時不會將一初始幾何物件與距離過遠的初始幾何物件(亦即,不在同一區域的初始幾何物件)相比,因此可減少前處理所需的時間及提升效能。
The wiring information of some printed circuit boards is more complicated, and the initial geometric objects contained in the computer-aided design files of such printed circuit boards define a large number of endpoints, for example, tens of thousands to hundreds of thousands of endpoints. In order to reduce the time required for pre-processing and improve performance, in some embodiments, the
現說明成型路徑產生裝置1於第二階段之運作,也就是成型路徑產生裝置1如何決定複數個子路徑,進而產生該印刷電路板之成型路徑30。The operation of the forming
為進行第二階段,需讓使用者知道該等已處理幾何物件。於本實施方式中,可於一顯示螢幕(例如:成型路徑產生裝置1之顯示螢幕或其他電子計算裝置之顯示螢幕)顯示該等已處理幾何物件,俾一使用者根據該等已處理幾何物件所呈現出來的印刷電路板之佈線資訊與自身經驗,標示出控制端點P1、P2、……、P
n。輸入介面15會接收控制端點P1、P2、……、P
n,處理器13再根據控制端點P1、P2、……、P
n從該等已處理幾何物件中決定出複數個子路徑,且所決定出來的該等子路徑涵蓋控制端點P1、P2、……、P
n。需說明者,處理器13所決定出來的各子路徑為某一已處理幾何物件中的一部分或全部。
In order to proceed to the second stage, the user needs to know the processed geometric objects. In this embodiment, the processed geometric objects can be displayed on a display screen (for example, the display screen of the forming
於某些實施方式中,控制端點P1、P2、……、P
n具有一順序,而各該子路徑係由依該順序相鄰之二個控制端點所決定。在該等實施方式中,處理器13針對該印刷電路板所產生之成型路徑30可區分為二種態樣,其中第一種態樣為一封閉路徑,而第二種態樣為一開放路徑(亦即,非封閉路徑)。在第一種態樣(亦即,封閉路徑)中,控制端點P1、P2、……、P
n所具有的該順序可為使用者標示控制端點P1、P2、……、P
n的順序,再接上使用者所標示的第一個控制端點P1(例如:該順序為控制端點P1、P2、……、P
n、P1)。在第二種態樣(亦即,開放路徑)中,控制端點P1、P2、……、P
n所具有的該順序可為使用者標示控制端點P1、P2、……、P
n的順序(例如:該順序為控制端點P1、P2、……、P
n)。於某些實施方式中,可由使用者決定成型路徑30應為封閉路徑或開放路徑(例如:使用者可透過輸入介面15輸入一指令以指示成型路徑30的類型)。
In some embodiments, the control endpoints P1, P2,... P n have a sequence, and each of the sub-paths is determined by two adjacent control endpoints in the sequence. In these embodiments, the
於某些實施方式中,處理器13可藉由執行以下運作決定出該等子路徑:(a)從控制端點P1、P2、……、P
n中選取一尚未處理者作為一第一控制端點(未繪示),(b)根據該順序,選取該第一控制端點之下一控制端點作為一第二控制端點(未繪示),(c)從該等已處理幾何物件中,找出涵蓋該第一控制端點及該第二控制端點之至少一候選子路徑,(d)從該至少一候選子路徑中選取路徑長度最短者作為該第一控制端點及該第二控制端點間之該子路徑,以及(e)重複上述運作(a)、運作(b)、運作(c)及運作(d),直到所有控制端點皆被處理完畢(亦即,直到決定出所有控制端點與相鄰之控制端點之間的子路徑)。在處理器13判斷已經沒有尚未處理的控制端點後,處理器13串連該等子路徑作為成型路徑30。
In some implementations, the
為便於理解,請參第1C圖、第1D圖及第1E圖所示的具體範例,其為第1B圖之具體範例的延伸。成型路徑產生裝置1透過輸入介面15接收使用者所標示的10個控制端點P1~P10(參第1C圖),依順序為控制端點P1、P2、P3、P4、P5、P6、P7、P8、P9、P10、P1。之後,處理器13會重覆地執行上述運作(a)~運作(d),直到所有控制端點皆被處理完畢(亦即,直到決定出所有控制端點與相鄰之控制端點之間的子路徑)。For ease of understanding, please refer to the specific examples shown in FIG. 1C, FIG. 1D, and FIG. 1E, which are an extension of the specific example in FIG. 1B. The forming
請參第1D圖,當處理器13選取控制端點P1作為第一控制端點時,處理器13會依據控制端點之順序(P1、P2、……、P10、P1)選取出控制端點P1的下一個控制端點P2作為第二控制端點,從該等已處理幾何物件中找出涵蓋該第一控制端點及該第二控制端點之至少一候選子路徑,再從該至少一候選子路徑中選取路徑長度最短者作為該第一控制端點(亦即,控制端點P1)及該第二控制端點(亦即,控制端點P2)間之子路徑R1。類似的,當處理器13選取控制端點P2作為第一控制端點時,處理器13會依據控制端點之順序(P1、P2、……、P10、P1)選取出控制端點P2的下一個控制端點P3作為第二控制端點,從該等已處理幾何物件中找出涵蓋該第一控制端點及該第二控制端點之至少一候選子路徑,再從該至少一候選子路徑中選取路徑長度最短者作為該第一控制端點(亦即,控制端點P2)及該第二控制端點(亦即,控制端點P3)間之子路徑R2。如前所述,處理器13會重覆地執行上述運作(a)~運作(d),直到所有控制端點皆被處理完畢(亦即,直到決定出所有控制端點與相鄰之控制端點之間的子路徑)。Please refer to Figure 1D. When the
透過上述運作(a)~運作(e),處理器13便會決定出在順序上相鄰的兩個控制端點間的子路徑。接著,請參第1E圖,處理器13再將全部的子路徑串連,以形成該印刷電路板之成型路徑30。在成型路徑產生裝置1產生該印刷電路板之成型路徑30後,印刷電路板切割機即可根據成型路徑30裁切該印刷電路板。Through the above operations (a) to (e), the
實務上,不同的印刷電路板切割機所使用的裁切刀具的規格(例如:半徑)可能不同,而同一印刷電路板切割機亦可能提供多種不同規格的裁切刀具。在裁切一印刷電路板的不同部分時,使用者可能會需要替換印刷電路板切割機的裁切刀具。因此,在某些實施方式中,在產生成型路徑30後,處理器13還可根據一切割修正值(例如:印刷電路板切割機的裁切刀具之規格)進行一過撈處理以移動成型路徑30,避免因不同裁切刀具的規格不同而在裁切時造成印刷電路板的損害。In practice, the specifications (for example: radius) of the cutting tools used by different printed circuit board cutting machines may be different, and the same printed circuit board cutting machine may also provide a variety of different specifications of cutting tools. When cutting different parts of a printed circuit board, the user may need to replace the cutting tool of the printed circuit board cutting machine. Therefore, in some embodiments, after the forming
如前所述,於某些實施方式中,處理器13可根據一切割修正值(未繪示)移動成型路徑30,其中切割修正值可取決於所要使用之裁切刀具之規格。需說明者,若成型路徑30係一封閉路徑,則處理器13會依據該切割修正值將成型路徑30往外擴張,且擴張的幅度為該切割修正值。為使處理器13快速地移動成型路徑30,可由使用者點選哪邊屬於成型路徑30的外部。若成型路徑30係一開放路徑(亦即,非封閉路徑),則處理器13可依據使用者所輸入的指示(例如:由使用者點選所欲偏移的方向),將成型路徑30往所欲偏移的方向偏移,且偏移的幅度為該切割修正值。為便於理解,請參第1F圖所繪示的具體範例,但其非用以限制本發明的範圍。第1F圖係描繪一封閉的成型路徑30以及依據切割修正值將成型路徑30往外擴張後所獲得的成型路徑30’。As mentioned above, in some embodiments, the
於某些實施方式中,成型路徑產生裝置1還提供其他的過撈處理機制。具體而言,成型路徑產生裝置1還可包含一顯示螢幕(未繪示),其中該顯示螢幕電性連接至處理器13。顯示螢幕顯示該印刷電路板之影像及成型路徑30,俾一使用者在成型路徑30上標示出二個調整端點(未繪示),而輸入介面15會接收該二個調整端點。需說明者,該二個調整端點對應至成型路徑30之一部分,且各調整端點可為控制端點P1、P2、……、P
n其中之一。此時,顯示螢幕可進一步地顯示該二個調整端點及一調整工具選項(例如:弧形、線段)。接著,使用者可從調整工具選項中選取所欲使用之調整工具,並進行操作。輸入介面15則因應地接收使用者操作該調整工具所引發之一操作指令,處理器13再根據該操作指令調整成型路徑30之該部分(亦即,由該二個調整端點所界定的部分)。簡言之,於該等實施方式中,使用者可藉由設定調整端點來調整成型路徑30,以使成型路徑30更符合實際的需求。
In some embodiments, the forming
綜上所述,成型路徑產生裝置1係先將一印刷電路板之一電腦輔助設計檔案CF進行一前處理(亦即,根據電腦輔助設計檔案CF所定義的初始幾何物件O
1、O
2、……、O
n之座標資訊進行前處理,以整合那些彼此之間距離過小之初始幾何物件)。之後,成型路徑產生裝置1接收複數個控制端點,再基於該等控制端點從複數個已處理幾何物件中決定出涵蓋該等控制端點的複數個子路徑,進而串連該等子路徑作為成型路徑30。藉由前述運作,成型路徑產生裝置1能根據複數個控制端點決定出複數個子路徑,進而產生該印刷電路板之成型路徑30。因此,使用者不需要耗費大量的時間描繪成型路徑30,僅需標示出複數個控制端點即可由成型路徑產生裝置1產生印刷電路板的完整的成型路徑。因此,可大幅提高產生成型路徑30之效率,降低時間成本。
In summary, the forming
本發明之第二實施方式為針對一印刷電路板產生一成型路徑之方法(下稱「成型路徑產生方法」),其流程圖係描繪於第2A圖及第2B圖。該成型路徑產生方法適用於一電子計算裝置(例如:第一實施方式中之成型路徑產生裝置1)。該電子計算裝置儲存該印刷電路板之一電腦輔助設計檔案,該電腦輔助設計檔案定義複數個初始幾何物件,且各該初始幾何物件具有一座標資訊。The second embodiment of the present invention is a method for generating a molding path for a printed circuit board (hereinafter referred to as "a molding path generation method"), and the flowchart is depicted in FIG. 2A and FIG. 2B. The forming path generation method is suitable for an electronic computing device (for example, the forming
於本實施方式中,成型路徑產生方法執行步驟S201、S203、S205及S207。於步驟S201,由該電子計算裝置根據該等座標資訊及一門檻值對該等初始幾何物件進行一前處理,藉此得到複數個已處理幾何物件,其中任二個已處理幾何物件間之一距離不小於該門檻值。於步驟S203,由該電子計算裝置接收複數個控制端點。之後,於步驟S205,由該電子計算裝置根據該等控制端點,從該等已處理幾何物件中決定複數個子路徑,其中該等子路徑涵蓋該等控制端點,且各子路徑為某一已處理幾何物件中的一部分或全部。接著,於步驟S207,由該電子計算裝置串連該等子路徑作為該成型路徑(亦即,該電子計算裝置將該等子路徑串連以形成該成型路徑)。In this embodiment, the forming path generation method executes steps S201, S203, S205, and S207. In step S201, the electronic computing device performs a pre-processing on the initial geometric objects according to the coordinate information and a threshold value, thereby obtaining a plurality of processed geometric objects, one of which is between any two processed geometric objects The distance is not less than the threshold value. In step S203, the electronic computing device receives a plurality of control endpoints. Then, in step S205, the electronic computing device determines a plurality of sub-paths from the processed geometric objects according to the control endpoints, wherein the sub-paths cover the control endpoints, and each sub-path is a certain Part or all of the processed geometric objects. Next, in step S207, the electronic computing device concatenates the sub-paths as the forming path (that is, the electronic computing device concatenates the sub-paths to form the forming path).
於某些實施方式中,成型路徑產生方法係以更有效率的方式執行步驟S201。由於該等初始幾何物件係包含於一個二維空間,因此該成型路徑產生方法於執行步驟S201前還會由該電子計算裝置執行一步驟以將該二維空間區分為複數個區域。接著,步驟S201係將各該區域所包含之該等初始幾何物件中兩兩間之一距離小於該門檻值者相連。透過將二維空間區分為複數個區域,成型路徑產生方法在執行步驟S201時可排除掉該等初始幾何物件中大部分不必比對的端點。換言之,步驟S201在判斷一初始幾何物件間是否應與其他的初始幾何物件相連時,不會將一初始幾何物件與距離過遠的初始幾何物件(亦即,不在同一區域的初始幾何物件)相比,因此可減少前處理所需的時間及提升效能。In some embodiments, the forming path generation method executes step S201 in a more efficient manner. Since the initial geometric objects are contained in a two-dimensional space, the electronic computing device executes a step to divide the two-dimensional space into a plurality of regions before performing step S201 in the forming path generation method. Next, in step S201, one of the two initial geometric objects included in each area is connected with the one whose distance is less than the threshold value. By dividing the two-dimensional space into a plurality of regions, the forming path generation method can eliminate most of the endpoints of the initial geometric objects that do not need to be compared when performing step S201. In other words, when determining whether an initial geometric object should be connected to other initial geometric objects in step S201, it will not compare an initial geometric object with an original geometric object that is too far apart (that is, an original geometric object that is not in the same area). Therefore, the time required for pre-processing can be reduced and performance can be improved.
於某些實施方式中,成型路徑產生方法之步驟S205可由步驟S211、S213、S215、S217及S219來實現,如第2B圖所示。於該等實施方式中,步驟S203所接收之該等控制端點具有一順序,且各該子路徑係由依該順序相鄰之二個控制端點所決定。於該等實施方式中,該電子計算裝置於執行完步驟S203後,執行步驟S211。於步驟S211,由該電子計算裝置從該等控制端點中選取一尚未處理者作為一第一控制端點。於步驟S213,由該電子計算裝置根據該順序,選取該第一控制端點之下一控制端點作為一第二控制端點。於步驟S215,由該電子計算裝置從該等已處理幾何物件中,找出涵蓋該第一控制端點及該第二控制端點之至少一候選子路徑。於步驟S217,由該電子計算裝置從該至少一候選子路徑中選取路徑長度最短者作為該第一控制端點及該第二控制端點間之該子路徑。之後,於步驟S219,由該電子計算裝置判斷是否還有尚未處理的控制端點。若有尚未處理的控制端點,則重複執行步驟S211至步驟S217,直到所有控制端點皆被處理完畢(亦即,直到決定出所有控制端點與相鄰之控制端點之間的子路徑)。當該電子計算裝置判斷已經沒有尚未處理的控制端點,則繼續執行步驟S207,俾串連該等子路徑作為該成型路徑。In some embodiments, step S205 of the forming path generation method can be implemented by steps S211, S213, S215, S217, and S219, as shown in FIG. 2B. In these embodiments, the control endpoints received in step S203 have a sequence, and each of the sub-paths is determined by two adjacent control endpoints in the sequence. In these embodiments, the electronic computing device executes step S211 after executing step S203. In step S211, the electronic computing device selects an unprocessed one from the control endpoints as a first control endpoint. In step S213, the electronic computing device selects a control terminal below the first control terminal as a second control terminal according to the sequence. In step S215, the electronic computing device finds at least one candidate sub-path that covers the first control end point and the second control end point from the processed geometric objects. In step S217, the electronic computing device selects the shortest path length from the at least one candidate sub-path as the sub-path between the first control terminal and the second control terminal. After that, in step S219, the electronic computing device determines whether there are still unprocessed control endpoints. If there are unprocessed control endpoints, repeat steps S211 to S217 until all control endpoints have been processed (that is, until the sub-paths between all control endpoints and adjacent control endpoints are determined ). When the electronic computing device determines that there are no unprocessed control endpoints, it continues to execute step S207 to concatenate the sub-paths as the shaping path.
於某些實施方式中,該成型路徑產生方法於執行步驟S207後,該電子計算裝置還可執行一步驟以根據一切割修正值移動該成型路徑。舉例而言,該切割修正值可取決於一裁切刀具之一規格。於該等實施方式中,若該成型路徑係一封閉路徑,則該成型路徑產生方法可將該成型路徑往外擴張,且擴張的幅度為該切割修正值。若該成型路徑係一開放路徑(亦即,非封閉路徑),則該成型路徑產生方法可將該成型路徑往所欲偏移的方向移動,且移動的幅度為該切割修正值。In some embodiments, after the forming path generation method executes step S207, the electronic computing device may also execute a step to move the forming path according to a cutting correction value. For example, the cutting correction value may depend on a specification of a cutting tool. In these embodiments, if the forming path is a closed path, the forming path generation method can expand the forming path outward, and the extent of the expansion is the cutting correction value. If the forming path is an open path (that is, a non-closed path), the forming path generation method can move the forming path in the desired offset direction, and the moving amplitude is the cutting correction value.
於某些實施方式中,該成型路徑產生方法於執行步驟S207後,還會執行下列步驟:由該電子計算裝置接收二個調整端點,其中該二調整端點對應至該成型路徑之一部分;由該電子計算裝置顯示該印刷電路板之一影像、該成型路徑、該二調整端點及一調整工具選項;由該電子計算裝置接收該調整工具選項中之一調整工具之一操作指令;以及由該電子計算裝置根據該操作指令調整該成型路徑之該部分。In some embodiments, after performing step S207, the forming path generation method further executes the following steps: receiving two adjustment endpoints from the electronic computing device, wherein the two adjustment endpoints correspond to a part of the forming path; The electronic computing device displays an image of the printed circuit board, the molding path, the two adjustment endpoints, and an adjustment tool option; the electronic computing device receives an operation instruction of one of the adjustment tool options; and The electronic computing device adjusts the part of the molding path according to the operation instruction.
除了上述步驟,第二實施方式亦能執行第一實施方式所描述之所有運作及步驟,具有同樣之功能,且達到同樣之技術效果。本發明所屬技術領域中具有通常知識者可直接瞭解第二實施方式如何基於上述第一實施方式以執行此等運作及步驟,具有同樣之功能,並達到同樣之技術效果,故不贅述。In addition to the above steps, the second embodiment can also perform all the operations and steps described in the first embodiment, have the same functions, and achieve the same technical effects. Those with ordinary knowledge in the technical field to which the present invention pertains can directly understand how the second embodiment performs these operations and steps based on the above-mentioned first embodiment, has the same functions, and achieves the same technical effects, so it will not be repeated.
第二實施方式中所闡述之成型路徑產生方法可由包含複數個程式指令之一電腦程式產品實現。該電腦程式產品可為能被於網路上傳輸之檔案,亦可被儲存於一非暫態電腦可讀取儲存媒體中。該非暫態電腦可讀取儲存媒體可為一電子產品,例如:一唯讀記憶體(Read Only Memory;ROM)、一快閃記憶體、一軟碟、一硬碟、一光碟(Compact Disk;CD)、一數位多功能光碟(Digital Versatile Disc;DVD)、一隨身碟或本發明所屬技術領域中具有通常知識者所知且具有相同功能之任何其他儲存媒體。該電腦程式產品所包含之該等程式指令被載入一電子計算裝置(例如:成型路徑產生裝置1)後,該電腦程式執行如在第二實施方式中所述之成型路徑產生方法。The forming path generation method described in the second embodiment can be implemented by a computer program product containing a plurality of program instructions. The computer program product can be a file that can be transmitted over the network, and can also be stored in a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium may be an electronic product, such as: a read only memory (ROM), a flash memory, a floppy disk, a hard disk, and a compact disk (Compact Disk; CD), a Digital Versatile Disc (DVD), a flash drive, or any other storage medium with the same functions known to those skilled in the art to which the present invention belongs. After the program instructions included in the computer program product are loaded into an electronic computing device (for example, the forming path generating device 1), the computer program executes the forming path generating method as described in the second embodiment.
需說明者,於本發明專利說明書中,第一控制端點及第二控制端點中之「第一」及「第二」僅用來表示該等控制端點為不同控制端點而已。It should be noted that in the patent specification of the present invention, the "first" and "second" in the first control endpoint and the second control endpoint are only used to indicate that these control endpoints are different control endpoints.
綜上所述,本發明所提供之為一印刷電路板產生一成型路徑技術(至少包含裝置、方法及其電腦程式產品)會先將一印刷電路板之一電腦輔助設計檔案進行一前處理(亦即,根據電腦輔助設計檔案所定義的複數個初始幾何物件之座標資訊進行該前處理,以整合那些彼此之間距離過小之初始幾何物件)。接著,本發明所提供之技術可接收複數個控制端點,且基於該等控制端點從該等已處理幾何物件中決定出涵蓋該等控制端點的複數個子路徑,進而串連該等子路徑作為該成型路徑。藉由前述運作,本發明所提供之技術能根據複數個控制端點即可決定出複數個子路徑,進而產生該印刷電路板之成型路徑。因此,使用者不需要耗費大量的時間描繪成型路徑,僅需標示出複數個控制端點即可由本發明所提供之技術產生印刷電路板的完整的成型路徑。因此,可大幅提高產生成型路徑之效率,降低時間成本。In summary, the technology provided by the present invention for generating a molding path for a printed circuit board (including at least the device, method and computer program products) first performs a pre-processing on a computer-aided design file of a printed circuit board ( That is, the pre-processing is performed according to the coordinate information of a plurality of initial geometric objects defined by the computer-aided design file to integrate those initial geometric objects whose distances are too small). Then, the technology provided by the present invention can receive a plurality of control endpoints, and based on the control endpoints, determine a plurality of sub-paths covering the control endpoints from the processed geometric objects, and then concatenate the sub-paths. The path is used as the molding path. Through the foregoing operations, the technology provided by the present invention can determine a plurality of sub-paths based on a plurality of control endpoints, thereby generating a molding path of the printed circuit board. Therefore, the user does not need to spend a lot of time drawing the molding path, and only needs to mark a plurality of control endpoints to generate a complete molding path of the printed circuit board by the technology provided by the present invention. Therefore, the efficiency of generating the forming path can be greatly improved, and the time cost can be reduced.
上述實施方式僅用來例舉本發明之部分實施態樣,以及闡釋本發明之技術特徵,而非用來限制本發明之保護範疇及範圍。任何本發明所屬技術領域中具有通常知識者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍,而本發明之權利保護範圍以申請專利範圍為準。The above-mentioned embodiments are only used to exemplify part of the implementation aspects of the present invention and to explain the technical features of the present invention, rather than to limit the protection scope and scope of the present invention. Any change or equal arrangement that can be easily accomplished by a person with ordinary knowledge in the technical field of the present invention belongs to the scope of the present invention, and the protection scope of the present invention is subject to the scope of the patent application.
1:成型路徑產生裝置
11:儲存器
13:處理器
15:輸入介面
30、30’:成型路徑
CF:電腦輔助設計檔案
O
1、O
2、……、O
n:初始幾何物件
P1、P2、……、P
n:控制端點
P3、P4、P5、P6、P7、P8、P9、P10:控制端點
S201~S207:步驟
S211~S219:步驟1: generating path forming means 11: reservoir 13: Processor 15:
第1A圖描繪本發明之第一實施方式之成型路徑產生裝置1之架構示意圖;
第1B圖描繪成型路徑產生裝置1所產生之已處理幾何物件之一具體範例;
第1C圖描繪成型路徑產生裝置1所接收之複數個控制端點之一具體範例;
第1D圖描繪成型路徑產生裝置1所決定之複數個子路徑之一具體範例;
第1E圖描繪成型路徑產生裝置1所產生之成型路徑之一具體範例;
第1F圖描繪成型路徑產生裝置1依據一切割修正值移動該成型路徑之一具體範例;
第2A圖描繪本發明之第二實施方式之成型路徑產生方法之流程圖;以及
第2B圖描繪本發明之某些實施方式之成型路徑產生方法之流程圖。
Figure 1A depicts a schematic diagram of the structure of the forming
S201~S207:步驟 S201~S207: steps
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW564359B (en) * | 2000-12-07 | 2003-12-01 | Simplex Solutions Inc | Routing method and apparatus |
TW201004506A (en) * | 2008-07-02 | 2010-01-16 | Nan Ya Printed Circuit Board | Printed circuit board structure before shaping and its fabricating method |
TW201824041A (en) * | 2016-09-20 | 2018-07-01 | 美商奧克塔佛系統有限責任公司 | Method for routing bond wires in system in a package (sip) devices |
CN109089379A (en) * | 2018-09-20 | 2018-12-25 | 浙江中茂科技有限公司 | Printed circuit board scoreboard path planning system and planing method |
-
2020
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW564359B (en) * | 2000-12-07 | 2003-12-01 | Simplex Solutions Inc | Routing method and apparatus |
TW201004506A (en) * | 2008-07-02 | 2010-01-16 | Nan Ya Printed Circuit Board | Printed circuit board structure before shaping and its fabricating method |
TW201824041A (en) * | 2016-09-20 | 2018-07-01 | 美商奧克塔佛系統有限責任公司 | Method for routing bond wires in system in a package (sip) devices |
CN109089379A (en) * | 2018-09-20 | 2018-12-25 | 浙江中茂科技有限公司 | Printed circuit board scoreboard path planning system and planing method |
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