TWI729907B - Display and multiplexer for display - Google Patents

Abstract

A display and a multiplexer are provided. The multiplexer includes a plurality of pixel units. In a first time interval, the first selection unit among the selection units transmits a data signal to a sub-pixel of a first pixel unit. In a second time interval, the first selection unit transmits the data signal to a sub-pixel of a second pixel unit. The second time interval lags behind the first time interval and partially overlaps the first time interval. After providing the data signal, the multiplexer instructs the display to adjust a common voltage to adjust the display status of sub-pixels.

Description

Display and multiplexer for display

The present invention relates to a display and a multiplexer, and more particularly to a display and a multiplexer capable of precharging sub-pixels and adjusting the data voltage value of the sub-pixels.

Current liquid crystal displays can transmit data signals to designated sub-pixels in a time-sharing manner through a multiplexer. However, the transistors in multiplexers and sub-pixels are mostly amorphous silicon thin film transistors. Therefore, when a multiplexer based on amorphous silicon thin film transistor (a-Si TFT) transmits data signals, it will have a poor charging effect based on the characteristics of a-Si TFT. The above-mentioned conditions may make the data voltage value of the sub-pixels unable to reach the expected voltage value, which may result in poor display effect. Therefore, how to improve the data transmission defect of the a-Si TFT multiplexer is one of the subjects that those skilled in the art are working hard to study.

The present invention provides a display and a multiplexer, which can precharge the sub-pixels and adjust the data voltage value of the sub-pixels.

The invention provides a multiplexer for a display. The display panel of the display includes a plurality of pixel units. The first sub-pixel of each of the plurality of pixel units is arranged between the second sub-pixel and the third sub-pixel. The multiplexer includes a plurality of selection units. The multiple selection units are respectively coupled to the multiple pixel units. In the first time interval, the first selection unit of the plurality of selection units responds to the first selection signal group transmitting the first data signal to the second sub-pixel of the first pixel unit. In the second time interval, the first selection unit transmits the first data signal to the first sub-pixel of the second pixel unit in response to the second selection signal group. The second time interval lags behind the first time interval and partially overlaps the first time interval. After providing the first data signal, the multiplexer instructs the display to adjust at least one common voltage corresponding to the plurality of sub-pixels receiving the first data signal to adjust the voltage corresponding to the plurality of sub-pixels receiving the first data signal Display status.

The display device of the present invention includes a display panel and the aforementioned multiplexer. The display panel includes a plurality of pixel units. The first sub-pixel of each of the plurality of pixel units is arranged between the second sub-pixel and the third sub-pixel. The multiplexer is coupled to the plurality of pixel units.

Based on the above, in the first time interval, the multiplexer transmits the first data signal to the first sub-pixel of the first pixel unit in response to the first selection signal group. In the second time interval, the first selection unit transmits the first data signal to the second sub-pixel of the second pixel unit in response to the second selection signal group, wherein the second time interval lags behind In the first time interval and partially overlapping with the first time interval. Therefore, the multiplexer can perform precharging of the first sub-pixel of the first pixel unit and the second sub-pixel of the second pixel unit in the first time interval and the second time interval. In addition, after providing the first data signal, the multiplexer instructs the display to adjust at least one common voltage corresponding to the plurality of sub-pixels receiving the first data signal, so as to further adjust the voltage corresponding to the received first data signal. The display status of the plurality of sub-pixels of the first data signal. In this way, the present invention can achieve the technical effects of pre-charging the sub-pixels and adjusting the data voltage values of the sub-pixels.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Part of the embodiments of the present invention will be described in detail in conjunction with the accompanying drawings. The reference symbols in the following description will be regarded as the same or similar elements when the same symbol appears in different drawings. These embodiments are only a part of the present invention, and do not disclose all the possible implementation modes of the present invention. To be more precise, these embodiments are only examples of the devices and methods within the scope of the patent application of the present invention.

Please refer to FIG. 1, which is a schematic diagram of a display according to an embodiment of the present invention. In this embodiment, the display 100 includes a display panel 110 and a multiplexer 120. The display panel 110 includes pixel units PU1 and PU2. For ease of description, this embodiment only uses two pixel units PU1 and PU2 as an example. The present invention is not limited to the number of pixel units in this embodiment. The display panel of the present invention may include a plurality of pixel units arranged arbitrarily. In this embodiment, the pixel unit PU1 includes sub-pixels SPU1 to SPU3. The sub-pixel SPU2 is arranged between the sub-pixel SPU1 and the sub-pixel SPU3. The pixel unit PU2 includes sub-pixels SPU4 to SPU6. The sub-pixel SPU5 is arranged between the sub-pixel SPU4 and the sub-pixel SPU6.

In this embodiment, the sub-pixel SPU1 includes a thin film transistor T1, a coupling capacitor CS1, and a liquid crystal structure (not shown). The first end of the thin film transistor T1 is coupled to the data line DL1. The second end of the thin film transistor T1 is coupled to the first end of the coupling capacitor CS1. The control terminal of the thin film transistor T1 is coupled to the scan line SL. The second terminal of the coupling capacitor CS1 is used to receive the common voltage VCOM1. The sub-pixel SPU2 includes a thin film transistor T2, a coupling capacitor CS2, and a liquid crystal structure (not shown). The first end of the thin film transistor T2 is coupled to the data line DL2. The second end of the thin film transistor T2 is coupled to the first end of the coupling capacitor CS2. The control terminal of the thin film transistor T2 is coupled to the scan line SL. The second end of the coupling capacitor CS2 is used to receive the common voltage VCOM2, and so on.

In this embodiment, the multiplexer 120 is coupled to the pixel units PU1 and PU2. The multiplexer 120 includes selection units 121 and 122. For ease of description, this embodiment only uses two selection units 121 and 122 as an example. The present invention is not limited to the number of selection units in this embodiment. The multiplexer of the present invention may include a plurality of selection units.

In this embodiment, the multiplexer 120 can be electrically connected to the sub-pixels SPU1 to SPU6 via the data lines DL1 to DL6. For example, the selection unit 121 of the multiplexer 120 may be connected to the sub-pixel SPU1 through the data line DL1, connected to the sub-pixel SPU5 through the data line DL5, and connected to the sub-pixel SPU3 through the data line DL3. The selection unit 122 can be connected to the sub-pixel SPU4 via the data line DL4, to the sub-pixel SPU2 via the data line DL2, and to the sub-pixel SPU6 via the data line DL6.

In this embodiment, in the first time interval, the selection unit 121 transmits the first data signal Sdata1 to the sub-pixel SPU1 in response to the selection signal group SSG1. In the second time interval, the selection unit 121 transmits the first data signal Sdata1 to the sub-pixel SPU5 in response to the selection signal group SSG2. The second time interval is behind the first time interval. In addition, the coupling manner between the selection unit 121 and the sub-pixels SPU1 and SPU5 can realize that the second time interval can partially overlap with the first time interval. The length of time for the sub-pixels SPU1 and SPU5 to receive the first data signal Sdata1 can be extended. In this way, the selection unit 121 can precharge the sub-pixel SPU1 in the non-overlapping time interval between the first time interval and the second time interval. The selection unit 121 can precharge the sub-pixel SPU5 in the overlapping time interval of the first time interval and the second time interval.

In this embodiment, in the third time interval, the selection unit 121 also responds to the selection signal group SSG3 to transmit the first data signal Sdata1 to the sub-pixel SPU3. The third time interval lags behind the second time interval. The coupling manner between the selection unit 121 and the sub-pixels SPU3 and SPU5 can realize that the third time interval can partially overlap with the second time interval. Therefore, the selection unit 121 can precharge the sub-pixel SPU3 in the overlapping time interval of the second time interval and the third time interval.

Further, in this embodiment, the selection unit 121 includes switch circuits SWC1 to SWC3. In the first time interval, the switch circuit SWC1 will respond to the selection signal group SSG1 to transmit the first data signal Sdata1 to the sub-pixel SPU1. In the second time interval, the switch circuit SWC2 will respond to the selection signal group SSG2 to transmit the first data signal Sdata1 to the sub-pixel SPU5. In the third time interval, the switch circuit SWC3 will respond to the selection signal group SSG3 to transmit the first data signal Sdata1 to the sub-pixel SPU3.

After providing the first data signal Sdata1, the multiplexer 120 also instructs the display 100 to adjust the common voltages VCOM1, VCOM3, and VCOM5 corresponding to the sub-pixels SPU1, SPU3, and SPU5 that have received the first data signal Sdata1 to adjust the sub-pixel SPU1 , SPU3, SPU5 display status. Taking the sub-pixel SPU1 as an example, the control end of the thin film transistor T1 receives the scan signal Sscan, and transmits the first data signal Sdata1 to the first end of the coupling capacitor CS1 according to the scan signal Sscan. The first terminal of the coupling capacitor CS1 obtains the data voltage value associated with the first data signal Sdata1. The coupling capacitor CS1 can adjust the data voltage value in the sub-pixel SPU1 through the capacitive coupling method and the change of the common voltage VCOM1.

In this embodiment, in the first time interval, the selection unit 122 transmits the second data signal Sdata2 to the sub-pixel SPU4 in response to the selection signal group SSG4. In the second time interval, the selection unit 122 transmits the second data signal Sdata2 to the sub-pixel SPU2 in response to the selection signal group SSG5. The second time interval lags behind the first time interval and partially overlaps the first time interval. In the third time interval, the selection unit 122 also responds to the selection signal group SSG6 to transmit the second data signal Sdata2 to the sub-pixel SPU6. The third time interval lags behind the second time interval and partially overlaps the second time interval. Therefore, the selection unit 122 can precharge the sub-pixels SPU2, SPU4, and SPU6.

In this embodiment, the selection unit 122 includes switch circuits SWC4 to SWC6. In the first time interval, the switch circuit SWC4 will respond to the selection signal group SSG4 to transmit the second data signal Sdata2 to the sub-pixel SPU4. In the second time interval, the switch circuit SWC5 will respond to the selection signal group SSG5 to transmit the second data signal Sdata2 to the sub-pixel SPU2. In the third time interval, the switch circuit SWC6 will respond to the selection signal group SSG6 to transmit the second data signal Sdata2 to the sub-pixel SPU6.

After providing the second data signal Sdata2, the multiplexer 120 also instructs the display 100 to adjust the common voltages VCOM2, VCOM4, and VCOM6 of the sub-pixels SPU2, SPU4, and SPU6 to adjust the display conditions of the sub-pixels SPU2, SPU4, and SPU6.

Incidentally, the multiplexer 120 of this embodiment can pre-charge the sub-pixels SPU1 to SPU6, and adjust the common voltages VCOM1, VCOM3, and VCOM5 of the sub-pixels SPU1 to SPU6. Therefore, in this embodiment, the sub-pixels SPU1 to SPU6 can be precharged, and the data voltage values of the sub-pixels SPU1 to SPU6 can be adjusted. This embodiment can compensate for the data transmission defect of the a-Si TFT multiplexer.

In some embodiments, the display 100 further includes a common voltage generator (not shown). The multiplexer 120 instructs the common voltage generator to adjust the corresponding VCOM1 to VCOM6 after the first time interval, the second time interval, and the third time interval.

Please refer to FIG. 1 and FIG. 2. FIG. 2 is a timing diagram of the first data signal and the second data signal according to an embodiment of the present invention. In this embodiment, the data polarity of the first data signal Sdata1 is opposite to the data polarity of the second data signal Sdata2. Therefore, the sub-pixels SPU1, SPU3, and SPU5 have the same first data polarity. The sub-pixels SPU2, SPU4, and SPU6 have the same second data polarity. The second data polarity is opposite to the first data polarity. In addition, the data polarity of the first data signal Sdata1 and the data polarity of the second data signal Sdata2 are inverted based on a predetermined period. In this way, the display can achieve column inversion or frame inversion. The preset period can be an integer multiple of the time length of the frame, but the present invention is not limited to this.

Please refer to FIG. 1 and FIG. 3 as well. FIG. 3 is a state timing diagram of the switch circuits SWC1 to SWC3 drawn according to the embodiment of FIG. 1. In this embodiment, the cooperative operation of the pixel units PU1 and PU2 and the selection unit 121 is taken as an example. When the scanning signal is at a high voltage level, the thin film transistors T1 to T3 are turned on. The switch circuit SWC1 changes from the off state to the on state at the time point tp1. The switch circuit SWC1 changes from the on state to the off state at the time point tp3. Therefore, the first data signal Sdata1 can be provided to the sub-pixel SPU1 between the time point tp1 and the time point tp3 (ie, the first time interval). The length of time between the time point tp1 and the time point tp2 is the precharge time length of the sub-pixel SPU1. The length of time between the time point tp2 and the time point tp3 is the display time length of the sub-pixel SPU1.

The switch circuit SWC2 changes from the off state to the on state at the time point tp2. The switch circuit SWC2 changes from the on state to the off state at the time point tp5. Therefore, the first data signal Sdata1 can be provided to the sub-pixel SPU5 between the time point tp2 and the time point tp5 (ie, the second time interval). The length of time between the time point tp2 and the time point tp3 is the precharge time length of the sub-pixel SPU5. The length of time between the time point tp3 and the time point tp5 is the display time length of the sub-pixel SPU5. In this way, when the sub-pixel SPU1 performs a display operation between the time point tp2 and the time point tp3, the sub-pixel SPU5 will be precharged.

The switch circuit SWC3 changes from the off state to the on state at the time point tp4. The switch circuit SWC3 changes from the on state to the off state at the time point tp6. Therefore, the first data signal Sdata1 can be provided to the sub-pixel SPU3 between the time point tp4 and the time point tp6 (ie, the third time interval). The length of time between the time point tp4 and the time point tp5 is the precharge time length of the sub-pixel SPU3. The length of time between the time point tp5 and the time point tp6 is the display time length of the sub-pixel SPU3. In this way, when the sub-pixel SPU5 performs a display operation between the time point tp4 and the time point tp5, the sub-pixel SPU3 will be precharged.

In this embodiment, the time point tp3 and the time point tp4 may be different time points. In some embodiments, the time point tp3 and the time point tp4 may be the same time point, and the present invention is not limited thereto.

Further explain the implementation details of the switch circuit. Please refer to Figure 4 and Figure 5 at the same time. FIG. 4 is a schematic diagram of the switch circuit according to the embodiment of FIG. 1. FIG. 5 is a timing diagram of a selection signal group according to an embodiment of the present invention. In this embodiment, the switch circuit SWC1 is taken as an example. The switch circuit SWC1 includes transistors M1 and M2. The first selection signal group SSG1 includes a first signal SK1 and a second signal SK2. The first end of the transistor M1 is used for receiving the first data signal Sdata1. The second end of the transistor M1 is coupled to the data line DL1. The control terminal of the transistor M1 is used to receive the first signal SK1. The first end of the transistor M2 is coupled to the first end of the transistor M1. The second end of the transistor M2 is coupled to the second end of the transistor M1. The control terminal of the transistor M2 is used to receive the second signal SK2. In this embodiment, the transistors M1 and M2 can be implemented by N-type thin film transistors. However, the present invention is not limited to the transistor of the switching circuit. The transistor of the switch circuit of the present invention can be any type of transistor element.

In this embodiment, during the first period TT1, the transistor M1 is turned on in the first period TD1. Transistor M2 is continuously disconnected. During the second period TT2, the transistor M2 will be turned on in the first time period TD1. Transistor M1 is continuously disconnected. For example, the first period TT1 corresponds to the first frame time. The second period TT2 corresponds to the second frame time. In this way, transistors M1 and M2 can take turns to rest.

In this embodiment, in the first period TT1, the voltage value of the first signal SK1 is the first voltage value V1 in the first time period TD1. The voltage value of the first signal SK1 outside the first time interval TD1 is the second voltage value V2. During the first period TT1, the voltage value of the second signal SK2 maintains the second voltage value V2. The first voltage value is a positive voltage (for example, 12 volts, the present invention is not limited to this). The second voltage value is a negative voltage (for example, -12 volts, the present invention is not limited to this). In the second period TT2, the voltage value of the second signal SK2 is the first voltage value V1 in the first time period TD1. The voltage value of the second signal SK2 outside the first time interval TD1 is the second voltage value V2. During the second period TT2, the voltage value of the first signal SK1 maintains the second voltage value V2.

In this embodiment, the second voltage value V2 is a negative voltage and is lower than the lowest voltage value of the first data signal Sdata1 (for example, -5 volts, the invention is not limited thereto). Therefore, when the transistor M1 receives the first signal SK1 with the second voltage value V2, the transistor M1 will be subjected to negative bias compensation. Similarly, when the transistor M2 receives the second signal SK2 with the second voltage value V2, the transistor M2 will be subjected to negative bias compensation. In this way, the signal aspect of the first selection signal group SSG1 can slow down the degradation of the transistors M1 and M2, thereby improving the reliability of the multiplexer (the multiplexer 120 shown in FIG. 1).

Please refer to FIG. 6 and FIG. 7 at the same time. FIG. 6 is a schematic diagram of the coupling between the sub-pixel and the switch circuit according to an embodiment of the present invention. FIG. 7 is a timing diagram of adjusting the data voltage values of sub-pixels according to an embodiment of the present invention. For ease of description, this embodiment only takes the operations of the sub-pixel SPU1 and the switch circuit SWC1 as an example. In this embodiment, the sub-pixel SPU1 includes a thin film transistor T1, a coupling capacitor CS1, and a liquid crystal structure LC1. The coupling method of the thin film transistor T1 and the coupling capacitor CS1 can be sufficiently taught in the embodiment of FIG. 1, so it will not be repeated here. The first end of the liquid crystal structure LC1, the first end of the coupling capacitor CS1, and the second end of the thin film transistor T1 are commonly coupled to the node Nspx. The second end of the liquid crystal structure LC1 receives a reference low voltage (for example, 0 volt).

For example, the thin film transistor T1 receives the scan signal Sscan with a high voltage level at the time point tp7 and is turned on and the switch circuit SWC1 is operated to transmit the first data signal Sdata1 (that is, in the first time interval TD1). The thin film transistor T1 charges the node Nspx according to the voltage level of the first data signal Sdata1. Therefore, the node Nspx can obtain the data voltage value that causes the liquid crystal in the liquid crystal structure LC1 to rotate. At the time point tp8, at the end of the first time interval TD1, the switch circuit SWC1 stops transmitting the first data signal Sdata1. Therefore, the data voltage value on the node Nspx may be slightly discharged. The data voltage value on the node Nspx and the voltage value of the second end of the coupling capacitor CS1 (the voltage value of the common voltage VCOM1) have a voltage difference DV. Therefore, in this embodiment, the common voltage VCOM1 can be adjusted after the time point tp8. The coupling capacitor CS1 can adjust the data voltage value on the node Nspx in response to the adjusted common voltage VCOM1, so as to maintain, correct or adjust the voltage difference between the two ends of the liquid crystal structure LC1.

For example, at the time point tp9, the thin film transistor T1 receives the scan signal Sscan with a low voltage level. For example, the voltage value of the common voltage VCOM1 is pulled down. Therefore, the data voltage value on the node Nspx is also pulled down by the capacitive coupling of the coupling capacitor CS1. Therefore, the display status of the sub-pixel SPU1 can be maintained, corrected or adjusted. In some examples, the voltage value of the common voltage VCOM1 may be adjusted between time points tp8 and tp9. In some examples, the voltage value of the common voltage VCOM1 may be adjusted after the time point tp9.

In summary, the multiplexer of the present invention can perform precharging of the first sub-pixel of the first pixel unit and the second sub-pixel of the second pixel unit in the first time interval and the second time interval. After providing the first data signal, the multiplexer also instructs the display to adjust at least one common voltage corresponding to the plurality of sub-pixels receiving the first data signal, so as to further adjust the sub-pixels corresponding to the first data signal. The display status. In this way, the present invention can achieve the technical effects of pre-charging the sub-pixels and adjusting the data voltage values of the sub-pixels. In addition, the first transistor and the second transistor of the switch circuit will not be turned on at the same time. Therefore, the present invention can slow down the deterioration of the first transistor and the second transistor, thereby improving the reliability of the multiplexer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: display 110: display panel 120: Multiplexer 121, 122: select unit CS1~CS6: Coupling capacitor DL1~ DL6: Data line DV: Voltage difference LC1: Liquid crystal structure M1, M2: Transistor Nspx: node PU1, PU2: pixel unit Sdata1: the first data signal Sdata2: second data signal SK1: The first signal SK2: The second signal SL: scan line SPU1~SPU6: sub-pixel Sscan: Scan signal SSG1~SSG6: select signal group SWC1~SWC6: switch circuit T1~T6: Thin film transistor TD1: the first time interval tp1~ tp9: time point TT1: The first period TT2: Second period VCOM1~VCOM6: common voltage

FIG. 1 is a schematic diagram of a display according to an embodiment of the present invention. FIG. 2 is a timing diagram of the first data signal and the second data signal according to an embodiment of the present invention. FIG. 3 is a state timing diagram of the switch circuits SWC1 to SWC3 drawn according to the embodiment of FIG. 1. FIG. 4 is a schematic diagram of the switch circuit according to the embodiment of FIG. 1. FIG. 5 is a timing diagram of a selection signal group according to an embodiment of the present invention. FIG. 6 is a schematic diagram of the coupling between the sub-pixels and the switch circuit according to an embodiment of the present invention. FIG. 7 is a timing diagram of adjusting the data voltage values of sub-pixels according to an embodiment of the present invention.

100: display

110: display panel

120: Multiplexer

121, 122: select unit

CS1~CS6: Coupling capacitor

DL1~DL6: data line

PU1, PU2: pixel unit

Sdata1: the first data signal

Sdata2: second data signal

SL: scan line

SPU1~SPU6: sub-pixel

Sscan: Scan signal

SSG1~SSG6: select signal group

SWC1~SWC6: switch circuit

T1~T6: Thin film transistor

VCOM1~VCOM6: common voltage

Claims (11)

A multiplexer for a display, wherein the display panel of the display includes a plurality of pixel units, wherein the first sub-pixel of each of the plurality of pixel units is arranged in the second sub-pixel and the third sub-pixel Between pixels, wherein the multiplexer includes: a plurality of selection units respectively coupled to the plurality of pixel units, wherein the first selection unit of the plurality of selection units is configured to: The time interval reflects that the first selection signal group transmits the first data signal to the second sub-pixel of the first pixel unit among the plurality of pixel units, and the second time interval reflects that the second selection signal group will The first data signal is transmitted to the first sub-pixel of the second pixel unit of the plurality of pixel units, wherein the second time interval lags behind the first time interval and differs from the first sub-pixel. The time intervals partially overlap, and the multiplexer instructs the display to adjust at least one common voltage corresponding to the plurality of sub-pixels receiving the first data signal after providing the first data signal Adjusting the display conditions of the plurality of sub-pixels corresponding to the received first data signal. The multiplexer according to claim 1, wherein the first selection unit is further configured to: respond to a third selection signal group in a third time interval to transmit the first data signal to the first pixel The third sub-pixel of the unit, wherein the third time interval lags the second time interval and partially overlaps the second time interval. The multiplexer according to claim 1, wherein the first selection unit includes: a first switch circuit, including: a first transistor, and a first end of the first transistor is used to receive the first data Signal, the second end of the first transistor is coupled to the data line of the second sub-pixel connected to the first pixel unit, and the control end of the first transistor is used to receive the The first signal in the first selection signal group; the second transistor, the first end of the second transistor is coupled to the first end of the first transistor, and the second end of the second transistor Is coupled to the second terminal of the first transistor, and the control terminal of the second transistor is used for receiving the second signal in the first selection signal group. The multiplexer according to claim 3, wherein: in the first period, the first transistor is turned on in the first time interval, and in the first period, the second transistor is turned off In the second period, the second transistor is turned on in the first time period, and in the second period, the first transistor is turned off. The multiplexer according to claim 4, wherein in the first period, the voltage value of the first signal is the first voltage value in the first time interval, and the voltage value of the first signal is in the first period The time interval other than the first time interval is a second voltage value, and the voltage value of the second signal maintains the second voltage value. The multiplexer according to claim 5, wherein the first voltage value is a positive voltage, and the second voltage value is a negative voltage. The multiplexer according to claim 4, wherein in the second period, the voltage value of the second signal is the first voltage value in the first time interval, and the voltage value of the second signal is in the first time interval. The time interval outside the first time interval is a second voltage value, and the voltage value of the first signal maintains the second voltage value. The multiplexer according to claim 4, wherein the first period corresponds to a first frame time, and the second period corresponds to a second frame time. The multiplexer according to claim 1, wherein the second selection unit of the plurality of selection units is configured to: respond to the fourth selection signal group in the first time interval to transmit the second data signal to the first time interval The second sub-pixel of a two-pixel unit; and the first sub-pixel of the first pixel unit that transmits the second data signal to the first sub-pixel of the first pixel unit in response to the fifth selection signal group in the second time interval; The time interval is reflected in that the sixth selection signal group transmits the second data signal to the third sub-pixel of the second pixel unit, wherein the data polarity of the first data signal is opposite to that of the second data signal Polarity of the data. The multiplexer according to claim 9, wherein after providing the second data signal, the multiplexer instructs the display to adjust at least one of the plurality of sub-pixels corresponding to the second data signal The common voltage is used to maintain the display status of the plurality of sub-pixels corresponding to the second data signal received. A display device includes: a display panel including a plurality of pixel units, wherein the first sub-pixel of each of the plurality of pixel units is arranged between the second sub-pixel and the third sub-pixel; and The multiplexer described in claim 1 is coupled to the plurality of pixel units.

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