TWI728920B - Electronic circuit for online monitoring a clock signal - Google Patents

Abstract

An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.

Description

Electronic circuit for on-line monitoring of clock signal

The invention relates to a circuit design, and in particular to an electronic circuit for online monitoring of clock signals.

For safety-critical cars or biomedical devices, online health monitoring has become increasingly important. These monitoring can help expose the potential weaknesses of the device during the silicon verification process, and quickly identify the root cause of the failed device returned by the consumer, and by this, the user can effectively shorten the turnaround time for product debugging and correction. In addition, these monitoring can further help capture performance hazards due to various reasons (such as deteriorated parameter defects, environmental noise, soft errors, and/or aging), and thereby warn the system to react in advance to avoid potentially fatal failures.

In this regard, one of the common methods is that the monitor can check the peak-to-peak jitter of the clock signal generated by the phase-locked loop (PLL) applied in the device, and the delay locked loop (delay locked loop). ; DLL) the phase error between the input signal and the output signal. For phase-locked loops, the clock cycle change is an important health indicator. Therefore, how to effectively monitor the clock signal generated by the phase-locked loop is an important research direction in the field, and the solutions of several embodiments are provided below.

The invention is directed to an electronic circuit for monitoring the clock signal, and can perform effective online monitoring of the clock signal provided by a phase-locked loop.

The electronic circuit of the present invention includes a period-to-pulse converter, a pulse reduction block, and an encoder. The period-to-pulse converter receives the clock signal output by the phase-locked loop, and converts each of a plurality of clock period samples of the clock signal to generate a pulse train signal with a plurality of pulses. The pulse reduction block receives multiple pulses of the pulse train signal, and generates multiple capture bits by reducing the multiple pulses of the pulse train signal. The encoder outputs a minimum code and a maximum code according to multiple captured bits. The minimum code indicates the minimum clock period of the clock signal, and the maximum code indicates the maximum clock period of the clock signal. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.

Based on the above, according to the electronic circuit of the present invention, the electronic circuit can obtain the minimum code and the maximum code corresponding to the clock signal by monitoring the reduction result of multiple pulses of the pulse train signal converted from the clock signal, and can obtain the minimum code and the maximum code corresponding to the clock signal by Subtract the minimum code and the maximum code to calculate the peak-to-peak jitter amount code associated with the clock signal.

In order to make the foregoing content easier to understand, several embodiments accompanying the drawings are described in detail as follows.

It should be understood that without departing from the scope of the present invention, other embodiments may be utilized, and structural changes may occur. In addition, it should be understood that the wording and terminology used herein are for descriptive purposes and should not be considered restrictive. The use of "include", "include" or "have" and their variations in this article means to cover the items listed thereafter and their equivalents and additional items. Unless restricted in other ways, the terms "connection", "coupling" and "installation" and their variations are widely used in this article, and cover direct and indirect connection, coupling, and installation.

Fig. 1 is a schematic diagram illustrating an electronic circuit according to an embodiment of the present invention. Referring to FIG. 1, the electronic circuit 100 is coupled to the phase locked loop 10 and used for receiving the clock signal CS generated by the phase locked loop 10. The phase-locked loop 10 can be used in, for example, safety-critical automobiles or biomedical devices. In the embodiment of the present invention, the electronic circuit 100 can continuously process the clock signal CS continuously generated by the phase-locked loop 10 to monitor the clock signal CS online, and output digital data that indicates the value of the clock signal CS Multiple clock cycle changes, such as the minimum clock cycle, the maximum clock signal, and the peak-to-peak jitter amount code related to the clock signal CS. Therefore, the electronic circuit 100 or other processing circuits of the device can effectively determine whether the operating state of the device is normal based on the analysis of the minimum clock period, the maximum clock signal, and the peak-to-peak jitter amount encoding, for example. However, the present invention is not limited to the clock signal CS generated by the phase-locked loop 10. In other embodiments of the present invention, the clock signal CS can be captured from other clock systems or other functional circuits, and the electronic circuit 100 can then determine the circuit operation state or the clock system operation state by monitoring the clock signal CS online. .

It should be explained that during normal operation, the output frequency of the phase-locked loop 10 in the locked state is usually extremely accurate in average sensing, where the output frequency may be 1 GHz. Therefore, its output clock period samples often have a distribution equal to the nominal value of the target clock period. In addition, the distribution tends to have a relative symmetric deviation from its nominal value, for example, [-10ps, +10ps]. However, when the phase-locked loop 10 is affected by an online fault or temporary noise, this symmetry property can be immediately destroyed, causing abnormal conditions, in which the minimum clock period can be too small (for example, from 43 to 36), and the maximum The pulse period can remain normal (for example, under 50), or vice versa. In this fault situation, the peak-to-peak jitter indicator can still indicate abnormal conditions (for example, from 50-43=7 to 50-36=14). However, it is hardly known whether its increase from 7 to 14 is due to an excessively small minimum clock period or an excessively large maximum clock period. On the other hand, the circuit of the present invention can not only exhibit the maximum clock period but also exhibit an abnormal minimum clock period.

Therefore, the electronic circuit 100 of the embodiment is used to focus on monitoring the phase-locked loop 10 for digital clock. Specifically, an abnormally small minimum clock period is particularly harmful (compared to an excessively large maximum clock period) because it can cause calculation failures in the logic circuit driven by the output clock signal of the phase-locked loop 10. Therefore, the electronic circuit 100 is designed to be able to report any changes in the minimum clock period and the maximum clock period in real time during the monitoring period. In addition, based on these two variables, the amount of peak-to-peak jitter can also be derived as a supplementary health indicator.

Specifically, the electronic circuit 100 of the embodiment includes a period-to-pulse converter 110, a pulse reduction block 120, an encoder 130, and a controller 140. The electronic circuit 100 may be a time-to-digital converter (TDC), but the invention is not limited thereto. In the embodiment of the present invention, the period-to-pulse converter 110 is coupled to the phase-locked loop 10 and receives the clock signal CS from the phase-locked loop 10. The pulse reduction block 120 is coupled to the period-to-pulse converter 110, the encoder 130 and the controller 140. The controller 140 can output a control signal or an enabling signal to the pulse reduction block 120 to control or enable the pulse reduction block 120. In an embodiment of the present invention, the period-to-pulse converter 110 may convert each of the multiple clock period samples of the clock signal CS to generate the pulse train signal PT to the pulse reduction block 120 with multiple pulses. In the embodiment of the present invention, the period-to-pulse converter 110 can convert each rising edge or each falling edge of the multiple signal waveforms of the clock signal CS into multiple pulses of the pulse train signal PT. Therefore, each pulse width of the multiple pulses of the pulse train signal PT is positively correlated with the length of each clock cycle of the multiple clock cycle samples of the clock signal CS.

In an embodiment of the present invention, the pulse reduction block 120 may generate a plurality of capture bits by reducing a plurality of pulses of the pulse train signal PT. The encoder 130 can generate a minimum code and a maximum code according to a plurality of captured bits, and output the minimum code and the maximum code to other processing circuits of the electronic circuit 100, and the minimum code indicates the minimum clock period of the clock signal CS, The maximum code indicates the maximum clock period of the clock signal CS. For example, the encoder 130 may be watermark to binary encoding, and the number of multiple capture bits may be 64. The encoder 130 generates a 5-bit binary code by converting 64 captured bits. In addition, the electronic circuit 100 can subtract the minimum code and the maximum code to generate a peak-to-peak jitter amount code indicating the peak-to-peak period jitter of the clock signal CS. In addition, the electronic circuit 100 of the embodiment may be an all-digital electronic circuit and the phase-locked loop 10 may be an all-digital phase-locked loop (ADPLL), but the invention is not limited thereto.

Fig. 2 is a trajectory diagram illustrating watermarking rules according to an embodiment of the present invention. 1 and 2, the following description first conceptually explains how to determine the minimum clock period and the maximum clock period of the clock signal CS based on the watermark rule. In the embodiment of the present invention, the electronic circuit 100 can change the survival trajectory of each pulse of the pulse train signal PT of the input pulse reduction block 120 into a "single-point watermark" or simply a watermark. As shown in FIG. 2, there are three input pulses P1 to P3 that sequentially input the pulse train signal PT of the pulse reduction block 120, and present three separate pulse reduction processes and retain three survival trajectories 201 to survive Track 203. The three input pulses P1 to P3 of the pulse train signal PT correspond to three clock cycle samples of the clock signal CS.

In the embodiment of the present invention, after the three survival trajectories 201 to 203 have been processed by the pulse reduction block 120, the electronic circuit 100 can record the three watermark orientations 201P to 203P. The electronic circuit 100 may further combine the three watermark positions 201P to the watermark positions 203P to quickly report the minimum clock period Pmin, the maximum clock period Pmax, and the peak-to-peak jitter amount encoding Pj of the clock signal CS at any time during the monitoring session. . Based on the above, the specific circuit implementation of the pulse reduction block 120 will be described in detail in the following embodiments.

FIG. 3 is a schematic diagram illustrating a pulse reduction block according to an embodiment of the invention. 3, in an embodiment of the present invention, the pulse reduction block 120 includes a plurality of reduction units 121_1 to 121_N, a plurality of first layer circuits 122_1 to first layer circuits 122_N, and a plurality of second layer circuits 123_1 to 121_N. The second layer circuit 123_N, where N is a positive integer. The plurality of first layer circuits 122_1 to first layer circuits 122_N and the plurality of second layer circuits 123_1 to second layer circuits 123_N are flip-flop (FF) circuits, respectively. The reduction unit 121_1 is composed of two inverters 121_1a and an inverter 121_1b coupled in series, and the internal components of the reduction unit 121_2 to the reduction unit 121_N are the same as the reduction unit 121_1. More specifically, the circuits and components of the pulse reduction block 120 can be classified into multiple stages, and each of the multiple stages includes a reduction unit, a first layer circuit, and a second layer circuit.

In the embodiment of the present invention, the input end of the first reduction unit 121_1 is used to receive the burst signal PT, and the output end of the first reduction unit 121_1 is coupled to the first layer circuit 122_1 and the next level reduction unit 121_2. The first layer circuit 122_1 is coupled to the second layer circuit 123_1. For one pulse of the pulse train signal PT, the first reduction unit 121_1 reduces one pulse of the pulse train signal PT to output the current reduced pulse X[0] to the first-layer circuit 122_1 and the next-stage reduction unit 121_2. In the embodiment of the present invention, the first layer circuit 122_1 outputs the current monostable signal Q[0] with the current steady state value to the second layer circuit 123_1 according to the current reduced pulse X[0]. The second layer circuit 123_1 receives the current monostable signal Q[0] with the current steady state value and receives the next monostable signal Q[1] with the next steady state value from the first layer circuit 122_1 of the next stage. In the embodiment of the present invention, the second layer circuit 123_1 compares the current steady state value with the next steady state value to determine the capture bit C[0]. Therefore, for multiple pulses of the pulse train signal 102, the second layer circuit 123_1 sequentially compares multiple current steady-state values and multiple next steady-state values to determine whether to set the capture bit C[0] to "1 ".

Then, the input terminal of the first reduction unit 121_2 is used to receive the previous reduction pulse from the previous stage (the first reduction unit 121_1), and the output terminal of the first reduction unit 121_2 is coupled to the first layer circuit 122_2 and the next stage reduction unit 121_3 . The first layer circuit 122_2 is coupled to the second layer circuit 123_2. The first reduction unit 121_2 reduces the previous reduction pulse X[0] to output the current reduction pulse X[1] to the first layer circuit 122_2 and the reduction unit 121_3 of the next stage. In the embodiment of the present invention, the first layer circuit 122_2 outputs the current monostable signal Q[1] with the current steady state value to the second layer circuit 123_2 according to the current reduced pulse X[1]. The second layer circuit 123_2 receives the current monostable signal Q[1] with the current steady state value and receives the next monostable signal Q[2] with the next steady state value from the first layer circuit 122_3 of the next stage. In the embodiment of the present invention, the second layer circuit 123_2 compares the current steady state value with the next steady state value to determine the capture bit C[1]. Therefore, by analogy, the second layer circuit 123_1 to the second layer circuit 123_N sequentially compare multiple current steady-state values with multiple next steady-state values to determine multiple capture bits C[0] to capture bits C[N-1].

Based on the structure of the pulse reduction block 120 shown in FIG. 3, referring to FIG. 1, the cycle-to-pulse converter 110 can continuously receive multiple clock signals to output multiple pulse train signals to the pulse reduction block 120. And the pulse reduction block 120 generates a plurality of capture bit sequences. Subsequently, the encoder 130 outputs multiple minimum codes and multiple maximum codes corresponding to multiple capture bit sequences during multiple monitoring periods, so that the electronic circuit 100 can instantly determine multiple signals corresponding to multiple clock signals. The amount of peak-to-peak jitter is encoded.

Fig. 4 is a schematic diagram illustrating the first layer circuit of the present invention. Referring to FIG. 4, each of the first layer circuit 122_1 to the first layer circuit 122_N of FIG. 3 may be similar to the first layer circuit 400. The first layer circuit 400 includes a first flip-flop unit 410, two buffers 420 and a buffer 430, and an inverter 440, but the invention is not limited thereto. In other embodiments of the present invention, the number of buffers can be determined according to different process conditions or different circuit design requirements. In the embodiment of the present invention, when the input terminal (data input pin) (D) of the first flip-flop unit 410 receives a signal with a high logic level ("1"), the first flip-flop unit 410 The trigger terminal of is coupled to the reduction unit of the same stage, the output terminal (data output pin) (Q) of the first flip-flop unit 410 is coupled to the second layer circuit of the same stage, and the first flip-flop unit 410 The output terminal of is coupled to the inverting reset terminal (asynchronous reset pin) of the first flip-flop unit 410 via the two buffers 420, the buffer 430 and the inverter 440 coupled in series.

In the embodiment of the present invention, the trigger end of the first flip-flop unit 440 receives the reduction pulse X[i] from the reduction unit of the same stage, where i is between a positive integer and N. Therefore, when the trigger terminal of the first flip-flop unit 410 receives the reduced pulse X[i], the output terminal of the first flip-flop unit 410 outputs a monostable with a high logic level ("1") of the steady-state value. State signal Q[i]. And then, when the inverting reset terminal of the first flip-flop unit 410 receives the inverted and delayed monostable signal Q[ When i], the monostable signal Q[i] is reset to a low logic level ("0"), so the monostable signal has a single-shot pulse width.

FIG. 5A is a schematic diagram illustrating the second layer circuit operating in the first case of the present invention. FIG. 5B is a schematic diagram illustrating the second layer circuit operating in the second case of the present invention. Referring to FIGS. 5A and 5B, each of the second layer circuit 123_1 to the second layer circuit 123_N of FIG. 3 may be similar to the second layer circuit 500. The second layer circuit 500 includes a second flip-flop unit 510 and an OR gate 520. In the embodiment of the present invention, the input terminal of the second flip-flop unit 510 is coupled to the output terminal of the OR gate 520, the inverting trigger terminal is coupled to the output terminal of the first flip-flop unit of the same stage, and the first flip-flop unit The output terminal of the two flip-flop units 510 is coupled to the input terminal of the OR gate, and the inverting input terminal of the OR gate is coupled to the output terminal of another first flip-flop unit of the next stage.

In the embodiment of the present invention, the trigger terminal of the second flip-flop unit 520 receives the monostable signal Q[i] from the first flip-flop unit of the same stage, and the inverting input terminal of the OR gate receives from the next stage The monostable signal Q[i+1]. Therefore, only when any capture bit C[i] has been previously set to a high logic level ("1"), the capture bit C[i] of the output terminal of the second flip-flop unit 510 will be in the monostable state. The falling edge of the signal Q[i] becomes a high logic level ("1"), and the monostable signal Q[i+1] is a low logic level ("0").

It should be noted that the second layer circuit 500 associated with the fine reduction unit is depicted in FIGS. 5A and 5B. Its behavior is to realize the aforementioned "watermarking rule". When generating its output, the capture bit C[i] is sticky. At the beginning of the monitoring session, the capture bit C[i] is reset to "0". Then the second layer circuit 500 repeatedly checks the watermark rules. After the capture bit C[i] is set to "1", it remains "1" throughout the monitoring session. In the circuit of the second layer circuit 500, the watermarking rules and the sticky requirements are combined by the following conditions: only when any capture bit C[i] has been previously set to "1", the capture bit C[i] It will become "1" at the falling edge of the monostable signal Q[i], or the monostable signal Q[i+1] will become "0". The timing relationship between the waveforms of the monostable signal Q[i] and the monostable signal Q[i+1] is illustrated in FIGS. 5A and 5B. The first situation in FIG. 5A is not a watermark situation, because the falling edges of the monostable signal Q[i] and the monostable signal Q[i+1] are "1". The second situation in FIG. 5B is the watermark situation, because the falling edges of the monostable signal Q[i] and the monostable signal Q[i+1] are "0".

FIG. 6 is a waveform diagram illustrating a pulse reduction block for reducing a plurality of pulses according to the present invention. 1, 3 and 6, the encoder 130 can convert the capture bit C[0] to the capture bit C[3] into a minimum code and a maximum code, and the electronic circuit 100 can subtract the maximum code and the minimum code To generate a peak-to-peak jitter amount encoding. For example, when the reduction unit 121_1 receives a burst signal PT having a series of 3 pulses P1 to P3. In this exemplary embodiment, the first pulse P1 is the smallest, so the first pulse P1 only survives in the reduction unit 121_1 from time t0 to time t1, so that the capture bit C[0] is "1". During the period from time t1 to time t2, the electronic circuit 100 can determine that the minimum code is "0", the maximum code is "0", and the peak-to-peak jitter amount code is "0" (0-0=0). Subsequently, the second pulse P2 is the maximum, so the second pulse P2 survives in the three reduction units 121_1 to 121_3 from time t2 to time t3, so that the capture bit C[2] is "1". During the period from time t3 to time t4, the electronic circuit 100 can determine that the minimum code is still "0", the maximum code is "2", and the peak-to-peak jitter amount code is "2" (2-0=2). Finally, the third pulse P3 survives in the two reduction units 121_1 to 121_2 from time t4 to time t5, so that the capture bit C[2] remains "1". During the period from time t3 to time t4, the electronic circuit 100 can determine that the minimum code is still “0”, the maximum code is still “2”, and the peak-to-peak jitter amount code is still “2” (2-0=0).

Therefore, in this exemplary embodiment, whenever it sees the reduced pulse X[0] to the reduced pulse X[3], each of the monostable signal Q[0] to the monostable signal Q[3] One responds to a one-shot signal. Due to its self-renewal characteristic, each of the monostable signal Q[0] to the monostable signal Q[3] can respond repeatedly. For the first pulse, the watermark is azimuth "0", so the capture bit C[0] becomes high after seeing the first pulse P1. Similarly, after the second pulse P2 and the third pulse P3 have traveled through the pulse reduction block 120, both the captured bit C[1] and the captured bit C[2] become sticky "1". In this exemplary embodiment, the minimum coding, maximum coding, and peak-to-peak jitter coding have been dynamically changed during the monitoring process to reflect the latest situation.

In summary, the electronic circuit of the present invention can perform online monitoring of the clock signal generated by the phase-locked loop, and the electronic circuit of the present invention can determine the period jitter of the clock signal. Specifically, the electronic circuit of the present invention can determine the minimum clock period and the maximum clock period of the clock signal. Therefore, the electronic circuit or other processing circuits of the present invention can effectively perform corresponding operations by using the above detailed information related to the period jitter of the clock signal.

It will be obvious to those skilled in the art that various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of the present invention. In view of the foregoing, the present invention intends to cover modifications and changes, provided that the modifications and changes fall within the scope of the following patent applications and their equivalents.

10: Phase locked loop 100: electronic circuit 102: Burst signal 110: Period to pulse converter 120: Pulse reduction block 121_1 to 121_N: reduction unit 121_1a, 121_1b: inverter 122_1 to 122_N, 400: first layer circuit 123_1 to 123_N, 500: second layer circuit 130: encoder 140: Controller 201, 202, 203: survival trajectory 201P, 202P, 203P: watermark orientation 410: The first flip-flop unit 420, 430: Buffer 440: inverter 510: The second flip-flop unit 520: OR gate C[0], C[1], C[2], C[3], C[i], C[N-1]: capture bit CS: Clock signal D: Input P1, P2, P3: input pulse Pj: peak-to-peak jitter coding Pmax: Maximum clock period Pmin: minimum clock period PT: Burst signal Q: output Q[0], Q[1], Q[2], Q[3], Q[i], Q[i+1]: monostable signal t1, t2, t3, t4, t5: time X[0], X[1], X[3], X[i]: reduced pulse

Fig. 1 is a schematic diagram illustrating an electronic circuit according to an embodiment of the present invention. Fig. 2 is a trajectory diagram illustrating the concept of survival trajectories and watermarks corresponding to multiple clock period samples according to an embodiment of the present invention. FIG. 3 is a schematic diagram illustrating a pulse reduction block according to an embodiment of the invention. Fig. 4 is a schematic diagram illustrating the first layer circuit of the present invention. FIG. 5A is a schematic diagram illustrating the second layer circuit operating in the first case of the present invention. FIG. 5B is a schematic diagram illustrating the second layer circuit operating in the second case of the present invention. FIG. 6 is a waveform diagram illustrating a pulse reduction block for reducing a plurality of pulses according to the present invention.

10: Phase locked loop

100: electronic circuit

110: Period to pulse converter

120: Pulse reduction block

130: encoder

140: Controller

CS: Clock signal

PT: Burst signal

Claims (10)

An electronic circuit for online monitoring of clock signals, including: A period-to-pulse converter, receiving the clock signal, and converting each of a plurality of clock period samples of the clock signal to generate a pulse train signal with a plurality of pulses; A pulse reduction block, coupled to the period-to-pulse converter, receives the multiple pulses of the pulse train signal, and generates multiple captures by reducing the multiple pulses of the pulse train signal Bit; and An encoder is coupled to the pulse reduction block, and outputs a minimum code and a maximum code according to the plurality of capture bits, the minimum code indicating a minimum clock period of the clock signal, so The maximum code indicates a maximum clock period of the clock signal, The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code. The electronic circuit according to claim 1, wherein the pulse reduction block includes a plurality of stages, and each of the plurality of stages includes: A reduction unit that continuously receives the plurality of pulses of the pulse train signal or receives a plurality of previous reduction pulses from a previous stage, and continuously outputs a plurality of current reduction pulses; A first layer circuit, coupled to the reduction unit, and output a plurality of current monostable signals with a plurality of current steady state values according to the plurality of current reduction pulses; and A second layer circuit, coupled to the first layer circuit, and receiving the plurality of current monostable signals with the plurality of current steady-state values and receiving from another first layer circuit of the next stage Multiple next monostable signals with multiple next steady state values, The second layer circuit sequentially compares the plurality of current steady state values with the plurality of next steady state values to determine one of the plurality of capture bits. The electronic circuit according to claim 2, wherein when the second layer circuit determines that any one of the plurality of current steady-state values is different from any corresponding one of the plurality of next steady-state values, The second layer circuit sets the one of the plurality of capture bits from "0" to "1". The electronic circuit according to claim 3, wherein the encoder outputs the minimum code according to a capture bit output by a minimum level of the capture bit set to "1", and the The encoder outputs the maximum code according to another capture bit output by a maximum level with another capture bit set to "1". The electronic circuit according to claim 2, wherein the reduction unit is composed of two inverters coupled in series. The electronic circuit according to claim 2, wherein the first layer circuit includes a first flip-flop unit, wherein an input terminal of the first flip-flop unit receives a signal with a high logic level, so A trigger end of the first flip-flop unit is coupled to the reduction unit, an output end of the first flip-flop unit is coupled to the second layer circuit, and the first flip-flop unit The output terminal of is coupled to an inverting reset terminal of the first flip-flop unit via one or more buffers and an inverter coupled in series. The electronic circuit according to claim 6, wherein the second layer circuit includes a second flip-flop unit and an OR gate, wherein the input end of the second flip-flop unit is coupled to the OR gate Output terminal, the inverting trigger terminal is coupled to the output terminal of the first flip-flop unit, and the output terminal of the second flip-flop unit is coupled to an input terminal of the OR gate, and An inverting input terminal of the OR gate is coupled to an output terminal of another first flip-flop unit of the next stage. The electronic circuit according to claim 1, wherein the electronic circuit is a fully digital electronic circuit. The electronic circuit according to claim 1, wherein each pulse width of the plurality of pulses of the pulse train signal is positively correlated with the length of each clock period of the plurality of clock period samples of the clock signal . The electronic circuit according to claim 1, wherein the cycle-to-pulse converter continuously receives a plurality of clock signals to output a plurality of pulse train signals to the pulse reduction block, and the pulse reduction block Generate multiple capture bit sequences, wherein the encoder outputs multiple minimum codes and multiple maximum codes corresponding to the multiple capture bit sequences during multiple monitoring periods, so that the electronic circuit can instantly determine the corresponding The multiple peak-to-peak jitter amounts of the multiple clock signals are encoded.

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