TWI452837B - Clock recovery circuit and frequency detection module thereof - Google Patents

Description

Clock recovery circuit and frequency detection module thereof

The present disclosure relates to a detection circuit, and more particularly to a frequency detection circuit that can be used in a clock recovery circuit.

In a communication system or other electronic transmission system (such as a display driving circuit), the transmitting end generates a data signal according to its clock and transmits the data signal to the receiving end through the channel. In order to correctly identify the logical level of the data signal, the receiving end must read the data signal according to the clock synchronized with the clock of the transmitting end. Therefore, the receiving end must use the clock data recovery circuit to know the clock used by the transmitting end.

In general, clock data recovery techniques can be divided into at least two types. One uses an additional channel to transmit the clock signal corresponding to the data signal to the receiving end. However, this technology has the disadvantage that an additional channel must be added. The other is to use the frequency detection circuit in the clock/data recovery circuit (CDR) at the receiving end to directly respond to the data signal and its clock by judging the transmitted data signal itself.

In some conventional clock data recovery circuits, the main processing can be divided into two processing stages. First, the frequency recovery phase, that is, the frequency detection circuit is used to detect the data signal to find a suitable clock frequency. In addition, it is a phase recovery phase in which the phase of the data signal is locked by sampling using the sampling clock frequency.

The clock recovery circuit usually sets the pulse generator and the frequency detection circuit. The clock generator is used to generate a sampling clock signal of a specific frequency. The frequency detection circuit is used for detecting the data signal and ensuring that the sampling clock signal can be effectively sampled. For example, when the sampling clock signal is too low, which may cause distortion of the sampling of the data signal, the frequency detecting circuit can generate a control signal to drive the clock generator to increase the frequency of the sampling clock signal.

However, with the development of communication technology, the current frequency detection circuit needs to operate at a relatively high frequency. In the high frequency case, the reset mechanism of the analog flip-flop component in the conventional frequency detection circuit is not easy to design. . Moreover, the clock signal path in the conventional frequency detecting circuit is too complicated, which makes it difficult to perform clock calibration in use.

Therefore, in order to solve the above problem, the present invention discloses a clock recovery circuit and a frequency detecting module thereof. The analog-like flip-flop component used in the frequency detecting module in the present disclosure can omit a reset mechanism. Moreover, the path and logical structure of the clock signal used by the clock signal is relatively simple, and the effect of frequency comparison can be achieved.

One aspect of the present invention provides a clock recovery circuit including a clock generation device and a frequency detection module. The clock generating device is configured to generate a clock signal. The frequency detecting module is configured to determine the clock edge of the data signal and the clock edge of the clock signal, and the clock edge of the clock signal is not detected between two consecutive clock edges of the data signal. The frequency detecting module generates a control signal to the clock generating device to improve the clock frequency of the clock signal.

According to an embodiment of the present invention, the clock edge of the data signal and the The clock edge of the clock signal contains the rising edge of the clock or the falling edge of the clock.

According to an embodiment of the invention, the frequency detecting module comprises a first flip flop, a second flip flop, a third flip flop, and a logic unit. When the clock edge of the data signal is triggered, the first flip-flop is used to output the voltage level of a first node to a second node. When the clock edge of the clock signal is triggered, the second flip-flop is used to invert the voltage level of the second node and output to the first node. The logic unit determines the voltage level of the first node and the voltage level of the second node. When the voltage level of the first node and the second node are logically the same, the logic unit is configured to generate a control signal. When the clock edge of the data signal is triggered, the third flip-flop is configured to output the control signal to the clock generation module, thereby increasing the clock frequency of the clock signal.

In the above embodiment, the logic unit may include an AND gate or an exclusive-OR gate (XOR gate).

In the above embodiment, the frequency detecting module further includes a delay unit coupled between the data signal and the third flip-flop. In this embodiment, the delay unit is configured to form a predetermined delay time for the data signal, and the predetermined delay time is substantially equal to a total delay time of the second flip-flop and the logic unit.

Another aspect of the present invention provides a frequency detecting module adapted to detect a relative relationship between a clock signal and a data signal. The frequency detection module includes a first flip-flop, a second flip-flop, a third flip-flop, and a logic unit. When the edge of the data signal is triggered, the first positive and negative The device is configured to output a voltage level of a first node to a second node. When the clock edge of the clock signal is triggered, the second flip-flop is used to invert the voltage level of the second node and output to the first node. The logic unit determines the voltage level of the first node and the voltage level of the second node. When the voltage level of the first node and the second node are logically the same, the logic unit is configured to generate a control signal. When the edge of the data signal is triggered, the third flip-flop is used to output the control signal, thereby increasing the clock frequency of the clock signal.

According to an embodiment of the invention, the clock edge of the data signal and the clock edge of the clock signal include a positive edge of the clock or a negative edge of the clock.

In the above embodiment, the logic unit may include a logic gate or a mutual exclusion or logic gate.

In the above embodiment, the frequency detecting module further includes a delay unit coupled between the data signal and the third flip-flop. In this embodiment, the delay unit is configured to form a predetermined delay time for the data signal, and the predetermined delay time is substantially equal to a total delay time of the second flip-flop and the logic unit.

Another aspect of the present invention provides a frequency detecting module adapted to detect a relative relationship between a clock signal and a data signal. The frequency detection module includes a first flip-flop, a second flip-flop, a third flip-flop, and a logic unit. The clock control terminal of the first flip-flop is coupled to the data signal, and the data input end of the first flip-flop is coupled to a first node, and the data output end of the first flip-flop is coupled to the first The second node. The clock control end of the second flip-flop is coupled to the clock signal, the data input end of the second flip-flop is coupled to the second node, and the data output end of the second flip-flop is coupled to The first node. The input ends of the logic unit are respectively coupled to the first node and the second node, and the output end of the logic unit selectively generates a control signal according to the voltage levels of the first node and the second node. The clock control end of the third flip-flop is coupled to the data signal, and the data input end of the third flip-flop is coupled to the output end of the logic unit, and the data output end of the third flip-flop is used for output The control signal.

According to an embodiment of the invention, the logic unit comprises a logic gate or a mutually exclusive or logic gate.

According to an embodiment of the invention, the frequency detecting module further includes a delay unit coupled between the data signal and the third flip-flop.

Referring to FIG. 1, FIG. 1 is a schematic diagram of a clock recovery circuit 100 in accordance with an embodiment of the present invention. The clock recovery circuit 100 in this embodiment can be used for the clock recovery portion in the clock/data recovery circuit (CDR).

In this embodiment, the clock recovery circuit 100 includes a clock generation device 120 and a frequency detection module 140. The clock generating device 120 is configured to generate the clock signal CLK according to a clock frequency.

At present, the common clock/data recovery circuit is divided into full-rate sampling and half-rate sampling according to sampling clock characteristics, or 1/4-speed sampling and 1/8-speed sampling, etc. . Among them, under full-speed sampling, the clock frequency for sampling is twice the data signal, in order to operate normally. In the case of half-speed sampling, the frequency of the clock signal used for sampling is approximately the same as the frequency of the data signal. In this embodiment, the clock recovery circuit 100 mainly uses the clock signal frequency of the half speed sampling.

The frequency detecting module 140 in FIG. 1 is configured to determine whether the clock frequency of the current clock signal CLK is based on the clock edge of the data signal DATA and the clock edge of the clock signal CLK. Suitable.

Please refer to FIG. 2 and FIG. 3 . FIG. 2 is a timing diagram of the ideal data signal DATA and the clock signal CLK according to an embodiment. FIG. 3 is a timing diagram showing the frequency of the clock signal CLK being lower than the frequency of the data signal DATA according to an embodiment. In the second and third figures, the frequency detecting module 140 judges based on the data edge DATA and the clock edge of the clock signal CLK, but the present invention is not limited to the positive edge of the clock. In another embodiment, the determination may also be made according to the falling edge of the clock.

As shown in FIG. 2, in an ideal case, at least one clock positive edge of the clock signal CLK exists between two consecutive clock positive edges of the data signal DATA. In this way, the conversion period of each data signal DATA can be sampled at least once.

However, as shown in FIG. 3, if the clock frequency of the clock signal CLK generated by the clock generating device 120 is too low, there may be no clock between the two consecutive clock edges of the data signal DATA. The positive edge of the signal CLK. For example, in the interval Er in FIG. 3, the positive edge of the two data signals DATA passes, but there is no positive edge of the clock signal CLK, indicating that the clock frequency of the clock signal CLK is too low. At this time, the response of the data signal DATA may be distorted.

In this embodiment, the frequency detecting module 140 is configured to determine the data signal. The edge of the clock of DATA and the edge of the clock of the clock signal CLK, when the two consecutive clock edges of the data signal DATA (in this case, the positive edge of the clock), the clock edge of the clock signal CLK is not detected. (In this example, the positive edge of the clock) (such as the interval Er in FIG. 2), the frequency detecting module 140 can generate the control signal Vout to the clock generating device 120 (as shown in FIG. 1). Increase the clock frequency of the clock signal CLK.

As shown in FIG. 1 , the frequency detecting module 140 includes a first flip flop 142 , a second flip flop 144 , a third flip flop 146 , and a logic unit 148 .

The clock control terminal of the first flip-flop 142 is coupled to the data signal DATA. The data input end of the first flip-flop 142 is coupled to the first node N1. In this embodiment, the second flip-flop 144 The data output end is coupled to the data input end of the first flip-flop 142 by a feedback method to form the first node N1. The data output end of the first flip-flop 142 is coupled to the second node N2.

The clock control terminal of the second flip-flop 144 is coupled to the clock signal CLK, the data input terminal of the second flip-flop 144 is coupled to the second node N2, and the data output terminal of the second flip-flop 144 is coupled to The first node N1.

The input ends of the logic unit 148 are respectively coupled to the first node N1 and the second node N2.

The clock control terminal of the third flip-flop 146 is coupled to the data signal DATA through a delay unit 149. The data input terminal of the third flip-flop 146 is coupled to the output terminal of the logic unit 148, and the third flip-flop 146 The data output terminal is configured to output the control signal Vout to the clock generating device 120.

In this embodiment, the delay unit 149 is coupled between the data signal DATA and the third flip-flop 146, wherein the delay unit 149 is used for data communication. The number DATA forms a predetermined delay time which is substantially equal to the summed delay time of the second flip-flop 144 and the logic unit 148.

Wherein, under normal circumstances, the clock frequency of the instant pulse signal CLK is sufficient (ie, greater than or equal to the clock frequency of the data signal DATA). When the clock of the data signal DATA is triggered, the first flip-flop 142 is configured to output the voltage level Vclrb of the first node N1 to the second node N2; and when the clock edge of the pulse signal CLK is triggered, The second flip-flop 144 is configured to invert the voltage level Va of the second node N2 and output it to the first node N1.

Due to the reverse output effect generated by the second flip-flop 144, the voltage level of the first node N1 and the voltage of the second node N2 are normal under the condition that the next positive edge of the data signal DATA is triggered. The level Va should have a different level. If the voltage level Vclrb is at a high level, the voltage level Va is a low level; if the voltage level Vclrb is at a high level, the voltage level Va is at a high level.

At this time, the logic unit 148 determines the voltage level Vclrb of the first node N1 and the voltage level Va of the second node N2. At this time, the voltage levels of the first node N1 and the second node N2 are logically different, so Logic unit 148 does not generate a control signal.

Then, please refer to FIG. 1 and FIG. 4 together. FIG. 4 is a diagram showing the frequency detecting module 140 of the frequency detecting module 140 in FIG. 1 when the clock frequency of the pulse signal CLK is too low, so that the frequency detecting module 140 generates Schematic diagram of the timing when the signal Vout is controlled.

As shown in FIG. 4, if there is a clock positive edge trigger of at least one clock signal CLK between two consecutive clock edge positive signal triggers of the data signal DATA, the second positive and negative is triggered. The voltage level Va of the second node N2 is reversed and output to the first node N1, that is, Vclrb = . In this way, the voltage levels of the first node N1 and the second node N2 are opposite logics, and the frequency detecting module 140 does not operate, such as between the time points T0~T1 and the time points T2~T3.

As shown in Fig. 4, between the time points T1~T2 and the time points T3~T4, there are two positive signal edge signals (DATA) of the data signal DATA, but there is no clock signal CLK. The clock is triggered by the positive edge.

In this embodiment, the portion between the time points T3 and T4 is discussed first, and the time point T3~T4 is triggered by the clock edge of the data signal DATA twice, but the clock of the clock signal CLK is not positive. The edge triggering, therefore, the voltage level Vclrb and the voltage level Va of the second node N2 are both at a high level. At this time, the logic unit 148 determines the voltage level Vclrb of the first node N1 and the voltage of the second node N2. The level Va is logically identical (same as the high level), so that the output of the logic unit 148 produces a high level output voltage Vb. Then, at the time point T4, the clock positive edge of the data signal DATA triggers the third flip-flop 146, and the third flip-flop 146 outputs the high level according to the output end of the logic unit 148 (the output voltage Vb of the high level). The control signal Vout is used to drive the clock generating device 120 to increase the clock frequency of the clock signal CLK after the time point T4.

In this way, the clock generating device 120 gradually increases the clock frequency of the clock signal CLK as needed, until the frequency detecting module 140 determines that the two consecutive clock edges of the data signal DATA can be detected. The clock edge of the pulse signal CLK.

In the above embodiment, the logic unit 148 in this embodiment may be employed. And an AND gate, but the logic unit 148 in the present invention is not limited to the logic gate. And the logic (AND) logic unit 148 can determine the voltage level Vclrb of the first node N1 and the voltage level Va of the second node N2, which are both high-level, and then serve as a basis for subsequent up-conversion control, but It is impossible to judge the same low level.

On the other hand, the portion between the time points T1 and T2 is triggered by the clock edge of the data signal DATA that has passed twice between the time point T1 and the time point T2 in FIG. 4, and there is no clock signal CLK. The clock is triggered by the positive edge. At this time, the voltage level Vclrb of the first node N1 and the voltage level Va of the second node N2 are the same logic, but are both low level, and therefore the output voltage of the output of the logical unit 148 of the logic type Vb has not changed. In this embodiment, the logic unit 148 can adopt the logic gate, and the logic gate structure is simple and the response is fast. However, under such a judgment mechanism, the clock recovery circuit 100 can increase the clock frequency of the clock signal CLK. It takes a long time to reach a sufficient frequency (using the first node N1 and the second node N2 to be the same as the high level portion).

Therefore, in another embodiment of the present invention, the logic unit may adopt an exclusive-OR gate (XOR gate). Please refer to FIG. 5 and FIG. 6. FIG. 5 is a schematic diagram of the clock recovery circuit 300 according to another embodiment of the present invention. FIG. 6 is a timing diagram of the frequency detecting module 340 in FIG. 5 when the clock frequency of the pulse signal CLK is too low and the frequency detecting module 340 generates the control signal Vout.

As shown in FIG. 5, the clock recovery circuit 300 includes a clock generation device 320 and a frequency detection module 340. The frequency detecting module 340 includes a first flip flop 342, a second flip flop 344, and a third flip flop 346. Logic unit 348. It should be particularly noted that in this embodiment, logic unit 348 employs a mutually exclusive or (XOR) logic gate.

As shown in FIG. 6, since the logic unit 348 adopts a mutually exclusive or (XOR) logic gate, when the voltage level Vclrb of the first node N1 and the voltage level Va of the second node N2 are at the same low level (eg, When the time point T1 ~ time point T2), and the same high level (such as time point T3 ~ time point T4), the output of the logic unit 348 generates a high-level output voltage Vb, thereby making the third positive The inverter 346 outputs the high-level control signal Vout (such as the time point T2 and the time point T4) according to the output terminal (the high-level output voltage Vb) of the logic unit 348, thereby controlling the clock generating device 320.

In this way, the clock generating device 320 gradually increases the clock frequency of the clock signal CLK as needed, until the frequency detecting module 340 determines that the consecutive two clock edges of the data signal DATA can be detected. The clock edge of the pulse signal CLK.

For the other detailed circuit and operation principle of the clock recovery circuit 300 in FIG. 5, reference may be made to the clock recovery circuit 100 in the previous embodiment of FIG. 1, which will not be further described herein.

In summary, the present invention discloses a clock recovery circuit and a frequency detecting module thereof, wherein the flip-flop component used in the frequency detecting module in the present disclosure does not need to be reset, and the The path and logical structure of the clock signal is relatively simple, and the effect of frequency comparison can be achieved.

The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is defined by the scope of the patent application attached. quasi.

100‧‧‧clock recovery circuit

120‧‧‧clock generator

140‧‧‧Frequency detection module

142‧‧‧First forward and reverse

144‧‧‧second flip-flop

146‧‧‧ third positive and negative

148‧‧‧Logical unit

149‧‧‧Delay unit

300‧‧‧clock recovery circuit

320‧‧‧clock generator

340‧‧‧Frequency detection module

342‧‧‧First forward and reverse

344‧‧‧second flip-flop

346‧‧‧ third positive and negative

348‧‧‧Logical unit

349‧‧‧Delay unit

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a clock recovery circuit in accordance with an embodiment of the present invention. FIG. 2 is a timing diagram of the ideal data signal and the clock signal according to an embodiment; FIG. 3 is a timing diagram of the frequency of the clock signal being lower than the frequency of the data signal according to an embodiment; 4 is a timing diagram of the frequency detecting module of the frequency detecting module in FIG. 1 when the clock frequency of the pulse signal is too low to cause the frequency detecting module to generate a control signal; FIG. 5 is another schematic diagram according to the present invention. A schematic diagram of a clock recovery circuit in the embodiment; FIG. 6 is a timing diagram of the frequency detection module of the frequency detecting module in FIG. 5 when the clock frequency of the pulse signal is too low to cause the frequency detecting module to generate a control signal.

100‧‧‧clock recovery circuit

120‧‧‧clock generator

140‧‧‧Frequency detection module

142‧‧‧First forward and reverse

144‧‧‧second flip-flop

146‧‧‧ third positive and negative

148‧‧‧Logical unit

149‧‧‧Delay unit

Claims (11)

A clock recovery circuit includes: a clock generation device for generating a clock signal; and a frequency detection module for determining a clock edge of a data signal and a clock edge of the clock signal When the clock edge of the clock signal is not detected between two consecutive clock edges of the data signal, the frequency detecting module generates a control signal to the clock generating device, thereby improving the clock. One of the clock frequencies of the signal. The clock recovery circuit of claim 1, wherein the clock edge of the data signal and the clock edge of the clock signal comprise a rising edge or a falling edge of the clock. . The clock recovery circuit of claim 1, wherein the frequency detecting module comprises: a first flip-flop, the first flip-flop is used when the clock edge of the data signal is triggered a voltage level of the first node is output to a second node; a second flip-flop is used to trigger the voltage level of the second node when the clock edge of the clock signal is triggered Reversely outputting to the first node; a logic unit, the logic unit determining a voltage level of the first node and a voltage level of the second node, when the voltage level of the first node and the second node When logically identical, the logic unit is used And generating a control signal; and a third flip-flop, when the clock edge of the data signal is triggered, the third flip-flop is configured to output the control signal to the clock generation module, thereby improving the clock signal The clock frequency. The clock recovery circuit of claim 3, wherein the logic unit comprises an AND gate or an exclusive-OR gate (XOR gate). The clock recovery circuit of claim 3, wherein the frequency detection module further comprises a delay unit coupled between the data signal and the third flip-flop. The clock recovery circuit of claim 5, wherein the delay unit is configured to form a predetermined delay time for the data signal, the predetermined delay time being substantially equal to one of the second flip-flop and the logic unit. Total delay time. A frequency detecting module is configured to detect a relative relationship between a clock signal and a data signal. The frequency detecting module includes: a first flip-flop, when the clock edge of the data signal is triggered, the The first flip-flop is used to output the voltage level of a first node to a second node; a second flip-flop is used to trigger the clock edge of the clock signal when the clock edge is triggered The voltage level of the second node is reversed and output to the first node; a logic unit, the logic unit determines a voltage level of the first node and a voltage level of the second node, and when the voltage level of the first node and the second node are logically the same, the logic unit is used to: And generating a control signal; and a third flip-flop, when the clock edge of the data signal is triggered, the third flip-flop is configured to output the control signal, thereby increasing a clock frequency of the clock signal. The frequency detecting module of claim 7, wherein the clock edge of the data signal and the clock edge of the clock signal comprise a rising edge or a falling edge (falling edge) ). The frequency detecting module of claim 7, wherein the logic unit comprises an AND gate or an exclusive-OR gate (XOR gate). The frequency detecting module of claim 7, wherein the frequency detecting module further comprises a delay unit coupled between the data signal and the third flip-flop. The frequency detecting module of claim 10, wherein the delay unit is configured to form a predetermined delay time for the data signal, the predetermined delay time being substantially equal to one of the second flip-flop and the logic unit Add a delay time.