TWI728753B - Display panel - Google Patents

Abstract

A display panel including a plurality of pixels, a gate driving circuit and m signal lines. The gate driving circuit is electrically connected to the pixels. Two opposite ends of each of the signal lines is electrically connected to a chip and the gate driving circuit. The chip is adapted to respectively provide m signals to the m signal lines so as to transfer them to the gate driving circuit. A Nth signal line crosses N-1 signal lines. At least one of the cross-line area of at least one crossed place of a signal line is determined by a standard signal characteristic time ratio and a standard cross-line area. Furthermore, another display panel is also provided.

Description

Display panel

The present invention relates to a display panel.

With the development of technology, display panels are widely used in a variety of different applications. Consumers' demand for larger panels and improved display performance is increasing day by day. The panel industry is moving towards larger sizes and ultra-high image quality technologies. The mainstream of the current ultra-high image quality technology is 4K (4K resolution) and 8K (8K resolution) technologies. The 4K technology standard is that the horizontal resolution and vertical resolution on the screen need to reach 4096 pixels and 2160 pixels, respectively, which is the panel used by 4K technology. The total number of pixels is about 8.84 million pixels. On the other hand, the 8K technology standard requires that the horizontal resolution and vertical resolution on the screen reach 7680 pixels and 4320 pixels, respectively. That is, the number of panel pixels used in 8K technology is about 33.14 million pixels.

However, the number of pixels has increased rapidly, and the number of signal traces used to control these pixels has also increased rapidly. The coupling effect between traces and traces will seriously affect the charge and discharge time (or rise time, fall time) of the signal. Time), resulting in serious signal distortion, causing the problem of bright and dark lines, resulting in poor display quality of the existing display panel.

The present invention provides a display panel with good display quality.

N，且M

2。經由M條訊號線中的一標準訊號線傳遞至閘極驅動電路後的訊號為一標準訊號，標準訊號具有一標準訊號特徵時間比，標準訊號線跨設這些訊號線中的一訊號線的跨線面積定義為一標準跨線面積。m條訊號線中的一訊號線的至少一被跨設處的跨線面積由標準訊號特徵時間比例及標準跨線面積來決定，其中標準訊號特徵時間比例Rs定義為：

The display panel in an embodiment of the present invention includes a plurality of pixels, a gate driving circuit, and M signal lines. The gate drive circuit is electrically connected to these pixels. The opposite ends of each signal line are electrically connected to a chip and the gate drive circuit, and the chip is adapted to provide M signals to the M signal lines to be transmitted to the gate drive circuit. One of the M signal lines The Nth signal line spans N-1 signal lines, and the N-1 signal line is located between the Nth signal line and the gate drive circuit, where N and M are both positive integers, and M

N, and M

2. The signal transmitted to the gate drive circuit through a standard signal line among the M signal lines is a standard signal. The standard signal has a characteristic time ratio of the standard signal. The standard signal line straddles the span of one of these signal lines. The line area is defined as a standard cross-line area. The cross-line area of at least one of the m signal lines is determined by the standard signal characteristic time ratio and the standard cross-line area. The standard signal characteristic time ratio Rs is defined as:

Among them, T _G represents the signal characteristic time of the standard signal at the gate drive circuit, and T _S represents the signal characteristic time of the standard signal at the chip.

In an embodiment of the present invention, the area of the N-1 crossovers of the above-mentioned N-th signal line across N-1 signal lines is the same as each other, and the area of the N-1 crossovers is different from the standard crossover area .

In an embodiment of the present invention, the above-mentioned Nth signal line is set across N-1 At least a part of the N-1 cross-line areas of the signal lines gradually changes from a direction away from the gate driving circuit to close to the gate driving circuit, and at least a part of the N-1 cross-line areas is different from the standard cross-line area.

In an embodiment of the present invention, the number of at least one of the above-mentioned signal lines is multiple, and one of these is referred to as a first. Except for the first straddled place, the other straddled places are called at least one second straddled place. A first crossover area of the first crossover is different from at least one second crossover area of at least one second crossover, and at least one second crossover area is equal to the standard crossover area.

In an embodiment of the present invention, the number of at least one crossed portion of one of the above-mentioned signal lines is multiple, and the cross-line area of these crossed portions is all the same.

The display panel in an embodiment of the present invention includes a plurality of pixels, a gate driving circuit, a first signal line, a second signal line, and a third signal line. The opposite ends of each of the first to third signal lines are electrically connected to a chip and the gate drive circuit, and the chip is suitable for providing the first signal, the second signal and the third signal to the first signal line and the second signal line, respectively And the third signal line to be transmitted to the gate drive circuit. The first signal line straddles the second signal line and the third signal line, and the second signal line and the third signal line are located between the first signal line and the gate drive circuit. The second signal line straddles the third signal line, and the third signal line is located between the second signal line and the gate drive circuit. The first signal line is a standard signal, and the first signal is a standard signal. The standard signal has a standard signal characteristic time ratio. The standard signal line span is defined as a standard span. Line area. The cross-line area of at least one of the second signal line and the third signal line is determined by the standard signal characteristic time ratio and the standard cross-line area. The standard signal characteristic time ratio Rs is defined as:

Among them, TG represents the signal characteristic time of the standard signal at the gate drive circuit, and TS represents the signal characteristic time of the standard signal at the chip.

In an embodiment of the present invention, the above-mentioned display panel further includes a fourth signal line. The opposite ends of the fourth signal line are electrically connected with the chip and the gate drive circuit. The chip is more suitable for providing a fourth signal to the fourth signal line for transmission to the gate driving circuit. The first signal line spans the second signal line, the third signal line and the fourth signal line, and the second signal line, the third signal line and the fourth signal line are located between the first signal line and the gate drive circuit. The second signal line straddles the third signal line and the fourth signal line, and the third signal line and the fourth signal line are located between the second signal line and the gate drive circuit. The third signal line straddles the fourth signal line, and the fourth signal line is located between the third signal line and the gate drive circuit.

In an embodiment of the present invention, one of the above-mentioned first to fourth signal lines straddles the corresponding signal line and all the cross-line areas are the same as each other and different from the standard cross-line area.

In an embodiment of the present invention, one of the above-mentioned first to fourth signal lines straddles at least a portion of the corresponding signal line. The cross-line area gradually changes from a direction away from the gate drive circuit to close to the gate drive circuit. , And at least part of the cross-line area Different from the standard cross-line area.

In an embodiment of the present invention, the number of at least one of the above-mentioned fourth signal line to the first signal line is multiple, and one of these is called a first signal line. A place to be straddled, except for the first place to be straddled, is called at least one second place to be straddled. A first crossover area of the first crossover is different from at least one second crossover area of the at least one second crossover, and at least one second crossover area is equal to the standard crossover area.

In an embodiment of the present invention, the number of at least one of the above-mentioned fourth signal line to the first signal line is multiple, and the area of the crossover is the same.

Based on the above, in the display panel of the embodiment of the present invention, the geometric design of the signal line between the chip and the gate drive circuit takes into account the standard signal characteristic time ratio and the standard cross-line area, etc., so that the signal line The signal characteristic time ratio is consistent with the standard signal characteristic time ratio. Therefore, when the chip transmits signals to the gate drive circuit through these signal lines, these signals are less likely to be distorted. Therefore, the display panel is less prone to the problem of bright and dark lines and has good performance. Display quality.

1: Reference display panel

100: display panel

110: Gate drive circuit

120, 1216~1201, 1216’~1201’, 1216a~1201a: signal line

122(16)~122(1), 122’(16)~122’(1), 122a(16)~122a(1): vertical line segment

124(16)~122(1), 124’(16)~124’(1), 124a(16)~124a(1): horizontal line segment

126, 126’: turning point

As: Standard cross-line area

A1: The cross-line area of the first cross-over

A2: The cross-line area of the second cross-over

AA: active area

C: chip

EA: Border area

GOA: GOA area

P: pixel

PD: vertical direction

HD: horizontal direction

S1~S16: Signal

SR: signal receiver

SO: signal output terminal

t: signal delay time

T: period

FIG. 1A is a schematic top view of a display panel according to an embodiment of the invention.

FIG. 1B is a partial enlarged schematic diagram of area A in FIG. 1A.

Figure 2 is a schematic diagram of multiple sets of signals provided by the chip.

FIG. 3A is a schematic top view of the reference display panel.

FIG. 3B is a table of the relationship between the signal characteristic time and the coupling coefficient information of the reference display panel.

4 is a table showing the relationship between the signal characteristic time and the cross-line area of the display panel in the embodiment of FIG. 1B.

FIG. 5 is a partial enlarged schematic diagram of another embodiment of the area A in FIG. 1A.

6 is a table showing the relationship between the signal characteristic time and the cross-line area of the display panel in the embodiment of FIG. 5.

FIG. 1A is a schematic top view of a display panel according to an embodiment of the invention. FIG. 1B is a partial enlarged schematic diagram of area A in FIG. 1A. Figure 2 is a schematic diagram of multiple sets of signals provided by the chip.

1A and 1B, the display panel 100 has an active area AA, a GOA area GOA, and a frame area EA. The display panel 100 includes a plurality of pixels P, a gate driving circuit 110 and M signal lines 120. In the following paragraphs, the above-mentioned components and the arrangement of the components will be described in detail.

These pixels P are arranged in the active area AA. A pixel circuit (not shown) is provided in the active area AA to electrically connect the pixels P and the gate driving circuit 110. Therefore, these pixels P can receive the signal from the gate drive circuit 110 and display a display Picture.

The gate driving circuit 110 is disposed in the GOA area GOA, and is electrically connected to the pixels P in the active area AA and the signal lines 120 in the frame area EA. The display panel 100 uses GOA (Gate on Array) technology, that is, the gate drive circuit 110 and these pixels P are directly integrated on an active device array substrate (not shown), and a narrow frame can be realized. Technical effect.

M signal lines 120 are arranged in the frame area EA, and each signal line 120 has a signal receiving terminal SR and a signal output terminal SO (only one set is marked) opposite to each other. The signal receiving terminal SR is electrically connected to the chip C. The signal output terminal SO is electrically connected to the gate drive circuit 110. The signal lines 120 can be divided into multiple periods T, where each period T includes, for example, 16 signal lines, but the present invention is not limited to the number of signal lines in the period T. The so-called signal lines 120 can be divided into a plurality of periods T means that each specific number (for example, 16) of the signal lines 120 has a specific arrangement and line width design method, and other periods T also have the same For a specific arrangement and line width design method, FIG. 1B shows a period T as an example. In the following paragraphs, the signal line 120 in a period T is discussed.

N，且M

2。舉例來說，當N=M=16時，第16條訊號線1216的橫線段124(16)跨設15(N-1=16-1)條訊號線的縱線段122(第15條至第1條訊號線1215~1201)而具有15個跨設處。當M>N=15時第15條訊號線1215跨設14(N-1=15-1)條訊號線而具有14個跨設處，其他以此類推，其中因縱線段122與橫線段124彼此位於不同層，故跨設處亦可被視為一訊號線的縱線段122與其他訊號線的橫線段124的重疊處。而當M>N=1時，第1條訊號線1201跨設0(N-1=1-1)條訊號線，也就是第1條訊號線1201沒有跨設訊號線，故沒有跨設處。 In detail, each signal line 120 includes a vertical line segment 122 and a horizontal line segment 124 located in different layers from each other, wherein the vertical line segment 122 is in a lower layer, and the horizontal line segment 124 is in a higher layer. The vertical line segment 122 and the horizontal line segment 124 intersect at a turning point 126, where the turning point 126 is, for example, a conductive hole (via hole, or via hole), and the vertical line segment 122 and the horizontal line segment 124 are connected to each other by the turning point 126. The vertical line segment 122, for example, extends in the vertical direction PD, and the horizontal line segment 124, for example, extends in the horizontal direction HD, but not limited to this. In addition, in the direction away from the gate drive circuit 110 to close to the gate drive circuit 110, according to the distance from the vertical line segment 122 of the different signal lines 120 to the gate drive circuit 110, one of these signal lines 120 The vertical line segment 122 that is the farthest from the gate drive circuit 110 is called the 16th signal line 1216, and one of the signal lines 120 has the vertical line section 122 that is closest to the gate drive circuit 110 is called the first signal line 1201. Others and so on, that is, these signal lines 120 are called the 16th signal line 1216 (which can be regarded as the first signal line) and the 15th signal line according to the different distances from the vertical line segment 122 to the gate drive circuit 110. Signal line 1215 (can be regarded as the second signal line), the 14th signal line (can be regarded as the third signal line), the 13th signal line (can be regarded as the fourth signal line),... 1 signal line 1201. One of the N-th signal lines in the 16(M) lines spans N-1 signal lines, and N-1 signal lines are located between the N-th signal line and the gate drive circuit 110, where N and M are both Is a positive integer, M

N, and M

2. For example, when N=M=16, the horizontal line segment 124(16) of the 16th signal line 1216 straddles the vertical line segment 122 (the 15th to the 15th) of the 15th signal line (N-1=16-1). 1 signal line 1215~1201) and 15 crossover locations. When M>N=15, the 15th signal line 1215 spans 14 (N-1=15-1) signal lines and has 14 crossing locations, and the rest can be deduced by analogy. Among them, the vertical line segment 122 and the horizontal line segment 124 They are located on different layers, so the crossover can also be regarded as the overlap of the vertical line segment 122 of one signal line and the horizontal line segment 124 of other signal lines. When M>N=1, the first signal line 1201 is crossed with 0 (N-1=1-1) signal lines, that is, the first signal line 1201 is not crossed with a signal line, so there is no crossover location .

It should be noted that the number 122 (16) in Figure 1B represents: Article 16 The vertical line segment 122 of the signal line 1216, number 124 (16) represents: the horizontal line segment 124 of the 16th signal line 1216, and so on.

The chip C is suitable for providing a plurality of signals S1 to S16 to the signal line 120 in a period T, respectively. In detail, the chip C provides signals S16 to the 16th signal line 1216 to be transmitted to the gate driving circuit 110, provides signals S15 to the 15th signal line 1215 to be transmitted to the gate driving circuit 110, and so on. As shown in FIG. 2, the signals S1 to S16 are, for example, a group of two identical signals, and there is a signal delay time t (unit: second) between groups. For example, the signals S16 and S15 have the same amplitude and waveform as each other, and the signals S14 and S13 have the same amplitude and waveform as each other, but the signal start time difference between the two signals is t seconds, that is, this group of signals S16 and S15 The start time (or end time) of S14 and S13 is t seconds faster than the start time (or end time) of the next set of signals S14 and S13. The start time (or end time) of the next set of signals S12 and S11 is t seconds faster than the start time (or end time) of the next set of signals S10 and S9, and so on.

FIG. 3A is a schematic top view of the reference display panel. FIG. 3B is a table of the relationship between the signal characteristic time and the coupling coefficient information of the reference display panel. 4 is a table showing the relationship between the signal characteristic time and the cross-line area of the display panel in the embodiment of FIG. 1B.

In order to explain the design method of the cross-line area of each signal line in FIG. 1B, in the following paragraphs, the design method of the cross-line area of the display panel 100 of the present embodiment will be described in detail in the following paragraphs. And technical effects.

Please refer to FIG. 3A first. The reference display panel 1 of FIG. 3A is substantially similar to the display panel 100 of FIG. 1B. The main difference is that the cross-line widths of the signal lines 120' are substantially the same as each other. Therefore, the cross-line area of all these cross-over locations is due to the cross-line width Degrees are substantially the same relationship with each other, so they are all substantially the same.

T_G代表為訊號在閘極驅動電路110處的訊號特徵時間，T_S代表為訊號在晶片C處的訊號特徵時間。為求方便說明，以下的段落皆以下降時間當作是訊號的訊號特徵時間。 Please refer to FIG. 3B again. The upper horizontal row of FIG. 3B represents the vertical line segments of different signal lines, and the leftmost vertical row represents the horizontal line segments of different signal lines. The multiple values between the upper horizontal row and the leftmost vertical row are the coupling coefficient information, and the ratio R in the rightmost vertical row represents the signal characteristic time ratio R, where the signal characteristic time can be the rise time of the signal (rise time). ) Or the fall time of the signal. The rise time is defined as the time required for the signal to rise from 10% of the steady-state value to 90% of the steady-state value. The fall time is defined as the signal from 90% of the steady-state value. The time required for% to drop to 10% of the steady-state value. The signal characteristic time ratio R is defined as follows:

T _G represents the signal characteristic time of the signal at the gate drive circuit 110, and T _S represents the signal characteristic time of the signal at the chip C. For the convenience of explanation, the following paragraphs all take the fall time as the signal characteristic time of the signal.

Please refer to FIG. 3A again. The reason for the coupling coefficient information is: during the transmission of the above-mentioned signals S16~S1, the distance between the signal lines 120' is not very far, and there is a coupling phenomenon between each other. Therefore, when a specific signal is transmitted to the gate driving circuit 110 along the corresponding signal line, it will be affected by other signal lines 120'. Please refer to Figure 3A at the same time. Take the signal S16 as an example. The signal S16 will be transmitted from the vertical line segment 122' (16) of the 16th signal line 1216' to the turning point 126' along the vertical direction PD, and then turning to the horizontal direction HD. 15 crossing locations are provided to be transmitted to the gate driving circuit 110. Please refer to Fig. 3B. For example, the information value of the coupling coefficient corresponding to the labels 122’14 and 124’16 is 98.17%, which means that the 14th signal line 1214’ is blocked by the 16th signal line. The horizontal line segment 124' (16) of the signal line 1216' spans and there is a coupling relationship between the two, and the above-mentioned coupling coefficient information value is the degree of influence of the coupling relationship on the signal fall time. Therefore, after the signal S16 has passed through 15 spans, the degree of its influence is: the horizontal row marked 124'(16) except for the information value of the self-coupling coefficient (namely 122'(16), 124'(16) ) The product of all coupling coefficient information values except the corresponding number coupling coefficient information value 100.00%), namely: 100.00%*98.17%*98.17%*100.00%*100.00%*99.82%*99.82%*100.00%*100.00%*100.00 %*100.00%*106.71%*106.71%*109.32%*109.32%=130.68%. Among them, the signal characteristic time ratio R is 130.68%, which means that if the fall time of the signal S16 at the chip C is f, the signal at the gate drive circuit 110 after the 16th signal line 1216 is transmitted The fall time of S16 is f*130.68%.

In addition, for a complete description, take the signal S14 as an example. 3A, the signal S14 will be transmitted from the longitudinal line segment 122 of the 14th signal line 1214' to the turning point 126 along the vertical direction PD, and then turning to the horizontal direction HD to straddle 13 spanning places and be transmitted to the gate drive Circuit 110. However, the 16th and 15th signal lines 1216' and 1215' on the left side of the 14th signal line 1214' will also have a coupling effect on the 14th signal line 1214'. Therefore, the extent to which the signal S14 is affected is: the product of all the coupling coefficient information values in the row marked 124'(14) except for the self coupling coefficient information, namely: 102.14%*102.14%*100.00%*98.17%* 98.17%*100.00%*1 00.00%*99.82%*99.82%*100.00%*100.00%*100.00%*100.00%*106.71%*106.71%=114.08%. Among them, the signal characteristic time ratio R is 114.08%, which means that if the fall time of the signal S14 at the chip C is f', the signal S14 is transmitted by the 14th signal line 1214' in the gate drive circuit 110 The fall time of the signal S14 at the position is f'*114.08%.

In view of the above, it can be seen from the ratio R in the rightmost column of FIG. 3B that the signal fall times after these signals S16~S1 are transmitted to the gate drive circuit 110 are more or less different, and the signal characteristic time ratio R is, for example Within the range of 130.68% to 114.30%, the standard deviation of the signal characteristic time ratio R is, for example, 9.66%, which leads to the problem that the reference display panel 1 has bright and dark lines.

In contrast, the cross-line area of the signal line in FIG. 1B is designed according to the following design principles.

In order to eliminate the problem of bright and dark lines, the main goal of the design of the signal line 120 of this embodiment is to make the signal characteristic time ratio R affected by the fall time of all the signals S16~S1 consistent. For example, this In the embodiment, the 16th signal line 1216 of FIG. 1B is used as the standard signal line, and the signal S16 transmitted by the standard signal line is used as the standard signal. The signal characteristic time ratio of the standard signal S16 is called the standard signal characteristic time ratio Rs. The signal characteristic time ratio corresponding to the 16 signal lines 1216 is 130.68%. Furthermore, the cross-line area of a signal line where the 16th signal line 1216 spans these signal lines 120 is defined as a standard cross-line area As. In this embodiment, for example, the 16th signal line 1216 is crossed over the first 15 signal lines 1215 The cross-line area is defined as the standard cross-line area As. In other words, the design goal of the signal line 120 of this embodiment is to make the signal characteristic time ratio R of the other signal lines 120 consistent with the standard signal characteristic time ratio Rs.

It should be noted that the above selection is only an example for the convenience of description. In other embodiments, other signal lines can be selected as standard signal lines, and other cross-line areas can also be selected as standard cross-line areas. The present invention does not Limited by this.

×…×

)相乘後，要等於標準訊號特徵時間比例Rs。即，除了標準訊號線(即第16條訊號線1216)外的任一訊號線120符合以下公式(2)：

其中，Rp代表的是：尚調整跨線面積前的訊號線的訊號特徵時間比，A₁~A_m分別代表的是調整後訊號線被跨設的m個跨設處的跨線面積。A_S代表的是標準訊號線的標準跨線面積。於以下的段落中會搭配圖3B及圖4來說明上述公式(2)的主要用法。 Next, the main factor affected by the signal characteristic time ratio R is the area where the signal line is crossed. That is to say, the signal characteristic time ratio Rp of the signal line before adjusting the crossover area needs to be compared with all the crossed settings after the adjustment. Cross-line area/standard cross-line area (

×...×

After multiplying, it should be equal to the standard signal characteristic time ratio Rs. That is, any signal line 120 except the standard signal line (that is, the 16th signal line 1216) conforms to the following formula (2):

Among them, Rp represents: the signal characteristic time ratio of the signal line before the cross-line area _{is adjusted, and A 1} to A _m respectively represent the cross-line area of m cross-over locations where the signal line is crossed after the adjustment. A _S represents the standard cross-line area of a standard signal line. In the following paragraphs, Figure 3B and Figure 4 will be used to illustrate the main usage of the above formula (2).

First, referring to FIG. 1B, since the 16th signal line 1216 is a standard signal line, the line width of the 16th signal line 1216 is substantially the same as the line width of the 16th signal line 1216' in FIG. 3A.

Next, please refer to FIG. 4, because in this embodiment, the cross-line area of the 16th signal line 1216 across the 15th signal line 1215 is defined as the standard cross-line area As, also This is the value corresponding to the vertical line segment 122 (15) of the 15th signal line 1215 and the horizontal line segment 124 (16) of the 16th signal line 1216 in FIG. 4, where the standard cross-line area As is set to 1.00.

故，調整後的第15條訊號線1215的一被跨設處的跨線面積A₁要等於130.68%/130.68%=1.00，即圖4中第15條訊號線1215的縱線段122(15)與第16條訊號線1216的橫線段124(16)所對應的數值1.00。 Next, referring to Figures 1B and 4, for the 15th signal line 1215, the vertical line segment 122 (15) of the 15th signal line 1215 is spanned by the horizontal line segment 124 (16) of the 16th signal line 1216, and There is a crossover. The signal characteristic time ratio R of the 15th signal line 1215' before adjustment is just 130.68%. After substituting the above formula (2), therefore, the adjusted cross-line area A ₁ of the 15th signal line 1215 should conform to the following equation:

_{Therefore, the adjusted cross-line area A 1} of the 15th signal line 1215 where it is crossed should be equal to 130.68%/130.68%=1.00, which is the vertical line segment 122 (15) of the 15th signal line 1215 in Figure 4 The value 1.00 corresponding to the horizontal line segment 124 (16) of the 16th signal line 1216.

故，調整後的第14條訊號線1214的兩個被跨設處的兩個跨線面 積A₁、A₂的相乘積要等於130.68%/114.08%=1.15。於圖4中，令A₁的跨線面積與標準跨線面積As相同，即為1.00，因此A₂處的跨線面積則為1.15。即圖4中第14條訊號線1214的縱線段122(14)與第16條訊號線1216的橫線段124(16)所對應的數值1.00以及第14條訊號線1214的縱線段122(14)與第15條訊號線1215的橫線段124(15)所對應的數值1.15。 Next, referring to Figures 1B and 4, for the 14th signal line 1214, the vertical line segment 122 (14) of the 14th signal line 1214 is replaced by the horizontal line segment 124 ( 16), 124(15) are straddled, and there are two straddled places A ₁ and A ₂ . In addition, the signal characteristic time ratio R of the 14th signal line 1214' before adjustment is 114.08%. _{Therefore, the two cross-line areas A 1} and A ₂ at the two cross-over locations of the adjusted 14th signal line 1214 should conform to the following equation:

_{Therefore, the product of the two crossover areas A 1} and A ₂ at the two crossover locations of the adjusted 14th signal line 1214 is equal to 130.68%/114.08%=1.15. In Figure 4, let _{the cross-line area of A 1 be} the same as the standard cross-line area As, which is 1.00, so the cross-line area at _{A 2 is 1.15.} That is, the vertical line segment 122 (14) of the 14th signal line 1214 in Figure 4 and the horizontal line segment 124 (16) of the 16th signal line 1216 correspond to the value 1.00 and the vertical line segment 122 (14) of the 14th signal line 1214. The value corresponding to the horizontal line segment 124 (15) of the 15th signal line 1215 is 1.15.

Then, the cross-over area of other signal lines is adjusted according to the above-mentioned method, which will not be repeated here. Accordingly, the relationship table between the signal characteristic time and the cross-line area as shown in FIG. 4 can be obtained.

In view of the above, in the vertical line segments 122(16)~122(1) of the 16 signal lines 1216~1201, the number of places where some of the signal lines 1215~1201 are crossed is one or more. For the convenience of explanation, taking the 14th signal line 1214 as an example, the longitudinal line segment 122 (14) of the 14th signal line 1214 is spanned by the 16th and 15th signal lines 1216 and 1215, and has two spanning devices. Among them, the crossing location spanned by the 15th signal line 1215 is called the first spanned location, and the spanning location spanned by the 16th signal line 1216 is called the second spanned location. The area of the first crossover line at the crossed location (see Figure 4, value 1.15) is different from the area of the second crossover line at the second crossed location (see Figure 4, value 1.00), and so on for other signal lines.

In the 14th signal line 1214, because _{the product value of the first crossover area A 1} and the second crossover area A ₂ needs to be equal to 1.15, but in the design of Figure 1B, the first crossover area A ₁ is set to 1.00 , And the second cross-line area A ₂ is designed to be 1.15. That is to say, in this embodiment, the adjustment of the line width of the 14th signal line 1214 is concentrated at some places where it is crossed. Taking the 6th signal line 1206 as an example again, in this embodiment, the adjustment of the line width of the 6th signal line 1206 is concentrated on the two straddling positions spanned by the 15th and 7th signal lines 1215 and 1207 (see The two circled locations in Fig. 1B and Fig. 4, 1.15 and 0.90 respectively), and the other crossing locations are not adjusted. The other signal lines can be deduced by analogy.

It can be seen from the above that, since the geometric design of the signal line 120 of this embodiment takes into account the standard signal characteristic time ratio Rs and the standard cross-line area _AS and other parameters, the signal characteristic time ratio R of each signal line can be compared with the standard signal characteristic time. The ratio Rs is the same. Therefore, when the chip C transmits signals to the gate drive circuit 110 via these signal lines 120, the signals S16~S1 are less likely to be distorted. Therefore, the display panel 100 of this embodiment is less prone to the problem of bright and dark lines. Has good display quality.

From another point of view, referring to FIG. 1B and FIG. 4, the area of the N-1 crossovers of the N-1 signal lines across the N-th signal line of the signal lines 120 are the same as each other, and N-1 a line across the area from the standard crossover area A _S. In detail, in this embodiment, N is 15, 7, or 3. In other words, the area of the 14 crossovers of the 15th signal line 1215 across the 14 signal lines is the same (for example, the area of the 14 crossovers are all 1.15), and the 7th signal line 1207 crosses 6 of the 6 signal lines. The areas of the two crossovers are the same (for example, the area of the six crossovers are all 0.90), and the area of the two crossovers of the two signal lines across the third signal line 1203 is the same as each other (for example, the areas of the two crossovers are both 0.99). In this embodiment, by designing the cross-line area to be the same as each other, the signal line is easier to manufacture.

It must be noted here that the following embodiments follow part of the content of the previous embodiments, and the description of the same technical content is omitted, and the same component names can be referred to Considering part of the content of the foregoing embodiments, the following embodiments will not be repeated.

FIG. 5 is a partial enlarged schematic diagram of another embodiment of the area A in FIG. 1A. 6 is a table showing the relationship between the signal characteristic time and the cross-line area of the display panel in the embodiment of FIG. 5.

於以下的段落中會搭配圖3B、圖5及圖6來說明上述公式(2)的主要用法。基本上，圖5及圖6的設計標準與圖1A與圖4的設計標準相同，於此不再贅述。 Please refer to Figures 5 and 6, basically the design concept of these signal lines 120a in Figure 5 is similar to the design concept of Figure 1B, that is, any signal line 120 other than the standard signal line (that is, the 16th signal line 1216a) conforms to Formula (2):

In the following paragraphs, Figure 3B, Figure 5 and Figure 6 will be used to illustrate the main usage of the above formula (2). Basically, the design standards of FIG. 5 and FIG. 6 are the same as the design standards of FIG. 1A and FIG. 4, and will not be repeated here.

Please refer to Figures 5 and 6, because in this embodiment, the cross-line area of the 16th signal line 1216a across the 15th signal line 1215a is defined as the standard cross-line area As, which is the 15th signal in Figure 5 The value corresponding to the vertical line segment 122a (15) of the line 1215a and the horizontal line segment 124a (16) of the 16th signal line 1216a, where the standard cross-line area As is set to 1.00.

故，調整後的第15條訊號線1215a的一被跨設處的跨線面積A₁要等於130.68%/130.68%=1.00，即圖6中第15條訊號線1215a的縱線段122a(15)與第16條訊號線1216a的橫線段124a(16)所對應的數值。 Next, referring to Figure 5, for the 15th signal line 1215a, because the vertical line segment 122a (15) of the 15th signal line 1215a is spanned by the horizontal line segment 124a (16) of the 16th signal line 1216a, there is a span Set up office. Please refer to FIG. 6, the signal characteristic time ratio R of the 15th signal line 1215' before adjustment is just 130.68%. _{Therefore, the adjusted cross-line area A 1} of a crossed position of the 15th signal line 1215a should conform to the following equation:

_{Therefore, the adjusted cross-line area A 1} of a crossed area of the 15th signal line 1215a should be equal to 130.68%/130.68%=1.00, that is, the vertical line segment 122a (15) of the 15th signal line 1215a in Figure 6 The value corresponding to the horizontal line segment 124a (16) of the 16th signal line 1216a.

故，調整後的第14條訊號線1214a的兩個被跨設處的兩個跨線面積A₁、A₂的相乘積要等於130.68%/114.08%=1.15。於圖6中，是將1.15開二次方根，而得到A₁、A₂分別應為1.07、1.07。即圖6中第14條訊號線1214a的縱線段122a(14)與第16條訊號線1216a的橫線段124a(16)所對應的數值1.07以及第14條訊號線1214a的縱線段122a(14)與第15條訊號線1215a的橫線段124a(15)所對應的數值1.07。 Next, referring to Figure 5, for the 14th signal line 1214a, the vertical line segment 122 (14) of the 14th signal line 1214a is replaced by the horizontal line segment 124a (16) of the 16th and 15th signal lines 1216a and 1215a. 124a(15) straddles, and has two straddled locations A ₁ and A ₂ . In addition, the signal characteristic time ratio R of the 14th signal line 1214' before adjustment is 114.08%. _{Therefore, the two cross-line areas A 1} and A ₂ at the two cross-over locations of the adjusted 14th signal line 1214 should conform to the following equation:

_{Therefore, the product of the two crossover areas A 1} and A ₂ at the two crossover locations of the adjusted 14th signal line 1214a is equal to 130.68%/114.08%=1.15. In Figure 6, the square root of 1.15 is taken, and A ₁ and A ₂ should be 1.07 and 1.07 respectively. That is, the vertical line segment 122a (14) of the 14th signal line 1214a in Figure 6 and the horizontal line segment 124a (16) of the 16th signal line 1216a correspond to the value 1.07, and the vertical line segment 122a (14) of the 14th signal line 1214a The value corresponding to the horizontal line segment 124a (15) of the 15th signal line 1215a is 1.07.

Then, the cross-over area of other signal lines is adjusted according to the above-mentioned method, which will not be repeated here. Accordingly, the relationship table between the signal characteristic time and the cross-line area as shown in FIG. 6 can be obtained.

In view of the above, in the vertical line segments 122a(16)-122a(1) of the 16 signal lines 1216a-1201a, the number of parts where the signal lines 1215a-1201a are straddled is one or more. For the convenience of explanation, taking the 14th signal line 1214a as an example, the longitudinal line segment 122a (14) of the 14th signal line 1214a is spanned by the 16th and 15th signal lines 1216a, 1215a, and has two spanning devices. Place. The cross-line areas of the two cross-over locations of the fourteenth signal line 1214a are the same, and are, for example, 1.07 and 1.07, respectively.

故，調整後的第13條訊號線1213a的三個被跨設處的兩個跨線面積A₁、A₂、A₃的相乘積要等於130.68%/114.08%=1.15。於圖6中，是將1.15開三次方根，而得到A₁、A₂、A₃分別應為1.05、1.05、1.05。即圖6中第13條訊號線1213a的縱線段122a(13)與第16條訊號線1216a的橫線段124a(16)所對應的數值1.05、第13條訊號線1213a的縱線段122a(13)與第15條訊號線1215a的橫線段124a(15)所對應的數值1.05，以及第13條訊號線1213a的縱線段122a(13)與第15條訊號線1215a的橫線段124a(15)所對應的數值1.05。換言之，在本實施例採取的訊號線幾何設計方式是：幾何平 均地調整用來覆蓋第13條訊號線1213a的三個被跨設處的訊號線(即第16條、第15條、第14條訊號線1216a、1215a、1214a)的跨線面積A₁、A₂、A₃。 In the 14th signal line 1214a, the product value of the cross-line area where these cross-overs are set needs to be equal to 1.15. The signal line geometric design method adopted in this embodiment is: geometrically adjust the two signal lines (that is, the 16th and 15th signal lines 1216a, 1215a) that are used to cover the 14th signal line 1214a. ). Take the thirteenth signal line 1213a as an example, because the product value of the cross-line area of these crossed locations must conform to the following equation:

_{Therefore, the product of the two cross-line areas A 1} , A ₂ , and A ₃ at the three cross-over locations of the adjusted thirteenth signal line 1213a is equal to 130.68%/114.08%=1.15. In Fig. 6, the square root of 1.15 is taken, and A ₁ , A ₂ , and A ₃ should be 1.05, 1.05, and 1.05, respectively. That is, the vertical line segment 122a (13) of the 13th signal line 1213a in Figure 6 and the horizontal line segment 124a (16) of the 16th signal line 1216a correspond to the value 1.05, and the vertical line segment 122a (13) of the 13th signal line 1213a The value 1.05 corresponding to the horizontal line segment 124a (15) of the 15th signal line 1215a, and the vertical line segment 122a (13) of the 13th signal line 1213a and the horizontal line segment 124a (15) of the 15th signal line 1215a The value is 1.05. In other words, the signal line geometric design method adopted in this embodiment is: geometrically evenly adjust the three signal lines (that is, the sixteenth, fifteenth, and fourteenth) that are used to cover the thirteenth signal line 1213a. _{The cross-line areas A 1} , A ₂ , and A ₃ of the signal lines 1216a, 1215a, 1214a).

From another point of view, please refer to FIG. 5 and FIG. 6, the N-th signal line of these signal lines 120 straddles at least a part of the N-1 cross-line area of the N-1 signal lines away from the gate. across the line area of the driving circuit 110 to close the gate driving circuit 110, the direction of the gradient, the N-1 and at least a portion different from the standard crossover area a _S. In detail, in this embodiment, N is 16-8. Taking the 16th signal line 1216a as an example, the 16th signal line 1216a spans 8 of the 15 cross-line areas of the 15 signal lines (that is, the 8 cross-line areas corresponding to the horizontal line segment 124a (16) in Figure 6). The numbers of the vertical line segments 122a (14) to 122a (7)) gradually change from the direction away from the gate drive circuit 110 to the direction close to the gate drive circuit 110, and the rest can be deduced by analogy.

It should be noted that the design of the cross-line area in FIGS. 5 and 6 is only an example, and the present invention is not limited to the design of FIGS. 5 and 6. In other embodiments, it can also focus on 7 to 2 cross-line areas, or 9 to 15 cross-line areas, as long as the area change design of the cross-line area conforms to the above formula (2) , Are all within the scope of the present invention, and the present invention is not limited thereto.

To sum up, in the display panel of the embodiment of the present invention, the geometric design of the signal line between the chip and the gate drive circuit takes into account the standard signal characteristic time ratio and the standard cross-line area and other parameters, so that each signal The signal characteristic time ratio of the line is consistent with the standard signal characteristic time ratio. Therefore, when the chip transmits signals to the gate drive circuit through these signal lines, these signals are less likely to be distorted, so the display panel is more It is not easy to have the problem of bright and dark lines and has good display quality.

100: display panel

110: Gate drive circuit

120, 1216~1201: signal line

122(16)~122(1): vertical line segment

124(16)~122(1): horizontal line segment

126: Turning Point

As: Standard cross-line area

A1: The cross-line area of the first cross-over

A2: The cross-line area of the second cross-over

GOA: GOA area

PD: vertical direction

HD: horizontal direction

SR: signal receiver

SO: signal output terminal

T: period

Claims (11)

A display panel includes: a plurality of pixels; a gate drive circuit electrically connected to the pixels; and M signal lines, the opposite ends of each signal line are connected to a chip and the gate drive circuit Are electrically connected, and the chip is suitable for providing M signals to the M signal lines to be transmitted to the gate drive circuit, wherein an Nth signal line in the M signal lines spans N-1 Signal line, and the N-1 signal lines are located between the Nth signal line and the gate drive circuit, where N and M are both positive integers, M≥N, and M≥2, where, through the The signal after a standard signal line in the M signal lines is transmitted to the gate drive circuit is a standard signal, the standard signal has a standard signal characteristic time ratio, and the standard signal line straddles one of the signal lines The cross-line area of the signal line is defined as a standard cross-line area, where the cross-line area of at least one of the m signal lines where the signal line is crossed is determined by the standard signal characteristic time ratio and the standard cross-line area. It is determined by the line area, where the characteristic time ratio Rs of the standard signal is defined as:

=Rs where T _G represents the signal characteristic time of the standard signal at the gate drive circuit, and T _S represents the signal characteristic time of the standard signal at the chip. The display panel as described in item 1 of the scope of patent application, wherein: The area of the N-1 crossovers of the N-1 signal lines of the Nth signal line is the same as each other, and the area of the N-1 crossovers is different from the standard crossover area. The display panel as described in item 1 of the scope of patent application, wherein: At least a part of the N-1 crossover area of the N-th signal line across N-1 signal lines gradually changes from a direction away from the gate drive circuit to a direction close to the gate drive circuit, and the N-1 The at least a portion of the cross-line area is different from the standard cross-line area. The display panel as described in item 1 of the scope of patent application, wherein: The number of the at least one crossed location for one of the signal lines is multiple, and one of the crossed locations is called a first crossed location, except for the first crossed location The other crossed locations are called at least one second crossed location, Wherein, a first crossover area of the first crossover is different from at least one second crossover area of the at least one second crossover, and the at least one second crossover area is equal to the standard crossover area area. The display panel described in item 2 of the scope of patent application, wherein: The number of the at least one crossed portion of one of the signal lines is multiple, and the cross-line area of the crossed portions is the same. A display panel includes: a plurality of pixels; a gate drive circuit electrically connected to the pixels; a first signal line; a second signal line; and a third signal line, wherein each of the first signal lines The opposite ends of one to the third signal line are electrically connected to a chip and the gate drive circuit, and the chip is adapted to provide a first signal, a second signal and a third signal to the first signal line, respectively , The second signal line and the third signal line are transmitted to the gate drive circuit, wherein the first signal line straddles the second signal line and the third signal line, the second signal line and the third signal line The three signal line is located between the first signal line and the gate drive circuit, the second signal line straddles the third signal line, and the third signal line is located between the second signal line and the gate drive circuit Among them, the first signal line is used as a standard signal, and the first signal is a standard signal, the standard signal has a standard signal characteristic time ratio, and the standard signal line spans one of the signal lines. The cross-line area of a line is defined as a standard cross-line area, where the cross-line area of at least one of the second signal line and the third signal line is determined by the standard signal characteristic time ratio and the standard cross-line area To determine, where the standard signal characteristic time ratio Rs is defined as:

=Rs where T _G represents the signal characteristic time of the standard signal at the gate drive circuit, and T _S represents the signal characteristic time of the standard signal at the chip. For example, the display panel described in item 6 of the scope of patent application further includes a fourth signal line. The opposite ends of the fourth signal line are electrically connected to the chip and the gate drive circuit. The chip is more suitable for providing a The fourth signal to the fourth signal line to be transmitted to the gate drive circuit, Wherein, the first signal line spans the second signal line, the third signal line, and the fourth signal line, and the second signal line, the third signal line, and the fourth signal line are located on the first signal line And the gate drive circuit, The second signal line spans the third signal line and the fourth signal line, and the third signal line and the fourth signal line are located between the second signal line and the gate drive circuit, The third signal line straddles the fourth signal line, and the fourth signal line is located between the third signal line and the gate drive circuit. According to the display panel described in claim 7, wherein, one of the first to the fourth signal lines straddles the corresponding signal line and all cross-line areas are the same as each other and different from the standard cross-line area. The display panel according to claim 7, wherein the cross-line area of at least a part of one of the first to fourth signal lines straddling the corresponding signal line ranges from being far away from the gate drive circuit to close to The direction of the gate driving circuit is gradually changed, and the cross-line area of the at least a part is different from the standard cross-line area. The display panel described in item 7 of the scope of patent application, wherein: The number of the at least one crossed location from the fourth signal line to the first signal line is multiple, and one of the crossed locations is called a first crossed location, except The other straddled places of the first straddled place are called at least one second straddled place, Wherein, a first crossover area of the first crossover is different from at least one second crossover area of the at least one second crossover, and the at least one second crossover area is equal to the standard crossover area area. The display panel described in item 7 of the scope of patent application, wherein: The number of the at least one crossed area from the fourth signal line to the first signal line is multiple, and the crossed areas of the crossed areas are all the same.

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