TWI724840B - Display panel - Google Patents

Abstract

A display panel is disclosed. The display panel includes a display area and a periphery area. The display area includes a pixel array and a plurality of data lines. The periphery area includes a multiplexer. A waveform modulation circuit of the multiplexer includes a control transistor, a control signal line, a reverse signal line and a capacitor. The first end of the control transistor is connected to the data line and the second end of the control transistor is connected to a source driver. The control end of the control transistor is connected to the control signal line. The capacitor is disposed corresponding to the control transistor. The first end of the capacitor is connected to the reverse signal line and the second end of the capacitor is connected to the low voltage source.

Description

Display panel

The present invention relates to a display panel, in particular to a display panel that uses reverse signals to cancel multiplexer signals, thereby suppressing panel noise.

In Low Temperature Poly-Silicon (LTPS) display products, a multiplexer (Multiplexer) is usually installed, which uses switch control to enable multiple pixel circuits to share the same signal source, thereby reducing the required input contacts. Simplify the design of peripheral circuits. Although the above design can reduce the external wiring, because the multiplexer signal has the characteristics of high cross voltage and high frequency, it will generate a lot of parasitic capacitance with the voltage source. These parasitic capacitances will cause unnecessary noise to the display and may Affect the function of the display. For example, interference with touch signals or touch panels, electromagnetic interference (EMI) from automotive products, etc. Under the trend of increasingly stringent terminal product specifications and specifications, the interference of the above-mentioned noise may make the display fail to pass the product inspection.

In order to solve the above-mentioned noise problem, a complementary metal oxide semiconductor (CMOS) process is used to manufacture, and the noise is suppressed by the cancellation between the N-type transistor and the P-type transistor. However, the CMOS process requires more process steps and equipment than a single type of transistor, which increases the complexity of the product process and increases the product cost. If only a single type of transistor is made, there will be obvious interference noise, which is difficult to meet the required standards for product operation and inspection.

In summary, the conventional display panel structure still generates noise in the multiplexer setting and affects the function of the final product, which has considerable defects. Therefore, the present invention aims at the prior art by designing a display panel structure. The deficiencies should be improved to solve the problem of noise interference, thereby enhancing the implementation and utilization of the industry.

In view of the above-mentioned problems of the conventional technology, the purpose of the present invention is to provide a display panel with a reverse signal and a special wiring structure, thereby solving the problem of noise interference generated by the display panel caused by the multiplexer signal on the existing display panel. problem.

According to the above objective, an embodiment of the present invention provides a display panel including a display area and a peripheral area. Wherein, the display area includes a pixel array, and a plurality of rows of pixels of the pixel array are respectively connected to a plurality of data lines. The peripheral area contains multiplexers. The multiplexers include a plurality of waveform modulation circuits, and the plurality of waveform modulation circuits respectively include a control transistor, a control signal line, a reverse signal line, and a capacitor. The control transistor includes a first terminal, a second terminal and a control terminal. The first terminal is connected to one of a plurality of data lines, and the second terminal is connected to the source driver. The control signal line is connected to the control terminal of the control transistor, and transmits the control signal to control the control transistor. The reverse signal line transmits the reverse signal synchronized with the control signal. The capacitor corresponds to the setting of the control transistor. The capacitor includes a first end and a second end. The first end is connected to a reverse signal line, and the second end is connected to a low-voltage source.

In an embodiment of the present invention, the plurality of waveform modulation circuits may further include auxiliary transistors. The auxiliary transistors include a first terminal, a second terminal, and a control terminal. The first terminal is connected to the second terminal of the capacitor, and the second terminal Connect the low-voltage source, and connect the control terminal to the control signal line.

In the embodiment of the present invention, the area of the capacitor may be larger than the area of the control transistor.

In the embodiment of the present invention, the capacitance difference between the capacitor and the gate-drain capacitance of the control transistor may be less than 20%.

In the embodiment of the present invention, the low voltage source may be the low level of the reverse signal line.

In the embodiment of the present invention, the gate electrode of the auxiliary transistor may be disposed on the first metal layer, and the first metal layer is connected to the control signal line. The first end of the capacitor is disposed on the first metal layer, and the second end of the capacitor is disposed on the second metal layer. The first metal layer is connected to the reverse signal line, and the second metal layer is connected to the low voltage source.

In the embodiment of the present invention, the size of the control transistor can be 10-30 times that of the auxiliary transistor.

Based on the foregoing, the display panel disclosed in the embodiment of the present invention can achieve a multiplexer with the same or even better effect as the CMOS process through the modulation circuit design using a single type of transistor process. Not only can the complexity of the process steps be reduced, but also the production cost can be reduced. The manufactured display panel can not only prevent unnecessary noise from the control signal, but also prevent the noise from causing interference during product operation or testing.

10: Display panel

101, 102: Waveform modulation circuit

A: Channel area

C1: The first capacitor

C2: second capacitor

C3: third capacitor

Ca: Capacitance value

Cgd: gate and drain capacitance

Cgs: Gate source capacitance

D: Drain area

D1: The first data line

D2: The second data line

D3: The third data line

D4: The fourth data line

D5: Fifth data line

D6: The sixth data line

DA: display area

G: Gate electrode

GI: Gate insulation layer

M1: first electrode

M2: second electrode

MUX1: the first multiplexer

MUX2: second multiplexer

P1: the first pixel

P2: second pixel

P3: third pixel

PA: Surrounding area

PM: pixel array

S: source region

S1: The first signal source

S2: Second signal source

Sub: Substrate

SW1: The first control signal line

SW2: The second control signal line

SW3: The third control signal line

T11: The first control transistor

T12: The first auxiliary transistor

T21: The second control transistor

T22: second auxiliary transistor

T31: The third control transistor

T32: Third auxiliary transistor

VSS: Low voltage source

XSW1: The first reverse signal line

XSW2: The second reverse signal line

XSW3: The third reverse signal line

In order to make the technical features, content and advantages of the present invention and the effects that can be achieved more obvious, the present invention is combined with the accompanying drawings and described in detail in the form of embodiments as follows: Figure 1 is an embodiment of the present invention Schematic diagram of the display panel.

FIG. 2 is a schematic diagram of the waveform modulation circuit of the multiplexer according to the embodiment of the present invention.

FIG. 3 is a schematic diagram of a waveform modulation circuit of a multiplexer according to another embodiment of the present invention.

FIG. 4 is a schematic diagram of the structure of a waveform modulation circuit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of the test result of the waveform modulation circuit according to the embodiment of the present invention.

In order to understand the technical features, content and advantages of the present invention as well as the effects that can be achieved, the present invention is described in detail with the accompanying drawings and in the form of embodiment expressions as follows, and the figures used therein are only For the purpose of illustration and supplementary description, it is not necessarily the true scale and precise configuration after the implementation of the invention. Therefore, the scale and configuration relationship of the attached drawings should not be interpreted, and the scope of rights of the invention in actual implementation should not be interpreted. Narrate.

In the drawings, the thickness or width of layers, films, panels, regions, light guides, etc. are exaggerated for the sake of clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to a physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" can mean that there are other elements between the two elements. In addition, it should be understood that although the terms "first", "second", and "third" may be used herein to describe various elements, components, regions, layers and/or parts, they are used to refer to an element, component , Region, layer and/or part are distinguished from another element, component, region, layer and/or part. Therefore, it is only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or its sequence relationship.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have meanings commonly understood by ordinary knowledge in the technical field to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having the technical The meaning consistent with the meaning in the context of the present invention will not be interpreted as an idealized or excessively formal meaning unless it is clearly defined as such herein.

Please refer to FIG. 1, which is a schematic diagram of a display panel according to an embodiment of the present invention. As shown in the figure, the display panel 10 includes a display area DA and a peripheral area PA. The display area DA is a pixel area for displaying images, which is a pixel array PM formed by a plurality of rows and columns. The peripheral area PA is set in the display area DA. Around the outside, it is the setting area of various control circuits. In this embodiment, the pixels in the first row of the pixel array PM include a first pixel P1, a second pixel P2, a third pixel P3..., each pixel is connected to the first data line D1, and each pixel in the second row The pixels are respectively connected to the second data line D2, and so on. When the number of rows of pixels in the pixel array PM requires a considerable number of data lines to transmit data signals to each pixel, each data line needs a corresponding source driver (Source) to provide the data signal, and therefore requires a corresponding number of connections Click to connect. In order to reduce the circuit configuration and complexity of the peripheral area PA, a multiplexer can be provided in the peripheral area PA to solve the above-mentioned problems.

As shown in Figure 1, one end of the first multiplexer MUX1 can be connected to the first data line D1, the second data line D2, and the third data line D3, and the other end is connected to the first signal source S1, that is, through the first The multiplexer MUX1 makes the three data lines share the same first signal source S1, reducing the number of signal sources to simplify the circuit in the peripheral area PA. Similarly, the second multiplexer MUX2 can be connected to the fourth data line D4, the fifth data line D5, and the sixth data line D6 to share the signal of the second signal source S2. The multiplexer described here is a one-to-three Take an example to illustrate, but the present disclosure is not limited to this. The multiplexer can also be arranged in one-to-two or one-to-one more numbers, depending on the panel size and the number of pixels. The following embodiments will further illustrate the circuit structure of the multiplexer.

Please refer to FIG. 2, which is a schematic diagram of a waveform modulation circuit of a multiplexer according to another embodiment of the present invention. The waveform modulation circuit includes a control transistor, a control signal line, a reverse signal line and a capacitor, As shown in the figure, taking the one-to-three multiplexer of the foregoing embodiment as an example, the waveform modulation circuit 101 includes a first control transistor T11, a second control transistor T21, and a third control transistor T31, each of which controls The first end of the transistor is respectively connected to the first data line D1, the second data line D2 and the third data line D3, the second end of each control transistor is connected to the first signal source S1, and the control end of each control transistor The first control signal line SW1, the second control signal line SW2 and the third control signal line SW3 are respectively connected. The first control signal line SW1 transmits a control signal to turn on the first control transistor T11, so that the data signal of the first signal source S1 can be transmitted to the first data line D1. Similarly, the second control signal line SW2 and the third control signal line SW3 can also transmit control signals to turn on the second control transistor T21 or the third control transistor T31 in different time frames, so that the data signal can also be transmitted to the second control transistor T21 or the third control transistor T31. Data line D2 or third data line D3. According to the above-mentioned circuit configuration, the first data line D1, the second data line D2, and the third data line D3 can share the first signal source S1, and there is no need to connect to an independent signal source, which simplifies the design of the peripheral circuit.

However, when the first control transistor T11, the second control transistor T21, and the third control transistor T31 are activated, due to the high voltage and high frequency characteristics of the control signal, the gate and source of the transistor are in contact with each other. The parasitic capacitance between the poles and the drain will cause the display panel to generate noise. These noises will interfere with the operation of the final product, such as affecting the touch signal or causing electromagnetic interference to automotive products. Therefore, in the present disclosure, a capacitor and a reverse signal line are further provided in the waveform modulation circuit 101 to cancel the above-mentioned noise. As shown in the figure, one end of the first capacitor C1 is connected to the first reverse signal line XSW1, and the other end is connected to a low-voltage source VSS. The low-voltage source VSS mentioned here can refer to a voltage source of any DC potential, such as a ground terminal (GND). ). The first reverse signal line XSW1 transmits a reverse signal synchronized with the control signal, and suppresses noise generation by canceling out the opposite signals. Similarly, one end of the second capacitor C2 is connected to the second reverse signal line XSW2, the other end is connected to the low voltage source VSS, one end of the third capacitor C3 is connected to the third reverse signal line XSW3, and the other end is connected to the low voltage source VSS. The second reverse signal line XSW2 and the third reverse The signal line XSW3 also transmits a reverse signal synchronized with the control signal to cancel the noise. Through the setting of the reverse signal, the noise caused by the control signal can be suppressed, the noise interference generated by the multiplexer during operation can be reduced, and the function of the product including the display panel can also be prevented from being affected.

Please refer to FIG. 3, which is a schematic diagram of a waveform modulation circuit of a multiplexer according to another embodiment of the present invention. The waveform modulation circuit includes a control transistor, an auxiliary transistor, a control signal line, a reverse signal line and a capacitor. As shown in the figure, the waveform modulation circuit 102 includes a first control transistor T11, a second control transistor T21, and a third control transistor T31. The first end of each control transistor is connected to the first data line D1, respectively. For the second data line D2 and the third data line D3, the second end of each control transistor is connected to the first signal source S1, and the control end of each control transistor is respectively connected to the first control signal line SW1 and the second control signal line SW2 and the third control signal line SW3. One end of the first capacitor C1 is connected to the first reverse signal line XSW1, one end of the second capacitor C2 is connected to the second reverse signal line XSW2, and one end of the third capacitor C3 is connected to the third reverse signal line XSW3. The above-mentioned waveform modulation circuit 102 is similar to the previous embodiment, and the technical features of the same components will not be repeated.

In this embodiment, the waveform modulation circuit 102 is further provided with a first auxiliary transistor T12, a second auxiliary transistor T22, and a third auxiliary transistor T32. The first terminal of the first auxiliary transistor T12 is connected to the other terminal of the first capacitor C1, the second terminal is connected to the low voltage source VSS, and the control terminal is connected to the first control signal line SW1. Similarly, the first terminal of the second auxiliary transistor T22 is connected to the other terminal of the second capacitor C2, the second terminal is connected to the low voltage source VSS, and the control terminal is connected to the second control signal line SW2. The first terminal of the third auxiliary transistor T32 is connected to the other terminal of the third capacitor C3, the second terminal is connected to the low voltage source VSS, and the control terminal is connected to the third control signal line SW3. The first auxiliary transistor T12 also receives the control signal of the first control signal line SW1 and turns on the first auxiliary transistor T12, so that the reverse signal received by the first capacitor C1 can simulate the gate when the first control transistor T11 is turned on. Between source and gate and drain The signal waveform that the parasitic capacitance gradually increases, and the waveform that causes the signal to rapidly decrease when the channel disappears when the channel is turned off, so as to more accurately cancel the noise. Similarly, the second auxiliary transistor T22 and the third auxiliary transistor T32 also receive the control signals of the second control signal line SW2 and the third control signal line SW3, and turn on the second auxiliary transistor T22 and the third auxiliary transistor T32, respectively. , So that the reverse signals received by the second capacitor C2 and the third capacitor C3 can also simulate the signal waveforms of the second control transistor T21 and the third control transistor T31.

In the above embodiment, one end of the first capacitor C1 is connected to the first reverse signal line XSW1, and the other end is connected to the low voltage source VSS. When a reverse signal is received, the capacitor can be generated by the voltage difference. The low voltage source VSS can be It is the low level of the first reverse signal line XSW1, such as -9V, which can avoid the high level at both ends of the first capacitor C1 when the reverse signal is received, and the capacitive effect cannot be generated to offset the control signal generation The parasitic capacitance. One end of the second capacitor C2 and the third capacitor C3 is respectively connected to the second reverse signal line XSW2 and the third reverse signal line XSW3, and the other end is respectively connected to the low voltage source VSS, which can also be the reverse signal line Low level. On the other hand, the first auxiliary transistor T12 is to adjust the waveform of the reverse signal to simulate the noise waveform generated by the first control transistor T11. The magnitude of the cancellation signal is controlled by the first reverse signal line XSW1. The auxiliary transistor T12 does not need to be set to the same size as the first control transistor T11. In this embodiment, the size of the first auxiliary transistor T12 can be much smaller than the first control transistor T11. In another embodiment, the size of the first control transistor T11 may be 10-30 times that of the first auxiliary transistor T12. Similarly, the size of the second control transistor T21 can also be 10-30 times that of the second auxiliary transistor T22, and the size of the third control transistor T31 can also be 10-30 times that of the third auxiliary transistor T32.

Please refer to FIG. 4, which is a schematic diagram of a waveform modulation circuit structure according to another embodiment of the present invention. As shown in the figure, taking the arrangement structure of the first control transistor T11 and the first capacitor C1 as an example, the first control transistor T11 is arranged on the substrate Sub, and its polysilicon layer includes a source region S, a drain region D, and two In the channel area A between the two, the polysilicon layer is then provided with a gate electrode G on the gate insulating layer GI. The gate electrode G is connected to the first control signal line SW1 and receives the control signal to turn on the first control transistor T11, thereby enabling The data signal of the signal source can be sent to each pixel on the data line. When the first control transistor T11 is turned on, the channel region A is turned on, the gate electrode G and the source region S generate a gate-source capacitance Cgs, and the gate electrode G and the drain region D generate a gate-drain capacitance Cgd. These parasitic capacitances will form unnecessary noise during the operation or detection of the display device, and cause interference to the operation of the device. In this embodiment, the first capacitor C1 is disposed on the gate insulating layer GI, and the capacitance value Ca is generated by the voltage difference between the first electrode M1 and the second electrode M2, and the capacitance value Ca is combined with the gate-source capacitance Cgs and the gate-drain capacitance Cgd cancel each other out to avoid the above-mentioned noise generation.

In order to offset the parasitic capacitance generated by the first control transistor T11, the capacitance value Ca of the first capacitance C1 can be the same as the capacitance value of the gate-source capacitance Cgs or the gate-drain capacitance Cgd, or the difference between the two is less than 20% . The capacitance value Ca of the first capacitor C1 can be calculated by the following formula:

Where W x L is the area of the first control transistor T11, d is the distance between the gate electrode G of the first control transistor T11 and the conduction area A, that is, the thickness of the gate insulating layer GI, and ε is the permittivity of the medium. In order to achieve a capacitance similar to that generated by the first control transistor T11, the area of the first capacitor C1 can be larger than the area of the first control transistor T11.

On the other hand, the gate electrode G of the first control transistor T11 and the first electrode M1 of the first capacitor C1 can be arranged on the same metal layer, and the second electrode M2 of the first capacitor C1 is arranged on another metal layer at intervals. In this embodiment, the first electrode M1 is connected to the first reverse signal line XSW1, and the second electrode M2 is connected to the low voltage source VSS. This arrangement makes the first reverse signal line XSW1 transmit the reverse signal At this time, the signal will not be radiated through the surface of the device, but the shielding effect will be generated by the second electrode M2. In other words, when the device is operated or tested on the surface, it will not cause additional interference.

Please refer to FIG. 5, which is a schematic diagram of the test result of the waveform modulation circuit according to the embodiment of the present invention. As shown in the figure, part (A) is a multiplexer made by CMOS process. Its N-type transistor (120/6) and P-type transistor (20/6) respectively receive the control signal line SW and the reverse signal The result of measuring the signal waveform after the line XSW; (B) part of this disclosure uses only the NMOS process to make the control transistor (120/6) and auxiliary transistor (6/6), and cooperate with the capacitor (150fF) to receive them separately The signal waveform of the control signal line SW and the reverse signal line XSW is measured after the signal waveform; part (C) is the result of the noise signal formed by superimposing the waveform of the control signal and the reverse signal. The superimposed results of part (C) respectively show the test results of part (A) and part (B), and the peak to peak and root mean square value (RMS) of the voltage are used to evaluate the two The offsetting effect.

According to the test results, part (B) is better than part (A) in both evaluation values, and the peak-to-peak value of voltage (B) is 4.73V less than (A) 5.45V, both The 2.03V of the root square value (B) part is also less than the 2.07V of the part (A). It can be seen that the multiplexer structure manufactured by the single-type transistor process in the present disclosure can be formed by the modulation circuit to be the same as or even better than the CMOS process. The excellent noise suppression effect can not only reduce the cost of the manufacturing process, but also enhance the competitiveness of the product at the same time.

The above description is only illustrative, and not restrictive. Any equivalent modifications or alterations that do not depart from the spirit and scope of the present invention should be included in the scope of the appended patent application.

10: Display panel

D1: The first data line

D2: The second data line

D3: The third data line

D4: The fourth data line

D5: Fifth data line

D6: The sixth data line

DA: display area

MUX1: the first multiplexer

MUX2: second multiplexer

P1: the first pixel

P2: second pixel

P3: third pixel

PA: Surrounding area

PM: pixel array

S1: The first signal source

S2: Second signal source

Claims (8)

A display panel includes: a display area including a pixel array, and a plurality of rows of pixels of the pixel array are respectively connected to a plurality of data lines; and a peripheral area including a multiplexer including a plurality of waveforms A modulation circuit, the plurality of waveform modulation circuits respectively include: a control transistor, the control transistor includes a first end, a second end and a control end, the first end is connected to the plurality of data lines One of them, the second terminal is connected to a source driver; a control signal line, which is connected to the control terminal of the control transistor, transmits a control signal to operate the control transistor; a reverse signal line, the transmission is synchronized with One of the control signals is a reverse signal; and a capacitor corresponding to the control transistor setting. The capacitor includes a first end and a second end. The first end is connected to the reverse signal line, and the second end is connected to a Low-voltage source; wherein the plurality of waveform modulation circuits also include an auxiliary transistor, the auxiliary transistor includes a first terminal, a second terminal and a control terminal, the first terminal is connected to the second capacitor Terminal, the second terminal is connected to the low voltage source, and the control terminal is connected to the control signal line. In the display panel described in item 1 of the scope of patent application, the area of the capacitor is larger than the area of the control transistor. For the display panel described in item 1 of the scope of patent application, the capacitor and the control The capacitance difference between the gate and drain capacitors of the transistor is less than 20%. In the display panel described in item 1 of the scope of patent application, the low voltage source is the low level of the reverse signal line. In the display panel described in claim 1, wherein a gate of the auxiliary transistor is disposed on a first metal layer, and the first metal layer is connected to the control signal line. According to the display panel described in item 5 of the scope of patent application, the first end of the capacitor is disposed on the first metal layer, and the second end of the capacitor is disposed on a second metal layer. According to the display panel described in claim 6, wherein the first metal layer is connected to the reverse signal line, and the second metal layer is connected to the low voltage source. In the display panel described in item 1 of the scope of patent application, the size of the control transistor is 10-30 times that of the auxiliary transistor.

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