TWI724815B - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure includes: forming an active layer on a substrate; forming a first hard mask layer and a second hard mask on the active layer; patterning the second hard mask layer to form a plurality of patterned second hard masks, and the plurality of patterned second hard masks include a second wide mask and a second narrow mask; forming a plurality of spacers on sidewalls of the second wide mask and the second narrow mask; forming a photoresist layer to cover a top surface of the second wide mask and the side surfaces of a pair of spacers on the sidewalls of the second wide mask, and perform a etching process to remove the second narrow mask between the plurality of spacers; and remove the photoresist layer, then etching the first hard mask layer with the plurality of spacers and the second wide mask together as an etching mask to form a plurality of patterned first hard mask on the active layer, wherein the plurality of spacers are used to define a first line width, and the second wide mask and the pair of spacers formed on the sidewalls of the second wide mask are used together to define a second line width.

Description

Method for forming semiconductor structure

The present invention relates to a method for forming a semiconductor structure, in particular to a method for forming a semiconductor structure in a flash memory device.

In order to increase the density of the devices in the flash memory device and improve its overall performance, the current manufacturing technology of the memory device continues to make efforts towards the miniaturization of the device size.

However, as component sizes continue to shrink, many challenges arise. For example, in the semiconductor manufacturing process, a patterned mask layer used to define features in the target layer is often formed through lithography and etching processes. However, when forming a small-sized semiconductor structure, the problems of overlay shift of the lithography process and scattering of the ion beam etching by the multilayer photoresist layer are prone to occur, resulting in the structure of the defined component not as expected.

Some embodiments of the present invention provide a method for forming a semiconductor structure, including: forming a target layer on a substrate; forming a hard mask stack on the target layer, wherein the hard mask stack includes first hard masks sequentially formed on the target layer. A mask layer and a second hard mask layer; the second hard mask layer is patterned to form a plurality of patterned second hard masks, wherein the patterned second hard masks include a second wide mask and a second Narrow mask; forming a plurality of spacers on the sidewalls of the second wide mask and the second narrow mask; forming a photoresist layer to cover the top surface of the second wide mask, and the photoresist layer covers the second wide mask The side surfaces of a pair of spacers on the sidewalls, and an etching process is performed to remove the second narrow mask located between the spacers; and the photoresist layer is removed, and then the spacers and the second wide The mask is used as an etching mask to etch the first hard mask layer to form a plurality of patterned first hard masks on the target layer, wherein the spacers are used to define the first line width, the second wide mask and A pair of spacers formed on the sidewalls of the second wide mask are used to define the second line width.

FIGS. 1-13 are schematic cross-sectional views illustrating various stages of forming the semiconductor structure 1000 shown in FIG. 14 according to some embodiments of the present invention. 1, a target layer 100 is formed on the substrate 10, a hard mask stack 200 is formed on the target layer 100, and an anti-reflection layer 301 and a patterned photoresist layer 300 are sequentially formed on the hard mask stack 200 . The target layer 100 includes a gate layer 101, a conductive material layer 102 formed on the gate layer 101, and a cap layer 103 formed on the conductive material layer 102. The hard mask stack 200 includes a first hard mask layer 210, a second hard mask layer 220, and a third hard mask layer 230 sequentially formed on the target layer 100. The patterned photoresist layer 300 formed on the third hard mask layer 230 includes a narrow photoresist pattern 300A having a width W1 and a wide photoresist pattern 300B having a width W2.

According to some embodiments of the present invention, the target layer 100 may be formed on the semiconductor substrate 10 including a tunneling oxide layer and a floating gate structure. It is understandable that, in order to clearly and concisely describe some embodiments of the present invention and highlight the technical features of the present invention, the components located in the semiconductor substrate are not shown here.

In some embodiments, the substrate 10 may be an elemental semiconductor, including silicon or germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide (Silicon carbide), gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide. In other embodiments, the substrate 10 may also be a semiconductor on insulator substrate. The semiconductor on insulator substrate may include a bottom plate, a buried oxide layer disposed on the bottom plate, and a buried oxide layer. On the semiconductor layer.

In some embodiments, the gate layer 101 included in the target layer 100 may be formed of a conductive material, for example, polysilicon, metal, or metal nitride. The conductive material layer 102 on the gate layer 101 may include, for example, tungsten (W), tungsten nitride (WN), other suitable conductive materials, or a combination of the foregoing. In some embodiments, the material of the cap layer 103 on the conductive material layer 102 may include nitride, such as silicon nitride (SiN).

Continuing to refer to FIG. 1, the first hard mask layer 210 includes an oxide layer 211 formed on the target layer 100 and a nitride layer 212 formed on the oxide layer 211. In some embodiments, the oxide layer 211 may be formed of, for example, tetraethyl orthosilicate (TEOS) oxide or other suitable oxides. The material of the nitride layer 212 includes silicon nitride (SiN), silicon oxynitride (SiON), titanium nitride (TiN), tantalum nitride (TaN), or other suitable nitrides. In some embodiments, the second hard mask layer 220 may be formed of tetraethoxysilane (TEOS) oxide. The third hard mask layer 230 may be formed of polysilicon. In some embodiments, the anti-reflective layer 301 formed on the third hard mask layer 230 may include, for example, spin-on carbon, silicon oxynitride (SiON), other suitable anti-reflective materials, or the foregoing的组合。 The combination.

It is understandable that some embodiments of the present invention utilize the difference in etch selectivity among the first hard mask layer 210, the second hard mask layer 220, and the third hard mask layer 230, so as to improve the etch selectivity in the subsequent steps. The specific film layer is etched during the etching process (details will be discussed below). Therefore, the materials of each film layer in the hard mask stack 200 mentioned here are only exemplary, and suitable mask materials can be matched according to the process conditions, and the embodiments of the present invention are not limited thereto.

According to some embodiments of the present invention, the patterned photoresist layer 300 can be formed by applying a photoresist on the anti-reflective layer 301 by a spin coating process, and using a suitable photomask to expose the photoresist. The patterned photoresist layer 300 of the narrow photoresist pattern 300A and the wide photoresist pattern 300B. In some embodiments, the width W1 of the narrow photoresist pattern 300A may be in the range of 0.045 μm (micrometers, um) to 0.055 μm, and the width W2 of the wide photoresist pattern 300B may be in the range of 0.1 μm to 5 μm.

Referring to Figure 2, the pattern of the patterned photoresist layer 300 (ie, the narrow photoresist pattern 300A and the wide photoresist pattern 300B) is transferred to the underlying anti-reflection layer 301 and the third hard mask layer 230 through an etching process. To form patterned anti-reflection layers 301A, 301B and a patterned third hard mask 230P including a plurality of third narrow masks 230A and third wide masks 230B. The widths of the formed third narrow mask 230A and third wide mask 230B are approximately the same as the width W1 of the narrow photoresist pattern 300A and the width W2 of the wide photoresist pattern 300B, respectively. In some embodiments, the patterned third hard mask 230P (that is, between the plurality of third narrow masks 230A and/or between the third narrow mask 230A and the third wide mask 230B) has a first The spacing S1 is in the range of 0.045 micrometers to 0.055 micrometers.

Referring to FIG. 3, the patterned photoresist layer 300 and the patterned anti-reflective layers 301A, 301B can be removed using, for example, ashing and/or wet strip processes, and a plurality of third narrow layers are retained. The mask 230A and the third wide mask 230B are on the second hard mask layer 220.

Referring to FIG. 4, the second hard mask layer 220 is etched by using a patterned third hard mask 230P including a third narrow mask 230A and a third wide mask 230B as an etching mask to form a second hard mask layer 220 located in the patterned first mask. The patterned second hard mask 220P under the three hard mask 230P. As shown in Figure 4, the patterned second hard mask 220P includes a plurality of second narrow masks 220A and second wide masks 220B. The second narrow mask 220A is defined by the third narrow mask 230A. The second wide mask 220B is defined by the third wide mask 230B. In some embodiments, between the plurality of patterned second hard masks 220P (that is, between the plurality of second narrow masks 220A and/or between the second narrow masks 220A and the second wide masks 220B) The spacing is substantially the same as the first spacing S1.

Referring to FIG. 5, the second hard mask 220P is patterned by side etching to form a narrowed patterned second hard mask 220P', and the first spacing S1 between the plurality of patterned second hard masks 220P is increased It is the second spacing S2. In some embodiments, the narrowed patterned second hard mask 220P' includes a narrowed second narrow mask 220A' and a narrowed second wide mask 220B', wherein the width of the second narrow mask 220A' is narrowed W3 may be in the range of 0.02 micrometers to 0.05 micrometers, and the width W4 of the narrowed second wide mask 220B′ may be in the range of 0.075 micrometers to 4.995 micrometers, and the second spacing S2 may be in the range of 0.05 micrometers to 0.07 micrometers. According to some embodiments of the present invention, by narrowing the patterned second hard mask 220P, the pitch of the character line structure in the flash memory device to be formed subsequently can be adjusted. Specifically, when the width of the narrowed patterned second hard mask 220P' is narrower, the pitch of the subsequent formed character line structure is also narrower.

According to some embodiments of the present invention, the step of patterning the second hard mask 220P by side etching may be a wet etching process.

Referring to FIG. 6, an etching process is performed on the patterned third hard mask 230P including the third narrow mask 230A and the third wide mask 230B to remove it from the top surface of the narrowed patterned second hard mask 220P' Remove.

Referring to FIG. 7, a spacer material layer 700 is deposited on the narrowed second narrow mask 220A' and the narrowed second wide mask 220B'. Specifically, the spacer material layer 700 covers the top surface of the first hard mask layer 210 and the sidewalls and top surfaces of the narrowed second narrow mask 220A' and the narrowed second wide mask 220B'. In some embodiments, the spacer material layer 700 includes polysilicon.

Referring to FIG. 8, a part of the spacer material layer 700 is etched to form a plurality of spacers 700A covering the sidewalls of the narrowed second narrow mask 220A', and a plurality of spacers 700A covering the sidewalls of the narrowed second wide mask 220B' There are two spacers 700B, and the top surfaces of the narrowed second narrow mask 220A' and the narrowed second wide mask 220B' are exposed. According to some embodiments of the present invention, the width of the spacer 700A and the spacer 700B are approximately the same, which may be in the range of 0.012 μm to 0.027 μm. In some embodiments, the width of the character line structure formed subsequently can be adjusted by adjusting the width of the spacers 700A and 700B to meet the product requirements, the details of which will be discussed below.

Referring to Figure 9, a photoresist layer 900 is formed to cover the narrowed second wide mask 220B'. According to some embodiments of the present invention, the boundary BD (or sidewall) of the photoresist layer 900 may be located between the sidewall SW1 of the narrowed second wide mask 220B' and the sidewall SW2 of the adjacent narrowed second narrow mask 220A' . In other words, in some embodiments, the photoresist layer 900 covering the narrowed second wide mask 220B' and the spacer 700B does not cover the narrowed second narrow mask 220A' to facilitate the subsequent etching process Remove the narrowed second narrow mask 220A'. For example, FIG. 9 shows the photoresist layer 900 covering the top surface of the narrowed second wide mask 220B', and covering the top surface of the narrowed second wide mask 220B' according to some embodiments of the present invention. Side surfaces of a pair of spacers 700B of the side wall. Accordingly, compared to directly forming a photoresist layer between the spacers without a mask (that is, without the second wide mask 220B') between them, and only using the photoresist layer and the spacers as the subsequent etching In the case of the etching mask of the process, the embodiments provided by the present invention can effectively improve the process tolerance of the formation of the photoresist layer 900.

Referring to FIG. 10, the formed photoresist layer 900 masks the narrowed second wide mask 220B', and performs an etching process to remove the narrowed second narrow mask 220A' between the spacers 700A. In some embodiments, after removing the narrowed second narrow mask 220A′, an opening OP is formed between the spacers 700A, wherein the first hard mask layer 210 (such as a nitride layer) located between the spacers 700A The top surface part of 212) is exposed from the opening OP.

Referring to FIG. 11, the photoresist layer 900 is removed by, for example, an ashing and/or wet strip process, leaving a plurality of spacers 700A, narrowing the second wide mask 220B', And the pair of spacers 700B covering the sidewalls of the narrowed second wide mask 220B′ are used as an etching mask in the subsequent etching process.

Referring to FIG. 12, the spacer 700A, the narrowed second wide mask 220B', and the spacer 700B covering the sidewalls of the narrowed second wide mask 220B' are used as an etching mask to etch (for example, perform reactive ion Dry etching (RIE)) the first hard mask layer 210 to form a plurality of patterned first hard mask layers 210P on the target layer 100. According to some embodiments of the present invention, the spacer 700A can be used to define the first line width (for example, the width of the character line structure (such as the width W7 shown in FIG. 14)), while narrowing the second wide mask 220B', and The pair of spacers 700B covering the sidewalls thereof can be used together to define the second line width (for example, the width of the selected gate structure (such as the width W8 shown in FIG. 14)).

According to some embodiments of the present invention, compared to the case where a mask with a thickness greater than the spacers (for example, a photoresist layer formed after the spacers are formed) is formed between the spacers and used as an etching mask with the spacers Since the narrowed second wide mask 220B' and the top surface of the spacer 700B covering its sidewall in the embodiment of the present case do not have a height difference, the etching mask formed together with the spacer 700A can effectively avoid During the etching process (for example, reactive ion etching (RIE) dry etching), the ion beam is scattered, thereby avoiding the problem of structural distortion of the patterned first hard mask layer 210P underneath.

Continuing to refer to FIG. 12, the patterned first hard mask layer 210P includes a first narrow mask 210A defined by spacers 700A and a narrowed second wide mask 220B' and the pair of spacers 700B covering the sidewalls thereof. The first wide mask 210B is defined. The first narrow mask 210A includes a patterned oxide layer 211A formed on the top surface of the target layer 100 (for example, the top surface of the cap layer 103) and a patterned nitride layer 212A formed thereon. The first wide mask 210B includes a patterned oxide layer 211B formed on the top surface of the target layer 100 (for example, the top surface of the capping layer 103) and a patterned nitride layer 212B formed thereon.

According to some embodiments of the present invention, the width W5 of the first narrow mask 210A is approximately equal to the width of the spacer 700A, and the width W6 of the first wide mask 210B is approximately equal to the width of the narrowed second wide mask 220B' The sum of the width of the pair of spacers 700B covering the sidewalls thereof. Specifically, the width W5 may be in the range of 0.012 μm to 0.027 μm, and the width W6 may be in the range of 0.09 μm to 5.045 μm.

Referring to FIG. 13, an etching process is performed to remove spacers 700A, narrow the second wide mask 220B', and cover the sidewalls of spacers 700B, and retain the patterned first hard layer formed on the top surface of the target layer 100 The mask layer 210P serves as an etching mask in the subsequent etching process.

Referring to FIG. 14, the pattern of the patterned first hard mask layer 210P (ie, a plurality of first narrow masks 210A and first wide masks 210B) formed on the target layer 100 is transferred to the target layer 100. According to some embodiments of the present invention, the first narrow mask 210A is used to define the patterned target layer 100A in the target layer 100, and the first wide mask 210B is used to define the patterned target layer 100B in the target layer 100 . According to some embodiments of the present invention, the target layer 100A included in the semiconductor structure 1000 can be used to form a word line structure in a flash memory device (not shown), which includes a patterned gate layer 101A, The patterned conductive material layer 102A and the patterned cap layer 103A. The target layer 100B can be used to form a select gate structure in a flash memory device (not shown), which includes a patterned gate layer 101B, a patterned conductive material layer 102B, and a patterned capping layer 103B that are sequentially stacked.

Continuing to refer to FIG. 14, in some embodiments, the width W7 of the target layer 100A (or called the word line structure 100A) included in the semiconductor structure 1000 that can be formed as a flash memory device and the first narrow mask 210A The width W5 of the target layer 100B (or referred to as the selective gate structure 100B) is approximately the same, and the width W8 of the target layer 100B (or referred to as the selective gate structure 100B) is approximately the same as the width W6 of the first wide mask 210B. According to some embodiments of the present invention, after the target layer (character line structure) 100A and the target layer (select gate structure) 100B are formed, the patterned first hard mask layer 210P can be removed by an etching process (not Illustrated).

In summary, the method for forming a semiconductor structure provided by an embodiment of the present invention includes forming a plurality of spacers on the sidewalls of the patterned hard mask and then removing the narrow hard mask between them, and The formed spacers (for example, spacers 700A, 700B) and the remaining wide and hard mask (for example, the narrowed second wide mask 220B′) together serve as an etching mask. The above-mentioned spacers can be used to define a device structure with a smaller width in the target layer located under the patterned hard mask (for example, the character line structure 100A), as well as the remaining wide and hard mask and a pair formed on its sidewalls. The spacers can be used together to define a device structure with a larger width in the target layer (for example, the select gate structure 100B in a flash memory device) without forming an additional photomask with a small line width. Therefore, the semiconductor structure forming method provided by the embodiment of the present invention can effectively reduce the process difficulty and process cost.

According to some embodiments of the present invention, after the word line structure and the select gate structure are formed by the above-mentioned semiconductor structure forming method, the word line structure can be combined with the floating gate structure and tunneling in the underlying semiconductor substrate. The oxide layer forms a memory cell, and the select gate structure and the source/drain subsequently formed on both sides of the semiconductor substrate form a select gate transistor, which can be connected to other semiconductor processes To form a flash memory device.

Several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field of the present invention should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and replacements.

10: substrate 100: target layer 100A, 100B: Patterned target layer 101: gate layer 101A, 101B: patterned gate layer 102: Conductive material layer 102A, 102B: Patterned conductive material layer 103: cap layer 103A, 103B: patterned cover layer 200: Hard mask stack 210: The first hard mask layer 210P: Patterned first hard mask layer 210A: The first narrow mask 210B: The first wide mask 211: oxide layer 211A, 211B: patterned oxide layer 212: Nitride layer 212A, 212B: patterned nitride layer 220: second hard mask layer 220P: Patterned second hard mask 220P’: Narrowing patterned second hard mask 220A: second narrower mask 220A’: Narrow the second narrow mask 220B: the second widest mask 220B’: Narrow the second widest mask 230: third hard mask layer 230P: Patterned third hard mask 230A: Third narrow mask 230B: Third wide mask 300: Patterned photoresist layer 300A: Narrow photoresist pattern 300B: wide photoresist pattern 301: Anti-reflective layer 301A, 301B: patterned anti-reflective layer 700: Spacer material layer 700A, 700B: interstitial objects 900: photoresist layer 1000: Semiconductor structure BD: Border OP: opening W1, W2, W3, W4, W5, W6, W7, W8: width S1: first spacing S2: second spacing SW1, SW2: side wall

FIGS. 1 to 13 are schematic cross-sectional views illustrating various stages of forming a semiconductor structure according to some embodiments of the present invention. FIG. 14 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

10: substrate

100: target layer

101: gate layer

102: Conductive material layer

103: cap layer

210P: Patterned first hard mask layer

210A: The first narrow mask

210B: The first wide mask

211A, 211B: patterned oxide layer

212A, 212B: patterned nitride layer

Claims (9)

A method for forming a semiconductor structure includes: forming a target layer on a substrate; forming a hard mask stack on the target layer, wherein the hard mask stack includes a first hard mask sequentially formed on the target layer A mask layer and a second hard mask layer; the second hard mask layer is patterned to form a plurality of patterned second hard masks, wherein the patterned second hard masks include a second wide mask And a second narrow mask; forming a plurality of spacers on the sidewalls of the second wide mask and the second narrow mask; forming a photoresist layer to cover the top surface of the second wide mask, and the light The resist layer covers the side surfaces of a pair of spacers located on the sidewalls of the second wide mask, and performs an etching process to remove the second narrow mask located between the spacers; and removes the photoresist Layer, and then use the spacers and the second wide mask as an etching mask to etch the first hard mask layer to form a plurality of patterned first hard masks on the target layer, where Before the step of etching the first hard mask layer, the photoresist layer is removed, and the spacers are used to define a first line width, and the second wide mask is formed on the second wide mask. The pair of spacers on the sidewall are used together to define a second line width. The method for forming a semiconductor structure according to claim 1, further comprising: forming a third hard mask layer on the second hard mask layer; forming a patterned photoresist layer on the third hard mask layer ; The pattern of the patterned photoresist layer is transferred to the third hard mask layer to form a plurality of patterned third hard masks, and the patterned third hard masks include a third wide mask and a The third narrow mask, wherein there is a first space between the patterned third hard masks And by using the third wide mask and the third narrow mask as another etching mask to etch the second hard mask layer to form the second wide mask and the second narrow mask. The method for forming a semiconductor structure according to claim 1, further comprising: performing a wet etching process to laterally etch the patterned second hard masks, so that there is one between the patterned second hard masks The first pitch is increased to a second pitch. The method for forming a semiconductor structure according to claim 1, wherein the boundary of the photoresist layer is located between the sidewall of the second wide mask and the sidewall of the adjacent second narrow mask. The method for forming a semiconductor structure according to claim 1, further comprising: transferring the patterns of the patterned first hard masks formed on the target layer to the target layer, wherein the patterned first hard masks The mask includes a first wide mask and a plurality of first narrow masks. The width of the first wide mask is approximately equal to the width of the second wide mask and the pair of gaps covering the sidewalls of the second wide mask The sum of the widths of the objects and the width of the first narrow masks are approximately equal to the widths of the spacers. Wherein, the first wide mask is used to define a select gate structure in the target layer, and the first narrow masks are used to define a plurality of word line structures in the target layer. The method for forming a semiconductor structure according to claim 1, wherein the target layer includes a gate layer, a conductive material layer, and a cap layer stacked in sequence. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the first hard mask layer includes: forming an oxide layer on the target layer; and A nitride layer is formed on the oxide layer, wherein the oxide layer and the nitride layer constitute the first hard mask layer. The method for forming a semiconductor structure according to claim 1, wherein the second hard mask layer includes an oxide layer. The method for forming a semiconductor structure according to claim 2, wherein the third hard mask layer includes a polysilicon layer.

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