TWI721999B - Vector length querying instruction - Google Patents

Abstract

A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.

Description

Vector length query command

This disclosure case is related to the field of data processing systems. More specifically, the present disclosure relates to a data processing system supporting vector processing.

It is known to provide a data processing system that supports the processing of vector operands, the vector operands including a plurality of vector elements. The number of bits in the vector register is usually defined by the relevant processor architecture. The number of bits in the vector register can be divided among vector elements of different sizes, so that a given vector register provides a different number of vector elements.

According to at least some embodiments of the present disclosure, a device for processing data is provided. The device includes a processing circuit system to perform vector processing operations; and a decoder circuit system to decode program instructions to generate control signals to control the processing circuit system To perform the vector processing operations; wherein the decoder circuit system responds to the scale vector length query command to control the processing circuit system to return a result value that depends on the vector length multiplied by the scale value, and the device is executing the vector The vector length is used in processing operations, and the scale value is specified by the scale vector length query instruction.

According to at least some embodiments of the present disclosure, a device for processing data is provided. The device includes processing means for performing vector processing operations; and decoder means for decoding program instructions to generate control signals to control the processing The circuit system performs the vector processing operations; wherein the decoder means responds to the scale vector length query command to control the processing means to return a result value determined by the vector length multiplied by the scale value, and the device is executing the vector The vector length is used in processing operations, and the scale value is specified by the scale vector length query instruction.

According to at least some embodiments of the present disclosure, a method for processing data is provided. The method includes decoding a scale vector length query command to control a processing circuit system to return a result value that depends on the vector length multiplied by the scale value. It is used in vector processing operations, and the scale value is specified by the scale vector length query instruction.

The above and other objectives, features, and advantages of the present disclosure will be apparent in the following detailed description of the illustrative embodiments, which will be read in conjunction with the accompanying drawings.

FIG. 1 schematically illustrates a data processing system 2 which includes a processor 4 coupled to a memory 6 which stores data values 8 and program instructions 10. The processor 4 includes an instruction fetching unit 12 for fetching program instructions 10 from the memory 6 and supplying the fetching program instructions to the decoder circuit system 14. The decoder circuitry 14 decodes the retrieved program instructions and generates a control signal 16 to control the vector processing circuitry 18 to perform vector processing operations on the vector registers stored in the vector register circuitry 20, such as Specified by the decoded vector instruction. It will be understood that, in practice, the processor 4 will usually include more circuit elements, and these circuit elements have been omitted from the drawings.

Figure 1 also schematically illustrates an exemplary vector register Z _i . In this example, the vector register has a vector bit size of 256. The vector register Z _{i is} formed by 16 vector elements a ₀ -a ₁₅ . Each of these vector elements in the bit vector having a size of 16 bits, therefore, the number of vector elements in the vector register 16 is Z _i. The vector element size is a variable that can be specified by the decoded vector instruction. For example, vector instructions can be encoded to specify vector elements as bytes, halfwords, words, or doublewords (8, 16, 32, 64 bits, respectively). Based on bit vector element size, the number of vector elements in the vector register Z _i will change. Accordingly, for the vector register formed by Z _i 256 yuan, which may support sixteen vector elements 16 yuan, 32 yuan eight vector elements or four elements of the vector 64 yuan.

A given implementation of the processor 4 will include a vector register circuit system 20 that supports a vector register Zi of the size of the location element. However, different implementations of the processor 4 using the same instruction set architecture can support vector registers of different sizes, such as 512-bit, 384-bit, 1024-bit, and so on.

As the enabling code comprises a vector instruction to accommodate varying sizes vector Z _i register without any significant manner or modifying the vector register circuitry 20, there is provided a vector length ratio or more query instruction. The proportional vector length query command returns a result value that depends on the number of elements in the vector to obtain a variable vector element size (for example, byte, halfword, word, or double word). The vector element size is queried by the proportional vector length The instruction specifies and multiplies the scale value specified by the scale vector length query instruction. This kind of proportional vector length query command can return a result, which can take into account the specific vector register size of the implementation, and also take into account the degree of program loop scrolling provided by the vector code being implemented. The scale value may be provided in the form of a constant integer value, which is encoded in the scale vector length query instruction (for example, an immediate value in the instruction).

Figure 2 schematically illustrates various types of proportional vector length query commands. Specifically, the type of the vector length query instruction can be a count instruction, an increment instruction, or a decrement instruction. More types of instructions as the length of the proportional vector query instructions are also possible. The proportional vector length query instruction additionally specifies the size of the vector element, which will determine the result value relative to this size. Therefore, the vector element size can be byte B, half word H, word W, or double word D. The proportional vector length query instruction also specifies a scalar register X _d , which can serve as the source of the input operand value for the instruction and the destination of the result value to be written.

The final two parameters in the proportional vector length query command shown in Figure 2 are a field that specifies the mode constraint, which is applied to the vector length used by the processing device, and can be specified based on the mode constraint The returned scale vector length query command result value. Vector mode constraints can take many different forms. The constraint may be, for example, that the maximum value provided by the device is a multiple of the prescribed value M, for example, the value of the number of vector elements is constrained to be a multiple of the value M (modulus (M)). Another example of the constraint mode is that the maximum value returned for the number of vector elements supported should be constrained to a power of two, such as 2, 4, 8, 16, 32, and so on. Another example is a constraint patterns exceeds the physical size of the vector Z _i of the register, the maximum number of elements does not support the utilization constraint. Therefore, if the length of the vector register is 256 bits and the element size is 16 bits, in this way, using the "All" constraint, the result value will be returned based on the number of vector elements being 16.

The final parameter specified by the proportional vector length query command is the proportional value. This value can be a constant integer value encoded in the scale vector length query instruction with its own immediate value. Although this scale value may have many values, it has been found that the scale value in the range of 1 to 8 (including 1 and 8) can support most of the loop expansion. The loop expansion is usually stored in the command to encode the length of the scale vector query command It was discovered when the bit space.

Figure 3 schematically illustrates the result values, which can be returned for use in some exemplary scale vector length query commands. The column illustrated is a vector bit size (i.e. the size in bits of the vector register Z _i), bit size vector elements (e.g., byte, halfword, word, double word), the vector mode confinement (e.g. A , Modulus (M), powers of 2, etc.), proportional values (such as a constant value encoded in the instruction itself, ranging from 1 to 8 (including 1 and 8)), and instruction types (such as counting, incrementing, Decrease). Compared with the counting instruction, the input value can be regarded as "0", and can be the value provided by the input register X _d in the case of increment and decrement instructions.

Consider the first line illustrated in Figure 3, which specifies a vector bit size of 128. The vector element bit size is 8. Therefore, the unconstrained maximum vector element count is 16. The mode constraint for this row is "All", and accordingly this corresponds to the unconstrained mode. The scale in the first row is "1", and therefore the result is not changed proportionally. The instruction type is count, and therefore, a simple count of the number of byte-sized vector elements in the vector register is provided and the count is equal to 16.

More complex examples are given in the fifth line. In this case, the vector bit size is 256, and the vector element bit size is 32. This indicates that the unconstrained number of vector elements supported is 8. However, the mode constraint is that the number of vector elements that should be the supported number should be a multiple of 3. Therefore, the mode constraint reduces the number of vector elements considered as the maximum supported value to 6. The scale value of the fifth row is 2, and the instruction type is count, and therefore, the result value is twice the result of the mode constraint, that is, 12.

Another example is given in the tenth row. In this row, the vector bit size is 384, and the vector element bit size is 16. This may indicate that the number of original vector elements supported by the vector register is 24. However, the mode constraint applied in this line is that the supported vector count should be a power of two, and thus, the maximum number of supported vector elements with a bit size of 16 is regarded as 16. A scale factor of 2 is applied. Therefore, the partial result value after scaling is 32. The instruction type is an increment type proportional vector length query instruction, and the input value for increment _{held in the scaler register X d is 48.} This produces the result value (incremental value) 80.

When the proportional vector length query command is a proportional counting command, the command returns a count value, which depends on the number of elements supported multiplied by the proportional value. When the proportional vector length query command is a proportional increase command, the command returns an increment result value, which depends on the input value to be incremented (by depending on the vector bit size, vector element bit size, mode constraints and The value determined by the proportional value increases). In a similar manner, when the proportional vector length query command is a proportional decrease command, the command returns a decrease result value, and the decrease result value depends on the input value to be decreased.

FIG. 4 illustrates an exemplary embodiment of a circuit system for determining a result value in response to a proportional vector length query command. This embodiment has the form of a look-up table, the table includes a table address decoder 22, and the decoder indexes into the result value table 24. The parameters (fields) from the proportional vector length query command are supplied as input to the table decoder 22. These fields include the element size (2 bits), the applied constraint mode (5 bits), and the applied scale value (3 bits). The table address decoder 22 has a fixed form for a specific implementation, that is, a specific vector length for the implementation. The table address decoder 22 generates 1 heat output in response to the input signal supplied to it to select a result value from the result value table 24. If the proportional vector length query command is a proportional increase command or a proportional decrease command, The resulting value is then supplied to the increment or decrement circuitry (adder or subtractor).

Figure 5 is a flow chart schematically illustrating the logic flow of processing a proportional vector length query command. It will be understood that, in practice, this type of processing is usually executed at the same time, and the individual steps illustrated in Figure 5 may actually be executed at the same time. In step 26, the process waits until the proportional vector length query instruction is received. Then, step 28 determines the original maximum number of vector elements supported by the vector register implementation in relation to the specified vector element size. Step 30 applies the constraint mode (if any) specified by the proportional vector length query command. Step 32 scales the partial results determined by applying the constraint mode in step 26. If the instruction type is a count instruction, then step 36 writes the count result into the destination register. If the command type is increment, in step 38, the destination register value that has been maintained by the increment value determined in step 32 is incremented, and the increment result is written into the destination register. If it is determined in step 34 that the command type is decrement, then in step 40, the destination register value is decremented by the decrement value calculated in step 32, and the result is written into the destination register.

Figure 6 illustrates a virtual machine implementation that can be used. Although the foregoing embodiment implements the present invention based on equipment and methods for operating specific processing hardware, which supports related technologies in this case, it is also possible to provide implementations of so-called virtual machines of hardware devices. These virtual machine implementations are executed on a host processor 530, which is executed on a host operating system 520 that supports a virtual machine program 510. Generally, a powerful processor is required to provide a virtual machine implementation that executes at a reasonable speed, but this method makes sense in some environments, such as when it is required for compatibility or reuse reasons When executing code originating from another processor. The virtual machine program 510 provides an application program interface to the application program 500, which is the same as the application program interface to be provided by actual hardware, which is a device being modeled by the virtual machine program 510. Thus, the program instructions including the control of the above-mentioned memory access can be executed from the application program 500 by using the virtual machine program 510 to model the interaction between the program instructions and the virtual machine hardware.

Although specific embodiments have been described herein, it will be understood that the present invention is not limited to these embodiments, and many modifications and additions can be made within the scope of the present invention. For example, without departing from the scope of the present invention, the features of the following subsidiary claims can be combined with the features of independent claims.

2‧‧‧Data Processing System 4‧‧‧Processor 6‧‧‧Memory 8‧‧‧Data value 10‧‧‧Program command 12‧‧‧Command fetching unit 14‧‧‧Decoder circuit system 16‧‧‧Control signal 18‧‧‧Vector processing circuit system 20‧‧‧Vector register circuit system 22‧‧‧Table Address Decoder 24‧‧‧Result value table 26‧‧‧Step 28‧‧‧Step 30‧‧‧Step 32‧‧‧Step 34‧‧‧Step 36‧‧‧Step 38‧‧‧Step 40‧‧‧Step 500‧‧‧Application 510‧‧‧Virtual Machine Program 520‧‧‧Host Operating System 530‧‧‧Host processor

Figure 1 schematically illustrates a data processing system supporting vector processing;

Figure 2 schematically illustrates a plurality of different forms of proportional vector length query commands;

Figure 3 schematically illustrates examples of the characteristics of different types of proportional vector length query commands in Figure 2;

Figure 4 schematically illustrates an implementation of a lookup table for generating a result value in response to a proportional vector length query command;

Figure 5 is a flow chart which schematically illustrates the characteristics of the proportional vector length query command; and

Figure 6 schematically illustrates a virtual machine implementation.

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Claims (15)

A device for processing data, the device comprising: a processing circuit system for performing vector processing operations; and a decoder circuit system for decoding program instructions to generate control signals to control the processing circuit system to execute the vectors Processing operation; wherein the decoder circuit system can respond to a ratio vector length query command specifying a vector element size and a ratio value to control the processing circuit system to return a result value, the result value depends on a predetermined vector The number of vector elements of the vector element size under the length is multiplied by the ratio value, and the predetermined vector length represents a length of a vector register used by the device. The device according to claim 1, wherein the scale value is a constant integer value encoded in the scale vector length query instruction. The device according to claim 1, wherein the ratio value is in a range extending from 1 to 8, and the range includes 1 and 8. The device according to claim 1, wherein the size of the vector element is selected from one of 8-bit, 16-bit, 32-bit, and 64-bit. The device according to claim 1, wherein the proportional vector length query instruction includes one or more other parameters, and the result value returned by the processing circuit system depends on the one or more other parameters number. The device according to claim 5, wherein the one or more other parameters include a vector mode constraint, and the vector length used by the device is determined under the restriction of the vector mode constraint. The device according to claim 6, wherein the vector mode constraint stipulates that the number of elements is one of the following: a maximum value provided by the device, and the maximum value is also a multiple of a prescribed value M; A maximum value provided by the device, the maximum value is also a power of 2; and a maximum value provided by the device. The device according to claim 1, wherein the proportional vector length query command is a proportional counting command, and the proportional counting command returns a counting result value, and the result value depends on the number of elements multiplied by the proportional value. The device according to claim 1, wherein the proportional vector length query command is a proportional increase command, the proportional increase command returns an increase result value, and the increase result value depends on an input value to be increased. The device according to claim 1, wherein the proportional vector length query command is a proportional decrement command, and the proportional decrement command returns a decrement result value, and the decrement result value depends on an input to be decremented Into the value. The device according to claim 1, wherein the vector processing circuit system includes a look-up table, the look-up table is addressed depending on the ratio value to at least partially determine the result value. The device according to claim 5, wherein the look-up table is addressed depending on the one or more other parameters. A device for processing data, the device comprising: processing means for performing vector processing operations; and decoding means for decoding program instructions to generate control signals to control the processing means to perform the vector processing operations; wherein the The decoder means can respond to a scale vector length query command specifying a vector element size and a scale value to control the processing means to return a result value that depends on the vector element size under a predetermined vector length The number of vector elements of is multiplied by the ratio, and the predetermined vector length represents a length of a vector register used by the device. A method for processing data. The method includes the following steps: decoding a scale vector length query command specifying a vector element size and a scale value to control the processing circuit system to return a result value, which depends on a predetermined value The number of vector elements of the vector element size under the vector length is multiplied by the ratio value, and the predetermined direction The quantity length represents a length of a vector register used by a device. A computer program stored on a non-transitory storage medium for controlling a computer to provide a virtual machine execution environment, the virtual machine execution environment corresponding to the device as described in claim 1.

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