JP2018521421A - Vector operand bit size control - Google Patents

Abstract

The data processing system 2 includes a processing circuit 18 and a decoder circuit 14 for decoding program instructions and controlling the processor circuit. The decoder circuit is responsive to a vector operand bit size dependent instruction that is executed in a selected exception level state of the hierarchy of exception level states, in a vector operand associated with the currently selected exception level state. Process with a vector operand bit size governed by child bit size limits, any programmable limit values set for exception level states closer to the highest exception level state in the hierarchy, and implementation limits The processing circuit is controlled to perform the following.

Description

  The present disclosure relates to the field of data processing systems. More specifically, the present disclosure relates to data processing systems that support vector processing operations.

  It is known to provide data processing systems that support vector processing operations that have at least one vector operand having a vector operand bit size and including a plurality of vector elements. Typically, the vector operand bit size is defined as part of the architecture of the data processing system. For example, the architecture defines that the vector operand bit size is some specific fixed value, such as 256 bits, 512 bits, 1024 bits.

At least some embodiments of the present disclosure are devices for processing data comprising:
A processing circuit for performing a processing operation in a selected exception level state in a hierarchy of exception level states ranging from the highest exception level state to the lowest exception level state;
A decoder circuit for decoding a program instruction and generating a control signal for controlling the processing circuit to perform the processing operation, wherein the processing operation uses at least one vector operand A decoder circuit including a vector processing operation to
The decoder circuit in response to a vector operand bit size dependent program instruction executed in the selected exception level state, the vector operand bit size limit value of the selected exception level state, and the selection To perform vector processing operations depending on at least one programmable vector operand bit size limit value of the exception level state closer to the topmost exception level state in the hierarchy than the specified exception level state An apparatus for controlling the processing circuit is provided.

At least some embodiments of the present disclosure are devices for processing data comprising:
Processing means for performing a processing operation in a selected exception level state in a hierarchy of exception level states ranging from the highest exception level state to the lowest exception level state;
Decoding means for decoding a program instruction and generating a control signal for controlling the processing means to perform a processing operation, the processing operation using at least one vector operand Decoder means including one or more vector processing operations;
The decoder means is responsive to a vector operand bit size dependent program instruction executed in the selected exception level state, the vector operand bit size limit value of the selected exception level state, and the selection To perform vector processing operations depending on at least one programmable vector operand bit size limit value of the exception level state closer to the topmost exception level state in the hierarchy than the specified exception level state An apparatus for controlling the processing means is provided.

At least some embodiments of the present disclosure are methods for processing data, comprising:
Performing a processing operation by a processing circuit in a selected exception level state in a hierarchy of exception level states ranging from an exception level state at a top layer to an exception level state at a bottom layer;
Decoding a program instruction and generating a control signal for controlling the processing circuit to perform the processing operation, wherein the processing operation uses at least one vector operand Including generating, including,
In response to a vector operand bit size dependent program instruction executed in the selected exception level state, the vector operand bit size limit value of the selected exception level state and the selected exception level state Controlling the processing circuit to perform vector processing operations depending on at least one programmable vector operand size limit value of an exception level state closer to the exception level state of the top layer in the hierarchy than Provide a method.

  The exemplary embodiments will now be described by way of example only with reference to the accompanying drawings.

1 schematically illustrates a data processing system that supports vector processing using vector operands. 3 schematically illustrates an example vector operand and vector predicate operand in the form of a general vector operand. Vector operand bit size dependent instructions and allowed vector operands in a system with multiple exception level states and programmable limit values for controlling the vector operand bit size associated with each exception level state A specific example of the behavior of a bit size query instruction is schematically illustrated. FIG. 4 is a generalized version of FIG. 3 illustrating the behavior of a system with N exception level states. Fig. 5 schematically illustrates a system configuration register that can be used to store programmable limit values from which a context-dependent read by an allowed vector operand bit size query instruction can be performed. 3 is a flowchart schematically illustrating the behavior of a context-dependent vector operand bit size dependent instruction and a context-dependent allowed vector operand size query instruction, respectively. 3 is a flowchart schematically illustrating the behavior of a context-dependent vector operand bit size dependent instruction and a context-dependent allowed vector operand size query instruction, respectively. 6 is a flowchart schematically illustrating a behavior when writing a programmable limit value. Fig. 6 schematically illustrates the behavior when the vector operand size is increased. 1 schematically illustrates a virtual machine implementation.

  FIG. 1 schematically illustrates a data processing system 2 that includes a processor 4 and a memory 6, which stores data 8 and program instructions 10. The processor 4 includes an instruction fetch circuit 12 that fetches the program instructions 10 from the memory 6 and passes them to the decoder circuit 14. The program instructions 10 are decoded by the decoder circuit 14 to control the operation of the processor 4. 16 is generated. More specifically, the control signal 16 controls the processing circuit 18 to perform a processing operation specified by the decoded program instruction. The processing circuit 18 is connected to a vector register circuit 20 for storing a vector operand having a vector operand bit size and including a plurality of vector elements. A system configuration register 22 is also coupled to the processing circuit 18. The system configuration register 22 is programmed by the processing circuit 18 under software control, such as constraints on the vector operand bit size used for vector processing instructions and vector operand bit size with programmable limit values (PLVs). It can serve to store configuration values that serve to configure the behavior of the processing circuit 18.

FIG. 2 schematically illustrates two exemplary forms of vector operands. The first exemplary vector operand 24 may be used as a source or destination operand when executing vector program instructions (eg, vector arithmetic instructions, vector logic instructions, etc.), such as A general vector operand. In this example, the general vector operand 24 is illustrated as having a vector operand bit size of 512 bits and including eight vector elements each having a vector element bit size of 64 bits. Vector elements _are displayed as a 0 ~a _7.

FIG. 2 also illustrates another exemplary form of vector operand, the vector predicate operand 26. This may be a vector predicate operand associated with a vector processing operation being performed on the general vector operand 24. The vector predicate operand 26 includes a plurality of predicate values p _{0 to} p ₇ , and the plurality of predicate values p _{0 to} p ₇ are vectors operated by the vector program instruction to execute the associated vector program instruction. Control over the corresponding vector element in the operand. As an example, the predicate value may switch on or off the vector processing associated with each vector element in the general vector operand. In the illustrated example, the vector predicate operand has 64 bits and each predicate value is 8 bits long.

  The data processing system 2 of FIG. 1 is implemented by a specific implementation of the vector register circuit 22 that is used to store the vector operands 24, 26. In practice, different physical implementations using the processor architecture of this disclosure may provide vector operands with maximum bit sizes with different implementation limits. Complex implementations aimed at high processing speed may provide vector operands with large bit sizes, such as 1024 bits. Conversely, processor implementations aimed at providing lower energy consumption during operation may support a smaller maximum vector operand bit size, such as 128 bits. Software written to run on the processor architecture of the data processing system 2 is used to run the software without requiring any modifications (or without requiring significant modifications) It may be desirable to be able to use depending on the implementation-specific vector operand bit size of the particular processor 4 being implemented. In addition, certain software may have been tested / verified to run at a particular vector operand bit size, and the software itself implements the vector operand bit size used in the execution of that software. It may be desired to constrain the maximum vector operand bit size to be different (less than). In systems that utilize multiple exception level states (eg, privilege levels), the vector operand bit size used by software running in the lower exception level state may be used by software in the higher privilege level. It may be desirable to be able to constrain. For example, an operating system that has been verified to operate correctly up to a given maximum vector operand bit size is that an application program running under that operating system is the largest vector for which the operating system has been verified. There may be a desire to constrain the operand bit size not to be exceeded.

FIG. 3 schematically illustrates programmable limit values associated with different exception level states for a particular implementation of processor 4. In this implementation, the maximum operand bit size at the implementation limit is 512. The processor 4 supports execution in four different exception level states, EL0, EL1, EL2, and EL3. These exception level states are arranged in a hierarchy of exception level states ranging from the lowest exception level state EL0 to the highest exception level state EL3. Each exception level state other than the lowest level exception level state has a programmable limit value (PLV _x ) associated with it. In other exemplary embodiments (not shown), the bottommost exception level state EL0 may also have a programmable limit value (PLV ₀ ) associated therewith. These programmable limit values indicate the vector operand bit size associated with each of the exception level states. In the example of FIG. 3, exception level state EL1 has a 384-bit programmable limit value, exception level state EL2 has a 256-bit programmable limit value, and exception level EL3 has a 512-bit programmable limit value. Has a limit level. These programmable limits are the maximum vector operand bits to be used to execute vector program instructions that are executed in the exception level state and all exception level states below the exception level state. Indicates size. Thus, a programmable limit value associated with an exception level state imposes a limit on the vector operand size of the program instruction executing at its own exception level, and further within the exception level state hierarchy. This limit is imposed on program instructions being executed at the lower exception level. As an example, a hypervisor running in exception level state EL2 may support a maximum vector operand bit size of 256, which is limited by operating system software running in exception level EL1 and exception level EL0. It will be imposed on the application software being executed. Even though these other instances of software themselves, such as operating systems in exception level state EL1, may use larger vector operand bit sizes as specified by their own programmable limits.

  When a vector operand bit size dependent instruction is executed, the vector operand bit size used is determined by the limits of the currently selected exception level state and the currently selected selection level state (which itself is Governed by any (all) programmable limit values set for exception level states closer to the topmost exception level state in the hierarchy than (may or may not be programmable) It is controlled (and used by the processing circuit 18) to perform processing with the vector operand bit size. The lowest level exception level state (in this exemplary embodiment) does not have an associated programmable limit value, but other exception level states closer to the top layer of the hierarchy than the lowest level exception level state. Subject to all our programmable limits. Vector program instructions will typically use the vector operand bit size that has the maximum value allowed for the vector operand bit size dependent instruction being executed. This provides an increased level of parallel operation.

  Software running in a particular exception level state must determine the maximum vector operand bit size that the software can potentially use because of exception level state constraints that are closer to the topmost exception level state There is a case. To accomplish this, decoder circuit 14 and processing circuit 18 support allowable operand bit size query instructions. This allowed vector operand bit size query instruction is an exception level state that is closer to the highest exception level state in the hierarchy than the selected exception level state in which the processing circuit 18 executes the allowed vector operand bit size query instruction. Returns the vector operand bit size indication value constrained by. Thus, in the example of FIG. 3, the allowed vector operand bit size query instruction executed in the exception level state EL0 corresponding to the lowest level exception level state used by the application program is (even in this exemplary embodiment). Even if the exception level state EL0 has no associated limit value and the limit value associated with the operating system running at exception level EL1 is the higher value of 384, the exception level state EL2 It will return 256 allowed vector operand bit size indication values constrained by 256 programmable limit values. The allowed vector operand bit size indication value returned depends on the programmable limit value associated with the higher exception level state, but the selected exception on which the allowable vector operand bit size query instruction itself is executed. Do not rely on any programmable limits associated with the state. In the example of FIG. 3, the programmable limit value associated with the exception level state EL2 itself is 256, but the execution of the allowable vector operand bit size query instruction in the exception level state EL2 is 512 allowable vector operands. Returns the bit size indication value. This is because this is a programmable limit value associated with the exception level state EL3. Permissive vector operand bit size query instructions allow software running in a particular exception level state to set its own programmable limits or to modify some other aspect of the software's behavior For example, the maximum vector operand bit size that the software can use can be determined.

FIG. 4 is a generalized version of the specific example given in FIG. In this generalized version, there are N exception levels. The vector operand bit size used for a vector operand bit size dependent instruction at a given exception level is further dependent on the programmable limit value of the exception level state itself and the highest exception level state in the hierarchy. Determined as the minimum number indicated by the nearest other programmable limit. In the case of exception level EL0 (in this exemplary embodiment), it itself has no programmable limit value, and therefore its vector operand bit size is that of the higher exception level state in the hierarchy. Determined as the minimum number indicated by all programmable limits. The topmost exception level state EL (N-1) is the vector operand used for its vector operand bit size dependent instruction, specified by its own programmable limit value PLV _(n-1). Has a child bit size.

  In the case of the vector operand bit size indication value returned in the generalized example of FIG. 4, this is compared to the exception level state where the allowed vector operand bit size query instruction itself is executed. Given by the minimum number indicated by all programmable limit values associated with the higher exception level state of the. For the topmost exception level state, the allowed vector operand bit size indication value returned is the implementation limited vector operand bit size of the particular implementation of processor 4 (and vector register circuit 20).

FIG. 5 schematically illustrates an example of a form of the system register 22 that can be used to control the behavior described above. These system registers 22 include an identification register ZIDR_EL1 along with a plurality of exception level configuration registers ZCR_EL _x . The decoder circuit 14 reads the identification register ZIDR_EL1 in response to the allowed vector operand bit size query instruction and the current exception level state (thus making the instruction context sensitive). The value returned from such a register read is the allowed vector operand bit size indication value determined with respect to FIGS. 3 and 4 as described above. In particular, while the execution of the allowable vector operand bit size query instruction may appear to the programmer to read the identification system register, in practice the result is that multiple exception level configuration registers ZCR_EL _x and the maximum implementation limit It can be derived from other sources including the operand bit size. In the program model, the effect of executing the vector operand bit size query instruction is to return the least significant bit of the identification register ZIDR_EL1. This has a value corresponding to the maximum allowable vector operand bit size indication value described above. Which of the exception level configuration registers ZCR_EL _x depends on this return value is controlled by the exception level state in which the allowed vector operand bit size query instruction is executed. When executed in the lowest level exception level state, an attempt to the read identification register ZIDR_EL1 may not return a value, and the instruction is then treated as an undefined instruction instead, and an undefined instruction exception is thrown. May trigger. The exception level configuration register ZCR_EL _x associated with each exception level state other than the lowest level exception level state is used to store programmable limit values PLV _x set by writing to these exception level configuration registers. Is done. A system register read or write instruction to the exception level configuration register ZCR_EL _x executed in a given exception level state will cause its own exception level state and any lower (lowest level exception in the exception level state hierarchy). Reading or writing the exception level configuration register with the exception level state (closer to the level state) is allowed. Attempts to read or write to the exception level configuration register ZCR_EL _x in the higher exception level state result in undefined instruction behavior.

  In this exemplary embodiment, the programmable limit value may be a 4-bit value and is used to indicate the vector operand bit size by incrementing by 1 and multiplying by 128. Obviously, other mappings between the programmable limit values and the vector operand bit size specified by the programmable limit values can also be used, eg specifying the vector operand size as a power of two. Let's go.

  FIG. 6A is a flow diagram that schematically illustrates execution of a context sensitive vector operand bit size dependent instruction. In step 28, the process waits until a vector operand bit size dependent instruction is received by the decoder 14. Next, in step 30, the decoder 14 reads the programmable limit value of the currently selected exception level state and the programmable limit value of all the higher exception level states to other processing circuits 18 and other processors in the processor. A control signal 16 for controlling the element is generated. Step 32 determines the minimum number of these read values. Step 34 performs a process (such as an arithmetic operation, a logical operation, or some other operation) specified by a vector operand bit size dependent instruction that uses the minimum value determined in Step 32 as the vector operand bit size. Carry out.

  FIG. 6B is a flow diagram that schematically illustrates the operation of the context-sensitive allowed vector operand bit size query instruction. In step 36, the process waits until an allowed vector operand bit size query instruction is received by the decoder circuit 14. This allowable vector operand bit size query instruction may be, for example, reading of the identification register ZIDR_EL1. When such an instruction is received, processing proceeds to step 38, where programmable limit values (and implementation limit maximum vector operands where applicable) set for all higher exception level conditions. (Bit size) is read out. Step 40 determines the minimum number of readings from step 38. Step 42 returns the minimum number of read values as the maximum allowable vector operand bit size (allowable vector operand bit size indication value). Then, the process ends.

FIG. 7 is a flow diagram that schematically illustrates the behavior of the processor 4 when writing the programmable limit value PLV to one of the system configuration registers 22. The programmable limit values that can be set for a given exception level state are limited by the programmable limit values set for the higher exception level state, and are also limited by the specific implementation constraints of the processor 4. For example, certain implementations of processor 4 can support 512, 256, and 128 vector operand bit sizes, but cannot support 384 vector operand bit sizes. Therefore, if a system register write instruction for one of the exception level configuration registers ZCR_EL _x is trying to define a programmable limit corresponding to a vector operand bit size of 384, this is the exception level state hierarchy. Can be allowed by the higher of the programmable limits, but not by the hardware implementation of the processor 4. In this case, the programmable limit value stored in the exception level configuration register ZCR_EL _x is rounded to the z low vector operand bit size supported by the hardware in response to a system register write instruction. Thus, in the above example, an attempt to write a programmable limit value corresponding to 384 may be tolerated by the programmable limit value of the higher exception level state, but is not tolerated by the hardware implementation and is therefore stored. The value being rounded to the next lowest supported vector operand size, ie 256. By attempting to write different programmable limit values to the exception level configuration register and then reading the stored value, the software running in a particular exception level state is set by the software in the higher exception level state Determine which vector operand bit sizes are supported and which vector operand bit sizes are not supported as a result of both the programmed limits and the limits set by the hardware implementation. obtain.

In step 44 of FIG. 7, the process waits until an instruction write to the exception level configuration register ZCR_EL _x is received by the decoder 14. Step 46 determines whether the specified programmable limit value being written is supported by the hardware. An additional check (not shown) is performed so that the written value never contradicts the programmable limit value of the higher exception level state.

  If the programmable limit value written by the instruction decoded in step 44 is supported by the hardware (and the configuration controlled by software), step 48 sets the specified programmable limit value to the state Serves to write to the configuration register. If the programmable limit value to be written is determined by step 46 to be unsupported by the hardware, processing proceeds through step 50 and the rounded programmable limit value is instead replaced by the relevant hardware. Rounded to the next lower value supported by the hardware implementation and written to the state configuration value.

  FIG. 8 schematically illustrates the behavior of the processing system when the vector operand bit size is increased. It will be appreciated that through the use of programmable limits, software can dynamically change the vector operand bit size during use. Such a change may have a significant operational impact on the system, which is one that does not allow the lowest level exception level state to control its own vector operand bit size. This is why it avoids application programs that typically run in this lowest level exception level state from causing undesirable behavior.

  Increased vector operand bit size (such as in response to a change in a programmable limit value or an exception level state to an operation in an exception level state that allows the use of a larger vector operand bit size) When done, the newly accessible portion 52 of the vector operand is made available for use by vector processing instructions. In order to help provide deterministic behavior of the processing system 2, the processing system 2 can accommodate the increase in vector operand bit size within the newly accessible portion of the vector operand. The value in the newly accessible part is always preserved by having the value of zero set to zero or in the state it had when the newly accessible part was last usable. Respond by making sure.

  FIG. 9 illustrates a virtual machine implementation that may be used. Although the embodiments described above implement the present invention with respect to apparatus and methods for operating specific processing hardware that supports the techniques, it is also possible to provide so-called virtual machine implementations of hardware devices. is there. These virtual machine implementations run on a host processor 530 that runs a host operating system 520 that supports a virtual machine program 510. Typically, a large and powerful processor is required to provide a virtual machine implementation that runs at a reasonable speed, but such an approach is compatible or reusable with the native code of another processor. Can be justified under certain circumstances, such as when there is a need to move to. The virtual machine program 510 provides the application program 500 with the same application programming interface that would be provided by real hardware, which is a device embodied by the virtual machine program 510. Accordingly, program instructions including memory access control as described above can be executed from within an application program 500 that embodies the interaction between program instructions and virtual machine hardware using the virtual machine program 510.

  Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, the present invention is not limited to those exact embodiments and various modifications to those embodiments are described. It should be understood that additions, modifications, and alterations may be made by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, the features of the dependent claims can be variously combined with the features of the independent claims without departing from the scope of the present invention.

Claims (15)

A device for processing data,
A processing circuit for performing a processing operation in a selected exception level state in a hierarchy of exception level states ranging from the highest exception level state to the lowest exception level state;
A decoder circuit for decoding a program instruction and generating a control signal for controlling the processing circuit to perform the processing operation, wherein the processing operation uses at least one vector operand A decoder circuit including a vector processing operation to
The decoder circuit in response to a vector operand bit size dependent program instruction executed in the selected exception level state, the vector operand bit size limit value of the selected exception level state; and the selection Performing a vector processing operation depending on at least one programmable vector operand bit size limit value of an exception level state closer to the uppermost exception level state in the hierarchy than the specified exception level state. An apparatus for controlling the processing circuit. The vector operand bit size is a maximum value allowed by the limit value of the selected exception level state, and the exception level state of the highest layer in the hierarchy than the selected exception level state 2. The apparatus of claim 1 having a maximum value that is allowed by any programmable limit value set for an exception level condition closer to. The decoder circuit is responsive to an allowed vector operand bit size query instruction to set any exception level state that is closer to the topmost exception level state in the hierarchy than the selected exception level state. The apparatus according to any one of claims 1 and 2, which returns an allowed vector operand bit size indication value governed by a programmable limit value. 4. The exception level configuration register of claim 1, comprising a plurality of exception level configuration registers storing respective programmable limit values of the vector operand bit size associated with corresponding exception level states in the hierarchy. A device according to claim 1. 5. The apparatus of claim 4, comprising a respective exception level configuration register for each exception level state in the hierarchy excluding the lowest level exception level state. The processing circuit includes an exception level configuration register in the selected exception state and an arbitrary exception level configuration register in an exception level state that is closer to the exception level state in the lowest layer in the hierarchy than the selected exception level state 6. The device according to any one of claims 4 and 5, wherein access to the device is permitted. The processing circuit is prevented from querying the allowable vector operand bit size using the allowable vector operand bit size query instruction when the processing circuit is in the lowest level exception level state. The apparatus according to claim 3. The processing circuit includes a vector operand register circuit for storing a vector operand having a vector operand bit size of a maximum implementation limit, and the programmable limit value is a vector operand of the implementation limit. The apparatus according to claim 1, wherein the processing circuit is controlled to perform the vector operand bit size dependent instruction using a vector operand bit size that is less than or equal to a child bit size. . 9. The vector operand according to claim 1, wherein the vector operand is one of a general vector operand and a vector predicate operand that specifies a predicate value for controlling execution of a vector program instruction. A device according to claim 1. In response to the processing circuit attempting to set a programmable limit value to accommodate a vector operand bit size not supported by the device, the programmable limit value is supported by the device. 10. Apparatus according to any one of the preceding claims, wherein the apparatus is set to the next lowest vector operand bit size. The processing circuit is responsive to an increase in the vector operand bit size at the time of at least one of the change of the selected exception level state and the change of at least one of the programmable limit values. Retained in the newly accessible part of the operand in the newly accessible part when the value of zero or the newly accessible part was last accessible 11. Apparatus according to any one of the preceding claims, providing one of the values equal to the value that has been made. 4. The apparatus of claim 3, wherein the allowed vector operand bit size query instruction is a system register read instruction. A device for processing data,
Processing means for performing a processing operation in a selected exception level state in a hierarchy of exception level states ranging from the highest exception level state to the lowest exception level state;
Decoding means for decoding a program instruction and generating a control signal for controlling the processing means to perform the processing operation, wherein the processing operation uses at least one vector operand Decoder means including one or more vector processing operations to
The decoder means, in response to a vector operand bit size dependent program instruction executed in the selected exception level state, the vector operand bit size limit value of the selected exception level state; and the selection Performing a vector processing operation depending on at least one programmable vector operand bit size limit value of an exception level state closer to the uppermost exception level state in the hierarchy than the specified exception level state. An apparatus for controlling the processing means. A method of processing data,
Performing a processing operation by a processing circuit in a selected exception level state in a hierarchy of exception level states ranging from an exception level state at a top layer to an exception level state at a bottom layer;
Decoding a program instruction to generate a control signal for controlling the processing circuit to perform the processing operation, wherein the processing operation uses at least one vector operand Including generating, including,
In response to a vector operand bit size dependent program instruction executed in the selected exception level state, the vector operand bit size limit value of the selected exception level state and the selected exception level state Controlling the processing circuit to perform a vector processing operation depending on at least one programmable vector operand size limit value in an exception level state closer to the exception level state in the hierarchy than in the hierarchy. ,Method. A computer program stored on a non-transitory storage medium for controlling a computer to provide a virtual machine execution environment corresponding to the apparatus according to claim 1.