TWI718409B - Power amplifier circuit - Google Patents

Abstract

A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies a signal corresponding to the second signal and outputs a third signal, a third transistor that supplies a first bias current or voltage to a base of the first transistor, and a fourth transistor that supplies a second bias current or voltage to a base of the second transistor. A ratio of an emitter area of the third transistor to an emitter area of the first transistor is larger than a ratio of an emitter area of the fourth transistor to an emitter area of the second transistor.

Description

Power amplifier circuit

The present invention relates to a power amplifier circuit.

In a mobile communication device such as a mobile phone, a power amplifier circuit is used to amplify the power of a radio frequency (RF: Radio-Frequency) signal transmitted to a base station. In the power amplifier circuit, a bias circuit for supplying a bias current to the transistor for power amplifier is used. For example, Patent Document 1 discloses a power amplifier circuit using a bias circuit including an emitter follower. In this bias circuit, a bias current is output from the emitter of the transistor for supplying bias current to the base of the transistor for amplification.

[Prior Technical Literature]

[Patent Literature]

[Patent Document 1] JP 2016-213557 Publication

In the bias circuit including the emitter follower as described above, the current amount of the bias current is affected by the RF signal. Specifically, when the level of the RF signal increases, a negative current (current from the base of the transistor for amplification to the emitter side of the transistor for supplying bias current) is generated in the bias current. At this time, the negative current is cut off due to the rectification characteristics of the PN junction between the base/emitter of the transistor for supplying the bias current. As a result, the ratio of the bias current flowing in the positive direction increases, and the average value of the bias current becomes higher. Therefore, the gain of the power amplifier circuit increases, and as a result, the linearity of the gain in the power amplifier circuit deteriorates.

In order to cope with this problem, in the structure disclosed in Patent Document 1, a current path for passing a negative current is provided between the base/emitter of the transistor for supplying the bias current, so that the negative part of the bias current is provided. Will not be cut off. As a result, even if the level of the RF signal is large, the increase in the average value of the bias current is suppressed.

However, since a capacitor is used as a path for passing a negative current in the above structure, the path has frequency characteristics. Therefore, for example, when the frequency band of the RF signal spreads over a wide range as seen in the multi-band technology, there is a problem that the characteristics vary with frequency.

The present invention was made in view of this situation, and its object is to provide a power amplifier circuit capable of suppressing the linear degradation of gain in a wide frequency band.

In order to achieve this objective, a power amplifier circuit according to one aspect of the present invention includes: a first transistor that amplifies a first signal to output a second signal; and a second transistor that amplifies a signal corresponding to the second signal to output a second signal. 3 signal; the third transistor provides the first bias current or voltage to the base of the first transistor; and the fourth transistor provides the second bias current or voltage to the base of the second transistor, and the third The ratio of the emitter area of the transistor to the emitter area of the first transistor is greater than the ratio of the emitter area of the fourth transistor to the emitter area of the second transistor.

According to the present invention, it is possible to provide a power amplifier circuit capable of suppressing linear degradation of gain in a wide frequency band.

100‧‧‧Power amplifier circuit

110、111‧‧‧Amplifier

120、121‧‧‧Bias circuit

Q1~Q8‧‧‧Transistor

R1~R4‧‧‧Resistive element

C1~C4‧‧‧Capacitor

10‧‧‧Semiconductor substrate

20‧‧‧Base layer

30a, 30b‧‧‧Emitter layer

40a, 40b‧‧‧ Collector layer

FIG. 1 is a diagram showing a configuration example of a power amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a plan view showing the structure of one unit constituting the transistor Q1.

FIG. 3 is a graph showing an example of the simulation result of the voltage Vbb in the power amplifier circuit according to the embodiment of the present invention.

FIG. 4 is a graph showing an example of a simulation result of the gain of the first stage in the power amplifier circuit according to the embodiment of the present invention.

5 is a graph showing an example of simulation results of ACLR characteristics in the power amplifier circuit of the comparative example of the present invention.

6 is a graph showing an example of simulation results of ACLR characteristics in the power amplifier circuit according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same symbols are assigned to the same elements, and repeated descriptions are omitted.

FIG. 1 is a diagram showing a configuration example of a power amplifier circuit according to an embodiment of the present invention. The power amplifier circuit 100 shown in FIG. 1 is mounted on, for example, a mobile communication device such as a mobile phone, and is used to amplify the power of a radio frequency (RF: Radio-Frequency) signal transmitted to a base station. The power amplifier circuit 100 is compatible with, for example, 2G (2nd generation mobile communication system), 3G (3rd generation mobile communication system), 4G (4th generation mobile communication system), 5G (5th generation mobile communication system), LTE (Long Term Evolution: Long-term evolution)-FDD (Frequency Division Duplex: Frequency Division Duplex), LTE-TDD (Time Division Duplex: Time Division Duplex), LTE-Advanced, LTE-Advanced Pro, etc., to amplify the power of signals in communication standards . In addition, the power amplifier circuit 100 amplifies the power of signals in a plurality of different frequency bands, for example. The frequency of the RF signal is, for example, about several hundred MHz to several tens of GHz. In addition, the communication specification and frequency of the signal amplified by the power amplifier circuit 100 are not limited to this.

The power amplifier circuit 100 includes, for example, amplifiers 110 and 111 and bias circuits 120 and 121.

The amplifiers 110 and 111 constitute a two-stage amplifier. The amplifier 110 in the front stage (drive stage) amplifies the RF signal RF1 (first signal), and outputs the RF signal RF2 (second signal). The amplifier 111 in the latter stage (power stage) further amplifies the RF signal RF2 and outputs the RF signal RF3 (the third signal). In addition, the number of stages of the amplifier is not limited to two stages, and may be three or more stages.

The bias circuits 120 and 121 provide bias currents or voltages to the amplifiers 110 and 111, respectively. Specifically, the bias circuit 120 (first bias circuit) supplies the bias current Ibias1 (first bias current) to the amplifier 110 in the preceding stage. In addition, the bias circuit 121 (second bias circuit) supplies the bias current Ibias2 (second bias current) to the amplifier 111 in the subsequent stage. The gains of the amplifiers 110 and 111 are controlled by the current amounts of the bias currents Ibias1 and Ibias2.

In addition, although illustration is omitted, the power amplifier circuit 100 may be provided with a matching circuit for matching the impedance between the circuits in the front stage and the rear stage of each of the amplifiers 110 and 111.

Next, specific configuration examples of the amplifiers 110 and 111 and the bias circuits 120 and 121 will be described.

The amplifier 110 in the previous stage includes, for example, a transistor Q1, a capacitor C1, and a resistance element R1. Similarly, the amplifier 111 in the latter stage includes, for example, a transistor Q2, a capacitor C2, and a resistance element R2.

Transistor Q1 (first transistor) and transistor Q2 (second transistor) are, for example, bipolar transistors such as Heterojunction Bipolar Transistor (HBT). The base of the transistor Q1 is provided with an RF signal RF1 and a bias current Ibias1, the collector is provided with a power supply voltage, and the emitter is grounded. Thereby, the transistor Q1 amplifies the RF signal RF1, and outputs the RF signal RF2 from the collector. The base of the transistor Q2 is provided with an RF signal RF2 and a bias current Ibias2, the collector is provided with a power supply voltage, and the emitter is grounded. Thereby, the transistor Q2 further amplifies the RF signal RF2, and outputs the RF signal RF3 from the collector.

In addition, although illustration is omitted, a power supply voltage may be supplied to the collectors of the transistors Q1 and Q2 via a choke inductor.

The capacitors C1 and C2 are coupling capacitors that cut off the DC component contained in the input RF signal and pass the AC component, respectively.

The resistance elements R1 and R2 are respectively connected between the bias circuits 120 and 121 and the bases of the transistors Q1 and Q2. By providing the bias currents Ibias1 and Ibias2 through the resistance elements R1 and R2, the increase in the bias currents Ibias1 and Ibias2 caused by the temperature rise of the transistors Q1 and Q2 is suppressed.

FIG. 2 is a plan view showing the structure of one unit constituting the transistor Q1. In addition, the transistor Q2 can include the same unit as the unit shown in the figure.

As shown in this figure, one unit includes: a base layer 20 formed on the main surface of the semiconductor substrate 10 in a plan view of the main surface, and two emitter layers 30a, 30b formed on both outer sides of the base layer 20, respectively , And collector layers 40a, 40b formed on both outer sides of the two emitter layers 30a, 30b, respectively. In this way, a unit transistor is formed. In addition, the “unit transistor” refers to a structure including at least a base layer, a collector layer, and an emitter layer, and the smallest unit functioning as a transistor.

In addition, although illustration is omitted in FIG. 2, in addition to the unit transistor described above, an element corresponding to the capacitor C1 and the resistance element R1 may be integrally formed in each unit. Although each element included in each amplifier 110 and 111 is illustrated by one circuit symbol in FIG. 1, the amplifiers 110 and 111 in this embodiment each include a plurality of units. In addition, among the plurality of cells, the collectors, emitters, and bases of the unit transistors are electrically connected to each other. Thereby, a plurality of units are connected in parallel, and the whole is operated as one amplifier. Although the number of units constituting the amplifier is not particularly limited, in the power amplifier circuit 100, since the power amplification level of the latter stage is higher than that of the former stage, the number of units in the latter stage (for example, 20) is greater than the number of units in the former stage (for example, 4). many.

Hereinafter, in each unit, the total area of the emitter layer in the plan view of the main surface of the semiconductor substrate 10 (the total area of the emitter layers 30a and 30b in FIG. 2) is also referred to as the "emitter area of the unit". ". In addition, the total of the emitter areas of a plurality of units constituting the amplifier is also referred to as the "emitter area of the amplifier (or the emitter area of the transistor)". For example, when the amplifier 110 includes 4 cells, if the area of the emitter layer 30a is set to 1, the emitter area of the amplifier 110 (transistor Q1) is 1×2×4 cells=8. In addition, the number of emitter layers included in one unit is not limited to two, and may be four, for example. When there are 4 emitter layers, 4 emitter layers and 3 base layers can also be alternately formed side by side.

Returning to FIG. 1, the bias circuit 120 includes, for example, transistors Q3 to Q5, a resistance element R3, and a capacitor C3.

The transistors Q3 to Q5 are, for example, HBT. The collector and base of the transistor Q3 are connected (hereinafter also referred to as "diode connection"), the collector is supplied with a voltage Vb1 via the resistance element R3, and the emitter is connected to the collector of the transistor Q4. Transistor Q4 is connected to the diode, the collector is connected to the emitter of transistor Q3, and the emitter is grounded. Thereby, a predetermined voltage (for example, about 2.6V) is generated at the collector of transistor Q3.

The collector of the transistor Q5 (third transistor) is supplied with the battery voltage Vbatt, the base is connected to the base of the transistor Q3, and the emitter is connected to the base of the transistor Q1 via the resistance element R1. Thereby, the bias current Ibias1 is output from the emitter of the transistor Q5. The transistor Q5 is the same as the above-mentioned transistors Q1 and Q2, and includes, for example, a plurality of units. As an example, Fig. 1 schematically shows that the transistor Q5 includes three units.

The voltage Vb1 is supplied to one end of the resistance element R3, and the other end is connected to the collector of the transistor Q3. In addition, instead of the voltage Vb1, a current Ib1 may be supplied from a current source to one end of the resistance element R3.

One end of the capacitor C3 is connected to the collector of the transistor Q3, and the other end is grounded. The capacitor C3 causes the AC component to flow into the ground, thereby suppressing the voltage amplitude of the base of the transistor Q3 caused by the detection of the RF signal.

The bias circuit 121 includes, for example, transistors Q6 to Q8, a resistance element R4, and a capacitor C4. In addition, since the structures of the transistors Q6, Q7, the resistance element R4, and the capacitor C4 are the same as the structures of the transistors Q3, Q4, the resistance element R3, and the capacitor C3 in the bias circuit 120, respectively, detailed descriptions are omitted.

The collector of the transistor Q8 (fourth transistor) is supplied with the battery voltage Vbatt, the base is connected to the base of the transistor Q6, and the emitter is connected to the base of the transistor Q2 via the resistance element R2. Thereby, the bias current Ibias2 is output from the emitter of the transistor Q8. Transistor Q8 may include a plurality of units similarly to the above-mentioned transistors Q1 and Q2, for example. As an example, Fig. 1 schematically shows that the transistor Q8 includes one unit.

In addition, the bias circuits 120 and 121 can also control the current amounts of the bias currents Ibias1 and Ibias2 by adjusting the voltage values of the voltages Vb1 and Vb2 (or the current values of the currents Ib1 and Ib2), respectively.

Next, taking the previous stage (the amplifier 110 and the bias circuit 120) as an example, the suppression of the variation of the current amounts of the bias currents Ibias1 and Ibias2 will be described.

Generally speaking, in a bias circuit composed of an emitter follower, the current amount of the bias current may vary due to the influence of the RF signal. Specifically, when the symbols shown in FIG. 1 are used for convenience, when the RF signal RF1 supplied to the base of the transistor Q1 is large, a negative current is generated in the bias current (from the transistor Q1 The base of the current flows to the emitter side of the transistor Q5). Although this negative current flows from the emitter of the transistor Q5 toward the base, it is blocked due to the rectification characteristics of the PN connection between the base/emitter of the transistor Q5. In this way, since the negative part of the bias current is cut off, as the level of the RF signal increases, the average value of the emitter voltage (voltage Vbb) of the transistor Q5 increases, and the average value of the bias current Ibias1 also increases.

To solve this problem, for example, in the structure disclosed in Patent Document 1, a transistor that provides a bias current is stacked, and it is desired to cause a negative current to flow into the upper transistor (equivalent to transistor Q5 in FIG. 1). Part of it flows to the lower transistor. However, in this structure, the impedance of the collector of the lower transistor as viewed from the emitter of the upper transistor is very high. Therefore, it is considered that it is difficult for current to flow to the lower transistor.

Furthermore, in the structure disclosed in Patent Document 1, by providing a current path for passing a negative current between the base and the emitter of the upper transistor, the negative part of the bias current is not cut off. However, in the above-mentioned structure, since a capacitor is used as a path for passing a negative current, the path has frequency characteristics. Therefore, for example, as seen in the multi-band technology, when the frequency band of the RF signal spreads over a wide range, it is considered that the characteristics will vary with frequency.

Regarding this point, the power amplifier circuit 100 is designed such that the ratio of the emitter area of the transistor Q5 to the emitter area of the transistor Q1 in the front stage is greater than that of the emitter area of the transistor Q8 to the latter transistor Q2. The ratio of the emitter area. Here, the so-called area ratio refers to the area of the emitter of the transistor for bias current supply (equivalent to transistors Q5, Q8) divided by the emitter of the transistor for amplification (equivalent to transistors Q1, Q2) The value obtained from the area. For example, it is assumed that the number of units of the transistor Q1 in the previous stage is 4, while the number of units of the transistor Q5 is 3 in contrast. On the other hand, it is assumed that in the latter stage, for example, the number of cells of the transistor Q2 is 20, while the number of cells of the transistor Q8 is one. At this time, if the emitter area of each unit is equal, the ratio of the emitter area is (transistor Q5/transistor Q1)=3/4 in the front section, and (transistor Q8/transistor Q2)= in the latter section 1/20. In this way, in this embodiment, the ratio of the emitter area of the transistor for supplying bias current in the front stage to the emitter area of the transistor for amplification is larger than that in the latter stage.

Here, it is known that the output impedance of the transistor composed of the emitter follower is inversely proportional to the current amount of the emitter current. Therefore, when the total amount of emitter current is constant, the larger the emitter area of the transistor, the less current flowing per unit area of the emitter, and therefore the higher the output impedance. In this embodiment, since the ratio of the emitter area of transistor Q5 to the emitter area of transistor Q1 is greater than the ratio of the emitter area of transistor Q8 to the emitter area of transistor Q2, the emitter current When the total amount of Q5 is constant, the output impedance of the transistor Q5 becomes higher. Therefore, even if the level of the RF signal RF1 is large and the amplitude of the AC at the base of the transistor Q1 is large, the AC fluctuation of the current at the emitter of the transistor Q5 is suppressed. In this way, in this embodiment, since the detection performance of the RF signal of the transistor Q5 is degraded, the generation of a negative current is suppressed, and as a result, the increase in the average current amount of the bias current Ibias1 can be suppressed. In addition, with this, the increase in voltage Vbb at the emitter of transistor Q5 is also suppressed.

That is, in the power amplifier circuit 100, it is possible to suppress the variation of the current amount of the bias current Ibias1 without using a capacitor connected between the overlapping and the base-emitter. Therefore, compared with the result disclosed in Patent Document 1, the power amplifier circuit 100 can suppress the linear degradation of the gain regardless of the frequency band of the RF signal, and suppress the linear degradation of the gain in a wide frequency band.

In addition, although the emitter area of the transistor Q5 in the front stage is not particularly limited, for example, it is preferably more than half of the emitter area of the transistor Q1 for amplification. That is, for example, when the number of units of the transistor Q1 is 4, the number of units of the transistor Q5 is preferably 2 or more.

Furthermore, in the latter stage, if the emitter area of the transistor Q8 of the bias circuit 121 is made too large, the power may be insufficient with respect to the power amplification level of the transistor Q2 for amplification. Therefore, it is preferable that the emitter area of the transistor Q8 at the rear stage is smaller than the emitter area of the transistor Q5 at the front stage, for example. If the emitter area of the transistor Q8 is small, as the level of the RF signal increases, the average value of the bias current increases, and the gain may increase. Here, by reducing the gain in the front stage so that the increase in the gain in the later stage is cancelled, it is possible to improve the linearity when matching the front stage and the rear stage.

In addition, the power amplifier circuit 100 may include, for example, a three-stage amplifier. In this case, for example, the configuration of the bias circuit 120 described above may be applied to the second stage amplifier (first transistor), and the above-mentioned bias circuit 121 may be applied to the third stage amplifier (second transistor). The structure of this counteracts the increase in the gain of the amplifier in the third stage. Alternatively, the structure of the bias circuit 120 described above may be applied to the amplifier (first transistor) of the first stage, and the structure of the bias circuit 121 described above may be applied to the amplifier (second transistor) of the third stage. This cancels the increase in gain in the third stage amplifier.

FIG. 3 is a graph showing an example of the simulation result of the voltage Vbb in the power amplifier circuit according to the embodiment of the present invention. Specifically, the graph shown in FIG. 3 shows that the number of units of transistor Q1 and transistor Q5 is set to (Q1: Q5) = (4: 0.5), (4:1), (4: 2), ( 4:3), (4:4), (4:5), (4:6), the relationship between the voltage Vbb at the emitter of the transistor Q5 and the output power Pout. Here, it is assumed that each unit constituting the transistor Q1 includes two emitter layers, and the emitter area of each unit is 3.0×40×2=240 μm ² . On the other hand, it is assumed that each unit constituting the transistor Q5 includes 4 emitter layers, and the emitter area of each unit is 3.0×20×4=240 μm ² . In addition, the number of cells of the transistor Q5 is 0.5, which is a calculation result when the ^{emitter area is 3.0×20×2=120 μm 2.} In the graph shown in FIG. 3, the horizontal axis represents the output power Pout (dBm), and the vertical axis represents the voltage Vbb (V).

As shown in FIG. 3, if the number of cells of the transistor Q1 is 4 and the number of cells of the transistor Q5 is 2 or more, the increase in the voltage Vbb accompanying the increase in output power is suppressed. Therefore, it can be said that it is preferable that the emitter area of the transistor Q5 is more than half of the emitter area of the transistor Q1.

FIG. 4 is a graph showing an example of a simulation result of the gain of the first stage in the power amplifier circuit according to the embodiment of the present invention. Specifically, the graph shown in FIG. 4 shows that the number of units of transistor Q1 and transistor Q5 is set to (Q1: Q5) = (4: 0.5), (4:1), (4: 2), ( 4:3), (4:4), (4:5), (4:6), when the number of units of transistor Q2 and transistor Q8 is set to (Q2: Q8) = (20: 2) , The relationship between the gain in the transistor Q1 in the previous section and the output power Pout. Here, it is assumed that each unit constituting the transistor Q2 has two emitter layers, and the emitter area of each unit is 3.0×40×2=240 μm ² . On the other hand, it is assumed that each unit constituting the transistor Q8 includes 4 emitter layers, and the emitter area of each unit is 3.0×20×4=240 μm ² . In addition, regarding the transistor Q1 and the transistor Q5, the conditions are the same as the simulation shown in FIG. 3 described above. In the graph shown in FIG. 4, the horizontal axis represents the output power Pout (dBm), and the vertical axis represents the gain (dB) of the transistor Q1. In addition, for reference, an example of the gain of the transistor Q2 in the latter stage is indicated by a broken line.

As shown in Fig. 4, even in the case where the emitter area of the transistor Q5 is arbitrary, the gain of the transistor Q1 in the front stage decreases gradually as the output power increases. On the other hand, the latter transistor Q2 can be set to increase the gain as the output power increases as shown in Figure 4. Therefore, it can be said that by matching these gain characteristics, the linear deterioration of the gain of the power amplifier circuit 100 can be suppressed.

5 is a graph showing an example of simulation results of ACLR characteristics in the power amplifier circuit of the comparative example of the present invention. 6 is a graph showing an example of simulation results of ACLR characteristics in the power amplifier circuit according to an embodiment of the present invention. The comparative example is a structure in which a capacitor is connected between the base and the emitter of the transistor Q5 shown in FIG. 1. Figures 5 and 6 show the adjacent channel leakage power ratio (Adjacent Channel Leakage Ratio: ACLR) when the power supply voltage is set to 3.4V and the frequency of the RF signal is set to 824MHz, 849MHz, 880MHz, 915MHz at room temperature The relationship between characteristics and output power Pout. In the graphs shown in FIGS. 5 and 6, the horizontal axis represents output power Pout (dBm), and the vertical axis represents ACLR (dBc).

As shown in FIG. 5, in the comparative example, it can be seen that the ACLR characteristic varies with the frequency band of the RF signal. Especially in the region where the level of output power is medium to small, the deviation of the characteristics is significant, which is considered to be the deterioration of the linearity.

On the other hand, as shown in FIG. 6, it can be seen that any frequency band in the power amplifier circuit 100 exhibits the same ACLR characteristic, and the deviation of the ACLR characteristic can be reduced compared to the comparative example. In addition, it can be seen that in a region where the level of output power is small or medium, compared to the comparative example, the ACLR is small, and the linearity is improved. In this way, according to the present embodiment, it is possible to suppress degradation of linearity in a wide frequency band.

Above, the exemplary embodiment of the present invention has been described. The power amplifier circuit 100 includes transistors Q1 and Q2 for amplifying and transistors Q5 and Q8 for supplying bias current. The emitter area of the transistor Q5 has a larger ratio to the emitter area of the transistor Q1 than that of the transistor Q8. The ratio of the pole area to the emitter area of the transistor Q2. As a result, since the output impedance of the transistor Q5 becomes high, it is possible to degrade the RF signal detection performance of the transistor Q5 without using an element having frequency characteristics such as a capacitor. Therefore, according to the power amplifier circuit 100, it is possible to suppress the linear deterioration of the gain in a wide frequency band.

In addition, in the power amplifier circuit 100, the emitter area of the transistor Q5 is more than half of the emitter area of the transistor Q1. Thereby, the increase in voltage Vbb at the emitter of transistor Q5 accompanying the increase in output power is suppressed. Therefore, it is possible to suppress the linear deterioration of the gain.

Moreover, in the power amplifier circuit 100, the emitter area of the transistor Q5 is larger than the emitter area of the transistor Q8. Thereby, it is possible to maintain the necessary capacity in the latter stage and to match the gain characteristics of the transistor Q1 in the previous stage and the transistor Q2 in the latter stage to improve linearity.

The respective embodiments described above are for facilitating the understanding of the present invention, and are not intended to limit the interpretation of the present invention. The present invention can be changed or improved without departing from its gist, and its equivalent parts are also included in the present invention. That is, a part obtained by a person skilled in the art appropriately implementing design changes for each embodiment is included in the scope of the present invention as long as it has the characteristics of the present invention. For example, the various elements and their configuration, materials, conditions, shapes, dimensions, and the like provided in each embodiment are not limited to the exemplified contents, and can be changed as appropriate. In addition, each element provided in each embodiment can be combined as long as it is within a technically possible range, and a part obtained by combining the above is also included in the scope of the present invention as long as it includes the characteristics of the present invention.

100‧‧‧Power amplifier circuit

110、111‧‧‧Amplifier

120、121‧‧‧Bias circuit

Q1~Q8‧‧‧Transistor

R1~R4‧‧‧Resistive element

C1~C4‧‧‧Capacitor

RF1~RF3‧‧‧RF signal

Ibias1, Ibias2‧‧‧bias current

Claims (3)

A power amplifier circuit includes: a first transistor that amplifies a first signal to output a second signal; a second transistor that amplifies a signal corresponding to the second signal to output a third signal; and a third transistor that amplifies the signal corresponding to the second signal to output a third signal; 1 The base of the transistor provides the first bias current or voltage; and the fourth transistor provides the second bias current or voltage to the base of the second transistor: and the emitter area of the third transistor is opposite to The ratio of the emitter area of the first transistor is greater than the ratio of the emitter area of the fourth transistor to the emitter area of the second transistor; the power amplifier circuit is in the base of the first transistor -No capacitor is connected between the emitters of the aforementioned third transistor. The power amplifier circuit according to claim 1, wherein the emitter area of the third transistor is more than half of the emitter area of the first transistor. The power amplifier circuit according to claim 1 or 2, wherein the emitter area of the third transistor is larger than the emitter area of the fourth transistor.

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