TWI717727B - Method of placing macro cells - Google Patents
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本發明係有關巨集(macro)設置,特別是關於一種基於模擬演化(simulated-evolution-based)的巨集優化(refinement)方法。The present invention relates to macro settings, and particularly relates to a method of refinement based on simulated-evolution-based macros.
巨集(macro)的設置對於線長(wirelength)與可繞度(routability)具有顯著的影響,且會影響到標準元件(standard cell)的擺設位置。由於巨集的尺寸遠大於標準元件,因此巨集的設置所產生的問題遠複雜於標準元件的設置。當許多巨集預設(pre-place)於晶片而造成障礙,問題將變得更複雜。當巨集無法設置於預定位置時,會造成更長線長與嚴重的繞線壅塞。因此,巨集通常是由有經驗的工程師以手動方式來進行設置的。當現代的單晶片系統(SoC)的巨集數目變得很大時,依賴有經驗工程師以進行大規模的巨集設置,將使得巨集的設置變得沒有效率。The setting of the macro has a significant effect on the wirelength and routability, and it also affects the placement of standard cells. Since the size of the macro is much larger than the standard component, the problems caused by the macro setting are far more complicated than the standard component setting. When many macros are pre-placed on the chip and cause obstacles, the problem becomes more complicated. When the macro cannot be set in the predetermined position, it will cause longer cable length and serious winding congestion. Therefore, the macro is usually set manually by an experienced engineer. When the number of macros in modern SoC systems becomes very large, relying on experienced engineers to perform large-scale macro settings will make the macro settings inefficient.
為了解決此問題,先前有人提出了模擬退火(simulated annealing)演算法。然而,此演算法需要耗費很多的時間。鑑於傳統方法無法有效改善巨集的設置,因此亟需提出一種新穎的巨集設置機制,用以有效地設置巨集。To solve this problem, someone previously proposed a simulated annealing algorithm. However, this algorithm takes a lot of time. Since traditional methods cannot effectively improve the setting of macros, it is urgent to propose a novel macro setting mechanism to effectively set macros.
鑑於上述,本發明實施例的目的之一在於提出一種基於模擬演化的巨集優化方法,其執行速度較快於傳統方法。In view of the foregoing, one of the objectives of the embodiments of the present invention is to propose a macro optimization method based on simulation evolution, which performs faster than traditional methods.
本發明實施例所提出之基於模擬演化的巨集優化方法包含以下步驟。評估以得到每一個設置的巨集元件的評分,且產生亂數。決定評分是否符合預設條件。如果巨集元件相應的評分符合預設條件,則讓巨集元件進入佇列。根據佇列之巨集元件的評分,排序並設置柱列中的巨集元件。The macro optimization method based on simulated evolution proposed in the embodiment of the present invention includes the following steps. Evaluate to get the score of each macro component set, and generate random numbers. Decide whether the score meets the preset conditions. If the corresponding score of the macro component meets the preset conditions, the macro component is put into the queue. According to the scores of the macro components in the queue, sort and set the macro components in the column.
第一A圖顯示基於角落縫合(corner-stitching-based)的巨集合法化(macro legalization)方法100的流程圖,第一B圖例示晶片(或微晶片)101的俯視圖,其表面可置放巨集元件。第二A圖至第二C圖顯示執行第一A圖之巨集合法化方法100的例子。值得注意的是,也可使用異於巨集合法化方法100(第一A圖)的其他巨集合法化方法來初始設置巨集於晶片101上。The first A shows a flowchart of a corner-stitching-based
於步驟10,決定並配置一個設置區域(placement region)102於晶片101上,用以設置包含複數巨集元件的巨集群(macro group)。在一實施例中,設置區域102係使用遞迴分割(recursive partition)演算法來決定。接著,於步驟11,根據預置(pre-placed)元件103,於晶片101上產生複數(長方形)空的磚(tile)104。如第一B圖所例示,晶片101上設有預置元件103(如斜線區域所示),且包含有未被預置元件103覆蓋的複數(長方形)空的磚104。空的磚104的水平邊界係由相鄰預置元件103的水平邊界延伸而得到。In
接著,對於每一待設置的巨集元件,執行步驟12~16。於步驟12,使用角落縫合(corner stitching)方法以計數設置區域102內磚104的數目,其細節可參考奧斯特豪特(J. K. Ousterhout)所提出的“角落縫合:超大型積體電路佈局工具的資料結構技術(Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools)”,發表於1984年電機電子工程師學會電腦輔助設計會刊(IEEE TCAD),第3冊,第1號,第87~100頁。如第二A圖所例示,設置區域102內的磚104分別標記為1、2、4、7、8、9、11。Then, for each macro element to be set, steps 12-16 are performed. In step 12, a corner stitching method is used to count the number of
於步驟13,修剪(trim)(或切除)超出設置區域102邊界的磚104的區域,如第二B圖所例示。In
於步驟14,如第二C圖所例示,對於每一個磚104(例如磚8),如果巨集元件的尺寸未大於磚104,將待設置巨集元件(如點區域所示)擺置於磚104的各個角落,並評估相應擺置成本(packing cost)。對於所有磚104,評估相應擺置成本。藉此,將巨集元件設置於最小百置成本的相應位置,並更新該位置的資料(步驟17)。In
如果沒有磚104可容納巨集元件(步驟105),則於步驟16增大設置區域102,再針對增大後的設置區域102重複執行步驟12~14。If there is no
第三圖顯示本發明實施例之基於模擬演化(simulated-evolution-based)的巨集優化(refinement)方法200(以下簡稱巨集優化方法)的流程圖。巨集優化方法200可執行於巨集合法化(例如第一A圖所示的角落縫合的巨集合法化方法100)之後。The third figure shows a flowchart of a simulated-evolution-based macro refinement method 200 (hereinafter referred to as a macro optimization method) according to an embodiment of the present invention. The
於步驟21,評估以得到每一個設置的巨集元件的評分。接著,於步驟22,常態化(normalize)該評分使其位於預設範圍內,例如介於0與1之範圍,因而產生常態評分。In
於步驟23,產生亂數,該產生的亂數也是位於相同的預設範圍內,例如介於0與1之範圍。接著,於步驟24,決定該亂數是否大於所產生的亂數(或者,概括來說,決定該亂數是否符合預設條件)。如果步驟24的結果為肯定的,則讓巨集元件進入佇列(enqueue)(步驟25),且根據常態評分的大小,排序並設置柱列中的巨集元件(步驟26);否則,流程跳過步驟25與步驟26。對於所有設置的巨集元件,重複執行步驟23~25。In
在本實施例中,使用評分函數F i以產生上述的評分,可表示如下: 其中D代表(待優化的)巨集元件與所屬巨集群之重心(gravity)的距離;如果巨集群僅包含單一巨集元件,該巨集元件設置於重心處,則D的值為零;W代表待優化的巨集元件的相應線長(wirelength);λ為使用者設定值;k為第三圖之流程的執行序。值得注意的是,於每一次執行後,重新決定巨集群的重心。 In this embodiment, the score function F i is used to generate the aforementioned score, which can be expressed as follows: Where D represents the distance between the macro element (to be optimized) and the gravity of the macro cluster to which it belongs; if the macro cluster contains only a single macro element and the macro element is set at the center of gravity, the value of D is zero; W Represents the corresponding wire length of the macro component to be optimized; λ is the value set by the user; k is the execution sequence of the process in the third figure. It is worth noting that after each execution, the center of gravity of the giant cluster is determined again.
根據本實施例的特徵之一,第二項的對數(log)函數係用以調整評分使其變大,使得步驟24的預設條件(例如,評分大於所產生亂數)更容易符合。對於最初的數個執行序的值k,由於對數函數產生很小的值,因此第二項的值變得很大,因此當k值很小時,距離D對於評分的值具有影響。然而,當k值增加時,對數函數產生較大且穩定的值。因此,第二項的值變得很小,使得距離D對於評分的值不具有影響。換句話說,執行序的值k愈大,距離D對於評分值的影響愈小。According to one of the characteristics of this embodiment, the log function of the second term is used to adjust the score to make it larger, so that the preset condition of step 24 (for example, the score is greater than the random number generated) is more easily met. For the first few execution order values k, because the logarithmic function produces a very small value, the value of the second term becomes very large, so when the value of k is very small, the distance D has an influence on the value of the score. However, when the value of k increases, the logarithmic function produces a larger and stable value. Therefore, the value of the second term becomes very small, so that the distance D has no influence on the value of the score. In other words, the larger the execution order value k, the smaller the influence of the distance D on the score value.
以上所述僅為本發明之較佳實施例而已,並非用以限定本發明之申請專利範圍;凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾,均應包含在下述之申請專利範圍內。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; all other equivalent changes or modifications made without departing from the spirit of the invention should be included in the following Within the scope of patent application.
100 基於角落縫合的巨集合法化方法
11 配置設置區域
12 計數磚的數目
13 修剪磚
14 評估擺置成本
15 判斷擺置是否可行
16 增大設置區域
17 更新資料
101 晶片
102 設置區域
103 預置元件
104 磚
200 基於模擬演化的巨集優化方法
21 評估以得到每一設置的巨集元件的評分
22 常態化評分
23 產生亂數
24 判斷評分是否大於亂數
25 進入佇列
26 排序並設置巨集元件
100 Large collection method based on
第一A圖顯示基於角落縫合的巨集合法化方法的流程圖。 第一B圖例示晶片的俯視圖,其表面可置放巨集元件。 第二A圖至第二C圖顯示執行第一A圖之巨集合法化方法的例子。 第三圖顯示本發明實施例之基於模擬演化的巨集優化方法的流程圖。 The first figure A shows the flow chart of the macro set normalization method based on corner stitching. Fig. 1B illustrates a top view of a wafer on which a macro element can be placed. The second A to the second C show an example of executing the macro set normalization method of the first A. The third figure shows a flowchart of a macro optimization method based on simulated evolution according to an embodiment of the present invention.
200 基於模擬演化的巨集優化方法
21 評估以得到每一設置的巨集元件的評分
22 常態化評分
23 產生亂數
24 判斷評分是否大於亂數
25 進入佇列
26 排序並設置巨集元件
200 Macro optimization method based on
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US7155440B1 (en) * | 2003-04-29 | 2006-12-26 | Cadence Design Systems, Inc. | Hierarchical data processing |
US20090063956A1 (en) * | 2007-08-27 | 2009-03-05 | International Business Machines Corporation | Apparatus and system for an automated bidirectional format transform |
US20120099658A1 (en) * | 2009-08-14 | 2012-04-26 | Samsung Electronics Co., Ltd. | Method and apparatus for encoding video, and method and apparatus for decoding video |
TWI612435B (en) * | 2016-12-20 | 2018-01-21 | 財團法人成大研究發展基金會 | Method of macro placement and a non-transitory computer readable medium thereof |
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US7155440B1 (en) * | 2003-04-29 | 2006-12-26 | Cadence Design Systems, Inc. | Hierarchical data processing |
US20090063956A1 (en) * | 2007-08-27 | 2009-03-05 | International Business Machines Corporation | Apparatus and system for an automated bidirectional format transform |
US20120099658A1 (en) * | 2009-08-14 | 2012-04-26 | Samsung Electronics Co., Ltd. | Method and apparatus for encoding video, and method and apparatus for decoding video |
TWI612435B (en) * | 2016-12-20 | 2018-01-21 | 財團法人成大研究發展基金會 | Method of macro placement and a non-transitory computer readable medium thereof |
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