TWI612435B - Method of macro placement and a non-transitory computer readable medium thereof - Google Patents

Abstract

A method for placing a macro circuit includes dividing a whole region of a semiconductor wafer into a plurality of sub-regions; determining a placement order of the plurality of movable macro circuits of the sub-region; and for a movable macro circuit, capturing a plurality of sub-regions The search point of the block; determine the feasible area related to the search point; place the movable macro circuit in the feasible area; evaluate the legal cost function; and determine whether the value of the legal cost function is less than the preset threshold.

Description

Macro circuit arrangement method and non-transient computer readable medium

The present invention relates to an electronic design automation (EDA), and more particularly to a method of placing a macro.

Electronic Design Automation (EDA) is one of the tools for designing integrated circuits. Wafer designers use electronic design automation tools to design and analyze semiconductor wafers. Placement is a necessary step in the automation of electronic design to dispatch various circuit components (such as macrocircuits) in the wafer area. To ensure performance requirements, placers must optimize criteria such as bus length, timing, congestion, power, and placement execution time.

Conventional electronic design automated placement methods are incapable of effectively processing floating pre-placed macro circuits that are not adjacent to the wafer edge or that cannot be connected to the wafer edge by pre-positioning the macro circuit. In addition, traditional electronic design automation placement methods cannot handle large (eg, more than ten) macro circuits. When there are many pre-arranged macro circuits or / and floating pre-arranged macro circuits, the macro circuit placement problem will become more serious.

In view of the fact that the traditional electronic design automation placement method can not be effectively implemented, it is urgent to propose a novel macro circuit legalizer, which can effectively handle the floating pre-arranged macro circuit and a large number of pre-arranged macro circuits.

In view of the above, one of the objects of the embodiments of the present invention is to provide a method for placing a macro circuit and a macro circuit legal device, which are effectively applicable to a large-scale circuit arrangement of a large design and can reduce execution time.

According to an embodiment of the present invention, a method for placing a macro circuit includes dividing a whole region of a semiconductor wafer into a plurality of sub-regions; determining a placement order of the plurality of movable macro circuits of the sub-region; and extracting a sub-region for a movable macro circuit The search point of the inner complex number block; determining the feasible area related to the search point; placing the movable macro circuit in the feasible area; evaluating the legal cost function; and determining whether the value of the legal cost function is less than a preset threshold.

FIG. 1A is a flow chart showing a method 100 of placing a macro circuit according to an embodiment of the present invention. The method for placing a macro circuit of the present embodiment (hereinafter referred to as the placement method) 100 can be applied to a macro circuit arrangement or a macro circuit legal device for dispatching a macro circuit on a chip to avoid macros. The overlap between the circuits. The method 100 of the present embodiment can be performed using a computer controlled by program instructions within a non-transitory computer readable medium.

In step 11, one or more placed blocks are replaced by one or more placement blocks in the entire area of the semiconductor wafer. If there is no placed block, it will not be replaced. The second A diagram illustrates an area of a semiconductor wafer (hereinafter referred to as an area) 200 including a placement block such as a floating placement block 201 or a non-floating placement block 202. The second B diagram illustrates the addition of the placement obstacle 203 to cover the placement block. The placement obstacle 203 is generally rectangular. The placement obstacle 203 is combined and subdivided into non-overlapping (rectangular) obstacles. The second C-picture shows the area 200 in which the placement obstacle 203 is joined and divided. It should be noted that the placement blocks (eg, the placement block 204) are not necessarily covered by the placement obstacle 203, and thus the placement blocks are not replaced by the placement obstacle 203.

Next, in step 12, the entire area of the semiconductor wafer is divided into a plurality of sub-regions. The third A diagram and the third B diagram illustrate the entire region 200 of the pre- and post-segment placement blocks (shown by oblique lines) and the movable blocks (not shown by oblique lines), respectively. In this embodiment, the partitioning can be performed according to the utilization constraint disclosed in the following document: title "MAPLE: Multilevel Adaptive PLacEment for Mixed-Size Designs", Myung-Chul Kim et al., publication "Proceedings of the 2012" ACM international symposium on International Symposium on Physical Design", pp. 193-200. In this embodiment, the segmentation is performed according to the center of gravity of the movable region circuit of the sub-region, the sub-region, and the sub-region. In general, the size of the segmentation sub-regions may be different, as illustrated in Figure 3B. The subsequent steps of the placement method 100 are performed for segmenting sub-regions. The processing of the other divided sub-areas can be performed according to the same placement method 100.

In step 13, a grid graph is constructed in the sub-region to record a feasible placement position. In an embodiment, if the grid is covered by the placement block, the value of the corresponding grid is "1", otherwise the value is "0". The fourth A diagram illustrates a sub-area 41 having four placement blocks (shown by oblique lines). The fourth B-picture shows a corresponding trellis diagram of the sub-area 41 of the fourth A-picture, in which the value of the lattice (shown by the oblique line) covered by the placed block is "1", and the grid not covered by the placed block (non-slashed) The value shown is "0".

In step 14, the packing sequence of the plurality of movable macro circuits is determined. The fifth diagram is exemplified in the sub-area 41 of the fourth A diagram to determine the arrangement order of the four movable macro circuits m ₁ , m ₂ , m ₃ , and m ₄ . In the present embodiment, the movable macro circuit is sorted according to the calculated value of the packing cost function, and thus the arrangement order is determined. In one example, the placement order of the movable macrocircuit is determined by its area, position, and aspect ratio. In this example, the placement cost function of the movable macro circuit m _i can be expressed as: cost(m _i )= αa _i + β l _i + γt _i where a _i is the area of the macro circuit m _i , l _i is The reciprocal of the distance between the initial position of the macro circuit m _i and the lower left point of the sub-region, t _i is the aspect ratio of the macro circuit m _i , and α, β, γ are corresponding weights.

In the present embodiment, the lower left point is taken as the origin of the sub-area. When a point moves in the positive direction (for example, to the right) in the horizontal direction, its x coordinate becomes larger; when the point moves in the vertical direction (for example, upward), its y coordinate becomes larger. The movable macro circuit with the calculated value of the larger placement cost function will be processed first. Taking the fifth figure as an example, the arrangement order of the macro circuits m ₁ , m ₂ , m ₃ , and m ₄ is Q={m ₂ , m ₃ , m ₁ , m ₄ }. Therefore, the subsequent steps (for example, steps 15 to 17) will be sequentially executed in accordance with the placement order Q.

In step 15, the search points of all the placed blocks are retrieved. In the present specification, the so-called search point refers to a possible placement position of the movable macro circuit. In this embodiment, for each of the placed blocks, the relative two points of the placed block are captured, and the projected points of the opposite two points are extracted. In detail, for each placement block, four search points S ₁ , S ₂ , S ₃ , and S ₄ are taken as follows: S ₁ : the upper left point of the placed block; S ₂ : S ₁ adjacent Projection of the edge of the left-handed block or the left edge of the sub-area; S ₃ : the lower right point of the placed block; and S ₄ : S ₃ at the edge of the adjacent lower-arranged block or the lower edge of the sub-area projection.

Then, in the order of bottom-up and left-to-right, the search points of all the placed blocks are sorted. The sixth A diagram illustrates the search points captured by the placement block 61. Figure 6B shows the search points after all the placed blocks of Figure 6A have been sorted (and rearranged).

In step 16, the feasible area associated with the search point is determined such that the macro circuit can be placed in the determined feasible area. The first B diagram shows a detailed flow chart of step 16 of the first A diagram, the order of execution of which steps can be adjusted. For example, step 161 can be performed before, after, or at the same time as step 162.

In step 161, at least one horizontal sweeping line is constructed that passes through the bottom (or first) edge of each of the tiles and horizontally passes through the sub-regions. In a similar situation, at least one vertical scan line is constructed that passes through the left (or second) edge of each tile and passes vertically through the sub-region. The seventh A diagram illustrates the horizontal scanning line 71 and the vertical scanning line 72 in a region including six placement blocks b ₁ to b ₆ .

In step 162, a search point is given, and it is vertically forward (for example, up) until it hits the placement block. At this time, the y coordinate of the search point (along with its x coordinate) is used as a top (or first). )point. If no placement block is encountered, the y coordinate of the top edge of the sub-region (along with its x coordinate) acts as a vertex. In a similar situation, the search point is moved horizontally forward (eg, to the right) until it hits the placed block, at which point the x coordinate of the search point (along with its y coordinate) acts as a right (or second) point. If no placement block is encountered, the x coordinate of the right edge of the sub-region (along with its y coordinate) is used as the right point. The vertex and the right point are relative points, which define the largest (rectangular) area, which is determined in subsequent steps to determine the feasible area associated with the search point. B shows the points of view of a seventh S VII A of FIG related _i P _top right vertex point P _right.

In step 163, the intersection of the horizontal scan line and the vertical scan line is obtained in the largest area defined by the vertex and the right point (but the same y coordinate or x coordinate as the search point is excluded). The seventh C-picture shows the intersections r ₁ to r ₆ in the maximum area defined by the vertices of the seventh B-picture and the right point. In the present embodiment, the intersections are ordered in a top-down and left-to-right order.

In step 164, the feasible area defined by the search point and the intersection is determined, and the touched block cannot be touched. Continuing to refer to the seventh C diagram, the search point Si and the feasible area defined by the intersections r ₂ and r ₃ respectively encounter the placement block b ₅ , so the areas must be discarded. In addition, small areas included in large areas must also be discarded. Continuing to refer to the seventh C map, the search area Si and the smaller area defined by the intersections r ₄ and r ₅ are respectively included in the larger area defined by the search point Si and the intersection r ₆ , thus discarding the smaller area. Thereby, the search point Si and the intersections r ₁ and r ₆ are respectively defined as feasible regions.

Returning to the first A picture, in step 17, the macro circuit is placed in the feasible area determined in step 16. The eighth A diagram illustrates the placement of a macro circuit in the feasible area 81. The width or/and height of the macro circuit can be lengthened to make it unnecessary to create a narrow channel after the macro circuit is placed, thereby reducing unnecessary searching of other macro circuits. The eighth B diagram illustrates that the macro circuit m _i (having a width W _i ) is placed in the feasible region f _j and its width is lengthened by W(f _j ).

Repeat steps 15 through 17 above for each macro circuit. When all of the macro circuits have been placed (step 18), the flow proceeds to step 19 to determine if the placement is feasible. If the placement is not feasible, the flow returns to step 14, otherwise the flow proceeds to step 20. At step 20, a legalizing cost function is evaluated. In this embodiment, the legal cost function can be expressed as follows: cost(s)= θO + μD + ωT + δC + εW where O is the total area of overlap between the two macro circuits, and D is the total displacement of the macro circuit. T is the total thickness of the placement block in the sub-area, C is the dead space, W is the semi-circumference line length (HPWL), and θ, μ, ω, δ, ε are the corresponding weights.

The ninth A diagram illustrates a method of placing the macro circuits m ₁ to m ₄ in the sub-area of the fifth figure. In this example, an invalid space is generated. The ninth B diagram illustrates another method of placing the macro circuits m ₁ to m ₄ in the sub-area of the fifth figure. In this example, the thickness of the macro circuit arrangements and m is less than ₁ ~ m ₄ m thickness 9th A circuit arrangements and macro FIG ₁ ~ m _4, and no dead space.

Next, in step 21, it is determined whether the value of the legal cost function is less than a preset threshold. If yes, the best legalization is obtained and the process is stopped, otherwise the process returns to step 13.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

100‧‧‧Magic circuit placement method

11‧‧‧Replace the placement block with obstacles

12‧‧‧Division of the area into sub-areas

13‧‧‧Building a grid map

14‧‧‧Determining the placement order

15‧‧‧Select search points

16‧‧‧Determining a viable area

161‧‧‧Build horizontal and vertical scan lines

162‧‧‧Determining the apex and the right point

163‧‧‧Get the intersection

164‧‧‧Determining a viable area

17‧‧‧ Place the giant circuit in the feasible area

18‧‧‧All macro circuits have been placed

19‧‧‧ Placed as feasible

20‧‧‧Assessing the legal cost function

21‧‧‧ legal cost function is less than the critical value

200‧‧‧Semiconductor wafer area

201‧‧‧ Floating Placement Block

202‧‧‧Non-floating placement block

203‧‧‧ Place obstacles

204‧‧‧ Placement block

41‧‧‧Sub-area

61‧‧‧ Placement block

71‧‧‧ horizontal scanning line

72‧‧‧Vertical scan line

81‧‧‧ Feasible area

m ₁ ~m ₄ ‧‧‧ movable macro circuit

S ₁ ~S ₆ ‧‧‧ Search points

S _i ‧‧‧ search point

b ₁ ~b ₆ ‧‧‧ Placement block

P _top ‧‧‧ apex

P _right ‧‧‧right point

r ₁ ~r ₆ ‧‧‧ intersection

x ₁ ~x ₅ ‧‧‧x coordinates

y ₁ ~y ₂ ‧‧‧y coordinates

f _j ‧‧‧ viable area

m _i ‧‧‧Giant circuit

w _i ‧‧‧width

m(f _j )‧‧‧Width

FIG. 1A is a flow chart showing a method of placing a macro circuit according to an embodiment of the present invention. The first B diagram shows a detailed flow chart of step 16 of the first A diagram. The second A diagram illustrates an area of a semiconductor wafer including a placement block. The second B diagram illustrates the inclusion of an obstacle to cover the placed block. The second C-picture shows the area where the placed obstacle is combined and divided. The third A picture and the third B picture respectively illustrate the entire area of the moving block before and after the splitting. The fourth A diagram illustrates a sub-area having four placed blocks. The fourth B-picture shows the corresponding trellis diagram of the sub-area of the fourth A-picture. The fifth figure illustrates the arrangement order of the four movable macro circuits in the sub-area of the fourth A picture. Figure 6A illustrates a search point captured by a placement block. Figure 6B shows the search points after all the placed blocks of Figure 6A have been sorted (and rearranged). Figure 7A illustrates a horizontal scan line and a vertical scan line in an area containing six placed blocks. Figure 7B shows the vertices and right points associated with the search point of Figure 7A. The seventh C-picture shows the intersection of the apex of the seventh B-picture and the maximum area defined by the right point. Figure 8A illustrates a possible area. Figure 8B illustrates the placement of a macro circuit in a feasible area and lengthening its width. Figure 9A illustrates a method of placing a macro circuit in a sub-area of the fifth figure. The ninth B diagram illustrates another way of placing the macro circuit in the sub-area of the fifth figure.

100‧‧‧Magic circuit placement method

11‧‧‧Replace the placement block with obstacles

12‧‧‧Division of the area into sub-areas

13‧‧‧Building a grid map

14‧‧‧Determining the placement order

15‧‧‧Select search points

16‧‧‧Determining a viable area

17‧‧‧ Place the giant circuit in the feasible area

18‧‧‧All macro circuits have been placed

19‧‧‧ Placed as feasible

20‧‧‧Assessing the legal cost function

21‧‧‧ legal cost function is less than the critical value

Claims (16)

A method for placing a macro circuit includes: dividing an entire area of the semiconductor wafer into a plurality of sub-areas; determining a placement order of the plurality of movable macro circuits of the sub-area; and extracting a sub-area for a movable macro circuit a search point of the plurality of blocks; determining a feasible area associated with the search point; placing the movable macro circuit in the feasible area; evaluating a legal cost function; and determining whether the value of the legal cost function is less than a preset threshold The placement order of the movable macro circuits is determined according to the order, the position and the aspect ratio of the movable macro circuits. According to the method of placing a macro circuit according to claim 1, wherein the arrangement order of the movable macro circuits is determined according to a calculated value of a placement cost function, and the placement cost function is expressed as: Cost(m _i )=α a _i +β l _i +γ t _i where a _i is the area of the macro circuit m _i , and l _i is the distance between the initial position of the macro circuit m _i and the lower left point of the sub-area The reciprocal, t _i is the aspect ratio of the macro circuit m _i , and α, β, γ are the corresponding weights. According to the method for placing the macro circuit according to the first aspect of the patent application, for each of the placement blocks, the relative two points of the placement block are captured, and the projection points of the relative two points are extracted. According to the method for placing a macro circuit according to claim 3, wherein the search points S ₁ , S ₂ , S ₃ , and S _{4 of} the placement block are as follows: S ₁ : the placement block The upper left point; S ₂ : S _{1 is} the projection of the edge of the adjacent left-handed block or the left edge of the sub-area; S ₃ : the lower right point of the placed block; and S ₄ : S ₃ adjacent The projection of the edge of the sub-block or the lower edge of the sub-area. The method for placing a macro circuit according to claim 4, wherein the search points of the placement block are sorted in a bottom-up and left-to-right order. The method of placing a macro circuit according to claim 1, wherein the step of determining the feasible region comprises: constructing at least one horizontal scan line, passing each of the first edges of the block and horizontally passing the sub- Constructing at least one vertical scan line passing through the second edge of each of the blocks and vertically passing through the sub-area; vertically moving the search point until it hits the placed block, thereby generating a first point; Moving the search point horizontally until it hits the placement block, thereby generating a second point; and obtaining the horizontal scan lines and the vertical scan lines in the area defined by the first point and the second point The intersection; and the feasible area defined by the search point and the intersections, which cannot touch the placement block. According to the method of placing the macro circuit described in claim 6, the method further includes a step of sorting the intersections in a top-down and left-to-right order. According to the method for placing a macro circuit according to claim 6, wherein the search area and a small area defined by one intersection are included in a larger area defined by the search point and another intersection, Discard this smaller area. According to the method for placing a macro circuit according to the first aspect of the patent application, after the movable macro circuit is placed in the feasible area, the width or height of the movable macro circuit is lengthened to avoid a narrow channel. According to the method of placing a macro circuit according to claim 1, wherein the legal cost function is expressed as follows: cost(s)=θ O+μ D+ω 7T+δ C+ε W where O is a two-moving giant The total area of overlap between the collector circuits, D is the total displacement of the movable macro circuits, T is the total thickness of the movable macro circuits placed in the sub-area, C is the ineffective space, and W is the semi-circumference line Long, θ, μ, ω, δ, ε are the corresponding weights. According to the method for placing the macro circuit according to the first aspect of the patent application, before determining the placement order, a step is further included, and a grid map is constructed in the sub-area to record a feasible placement position. A non-transitory computer readable medium, comprising program instructions to control a computer to perform the steps of: dividing an entire area of the semiconductor wafer into a plurality of sub-areas; determining a placement order of the plurality of movable macro circuits of the sub-area; a macro circuit that captures a search point of a plurality of blocks in the sub-area; Determining a feasible area related to the search point; placing the movable macro circuit in the feasible area; evaluating a legal cost function; and determining whether the value of the legal cost function is less than a preset threshold; wherein the movable macro circuit The placement order is determined by the order of its area, position and aspect ratio. According to the non-transitory computer readable medium of claim 12, for each of the placement blocks, the relative two points of the placement block are captured, and the projection points of the relative two points are extracted. The non-transitory computer readable medium of claim 12, wherein the determining the feasible area comprises: constructing at least one horizontal scan line that passes through the first edge of each of the blocks and passes horizontally The sub-area; constructing at least one vertical scan line, passing each of the second edges of the block and vertically passing through the sub-area; vertically moving the search point until the frame is touched, thereby generating the first Pointing; moving the search point horizontally until it hits the placement block, thereby generating a second point; in the area defined by the first point and the second point, obtaining the horizontal scan lines and the vertical points The intersection of the scan lines; and the feasible area defined by the search point and the intersections, which cannot touch the placement block. According to the non-transitory computer readable medium of claim 12, after the movable macro circuit is placed in the feasible area, the width or height of the movable macro circuit is lengthened to avoid a narrow channel. According to the non-transitory computer readable medium described in claim 12, before determining the placement order, a step is further included, and a grid map is constructed in the sub-area to record a feasible placement position.