TWI717062B - Patterning method - Google Patents

Abstract

A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of periphery openings surrounding a center opening in the first spacer. A rounding process is performed to round the periphery openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.

Description

Patterning method

The present invention relates to a patterning method, and particularly relates to a method for manufacturing a landing pad structure.

With the advancement of science and technology, all kinds of electronic products are developing towards the trend of light, thin and short. Under this trend, the critical size of DRAM is also gradually shrinking, which causes the capacitor contact window and the landing pads under it to become more and more dense, which in turn causes many problems, such as the inconsistency of the shape of each landing pad and the formation between adjacent landing pads. Undesired bridge (undesired bridge) etc. In addition, when the integration degree of the landing pad increases, the manufacturing process of the landing pad becomes more and more complicated, which in turn leads to a smaller process window. Therefore, while those skilled in the art are committed to improving the integration of the capacitor contact window and the land pad underneath, it is also necessary to consider the process margin and the device yield.

The present invention provides a patterning method, which can manufacture a plurality of semiconductor structures of uniform shape, so as to improve the integration degree of semiconductor structures in a unit area.

The present invention provides a patterning method, which can increase the integration degree of the semiconductor structure, increase the process margin of the semiconductor structure and improve the device yield.

The present invention provides a patterning method, the steps of which are as follows. A conductor layer, a first nitrogen-containing material layer, a first carbon-containing material layer, a second nitrogen-containing material layer, a second carbon-containing material layer, and a photoresist pattern are sequentially formed on the substrate. Using the photoresist pattern as a mask, a part of the second carbon-containing material layer is removed to form a first mask pattern. A first gap wall is formed on the side wall of the first mask pattern. The first mask pattern is removed to form a central opening and a plurality of peripheral openings surrounding the central opening in the first spacer. Perform a rounding process to remove part of the second nitrogen-containing material layer to form a second mask pattern.

The present invention provides another patterning method, the steps of which are as follows. A target layer, a first layer, a second layer, a third layer, and a first mask pattern are sequentially formed on the substrate. A first gap wall is formed on the side wall of the first mask pattern. The first mask pattern is removed to form a plurality of central openings and peripheral openings surrounding the plurality of central openings in the first spacer. A rounding process is performed to round a plurality of peripheral openings to form a second mask pattern. Take the second mask pattern as the mask, and remove part of the second layer to form the third mask pattern. A second gap wall is formed in the third mask pattern. Remove the third mask pattern. Using the second spacer as a mask, part of the first layer and part of the target layer are removed.

The patterning method described in the following embodiments can be regarded as a manufacturing method of a semiconductor structure. The semiconductor structure can be a landing pad of a dynamic random access memory (DRAM) or a capacitor contact structure, but the invention is not limited to this.

1A and 2A, this embodiment provides a method for manufacturing a semiconductor structure, the steps of which are as follows. First, the substrate 100 is provided.

Specifically, as shown in FIG. 2A, the substrate 100 includes a unit cell region R1, a peripheral region R2, and a guard ring region R3 located between the unit cell region R1 and the peripheral region R2.

As shown in FIG. 2A, a composite layer stack is formed on the substrate 100, which sequentially includes a dielectric layer 102, a barrier layer 104, a conductor layer 106, a first nitrogen-containing material layer 108, and a first carbon-containing material layer from bottom to top. 110, a second nitrogen-containing material layer 112, a second carbon-containing material layer 114, an anti-reflection layer 116, and a photoresist pattern 118.

In an embodiment, the dielectric layer 102 may be a silicon nitride layer, which may be formed by chemical vapor deposition (CVD). The material of the barrier layer 104 may be a metal (for example, Ti, Ta, etc.), which may be formed by CVD. The material of the conductor layer 106 may be, for example, a metal (for example, W, Cu, AlCu, etc.), which may be formed by CVD. In one embodiment, the material of the first nitrogen-containing material layer 108 and the second nitrogen-containing material layer 112 is, for example, silicon nitride, silicon oxynitride, or a combination thereof, and the thickness of the first nitrogen-containing material layer 108 is about 30 nm to 50 nm, the thickness of the second nitrogen-containing material layer 112 is about 60 nm to 80 nm, which can be formed by CVD or atomic layer deposition (ALD). In an embodiment, the materials of the first carbon-containing material layer 110 and the second carbon-containing material layer 114 are, for example, diamond-like carbon, amorphous carbon film, and highly selective transparent ( High selectivity Transparency) film or a combination thereof, the thickness of which is about 70 nm to 100 nm, which can be formed by CVD. In one embodiment, the material of the anti-reflective layer 116 includes organic polymer, carbon or silicon oxynitride, etc., with a thickness of about 20 nm to 30 nm, which can be formed by CVD. In an embodiment, the material of the photoresist pattern 118 includes a positive photoresist, a negative photoresist, etc., which can be formed by a spin coating method and a development process.

It is worth noting that, as shown in FIG. 1A, the photoresist pattern 118 includes photoresist patterns 118a and 118b. The photoresist pattern 118a includes a plurality of island-shaped patterns separated from each other in the unit cell region R1. The photoresist pattern 118b includes a stripe pattern extending along the Y direction in the guard ring region R3. In addition, although the tangent line I-I' of FIG. 1A only crosses two photoresist patterns 118a, there are also a plurality of photoresist patterns 118a on a cross section different from the tangent line I-I' (which is shown as a dashed line).

1A-1B and 2A-2B, the photoresist pattern 118 is used as a mask, and a portion of the anti-reflection layer 116 and a portion of the second carbon-containing material layer 114 are removed to form a first mask pattern 214. In this case, as shown in FIG. 1B, the first mask pattern 214 replicates the photoresist pattern 118, which also includes the first mask patterns 214a and 214b. The first mask pattern 214a includes a plurality of island-shaped patterns separated from each other in the unit cell region R1. The first mask pattern 214b includes a stripe pattern extending along the Y direction in the guard ring region R3. In this embodiment, the second nitrogen-containing material layer 112 can be used as an etch stop layer for forming the first mask pattern 214. In addition, as shown in FIG. 2B, part of the anti-reflection layer 116a remains on the top surface of the first mask pattern 214.

1C, 2C, and 3, a first spacer material 120 is formed on the substrate 100 to conformally cover the top surface and sidewalls of the first mask pattern 214. In one embodiment, the first spacer material 120 includes a dielectric material, which can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The thickness is about 30 nm to 50 nm. form.

It is worth noting that, as shown in FIG. 1C, the first mask pattern 214a located in the unit cell region R1 is a columnar pattern arranged in the form of hexagonal closed packing (from the cross-sectional view of FIG. 2C) Or island pattern (from the top view 1C). Specifically, the distance D1 of the gap G1 between two adjacent first mask patterns 214a along the Y direction is smaller than the gap G2 between two adjacent first mask patterns 214a along the X direction. Distance D2. In this case, as shown in FIGS. 2C and 3, the first spacer material 120 has a protrusion 120p and a recess 120r. The protrusion 120p is located in the gap G1 between two adjacent first mask patterns 214a; and the recess 120r is located on both sides of the protrusion 120p, as shown in FIG. 2C. The top surface 120t1 of the protrusion 120p is higher than the top surface 120t2 of the recess 120r. In an embodiment, as shown in FIG. 1C, the recess 120r corresponds to the centroid C between three adjacent first mask patterns 214.

On the other hand, the distance D1 of the gap G1 between two adjacent first mask patterns 214a along the Y direction is also smaller than the distance D3 of the gap G3 between the first mask patterns 214a, 214b along the Y direction. . In this case, as shown in FIG. 3, the first spacer material 120 will fill the gap G1 but not the gap G3. Therefore, the top surface 120t1 of the first spacer material 120 filled in the gap G1 is higher than the top surface 120t3 of the first spacer material 120 filled in the gap G3.

Please refer to FIGS. 1C-1D, 2C-2D and FIGS. 3-4 to perform an etching process to remove part of the first spacer material 120, the anti-reflection layer 116a on the first mask pattern 214, and part of the second nitrogen-containing material Layer 112 to expose the top surface 214t of the first mask pattern 214. In this case, as shown in FIG. 2D, the first spacer 220 is formed on the sidewall of the first mask pattern 214. The height of the protrusion 120p (as shown in FIG. 3) is reduced to form a connecting part 220c (as shown in FIG. 4), which connects the first gap G1 between two adjacent first mask patterns 214a in the Y direction. The gap wall 220. In addition, the recess 120r (as shown in FIG. 2C) and a portion of the second nitrogen-containing material layer 112 underneath are also removed to form an opening 221 (as shown in FIG. 2D). As shown in FIG. 1D, the opening 221 can be regarded as a peripheral opening, which surrounds the first mask pattern 214a. The above-mentioned etching process may be an anisotropic etching process, such as a reactive ion etching (RIE) process or a dry etching process.

Referring to FIGS. 1D-1E and 2D-2E, the first mask pattern 214 is removed to form a central opening 223 and an opening 225. , The peripheral opening 221 surrounds the central opening 223. It is worth noting that, as shown in FIG. 1E, compared to the central opening 223 having a circular pattern, the peripheral opening 221 is triangular or triangular-like. In some embodiments, the six peripheral openings 221 are arranged radially with the central opening 223 as the center. In addition, as shown in FIG. 2E, the top surface 220t1 of the first spacer 220 on both sides of the central opening 223 is higher than the top surface 220t2 of the connecting portion 220c. On the other hand, the opening 225 can be regarded as a strip-shaped opening, which is located in the guard ring region R3 and extends along the Y direction.

Please refer to FIGS. 1E-1F and FIGS. 2E-2F to perform a rounding process to remove part of the second nitrogen-containing material layer 112a to form a second mask pattern 212. In some embodiments, the above-mentioned filleting process includes a deposition step and an etching step. Specifically, as shown in FIGS. 5A and 5B, a deposition step is performed to form an oxide layer 227 on the sidewall of the peripheral opening 221. In this case, as shown in FIG. 5B, the oxide layer 227 easily fills up the sharp corners of the triangular peripheral opening 221, so that the deposited peripheral opening 221a becomes smooth. In addition, an oxide layer 227 is also formed on the sidewall of the central opening 223 to make the deposited central opening 223a smoother. In one embodiment, the above-mentioned deposition step may use a reactive gas including SiCl ₄ and O ₂ to form the silicon oxide layer 227. However, the present invention is not limited to this. On the other hand, from the enlarged cross-sectional view 6, the oxide layer 227 not only covers the side walls of the peripheral opening 221 and the side walls of the central opening 223, but also extends to cover the top surface 220t1 of the first spacer 220 and the top surface 220t2 of the connecting portion 220c. . In some embodiments, the oxide layer 227 is also formed on the bottom surface of the peripheral opening 221 and the bottom surface of the central opening 223 to form a continuous structure, which is blanketed on the structure of FIG. 6. It is worth noting that the thickness T1 of the oxide layer 227 on the top surface 220t2 of the connecting portion 220c is greater than the thickness T2 of the oxide layer 227 on the sidewall of the connecting portion 220c. In this way, the oxide layer 227 can further block subsequent etching steps, thereby avoiding the connection between two adjacent peripheral openings 221 (especially in the edge region of the unit cell region R1), which may cause the subsequent bridging problem of the landing pad structure. In other words, the oxide layer 227 can effectively increase the process margin, thereby improving the yield.

After the oxide layer 227 is formed, an etching step may be performed to enlarge and fillet the peripheral opening 221b and the central opening 223b to complete the first cycle, as shown in FIGS. 5B and 5C. In one embodiment, the above-mentioned etching step may use an etching gas including CH ₃ F and O ₂ to remove the silicon oxide layer 227. However, the present invention is not limited to this. In an alternative embodiment, the above-mentioned etching step may include a main etching step and an over-etching step. The etching rate of the second nitrogen-containing material layer 112a in the above-mentioned main etching step is greater than the etching rate of the oxide layer 227. The etching rate of the second nitrogen-containing material layer 112a in the above-mentioned over-etching step is greater than the etching rate of the first carbon-containing material layer 110. In this case, as shown in FIGS. 1F and 2F, the first carbon-containing material layer 110 can be regarded as an etching stop layer for removing the second nitrogen-containing material layer 112a, so that the first carbon-containing material layer 110 is exposed to the second cover Screen pattern 212. In an alternative embodiment, after the above-mentioned first cycle is completed, as shown in FIG. 5C, part of the oxide layer 227a still remains around the peripheral opening 221b. In addition, after completing the above-mentioned first cycle, the above-mentioned deposition step and the above-mentioned etching step can be selectively repeated to complete the second cycle. According to actual requirements, the above-mentioned second cycle may be multiple second cycles, so that the peripheral opening 221b and the central opening 223b extend downward to the first carbonaceous material layer 110 and reach the required size. In this case, as shown in FIG. 1F, the peripheral opening 221b and the central opening 223b may be circular openings with the same shape. In an embodiment, the diameter of the peripheral opening 221b and the central opening 223b may be between 30 nm and 40 nm. The standard deviation of the diameter distribution of the peripheral opening 221b and the central opening 223b may be less than or equal to 5 nm or between 10% and 15%.

In addition, there is a connecting portion 212c between two adjacent second mask patterns 212 along the Y direction to connect two adjacent second mask patterns 212 along the Y direction. In addition, a portion of the first spacer 220a remains on the second mask pattern 212.

In one embodiment, the first spacer 220 is formed on the sidewall of the first mask pattern 214, and the first spacer 220 is used as an etching mask to increase the pattern density or feature density. It is a self-alignment double patterning (SADP) process. Specifically, after the self-aligned double patterning process, as shown in FIG. 1F, at least 6 peripheral patterns are added around a single central pattern CP (which corresponds to the first mask pattern 214a in FIG. 1C) PP. In other words, the self-aligned double patterning process can increase the pattern density or feature density integration, so as to overcome the limitation of the light source resolution in the current lithography process.

Referring to FIGS. 1F-1G and 2F-2G, taking the second mask pattern 212 as a mask, a portion of the first carbon-containing material layer 110 is removed to form a third mask pattern 210. In this case, as shown in FIGS. 1G and 2G, the first nitrogen-containing material layer 108 can be regarded as the etching stop layer for removing the first carbon-containing material layer 110, so that the first nitrogen-containing material layer 108 is exposed to the third cover Screen pattern 210. It is worth noting that when the materials of the second mask pattern 212 and the first nitrogen-containing material layer 108 are both silicon nitride, the density of the first nitrogen-containing material layer 108 is greater than that of the second mask pattern 212. In other words, the first nitrogen-containing material layer 108 can be used as an etch stop layer for removing the first carbon-containing material layer 110 without loss or only a slight loss.

1G-1H and 2G-2H, the second mask pattern 212 and the first spacer 220a on the third mask pattern 210 are removed by a wet etching process to expose the third mask pattern The top surface of 210 is 210t.

Referring to FIG. 1I and FIG. 2I, a second spacer material 122 is formed on the first nitrogen-containing material layer 108. As shown in FIG. 2I, the second spacer material 122 covers the top surface 210t of the third mask pattern 210 and fills the gaps in the third mask pattern 210. In one embodiment, the second spacer material 122 includes a dielectric material, which can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and its thickness is about 40 nm to 50 nm. It can use CVD or ALD to form.

Please refer to FIGS. 1I-1J and 2I-2J, and then perform an etch-back process on the second spacer material 122 to remove part of the second spacer material 122 to expose the top surface 210t of the third mask pattern 210 . In this case, as shown in FIG. 2J, the second spacer 222 is formed in the third mask pattern 210, and the top surface 222t of the second spacer 222 in the cell region R1 and the third mask pattern 210 The top surface 210t is substantially coplanar.

1J-1K and 2J-2K, the third mask pattern 210 is removed to expose the top surface of the first nitrogen-containing material layer 108. In this case, as shown in FIG. 2K, the second spacer 222 remaining on the first nitrogen-containing material layer 108 can be used as an etching mask to pattern the first nitrogen-containing material layer 108 and the conductor layer below. 106, to form a plurality of landing pads on the substrate 100 in the unit cell region R1, and form a guard ring on the substrate 100 in the guard ring region R3.

Specifically, after the structure of FIG. 2K is formed, as shown in FIG. 2L, a portion of the first nitrogen-containing material layer 108, a portion of the conductor layer 106, and a portion of the barrier layer 104 are removed using the second spacer 222 as a mask. To expose the top surface of the dielectric layer 102. In this case, the patterned conductor layer 206 replicates the pattern of the second spacer 222 to form a landing pad 206a and a guard ring 206b. The landing pad 206a is located in the cell region R1, and the guard ring 206b is located in the guard ring Zone R3. In some embodiments, the landing pad 206a includes a central pattern CP and a peripheral pattern PP surrounding the central pattern CP. In another embodiment, the landing pad 206a and the guard ring 206b are formed at the same time and have the same material. In addition, as shown in FIG. 2L, part of the first nitrogen-containing material layer 108a remains on the top surface of the patterned conductor layer 206. In some embodiments, the diameter of the central pattern CP and the peripheral pattern PP may be between 30 nm and 40 nm. The standard deviation of the diameter distribution of the central pattern CP and the peripheral pattern PP may be less than or equal to 5 nm or between 10% and 15%.

2L and 2M, a dielectric material (not shown) is formed on the dielectric layer 102 to fill the voids in the patterned conductive layer 206 and cover the top surface 206t of the patterned conductive layer 206. Then, an etch-back process is performed to remove part of the dielectric material and the first nitrogen-containing material layer 108a, thereby exposing the top surface 206t of the patterned conductive layer 206. In this case, as shown in FIG. 2M, the top surface 206t of the patterned conductive layer 206 and the top surface 130t of the dielectric layer 130 can be regarded as coplanar. In some embodiments, the material of the dielectric layer 130 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

2M and 2N, after the etch-back process, another dielectric layer 132 may be formed on the dielectric layer 130. Next, a plurality of capacitor openings 134 are formed in the dielectric layer 132, and a plurality of capacitors 136 are respectively formed in the capacitor openings 134. Specifically, each capacitor 136 may include a lower electrode, an upper electrode, and a capacitive dielectric layer (not shown) between the lower electrode and the upper electrode. In an embodiment, the material of the dielectric layer 132 may be silicon oxide, for example. The material of the lower electrode and the upper electrode is, for example, titanium nitride, tantalum nitride, tungsten, titanium tungsten, aluminum, copper or metal silicide. The capacitor dielectric layer may include a high dielectric constant material layer (ie, a dielectric material with a dielectric constant higher than 4), the material of which is, for example, oxides of the following elements, such as hafnium, zirconium, aluminum, titanium, lanthanum, and yttrium , Gamma or tantalum, or aluminum nitride, or any combination of the above.

In this embodiment, as shown in FIG. 2N, the landing pad 206a of the unit cell region R1 can be regarded as a capacitor contact window to electrically connect the capacitor 136 and the active region (not shown). However, the present invention is not limited to this. In other embodiments, the above-mentioned patterning method can also be applied to different semiconductor structures to increase the pattern density or feature density integration.

For example, the embodiment of the present invention may provide another patterning method, the steps of which are as follows. A target layer, a first layer, a second layer, a third layer, and a first mask pattern are sequentially formed on the substrate. A first gap wall is formed on the side wall of the first mask pattern. The first mask pattern is removed to form a plurality of central openings and peripheral openings surrounding the plurality of central openings in the first spacer. A rounding process is performed to round a plurality of peripheral openings to form a second mask pattern. Take the second mask pattern as the mask, and remove part of the second layer to form the third mask pattern. A second gap wall is formed in the third mask pattern. Remove the third mask pattern. Using the second spacer as a mask, part of the first layer and part of the target layer are removed to form a target pattern. In this embodiment, the pattern density of the target pattern may be greater than the pattern density of the first mask pattern, so as to effectively improve the integration degree of the semiconductor structure. In some embodiments, the diameter of the target pattern may be between 30 nm and 40 nm. In addition, the standard deviation of the diameter distribution of the target pattern may be less than or equal to 5 nm or between 10% and 15%.

In summary, in the embodiment of the present invention, multiple target patterns are formed at the same time by stacking multiple layers with a double patterning process. The multiple target patterns are arranged in a hexagonal most densely packed form, which can effectively increase the degree of integration of the semiconductor structure. In addition, the embodiment of the present invention can make the peripheral openings become more rounded through the rounding process, so as to approximate the size of the central opening. In addition, the oxide layer formed by the above-mentioned filleting process can further block the subsequent etching steps, thereby avoiding the connection of two adjacent peripheral openings (especially in the edge area of the cell region), which may cause the subsequent semiconductor structure to bridge The problem. In other words, the embodiment of the present invention can effectively increase the process margin, thereby improving the yield.

100: base 102, 130, 132: Dielectric layer 104: barrier layer 106: Conductor layer 108, 108a: the first nitrogen-containing material layer 110: The first layer of carbonaceous material 112, 112a: second nitrogen-containing material layer 114: The second layer of carbonaceous material 116, 116a: Anti-reflection layer 118, 118a, 118b: photoresist pattern 120: first spacer material 120p: protrusion 120r: Depressed part 120t1, 120t2, 120t3: top surface 122: second spacer material 134: Capacitor opening 136: capacitor 206: patterned conductor layer 206a: landing pad 206b: Guard ring 206t: top surface 210: The third mask pattern 210t: top surface 212: The second mask pattern 212c: connecting part 214, 214a, 214b: the first mask pattern 220, 220a: the first gap wall 220c: connecting part 221, 221a, 221b: peripheral opening 222: second gap wall 222t: top surface 223, 223a, 223b: center opening 225: open 227, 227a: oxide layer C: Centroid CP: Center pattern PP: Peripheral pattern SR: Protective ring D1, D2, D3: distance G1, G2, G3: gap R1: unit cell area R2: Surrounding area R3: Protective ring area X, Y: direction

1A to 1K are schematic top views of a manufacturing process of a semiconductor structure according to the first embodiment of the present invention. 2A to 2K are schematic cross-sectional views taken along the tangent line I-I' of FIGS. 1A to 1K. 2L to 2N are schematic cross-sectional views of a manufacturing process of a semiconductor structure according to a second embodiment of the present invention. Fig. 3 is a schematic cross-sectional view taken along the line II-II' of Fig. 1C. Fig. 4 is a schematic cross-sectional view taken along the line II-II' of Fig. 1D. 5A to 5C are schematic top views of a rounding process according to an embodiment of the invention. Fig. 6 is an enlarged schematic view of Fig. 2E.

112a: The second nitrogen-containing material layer

220: first gap

220c: connecting part

221b: Peripheral opening

223b: Center opening

227a: oxide layer

Claims (10)

A patterning method includes: Sequentially forming a conductor layer, a first nitrogen-containing material layer, a first carbon-containing material layer, a second nitrogen-containing material layer, a second carbon-containing material layer, and a photoresist pattern on the substrate; Using the photoresist pattern as a mask, removing part of the second carbon-containing material layer to form a first mask pattern; Forming a first gap wall on the side wall of the first mask pattern; Removing the first mask pattern to form a central opening and a plurality of peripheral openings surrounding the central opening in the first spacer; and A rounding process is performed to remove part of the second nitrogen-containing material layer to form a second mask pattern. The patterning method according to the first item of the scope of patent application, wherein the performing the filleting process includes: Performing a deposition step to form an oxide layer on the sidewalls of the plurality of peripheral openings: and An etching step is performed to enlarge and fillet the plurality of peripheral openings, thereby completing the first cycle. The patterning method according to the second item of the patent application, wherein the deposition step includes using a reaction gas including SiCl ₄ and O ₂ , and the oxide layer is silicon oxide. The patterning method as described in the scope of patent application 2, wherein the etching step includes using an etching gas including CH ₃ F and O ₂ . The patterning method as described in item 4 of the scope of patent application, wherein the etching step includes: A main etching step, the etching rate of the main etching step to the second nitrogen-containing material layer is greater than the etching rate to the oxide layer; and In the over-etching step, the etching rate of the second nitrogen-containing material layer in the over-etching step is greater than the etching rate of the first carbon-containing material layer. The patterning method as described in item 2 of the scope of patent application, wherein the oxide layer covers the top surface and sidewalls of the first spacer, and the oxide layer on the top surface of the first spacer The thickness of the object layer is greater than the thickness of the oxide layer on the sidewall of the first spacer. The patterning method as described in item 2 of the scope of patent application, wherein after the first cycle is completed, it further includes repeating the deposition step and the etching step to complete the second cycle. The patterning method according to the first item of the scope of patent application, wherein the substrate includes a unit cell region, a peripheral region, and a guard ring region located between the unit cell region and the peripheral region, and is formed in the The first mask pattern in the unit cell region includes a plurality of columnar patterns, which are arranged in a hexagonal most densely packed form. The patterning method described in item 1 of the scope of patent application further includes: Taking the second mask pattern as a mask, removing part of the first carbon-containing material layer to form a third mask pattern; Forming a second gap wall in the third mask pattern; and Remove the third mask pattern. A patterning method includes: Forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern on the substrate in sequence; Forming a first gap wall on the side wall of the first mask pattern; Removing the first mask pattern to form a central opening and a plurality of peripheral openings surrounding the central opening in the first gap wall; Performing a rounding process to round the plurality of peripheral openings to form a second mask pattern; Taking the second mask pattern as a mask, removing part of the second layer to form a third mask pattern; Forming a second gap wall in the third mask pattern; Removing the third mask pattern; and Using the second spacer as a mask, part of the first layer and part of the target layer are removed.

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