TWI716211B - Pixel structure and display panel - Google Patents

Abstract

A pixel structure includes multiple sub-pixels arranged as an array. Each of the multiple sub-pixels includes a first common electrode, a second common electrode, a first pixel electrode, a second pixel electrode, a first active element, and a second active element. The first common electrode and the second common electrode are electrically isolated with each other. The first pixel electrode and the first common electrode form a first storage capacitor. The second pixel electrode and the second common electrode form a second storage capacitor. A first terminal of the first active element is electrically coupled with a data line. A second terminal of the first active element is electrically coupled with the first pixel electrode. A first terminal of the second active element is electrically coupled with the data line. A second terminal of the second active element is electrically coupled with the second pixel electrode.

Description

Pixel structure and display panel

This disclosure relates to a display panel, especially a pixel structure in the display panel that can provide a stable common voltage to solve the problem of color washout in the side view.

Liquid crystal displays have the advantages of lightness and thinness, high response speed and low power consumption, and thus become the mainstream of the current market. In order to improve the quality of liquid crystal displays, the industry has developed various wide viewing angle liquid crystal displays, such as Multi-Domain Vertical Alignment (MVA) liquid crystal displays and In-Plane-Switching (IPS) liquid crystals. Monitor and so on. The response speed of a multi-region vertically aligned liquid crystal display is higher than that of a coplanar switching liquid crystal display. However, when a user views a multi-area vertically aligned liquid crystal display from a side view, the color saturation will be lower than that of the front view. The industry refers to this phenomenon as color washout.

The present disclosure provides a pixel structure, which includes arrays A plurality of sub-pixels in the column, and each sub-pixel includes a first common electrode, a second common electrode, a first pixel electrode, a second pixel electrode, a first active element, and a second active element. The second common electrode is electrically insulated from the first common electrode. The first pixel electrode and the first common electrode form a first storage capacitor. The second pixel electrode and the second common electrode form a second storage capacitor. The first active element includes a first terminal, a second terminal and a control terminal. The first terminal of the first active device is electrically connected to a data line, and the second terminal of the first active device is electrically connected to the first pixel electrode. The second active element includes a first terminal, a second terminal and a control terminal. The first end of the second active device is electrically connected to the data line, and the second end of the second active device is electrically connected to the second pixel electrode.

The present disclosure provides a display panel, which includes a plurality of first common voltage lines, a plurality of second common voltage lines, and a plurality of pixel circuits. Each pixel circuit includes a switch circuit, a first capacitor unit and a second capacitor unit. The first terminal of the first capacitor unit is coupled to one of the first common voltage lines. The first end of the second capacitor unit is coupled to one of the second common voltage lines. One of the first common voltage lines and one of the second common voltage lines are electrically insulated from each other. The switch circuit is coupled to one of the first capacitor unit, the second capacitor unit and the plurality of second common voltage lines.

The present disclosure provides a display panel which includes a plurality of pixel circuits arranged in an array, and each pixel circuit includes a main display area and a sub display area. The main display area includes a first transistor and a first capacitor unit. The first terminal of the first capacitor unit is coupled to the first common voltage line. The first transistor has a first end, a second end and a control end. The first end of the first transistor is coupled to the resource The material line, the second end of the first transistor is coupled to the second end of the first capacitor unit. The sub-display area includes a second transistor and a second capacitor unit. The first terminal of the second capacitor unit is coupled to the second common voltage line. The first common voltage line and the second common voltage line are electrically insulated from each other. The first transistor has a first end, a second end and a control end. The first end of the second transistor is coupled to the data line, and the second end of the second transistor is coupled to the second end of the second capacitor unit.

The above-mentioned pixel structure and display panel can provide a stable voltage to solve the problem of color loss in side view.

100‧‧‧Pixel circuit

110、130、140‧‧‧Transistor

120, 150‧‧‧Common voltage line

Csa, Csb‧‧‧Storage capacitor

Cla、Clb‧‧‧Liquid crystal capacitor

DL[n]‧‧‧Data line

GL[n]‧‧‧Gate line

Vdata‧‧‧Data voltage

Vtcm‧‧‧Common voltage

Cpa~Cpc‧‧‧parasitic capacitance

N1‧‧‧First node

N2‧‧‧Second node

200‧‧‧Pixel structure

PX1‧‧‧First sub-pixel

PX2‧‧‧Second sub-pixel

PX3‧‧‧The third sub-pixel

PX4‧‧‧Fourth sub-pixel

SB‧‧‧Substrate

GL[i]~GL[i+1]‧‧‧Gate line

DL[i]~DL[i+1]‧‧‧Data line

200‧‧‧Pixel structure

210‧‧‧First common electrode

212‧‧‧The first main cadre

214a~214c‧‧‧First extension

220‧‧‧Second common electrode

222‧‧‧The second main cadre

224a~224c‧‧‧Second extension

230‧‧‧Switch circuit

232‧‧‧The first active component

234‧‧‧Second active component

236‧‧‧Third active component

238‧‧‧Connecting layer

240‧‧‧First pixel electrode

242‧‧‧Connecting part

244‧‧‧Geometric structure

250‧‧‧Second pixel electrode

252‧‧‧Connecting part

254‧‧‧Geometric structure

RV‧‧‧Longitudinal beam

RH‧‧‧Transverse beam

PT‧‧‧Stripe pattern

A-A’, B-B’‧‧‧ Section

SB‧‧‧Substrate

SE‧‧‧Source

DE‧‧‧Dip pole

CH‧‧‧Channel layer

GI‧‧‧Gate insulation layer

GE‧‧‧Gate

IN‧‧‧Insulation layer

VA1, VA2, VA3‧‧‧Through hole

400‧‧‧Display Panel

Cma[1]~Cma[n]‧‧‧The first common voltage line

Cmb[1]~Cmb[n]‧‧‧The second common voltage line

DL[1]~DL[n]‧‧‧Data line

GL[1]~GL[n]‧‧‧Gate line

410‧‧‧Pixel circuit

412‧‧‧switch circuit

414‧‧‧The first capacitor unit

416‧‧‧Second capacitor unit

T1‧‧‧First transistor

T2‧‧‧Second Transistor

T3‧‧‧Third Transistor

Csa, Csb‧‧‧Storage capacitor

Cla、Clb‧‧‧Liquid crystal capacitor

FIG. 1 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

FIG. 2A is a schematic top view of a simplified pixel structure according to an embodiment of the present disclosure.

FIG. 2B is a schematic top view of the pixel structure of FIG. 2A omitting the first pixel electrode and the second pixel electrode.

Figure 3A is a simplified schematic cross-sectional view taken along the line A-A' in Figure 2A.

Figure 3B is a simplified cross-sectional view taken along the line B-B' in Figure 2A.

FIG. 4 is a simplified functional block diagram of the display panel according to an embodiment of the present disclosure.

The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

FIG. 1 is a schematic circuit diagram of a pixel circuit 100 according to an embodiment of the present disclosure. The pixel circuit 100 includes a transistor 110 forming a main display area, a storage capacitor Csa, and a liquid crystal capacitor Cla. The liquid crystal capacitor Cla is coupled to the transistor 110 through a first node N1, and the storage capacitor Csa is coupled to the first node N1 and Between the common voltage lines 120. The pixel circuit 100 further includes a transistor 130 forming a sub-display area, a transistor 140, a storage capacitor Csb, and a liquid crystal capacitor Clb. The liquid crystal capacitor Clb is coupled to the transistor 130 and the transistor 140 through a second node N2, and the storage capacitor Csb is coupled between the second node N2 and the common voltage line 150. The sub-display area is used to emit light at high gray levels to solve the color washout problem of the high gray level display screen under the lateral viewing angle.

The control terminals of the transistor 110, the transistor 130, and the transistor 140 are all coupled to the gate line GL[n]. Therefore, the transistor 110, the transistor 130, and the transistor 140 are simultaneously turned on to transfer the data voltage Vdata on the data line DL[n] to the first node N1 and the second node N2. At this time, the voltage of the second node N2 will be the divided voltage of the data voltage Vdata and the common voltage Vtcm on the common voltage line 150.

In this embodiment, since the common voltage line 120 and the common voltage line 150 are coupled to each other, when the storage capacitor Csa receives the data voltage Vdata, the common voltage Vtcm will be disturbed as the voltage of the first node N1 changes. In addition, the voltage changes on the data line DL[n] and the gate line GL[n] will also affect the stability of the common voltage Vtcm through the parasitic capacitances Cpa~Cpc. Therefore, the second node N2 may store the wrong voltage division result, so that the secondary display area cannot provide the correct grayscale value (brightness), and thus cannot solve the problem of color loss of the high grayscale display screen under the lateral viewing angle.

The present disclosure proposes a pixel structure 200 that can solve the problem of color loss when the screen is viewed from the side and can provide a stable voltage. FIG. 2A is a schematic top view of a simplified pixel structure 200 according to an embodiment of the present disclosure. FIG. 2B is a schematic top view of the pixel structure 200 in FIG. 2A with the first pixel electrode 240 and the second pixel electrode 250 omitted. Figures 3A and 3B are respectively simplified schematic cross-sectional views taken along the line A-A' and B-B' in Figure 2A. Please refer to Figure 2A, Figure 2B, Figure 3A, and Figure 3B at the same time. The pixel structure 200 includes a plurality of sub-pixels arranged in an array, such as the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel. Pixel PX3 and fourth sub-pixel PX4. The pixel structure 200 is disposed on the substrate SB, and a plurality of gate lines and a plurality of data lines are arranged on the substrate SB. The positions of the plurality of sub-pixels of the pixel structure 200 correspond to the plurality of gate lines and the plurality of data The intersection of lines. For brevity, Figures 2A~2B only show two gate lines GL[i]~GL[i+1] and two data lines DL[i]~DL[i+1], where i is Positive integer.

Each sub-pixel includes a first common electrode 210, a second common electrode 220, a switch circuit 230, a first pixel electrode 240, and a second pixel electrode 250. The switch circuit 230 is disposed between the first common electrode 210 and the second common electrode 220 in a direction parallel to the data line DL[i], and the switch circuit 230 is electrically connected to the gate line GL[i] and the data line DL [i]. First pixel The pole 240 and the second pixel electrode 250 are electrically connected to the switch circuit 230. The first common electrode 210 and the second common electrode 220 are electrically insulated from each other. The first common electrode 210 and the second common electrode 220 respectively define a main display area and a sub-display area, and the first pixel electrode 240 and the second picture The element electrodes 250 are respectively located in the main display area and the sub display area.

The switch circuit 230 includes a first active device 232, a second active device 234, a third active device 236, and a connection layer 238. As shown in FIG. 3A, each transistor (for example, the first active device) includes a source SE, a drain DE, a channel layer CH, a gate insulating layer GI, and a gate GE. The gate electrode GE is electrically connected to the gate line GL[i] and is disposed above the substrate SB, and the gate insulating layer GI is disposed above the gate electrode GE. The source SE, the drain DE, and the channel layer CH are disposed above the gate insulating layer GI, and the source SE and the drain DE extend above the channel layer CH. The insulating layer IN covers the switch circuit 230, and the insulating layer IN includes a through hole VA1. The through hole VA1 exposes the drain electrode DE, so that the first pixel electrode 240 is electrically connected to the drain electrode DE through the through hole VA1. In this embodiment, the first active device 232, the second active device 234, and the third active device 236 are bottom gate thin-film transistors, but the disclosure is not limited thereto. The first active element 232, the second active element 234, and the third active element 236 can be implemented by using any suitable transistors according to actual design requirements.

The source SE of the first active device 232 is electrically connected to the data line DL[i]. The source SE of the second active element 234 is electrically connected to the drain DE of the first active element 232, and the drain DE of the second active element 234 is electrically connected to the second pixel electrode 250. The source SE of the third active element 236 is electrically connected The drain electrode DE of the second active device 234 is connected to the drain electrode DE of the third active device 236 electrically connected to the connection layer 238. As shown in FIG. 3B, the insulating layer IN further includes through holes VA2 and VA3, wherein the through hole VA2 exposes the drain electrode DE of the third active device 236, and the through hole VA3 exposes the second common electrode 220. Therefore, the third active device 236 is electrically connected to the second common electrode 220 through the via VA2, the connection layer 238, and the via VA3 in sequence.

In other words, the switch circuit 230 is electrically connected to the second common electrode 220 but not electrically connected to the first common electrode 210.

In this embodiment, the connection layer 238, the first pixel electrode 240 and the second pixel electrode 250 may be located on the same layer, the first common electrode 210, the second common electrode 220, the gate electrode GE and the gate line GL[i ] Can be located in the same layer (for example, all formed on the substrate SB with metal), and the source SE, the drain DE, and the data line DL[i] can be located in the same layer.

In some embodiments, the material (for example, polysilicon) forming the channel layer CH may be correspondingly disposed under the material (for example, a metal layer) forming the source SE, drain DE, and data line DL[i], without It is only arranged at the positions of the first active element 232, the second active element 234, and the third active element 236 to save the number of masks.

Please refer to FIG. 2B, the first common electrode 210 includes a first main portion 212 and a plurality of first extension portions 214a~214c, and the second common electrode 220 includes a second main portion 222 and a plurality of second extension portions 224a~224c . The first extension portions 214 a-214 c are arranged in parallel to each other and connected to the first trunk portion 212, and the first extension portions 214 a-214 c extend from the first trunk portion 212 toward a direction away from the switch circuit 230. The second extensions 224a~224c are parallel to each other Arranged and connected to the second trunk portion 222, and the second extension portions 224 a to 224 c extend from the second trunk portion 222 toward a direction away from the switch circuit 230. In detail, the first extensions (for example, the first extension 214a and the first extension 214c) connected to both ends of the first main portion 212 define the main display area, and the second extensions connected to the two ends of the second main portion 222 The extension portions (for example, the second extension portion 224a and the second extension portion 224c) define the sub-display area.

The first pixel electrode 240 and the second pixel electrode 250 are respectively disposed in the main display area and the sub display area, and are respectively located above the first common electrode 210 and the second common electrode 220. In detail, the first pixel electrode 240 and the second pixel electrode 250 respectively at least partially overlap the first common electrode 210 and the second common electrode 220 in the vertical projection direction. In some embodiments, the liquid crystal layer (not shown) may be disposed above where the first pixel electrode 240 and the second pixel electrode 250 do not overlap the first common electrode 210 and the second common electrode 220. The overlapping part of the first pixel electrode 240 and the first common electrode 210 forms a first storage capacitor, wherein the first pixel electrode 240 and the first common electrode 210 respectively serve as the upper plate electrode and the lower plate electrode of the first storage capacitor, and The first storage capacitor helps stabilize the electric field supplied to the liquid crystal layer. Similarly, the overlapping portion of the second pixel electrode 250 and the second common electrode 220 forms a second storage capacitor, wherein the second pixel electrode 250 and the second common electrode 220 respectively serve as the upper plate electrode and the lower plate of the second storage capacitor electrode.

Please refer to FIG. 2A again, the first pixel electrode 240 includes a connecting portion 242 and a plurality of geometric structures 244, and the second pixel electrode 250 includes a connecting portion 252 and a plurality of geometric structures 254. The shapes of the connecting portion 242 and the connecting portion 252 include, for example, a cross shape, so that the first pixel electrode 240 and the second pixel electrode Each 250 is divided into four areas. Furthermore, the connecting portion 242 includes a longitudinal beam portion RV and a lateral beam portion RH, and the longitudinal beam portion RV and the lateral beam portion RH are staggered at the center of the first pixel electrode 240. The multiple geometric structures 244 are symmetrically arranged on both sides of the longitudinal beam portion RV, and are also symmetrically arranged on both sides of the transverse beam portion RH. For example, the upper left, upper right, lower left, and lower right regions defined by the connecting portion 242 each contain a geometric Structure 244. Each geometric structure 244 includes a plurality of strip patterns PT parallel to each other. The strip patterns PT extend from the connecting portion 242 toward a direction away from the connecting portion 242, and are not parallel or perpendicular to the longitudinal beam portion RV and the transverse direction.梁部RH. The strip patterns PT on both sides of the longitudinal beam portion RV are symmetrical with each other, and the strip patterns PT on both sides of the transverse beam portion RH are also symmetrical with each other, so that the shape of the first pixel electrode 240 is similar to a fishbone shape. The arrangement of the connecting portion 252 and the plurality of geometric structures 254 in the second pixel electrode 250 is similar to the arrangement of the first pixel electrode 240 described above, and is not repeated here for the sake of brevity.

In some embodiments, the longitudinal beam portion RV of the first pixel electrode 240 at least partially overlaps the first extension portion 214b in the vertical projection direction, and the longitudinal beam portion RV of the second pixel electrode 250 at least partially overlaps the first extension portion 214b in the vertical projection direction. Partly overlaps the second extension portion 224b.

Please refer to FIG. 2B again, the first sub-pixel PX1 and the second sub-pixel PX2 are adjacent in a direction parallel to the data line DL[i]. Furthermore, the first common 210 electrode of the first sub-pixel PX1 is adjacent to the second common 220 electrode of the second sub-pixel PX2, and the main display area of the first sub-pixel PX1 is adjacent to the second sub-pixel. Sub-display area of PX2. The first extension portions 214a~214c of the first sub-pixel PX1 and the second extension portion of the second sub-pixel PX2 224a-224c extend toward each other, but the first extension portions 214a-214c of the first sub-pixel PX1 are electrically insulated from the second extension portions 224a-224c of the second sub-pixel PX2.

In some embodiments, if a plurality of sub-pixels are electrically connected to the same gate line (for example, the gate line GL[i]), the first common electrode 210 of the plurality of sub-pixels uses the respective first main The stem portions 212 are electrically connected to each other, and the second common electrodes 220 of the plurality of sub-pixels are electrically connected to each other by the respective second stem portions 222.

In other embodiments, another substrate (not shown) may be disposed above the substrate SB, and the pixel structure 200 may further include an upper plate common electrode (not shown) disposed on the other substrate. A vertical projection of the upper plate common electrode at least partially overlaps the first pixel electrode 240 and the second pixel electrode 250. A liquid crystal layer can be filled between the upper plate common electrode and the first pixel electrode 240 and the second pixel electrode 250, so that the upper plate common electrode and the first pixel electrode 240 form a first liquid crystal capacitor and are connected to the second pixel electrode. The element electrode 250 forms a second liquid crystal capacitor.

In summary, the first common electrode 210 and the second common electrode 220 in each sub-pixel are electrically insulated from each other, and the first common electrode 210 and the second common electrode 210 and the second common electrode 220 of any sub-pixel are parallel to the data line DL[i]. The common electrode 220 is electrically insulated from the first common electrode 210 and the second common electrode 220 of different sub-pixels. Therefore, the voltage on the second common electrode 220 will not be affected by the voltage fluctuations of the first common electrode 210 of the same sub-pixel, nor will it be affected by the voltage fluctuations of the first common electrode 210 of other sub-pixels. The switch circuit 230 divides the voltage difference between the data line (for example, the data line DL[i]) and the second common electrode 220, and transmits the result of the divided voltage through The drain electrode DE of the second active element 234 is provided to the second pixel electrode 250. The second common electrode 220 with a stable voltage will help the sub-display area to provide the correct grayscale value, so as to solve the problem of color loss when the display screen is viewed from the side.

FIG. 4 is a simplified functional block diagram of the display panel 400 according to an embodiment of the present disclosure. The display panel 400 includes a plurality of first common voltage lines Cma[1]~Cma[n], a plurality of second common voltage lines Cmb[1]~Cmb[n], and a plurality of pixel circuits 410 arranged in a matrix. Each pixel circuit 410 can be implemented by using the pixel structure 200 shown in Figures 2A-2B, and n is a positive integer. The display panel 400 may further include a plurality of data lines DL[1]~DL[n] and a plurality of gate lines GL[1]~GL[n], where the positions of the plurality of pixel circuits 410 correspond to the data lines The intersection of DL[1]~DL[n] and gate line GL[1]~GL[n]. In addition, the first common voltage lines Cma[1]~Cma[n] and the second common voltage lines Cmb[1]~Cmb[n] are arranged alternately.

Each pixel circuit 410 includes a switch circuit 412, a first capacitor unit 414, and a second capacitor unit 416. The first terminal of the first capacitor unit 414 is coupled to a corresponding one of the first common voltage lines Cma[1] ~ Cma[n], and the first terminal of the second capacitor unit 416 is coupled to the second common voltage line In the corresponding one of Cmb[1] to Cmb[n], the first common voltage line Cma and the second common voltage line Cmb coupled to any pixel circuit 410 are electrically insulated from each other. The switch circuit 412 is coupled to a corresponding one of the data lines DL[1]~DL[n], a corresponding one of the gate lines GL[1]~GL[n], and the second common voltage line Cmb[1] The corresponding one in ~Cmb[n]. The switch circuit 412 is used to provide the voltage on the data line DL to the first capacitor unit 414, and is used to The voltage difference between the data line DL and the gate line GL is divided to generate a divided voltage, and the divided voltage is used to provide the divided voltage to the second capacitor unit 416. In the specification and drawings of this case, if a component number is used without specifying the index of the component number, it means that the component number refers to any unspecified component in the component group. For example, the data line DL refers to an unspecified arbitrary data line among the data lines DL[1]~DL[n]. For another example, the object referred to by the gate line GL is an unspecified arbitrary gate line among the gate lines GL[1]~GL[n].

In detail, the switch circuit 412 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 and the first capacitor unit 414 form a main display area, and the second transistor T2, The third transistor T3 and the second capacitor unit 416 form a sub-display area. The first transistor T1, the second transistor T2, and the third transistor T3 each include a first terminal, a second terminal, and a control terminal. The first end of the first transistor T1 is coupled to the data line DL; the second end of the first transistor T1 is coupled to the second end of the first capacitor unit 414; the control end of the first transistor T1 is coupled to the gate Polar line GL. The first end of the second transistor T2 is coupled to the data line DL; the second end of the second transistor T2 is coupled to the second capacitor unit 416; the control end of the second transistor T2 is coupled to the gate line GL. The first end of the third transistor T3 is coupled to the second end of the second transistor T2 and the second end of the second capacitor unit 416; the second end of the third transistor T3 is coupled to the second common voltage line Cmb ; The control end of the third transistor T3 is coupled to the gate line GL.

In some embodiments, the first transistor T1, the second transistor T2, and the third transistor T3 can use the first active element shown in Figures 2A-2B, respectively. The component 232, the second active element 234 and the third active element 236 are implemented.

The first capacitor unit 414 includes a storage capacitor Csa and a liquid crystal capacitor Cla. The storage capacitor Csa is coupled between the second terminal of the first transistor T1 and the first common voltage line Cma. Similarly, the second capacitor unit 416 includes a storage capacitor Csb and a liquid crystal capacitor Clb, where the storage capacitor Csb is coupled between the second terminal of the second transistor T2 and the second common voltage line Cmb.

In some embodiments, the storage capacitor Csa can be implemented by using the overlapping portion of the first pixel electrode 240 and the first common electrode 210 in Figures 2A-2B, and the liquid crystal capacitor Cla can be implemented by the first pixel in Figures 2A-2B. The element electrode 240 has no overlap with the first common electrode 210, and the liquid crystal layer and the upper plate are implemented as a common electrode. Similarly, the storage capacitor Csb can be realized by the overlapping part of the second pixel electrode 250 and the second common electrode 220 in Figures 2A-2B, and the liquid crystal capacitor Clb can be realized by the second pixel electrode 250 in Figures 2A-2B. The part that does not overlap with the second common electrode 220, the liquid crystal layer and the upper plate common electrode are implemented.

It can be seen from the above that, since the first common voltage line Cma and the second common voltage line Cmb coupled to the pixel circuits 410 in the same column are electrically insulated from each other, when the pixel circuits 410 in the column are selected for data writing, The second transistor T2 and the third transistor T3 can provide correct voltage division results. In this way, the secondary display area of the pixel circuit 410 can provide the correct grayscale value, thereby helping to solve the problem of color loss of the display image under the lateral viewing angle.

Certain words are used in the specification and the scope of the patent application to refer to specific elements. However, those with ordinary knowledge in the technical field should understand that the same element may be called by different terms. Description The scope of the book and the patent application does not use the difference in names as the way to distinguish the components, but the difference in the functions of the components as the basis for distinction. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection methods, or through other elements or connections. The means is indirectly connected to the second element electrically or signally.

The size and relative size of some elements in the figure will be enlarged, or the shape of some elements will be simplified, so as to more clearly express the content of the embodiment. Therefore, unless otherwise specified by the applicant, the shape, size, relative size and relative position of each element in the figure are only for convenience of description, and should not be used to limit the patent scope of this disclosure. In addition, the present disclosure can be embodied in many different forms, and when interpreting the present disclosure, it should not be limited to the embodiments presented in this specification.

In the specification and the scope of the patent application, if it is described that the first element is located on the second element, above the second element, connected to, joined to, or connected to the second element, it means that the first element can be directly located on the second element. On two components, directly connected to the second component, directly connected to the second component can also indicate that there are other components between the first component and the second component. In contrast, if it is described that the first element is directly on the second element, directly connected, directly joined, or directly connected to the second element, it means that there are no other elements between the first element and the second element.

In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case. The above are only the preferred embodiments of the present disclosure, and all equal changes and modifications made in accordance with the requirements of the present disclosure should fall within the scope of the disclosure.

200‧‧‧Pixel structure

230‧‧‧Switch circuit

232‧‧‧The first active component

234‧‧‧Second active component

236‧‧‧Third active component

238‧‧‧Connecting layer

240‧‧‧First pixel electrode

242‧‧‧Connecting part

244‧‧‧Geometric structure

250‧‧‧Second pixel electrode

252‧‧‧Connecting part

254‧‧‧Geometric structure

PX1‧‧‧First sub-pixel

PX2‧‧‧Second sub-pixel

PX3‧‧‧The third sub-pixel

PX4‧‧‧Fourth sub-pixel

GL[i]~GL[i+1]‧‧‧Gate line

DL[i]~DL[i+1]‧‧‧Data line

RV‧‧‧Longitudinal beam

RH‧‧‧Transverse beam

PT‧‧‧Stripe pattern

A-A’, B-B’‧‧‧ Section

Claims (12)

A pixel structure includes a plurality of sub-pixels arranged in an array, wherein each sub-pixel includes: a first common electrode; a second common electrode electrically insulated from the first common electrode; and a first pixel electrode, Wherein the first pixel electrode and the first common electrode form a first storage capacitor; a second pixel electrode, wherein the second pixel electrode and the second common electrode form a second storage capacitor; a first The active device includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first active device is electrically connected to a data line, and the second terminal of the first active device is electrically connected At the first pixel electrode; and a second active device, including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second active device is electrically connected to the data line, the The second end of the second active element is electrically connected to the second pixel electrode; wherein the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, and the second sub-pixel of the first sub-pixel A common electrode is adjacent to and insulated from the second common electrode of the second sub-pixel. The pixel structure according to claim 1, wherein the first common electrode includes a first trunk portion and a plurality of first extension portions, and the second common electrode includes a second trunk portion and a plurality of second extension portions , The first master The moving element and the second active element are disposed between the first trunk portion and the second trunk portion, and the plurality of first extension portions are away from the first active element and the second active element from the first trunk portion Extending in the direction of, the plurality of second extension portions extend from the second trunk portion toward a direction away from the first active element and the second active element. The pixel structure according to claim 2, wherein the first extension portions of the first sub-pixel and the second extension portions of the second sub-pixel extend toward each other, and the first The first extension portions of the sub-pixel are electrically insulated from the second extension portions of the second sub-pixel. The pixel structure according to claim 1, further comprising a third active element, wherein the third active element includes a first end, a second end and a control end, and the first end of the third active element It is electrically connected to the second end of the second active element, and the second end of the third active element is electrically connected to the second common electrode. The pixel structure according to claim 1, wherein the first pixel electrode and the second pixel electrode each include a connecting portion and a plurality of geometric structures, and the plurality of geometric structures are separated by the connecting portion, and Each geometric structure contains multiple parallel strip patterns. The pixel structure according to claim 5, wherein the connection The connecting portion includes a longitudinal beam portion and a transverse beam portion forming a cross pattern. The pixel structure according to claim 6, wherein the plurality of geometric structures are symmetrically arranged on both sides of the longitudinal beam portion and both sides of the lateral beam portion, and the first pixel electrode and the second pixel The shape of the element electrode includes a fishbone shape. The pixel structure according to claim 1, wherein the first common electrode and the second common electrode are formed of metal on a lower substrate. The pixel structure according to claim 1, further comprising an upper plate common electrode formed on an upper substrate, wherein the upper plate common electrode and the first pixel electrode form a first liquid crystal capacitor, and the upper plate common The electrode and the second pixel electrode form a second liquid crystal capacitor. A display panel includes: a plurality of first common voltage lines; a plurality of second common voltage lines; and a plurality of pixel circuits, wherein each pixel circuit includes a switch circuit, a first capacitor unit, and a second capacitor Unit, a first end of the first capacitor unit is coupled to one of the plurality of first common voltage lines, and a first end of the second capacitor unit is coupled to one of the plurality of second common voltage lines One of them, and the one of the first common voltage lines and the one of the second common voltage lines are electrically insulated from each other; The switch circuit is coupled to the one of the first capacitor unit, the second capacitor unit, and the plurality of second common voltage lines; wherein, the display panel further includes a plurality of data lines and a plurality of gate lines , And the switch circuit includes: a first transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to one of the plurality of data lines 1. The second end of the first transistor is coupled to a second end of the first capacitor unit, and the control end of the first transistor is coupled to one of the gate lines; The second transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the one of the plurality of data lines, the second transistor The second end of the second capacitor is coupled to a second end of the second capacitor unit, the control end of the second transistor is coupled to the one of the gate lines; and a third transistor, It includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the second transistor and a second terminal of the second capacitor unit , The second end of the third transistor is coupled to one of the plurality of second common voltage lines, and the control end of the third transistor is coupled to one of the plurality of gate lines One. The display panel according to claim 10, wherein the first capacitor unit and the second capacitor unit each include a liquid crystal capacitor and a storage capacitor, The storage capacitor of the first capacitor unit is coupled between the second terminal of the first transistor and the one of the first common voltage lines, and the storage capacitor of the second capacitor unit is coupled Between the second end of the second transistor and the one of the second common voltage lines. A display panel includes a plurality of pixel circuits arranged in an array, wherein each pixel circuit includes: a main display area, including a first transistor and a first capacitor unit, wherein a first capacitor unit of the first capacitor unit Terminal is coupled to a first common voltage line, the first transistor has a first terminal, a second terminal and a control terminal, the first terminal of the first transistor is coupled to a data line, the first transistor The second end of a transistor is coupled to a second end of the first capacitor unit; and a sub-display area includes a second transistor and a second capacitor unit, wherein a first capacitor unit of the second capacitor unit One end is coupled to a second common voltage line, the first common voltage line and the second common voltage line are electrically insulated from each other, the second transistor has a first end, a second end and a control end, The first end of the second transistor is coupled to the data line, and the second end of the second transistor is coupled to a second end of the second capacitor unit; wherein the sub-display area further includes a first Three transistors, the third transistor includes a first terminal, a second terminal and a control terminal, the first terminal of the third transistor is coupled to the second terminal of the second transistor and the first terminal The second end of the two capacitor units and the second end of the third transistor are coupled to the second common voltage line.

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