TWI714806B - Dpu architecture - Google Patents

Abstract

A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.

Description

Dynamic random access memory processing unit architecture [Cross reference of related applications]

This patent application claims the priority of U.S. Provisional Patent Application No. 62/413,977 filed on October 27, 2016, and the disclosure content of the U.S. Provisional Patent Application is incorporated into this case for reference in its entirety.

The present invention herein relates to a memory system, and more specifically relates to a dynamic random access memory (DRAM) processing unit (DPU).

Traditionally, a graphics processing unit (GPU) and a tensor processing unit (TPU) are used for deep learning processing. Deep learning processing includes highly parallel processing that may not be efficiently executed by graphics processing units or tensor processing units.

Exemplary embodiments provide a dynamic random access memory (DRAM) processing unit (DPU). The DPU may include: at least one computing cell array having a plurality of DRAM-type computing cells arranged in an array, the array Have at least one Rows, wherein the at least one row may include at least three columns of DRAM-based computing cells, and the at least three columns of DRAM-based computing cells are configured to provide a reference to the first of the at least three columns And a second row of logical functions for performing operations and configured to store the result of the logical function in a third row of the at least three rows; and a controller, which can be coupled to the at least one computing cell The array is configured to configure the at least one computing cell array to perform DPU operations.

An exemplary embodiment provides a DPU, which may include: at least one computing cell array, which may include a plurality of DRAM-type computing cells arranged in an array, the array having at least one row, wherein the at least one row may A DRAM-based computing cell including at least three columns, the DRAM-based computing cell of the at least three columns being configured to provide a logic function for performing operations on a first column and a second column of the at least three columns, and Is configured to store the result of the logic function in the third row of the at least three rows; at least one data cell array may include at least one DRAM-type memory cell arranged in at least one row; and The controller is coupled to the at least one computing cell array to configure the at least one computing cell array to perform DPU operations, and the controller is coupled to the at least one data cell array to perform memory Operation. In one embodiment, the DRAM-type computing cells of the at least one row may each include a three transistor and a capacitor (three transistor, one capacitor, 3T1C) DRAM memory cell, and the at least one row The DRAM-type computing cell can provide an inverse OR logic function. In another embodiment, the DRAM computing cells of the at least one row may each include a transistor and a capacitor (one transistor, one capacitor, 1T1C) DRAM memory cell And each of the DRAM-based calculation cells may further include an arithmetic logic unit (ALU), which is coupled to the bit line of the DRAM-based calculation cell, wherein the arithmetic logic The unit can provide the logic function.

Exemplary embodiments provide a DPU, which may include: at least one computing cell array, which may include a plurality of DRAM-type computing cells arranged in an array, the array having at least one row, wherein the at least one row may include At least three columns of DRAM-based computing cells, the at least three columns of DRAM-based computing cells are configured to provide a logic function for performing operations on the first and second columns of the at least three columns and are It is configured to store the result of the logic function in the third column of the at least three columns; at least one random calculation cell array may include a plurality of DRAM-type random calculation cells arranged in an array, the array There is at least one row, wherein the at least one row may include at least three columns of DRAM-based random computing cells, and the at least three columns of DRAM-based random computing cells are configured to provide The first row and the second row of the logic function of the calculation are configured to store the result of the logic function in the third row of the at least three rows; the controller is coupled to the at least one calculation The cell array is configured to configure the at least one computing cell array to perform DPU operations, and the controller is coupled to the at least one random computing cell array to perform random logic operations.

100, 700: DPU

101a, 101b: memory bank

102a, 102b: sub-array

103: Buffer

104: system bus

105, 105n: memory array chip

105a, 105b: memory array slice/computing cell row

106: data cell array

107: Calculate cell array/calculate cell

107a, 107b, 107c, 107d: calculation cell

108: shift array/memory array on-chip shift array

109: dotted line

110: decoder/data cell array decoder

111: decoder/computing cell array decoder

112: shift array/memory array inter-chip shift array

112e, 112f: data shift line

113: Memory array inter-chip forwarding array

113g: The first data forwarding line

113h: The second data forwarding line

114: Controller/sub-array controller

201: 3T1C DRAM calculation cell shape/3T1C calculation cell shape

202:1T1C DRAM calculation cell shape/1T1C calculation cell shape

715: Random data area/random data array

716: Converter-Random Array

900: System Architecture

910: hardware layer

911: Rapid peripheral component interconnection device

912: Dual in-line memory module

920: Library and driver layer/DPU library and driver layer

921: DPU library

922: DPU drive

923: DPU compiler

930: Frame layer

940: application layer

addr: address

BL: bit line

C ₁ , C ₂ : Capacitor

CNTL1, CNTL2, CNTL3, CNTL4: control signal

FCL: Forwarding control line

FDL: Forwarding data line

FSL: Forwarding section line

ISLcL: Inter-chip shift control line for memory array

SA: sense amplifier

SL: shift line

SLcL: control line/left shift control line

SML: shift mask line

SRcL: control line/right shift control line

T ₁ : Transistor/first transistor

T ₂ : Transistor/Second Transistor

T ₃ : Transistor/Third Transistor

T ₄ , T _112a , T _112b , T _112c , T _112d , T _113a , T _113b , T _113c , T _113d , T _113e , T _113f : Transistor

T ₅ : fifth transistor

T ₆ : Transistor/Sixth Transistor

WEN _X , WEN _Y , WEN _R : write enable line

WL, WL _X , WL _Y , WL _R : character line

In the following sections, the aspects of the subject matter disclosed herein will be explained with reference to the exemplary embodiments shown in the figures, in which: FIG. 1 shows a block diagram of an exemplary embodiment of a dynamic random access memory (DRAM) processing unit (DPU) according to the subject matter disclosed herein.

FIG. 2A shows an exemplary embodiment of a three-transistor and a capacitor DRAM that can be used to calculate the shape of the calculation cell in the calculation cell array.

FIG. 2B shows an alternative exemplary embodiment of a transistor and a capacitor DRAM that can be used to calculate the shape of the calculation cell in the calculation cell array.

FIG. 3 illustrates an exemplary embodiment of an intra-mat shift array of a memory array according to the subject matter disclosed herein.

FIG. 4A shows an embodiment of an inter-mat shift array of a memory array according to the subject matter disclosed herein.

FIG. 4B conceptually illustrates the inter-memory array shift between two computation cells at the same position in the adjacent computation cell row for shifting between the left memory array chips according to the subject matter disclosed in this article Bit interconnect configuration.

FIG. 4C conceptually illustrates the inter-memory array inter-slice shift between two different positions in the adjacent computing cell row in the left memory array inter-slice shift according to the subject matter disclosed herein Bit interconnect configuration.

FIG. 5 shows an embodiment of an inter-mat forwarding array of a memory array according to the subject matter disclosed herein.

6A to 6G illustrate operations based on inverse OR logic that can be provided by the DPU according to the subject matter disclosed herein.

FIG. 7 shows a block diagram of an exemplary embodiment of a DPU including a stochastic data region according to the subject matter disclosed herein.

FIGS. 8A and 8B respectively illustrate random calculation operations of addition operations that can be converted into multiplexing operations and multiplication operations that can be converted into AND logic operations.

FIG. 9 shows a system architecture including a DPU according to the subject matter disclosed herein.

In the following detailed description, many specific details are described to provide a thorough understanding of the present invention. However, those familiar with the art will understand that the disclosed aspect can be practiced without these specific details. In other instances, the well-known methods, procedures, components and circuits are not described in detail to avoid obscuring the subject matter disclosed in this article.

The “one embodiment” or “embodiment” mentioned throughout this specification means that a specific feature, structure, or characteristic described in conjunction with the embodiment can be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to one embodiment" (or other phrases with similar meanings) appearing in various places throughout this specification may not all refer to the same Examples. In addition, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner. In this regard, the word "exemplary" as used herein means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not to be regarded as necessarily better or advantageous than other embodiments. Furthermore, depending on the context discussed herein, singular terms may include corresponding plural forms and plural terms may include corresponding singular forms. It should be further noted that the various diagrams (including component diagrams) shown and discussed in this article are for illustrative purposes only and are not to be compared. Example drawing. Likewise, various waveform diagrams and timing diagrams are shown for illustrative purposes only. For example, the size of some elements may be exaggerated relative to other elements for clarity. In addition, where appropriate, reference numbers have been repeatedly used in each figure to indicate corresponding and/or similar elements.

The terminology used herein is only used to describe specific exemplary embodiments and is not intended to limit the claimed subject matter. Unless the context clearly indicates otherwise, the singular forms "一 (a, an)" and "the" used herein are intended to also include the plural forms. It should be understood that when the term "comprises and/or comprising" is used in this specification, it refers to the existence of the stated features, integers, steps, operations, elements, and/or components, but does not exclude one or more The existence or addition of several other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "first", "second", etc. used in this article are used as marks for the nouns that follow them, and unless explicitly stated otherwise, they do not imply any type of order (for example, spatial, temporal, Logical etc.). In addition, the same reference numbers may be used interchangeably in two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. However, such usage is only for the purpose of concise description and ease of discussion, and does not imply that the structure or structure details of such components or units are the same in all embodiments or that such components/modules with common reference numbers It is the only way to implement the teaching content of the specific embodiments disclosed in this article.

Unless otherwise defined, the meanings of all terms (including technical and scientific terms) used herein are the same as those commonly understood by those with ordinary knowledge in the technical field to which the subject belongs. It should be understood that the terms (such as those defined in commonly used dictionaries) The term “meaningful” should be interpreted as having a meaning consistent with its meaning in the context of related technologies, and unless it is clearly defined in this article, it should not be interpreted as having an idealized or overly formal meaning.

The subject disclosed in this article provides a dynamic random access memory (DRAM) that is programmable and reconfigurable to perform different operations (such as but not limited to addition, multiplication, shifting, maximum/minimum, and comparison) Type processing unit (DPU). In one embodiment, the DPU is based on three transistors and one capacitor (3T1C) DRAM processing and structure. In another embodiment, the DPU is based on a slightly modified DRAM process and structure of a transistor and a capacitor (1T1C). Therefore, the DPU does not contain a special calculation logic circuit system (such as an adder), but uses memory cells to provide calculations with highly parallel operations. In one embodiment, the DPU may include a random calculation array in which addition may be converted into a multiplex operation and multiplication may be converted into a logical operation.

The subject disclosed in this article also provides an environment for programming and reconfiguring DPU including framework extensions, libraries, drivers, compilers, and instruction set architecture (ISA) (Ecosystem) system architecture.

In addition, the subject disclosed in this article provides a processor-in-memory (PIM) solution suitable for data centers and/or mobile applications and for machine learning applications for both binary computing and fixed-point computing. System architecture. The machine learning application of both binary calculation and fixed-point calculation is an application specific integrated circuit for graphics processing unit/application specific integrated circuit (Application Specific Integrated Circuit). Circuit, ASIC) (TPU) / Field Programmable Gate Array (Field Programmable Gate Array, FPGA) machine learning application replacement. In one embodiment, the subject disclosed herein provides a high-performance, high-energy-efficiency, and low-cost system for accelerating deep learning for, for example, a Binary Weight Neural Network.

The subject disclosed in this article is about a DRAM-based processing unit (DPU) that can be formed using dynamic random access memory (DRAM) technology and is reconfigurable and programmable. In one embodiment, the DPU may include a DRAM-type memory cell array and a DRAM-type calculation cell array that may be configured to perform different operations such as addition, multiplication, and sorting.

The internal architecture of the DPU may include a system bus connected to multiple sub-array memory banks. In one embodiment, the system bus can be configured to provide an H-tree-connected sub-array memory bank. Each sub-array can include a local controller, and each individual sub-array can be activated individually or simultaneously. In one embodiment, the DRAM cell can be divided into two arrays-a data cell array and a computing cell array. In one embodiment, the computing cell array can be implemented by DRAM-type memory cells. In another embodiment, the computing cell array can be implemented by a DRAM-type memory cell with a logic circuit system. The internal structure of the DPU may also include a data-shifting circuit and a data-movement circuit. In some embodiments, there may be a third DRAM-like cell array that can be configured for random data calculation.

Figure 1 shows an exemplary implementation of the DPU 100 according to the subject matter disclosed herein Example block diagram. The DPU 100 may include one or more memory banks 101a to 101m, and only the memory banks 101a and 101b of the one or more memory banks 101a to 101m are shown in FIG. 1. Each memory bank 101 may include one or more sub-arrays 102a to 102n, and only the sub-arrays 102a and 102b of the one or more sub-arrays 102a to 102n are shown in FIG. Each memory bank 101 can also include a buffer 103. The buffer 103 can be coupled to the respective sub-array 102 and to the system bus 104. The buffer 103 can read an entire row in the memory bank 102, and then write the row back to the same memory bank or write to another memory bank. The buffer 103 can also broadcast a copy of the row data to a plurality of memory array chips (Mat) 105a to 105n in the sub-array 102. In one embodiment, the memory bank 101 and the system bus 104 may be configured to provide an H-tree connected memory bank.

Each sub-array 102 may include one or more memory array chips (or lanes) 105, and only the memory array of the one or more memory array chips 105 of the sub-array 102a is shown in FIG. Pieces 105a to 105n. Each memory array chip 105 is an area of the DPU 100 that may include a data cell array 106, a calculation cell array 107, and a shift array 108 on the memory array chip. An exemplary memory array chip 105 is indicated in a manner surrounded by a dotted line 109 in FIG. 1. Each memory array chip 105 can share data cell array decoder 110, computing cell array decoder 111, memory array inter-chip shift array 112, and memory array inter-chip forwarding array with adjacent memory array chips 113. In one embodiment, the data cell array decoder 110, the computing cell array decoder 111, and the memory array inter-chip shift array 112 may be physically connected to the sub-array controller 114 between the adjacent memory array chips 105 To alternate arrangement. In a real In an embodiment, the decoders 110 and 111 can operate as conventional DRAM-type memory decoders.

In one embodiment, each memory array chip 105 can be communicatively coupled to the sub-array controller 114. Each sub-array controller 114 can be configured to be independent of other sub-array controllers 114. The sub-array controller 114 can receive commands from the DRAM address bus as an address (addr). In response to the address (ie, address signal), the sub-array controller 114 can provide the decoded address as an output to one of the data cell array 106 and the calculation cell array 107 or the data cell array 106 And calculate both the cell array 107. That is, the sub-array controller 114 can output the source/destination (src/dst) address decoded by the data cell array decoder 110 of the associated data cell array 106, and calculate the cell array In the case of 107, the operation/calculation (op/calc) address decoded by the calculation cell array decoder 111 can be output. The sub-array controller 114 may also receive instructions from the DRAM bus to make two or more sub-array controllers 114 operate in a coordinated manner as an address. The sub-array controller 114 can also control the data movement circuit, such as controlling the memory array on-chip shift array 108, the memory array inter-chip shift array 112, and the memory array inter-chip transfer array 113.

Each data cell array 106 may include one or more dynamic random access memory (DRAM) cells arranged in at least one row and at least one column. In one embodiment, the data cell array 106 may be configured as a traditional DRAM cell array. In one embodiment, the data cell array 106 may include 2K rows and 16 columns. In another embodiment, the data cell array 106 may include less than or more than 2K rows and / Or less or more than 16 columns.

Each computing cell array 107 may include one or more computing cells arranged in at least one row and at least one column. The number of rows in the counting cell array 107 is the same as the number of rows in the data cell array 106. In one embodiment, the computing cell array 107 may include 2K rows and 16 columns. In another embodiment, the computing cell array 107 may include less or more than 2K rows and/or less than or more than 16 columns.

FIG. 2A illustrates an exemplary embodiment of a three-transistor and a capacitor (3T1C) type DRAM calculation cell shape 201 that can be used to calculate the calculation cell in the cell array 107. As shown in FIG. 2A, the 3T1C calculation cell in column X includes a first transistor T ₁ , and the first transistor T ₁ has a source terminal electrically coupled to the write bit line (write BL) promoter, is electrically coupled to a first terminal of capacitor C ₁ and the second transistor gate terminal T ₂ of the two drain terminals, and electrically coupled to the gate terminal forming the write enable line (WEN _X) of child. The second terminal of the capacitor C ₁ is electrically coupled to the ground line. The second transistor T ₂ includes a source terminal electrically coupled to the ground line and a drain terminal electrically coupled to the source terminal of the third transistor T ₃ . It comprises a third transistor T ₃ is electrically coupled to a word line (WL _X) of the gate terminal, and is electrically coupled to a read bit line (read BL) of the drain terminal. The 3T1C calculation cell shape 201 includes a sense amplifier SA, which has an input electrically coupled to the read bit line and an output electrically coupled to the write bit line.

The calculation cells in row Y and the calculation cells in row R can also include three transistors T ₁ to T ₃ and capacitors arranged in a 3T1C DRAM configuration similar to the arrangement of the calculation cells in row X C ₁ . The exemplary three calculation cells and the sense amplifier SA shown in FIG. 2A are configured to provide inverse OR logic operations (ie, X NOR Y logic operations), wherein the results are stored in row R. Although FIG. 2A clearly shows a 3T1C DRAM computing cell with only one row, it should be understood that in another embodiment, the 3T1C computing cell may be configured into multiple rows (ie, 2K rows). It should also be understood that in another embodiment, more than three columns may be provided. In addition, although the 3T1C DRAM calculation cell configuration shown in FIG. 2A provides the inverse OR logic operation, it should be understood that the inverse OR logic operation of the 3TIC DRAM calculation cell shape 201 can be used to provide various functional operations, such as But not limited to mutually exclusive inverse OR (XNOR), addition (ADD), selection (SET), maximum value (MAX), sign (SIGN), multiplexing (MUX), conditional-sum addition logic, CSA), multiplication, popcount, and comparison. The shift arrays 108 and 112 also provide a shift function.

FIG. 2B shows an alternative exemplary embodiment of a transistor and a capacitor (1T1C) type DRAM calculation cell shape 202 that can be used for the calculation cell in the calculation cell array 107 shown in FIG. 1. Depicted in FIG. 2B is shown, calculated 1T1C type DRAM cell comprising a transistor element T _4, T ₄ transistor having a source terminal electrically connected to a first terminal of capacitor C ₂ electrically connected to the bit line (BL The drain terminal of) and the gate terminal electrically connected to the word line (WL). The second terminal of the capacitor C ₂ is electrically coupled to the ground wire. The bit line BL is electrically coupled to the input of the sense amplifier SA. Output of the sense amplifier SA is coupled to the first input multiplexer (MUX), the fifth input terminal of the drain transistor T _5, and an arithmetic logic unit (arithmetic logic unit, ALU) of. The output of the multiplexer is electrically coupled to the input of the latch (LATCH). The source terminal of the fifth transistor T ₅ is electrically coupled to the output of the latch. The output of the arithmetic logic unit is electrically coupled to the second input of the multiplexer. The fifth transistor T ₅ , the multiplexer, the latch, and the arithmetic logic unit in FIG. 2B respectively receive control signals CNTL1 to CNTL4 from the controller 114. In one embodiment, the arithmetic logic unit may be configured to provide an inverse OR function. Although the logic circuit system electrically coupled to the bit line BL in FIG. 2B provides an inverse OR logic operation, it should be understood that the logic circuit system (ie, arithmetic logic unit) electrically coupled to the bit line BL Other functional operations can be provided, such as but not limited to mutually exclusive or (XNOR), addition (ADD), selection (SET), maximum value, sign, multiplexing (MUX), condition and addition logic (CSA), multiplication, Bit 1 counts and compares. The shift arrays 108 and 112 also provide a shift function. It should be understood that only one 1T1C calculation cell is shown in FIG. 2B, and it should be understood that multiple rows and multiple columns of 1T1C calculation cells may be provided.

As can be seen in Figures 2A and 2B, the calculation cell of the DPU does not include specialized complex calculation logic, but includes a relatively simple shape that provides the ability to perform multiple different types of calculations. Re-programmable nature. In addition, the shape of the DPU can be arranged to take advantage of the massive parallelism inherent in the memory structure to perform more calculations faster and more efficiently.

FIG. 3 shows an exemplary embodiment of the memory array on-chip shift array 108 according to the subject matter disclosed herein. To simplify the description of the shift array 108 on the memory array chip, consider the memory array chip 105 in which the width is four rows of calculation cells 107 (for example, the one shown in FIG. 3). Shifting the array of memory array 108 comprises a plurality of sheets arranged in an array of the sixth transistor _{T. 6} (in FIG. 3 are indicative of the plurality of sixth transistors T in a transistor T _{6 6),} 2n shifting Bit line SL (where n is the row of the calculation cell in the memory array chip 105), n+2 left shift control lines SLcL, 2 right shift control lines SRcL, and n shift mask lines SML . Some sixth transistors T _{6 of the on} -chip shift array 108 of the memory array are electrically connected between the write bit line and the 2n shift lines SL, and the others of the shift array 108 on the memory array The sixth transistor T _{6 is} connected between the read bit line and the 2n shift lines SL. The gates of these sixth transistors T ₆ are electrically coupled to the n+2 left shift control lines SLcL and the 2 right shift control lines SRcL. The other sixth transistors T _{6 of the on} -chip shift array 108 of the memory array are electrically connected between the n shift mask lines SML and the 2n shift lines SL. The control line of the shift array 108 on the memory array chip is electrically coupled to the sub-array controller 114 associated with the memory array chip 105.

The on-chip shifting array 108 of the memory array can shift the data in the memory array 105 to the left and right by the appropriate signals on the control lines SLcL and SRcL. For the left shift, data can be filled with sign bits, and each operation is shifted by 1 bit or (n-1) bit, where n is the number of rows of each memory array chip 105 . For the right shift, the information may be 0 or 1 is filled under control of the instruction, and shifted ^{2 0, 2 1, ...,} 2 k-1, 2 k until the line of each memory array sheet Number, where 2 ^k is the number of rows.

FIG. 4A shows an embodiment of a memory array inter-chip shift array 112 according to the subject matter disclosed herein. In order to simplify the description of the inter-chip shift array 112 of the memory array, consider a configuration in which the width of the memory array chip 105 is two rows of calculation cells 107 (for example, as shown in FIGS. 4A to 4C). That is, each memory array chip 105 includes the first row of calculation cells 107a and the second row of calculation cells 107b. The memory array inter-chip shift array 112 includes transistors T _112a and T _112b , transistors T _112c and T _112d , data shift lines 112e and 112f, and a memory array inter-chip shift control line ISLcL. In the memory array chip, the transistor T _112a includes a source terminal electrically coupled to the read bit line of the computing cell 107a in the first row, and a drain terminal electrically coupled to the data shift line 112e . The transistor T _112b includes a source terminal electrically coupled to the read bit line of the computing cell 107b in the second row, and a drain terminal electrically coupled to the data shift line 112f. The data shift lines 112e and 112f are electrically coupled to the buffer 103 (not shown in FIG. 4A). Between different memory array chips, the transistor T _112c includes a source terminal and a drain terminal electrically coupled to the data shift line 112e in the adjacent memory array chip, respectively. The transistor T _112d includes a source terminal and a drain terminal respectively electrically coupled to the data shift line 112f in the adjacent memory array chip. The gates of the transistors T _112c and T _112d are respectively electrically coupled to the respective different inter-chip shift control lines ISLcL of the memory array. The inter-chip shifting array 112 of the memory array can shift the data left and right between different memory arrays by using appropriate signals on the inter-chip shift control line ISLcL of the memory array. The control line of the memory array chip shifting array 112 is electrically coupled to the sub-array controller 114 associated with the memory array chip 105.

FIG. 4B conceptually illustrates a memory array between two calculation cells at the same position in adjacent calculation cell rows 105a and 105b for inter-chip shifting of the left memory array according to the subject matter disclosed in this article Inter-chip shift interconnect configuration. The interconnection configuration shown in FIG. 4B can be conceptually illustrated by an operative interconnection node that is highlighted. For example, the transistors T _112c and T _112d are activated so that a conductive path exists between each transistor, thereby connecting the data shift line 112e between the computing cell rows 105a (left side) and 105b (right side) and 112f. The gate terminals of the transistors T _112c and T _112d are electrically connected to the activated inter-chip shift control line ISLcL of the memory array. The transistors T _112a and T _112b in the memory array 105b are activated to electrically connect the read bit line of the computing cell 107a in the memory array 105b to the memory array on the left side of the memory array 105b The write bit line of the calculation cell 107a in the slice 105a, and the read bit line of the calculation cell 107b in the memory array slice 105b is electrically connected to the memory array slice on the left side of the memory array slice 105b The write bit line of cell 107b in 105a is calculated.

FIG. 4C conceptually illustrates a memory array between two calculation cells at two different positions in adjacent calculation cell rows 105a and 105b for inter-chip shifting of the left memory array according to the subject matter disclosed herein Inter-chip shift interconnect configuration. The interconnection configuration shown in FIG. 4C can be conceptually illustrated by operating interconnection nodes shown emphatically. For example, the transistors T _112c and T _112d are activated so that a conductive path exists between each transistor, thereby connecting the data shift line 112e between the computing cell rows 105a (left side) and 105b (right side) and 112f. The gate terminals of the transistors T _112c and T _112d are electrically connected to the activated inter-chip shift control line ISLcL of the memory array. The transistors T _112a and T _112b in the memory array chip 105a are activated to electrically connect the read bit line of the computing cell 107a in the memory array chip 105a to the memory array located on the right side of the memory array chip 105a The write bit line of the calculation cell 107a in the slice 105b, and the read bit line of the calculation cell 107b in the memory array slice 105a is electrically connected to the memory array slice on the right side of the memory array slice 105a The write bit line of cell 107b in 105b is calculated.

FIG. 5 shows an embodiment of a memory array inter-chip forwarding array 113 according to the subject matter disclosed herein. To simplify the description of the inter-chip transfer array 113 of the memory array, consider a configuration in which the width of the memory array chip 105 is two rows of computing cells 107 (for example, the one shown in FIG. 5). That is, each memory array chip 105 includes the first row of calculation cells 107a and the second row of calculation cells 107b. For the memory array chip 105, the memory array inter-chip forwarding array 113 includes transistors T _113a and T _113b , transistors T _113c and T _113d , and transistors T _113e and T _113f , and 2 ⁿ forwarding data lines FDL (of which n is the number of calculation cell rows in the memory array slice), the forwarding control line FCL, and 2 ^m forwarding section lines FSL (where m is the number of sections). The source terminals of the transistors T _113a and T _113b are respectively electrically connected to the write bit line and the read bit line of the computing cell 107a in the first row. The drain terminals of the transistors T _113a and T _113b are electrically coupled to the first data transfer line FDL 113g. The source terminals of the transistors T _113c and T _113d are respectively electrically connected to the write bit line and the read bit line of the computing cell 107b in the second row. The drain terminals of the transistors T _113c and T _113d are electrically coupled to the second data transfer line FDL 113h. The source terminals of the transistors T _113e and T _113f are electrically coupled to the gate terminals of the transistors T _113a and T _113b , respectively. The drain terminals of the transistors T _113e and T _113f are both coupled to the same forwarding section line FSL. The gate terminals of the transistors T _113e and T _113f are respectively coupled to different forwarding control lines FCL. The inter-chip transfer array 113 of the memory array can transfer data between the memory array slices by transferring appropriate signals on the control line FCL. The control line of the memory array inter-chip transfer array 113 is electrically coupled to the sub-array controller 114 associated with the memory array chip 105 between which data is transferred.

6A to 6G illustrate operations based on inverse OR logic that can be provided by the DPU according to the subject matter disclosed herein. In FIGS. 6A to 6G, the first operand can be stored in row X and the second operand can be stored in row Y or row W. The arrows in FIGS. 6A to 6G indicate the input flow and output flow of the inverse OR logic operation on the entire column of calculation cells. For example, the row X in FIG. 6A may represent the entire row of operands stored in the calculation cell of row X. The result of the inverse logical operation on the operands stored in row X and the operands stored in row Y is stored in the resulting row R. In one embodiment, the operands in column X and column Y may include, for example, 100 rows (ie, x ₁ , x ₂ , ..., x ₁₀₀ , and y ₁ , y ₂ , ..., y ₁₀₀ ) And the result can be stored in the row R (ie, r ₁ , r ₂ ,..., r ₁₀₀ ). That is, x _i NOR y _i = r _i , where i is the row index. In another embodiment, column X may represent only selected groups of calculation cells in the column.

FIG. 6B illustrates an exemplary full adder operation based on a prefix Kogge-Stone adder for N digits. In FIG. 6B, the first N-bit operand is stored in row X and the second N-bit operand is stored in row Y. For the exemplary addition operation shown in FIG. 6B, the intermediate terms G ₀ , P ₀ , G ₁ , P ₁ , G ₂ , P ₂ , ..., G _logN+1 , and P _logN+1 will be calculated. The top block shown in FIG. 6B represents five separate operations that use input operands from column X and column Y to determine G ₀ and P ₀ . In the first operation, the top block determines the inverse of row X (ie, ~X), which is stored in row 1. The second operation determines the inverse of row Y (ie, ~Y), which is stored in row 2. The third operation determines the operation row X NOR row Y, which is stored in row 3. The fourth operation determines the operation G ₀ = column 1 NOR column 2, which is stored in column 4. The fifth operation determines that P ₀ = column 3 NOR column 4, which is stored in column 5.

In the intermediate block shown in FIG. 6B, the intermediate results G ₀ and P ₀ from the top block are used to determine the intermediate results G _i+1 and P _i+1 , where i is the row index. That is, the intermediate results G ₀ and P ₀ determined in the uppermost block shown in FIG. 6B are used to determine the intermediate results G ₁ and P ₁ . The intermediate results G ₁ and P _{1 are} used to determine the intermediate results G ₂ and P ₂ , and the intermediate results G _logN+1 and P _{logN+1 are determined accordingly} . In the bottom block shown in FIG. 6B, the result row R1 and row R2 respectively store the carry result and the sum result of the full adder operation.

FIG. 6C illustrates an exemplary selector operation that can be provided by the 3T1C DRAM to calculate the cell shape 201. Row 1 stores the intermediate result of the inverse of row X (ie, ~X). Row 2 stores the intermediate result of the inverse of row Y (ie, ~Y). Row 3 stores the intermediate result of the inverse of row S (ie, ~S). Row 4 stores the intermediate results of row 1 and NOR row 3. Row 5 stores the intermediate results of row 2 NOR row S. Row 6 stores the intermediate results of row 4 and NOR row 5. Column R stores the inverse result of column 6 (ie, S? X: Y).

FIG. 6D illustrates an alternative exemplary selector operation that can be provided by the 3T1C DRAM calculating cell shape 201. Row 1 stores the intermediate result of the inverse of row X (ie, ~X). Row 2 stores the intermediate result of the inverse of row S (ie, ~S). Row 3 stores the intermediate results of row 1 NOR row S. Row 4 stores the intermediate result of the inverse of row X (ie, ~X). Row R stores the results of row 3 and NOR row 4 (ie, S? X: ~X).

FIG. 6E illustrates an exemplary maximum/minimum calculation that can be provided by the 3T1C DRAM calculating cell shape 201. Row 1 stores the intermediate result of the inverse of row Y (ie, ~Y). Row 2 stores the intermediate result of row X+ (~Y+1). Column 3 stores the intermediate result of C _out >>n. Row 4 stores C _out ? X: The intermediate result of Y. Row R stores the result of MAX(X:Y).

FIG. 6F illustrates an exemplary 1-bit multiplication operation that can be provided by the 3T1C DRAM calculating cell shape 201. Row 1 stores the intermediate results of row X NOR row W. Row 2 stores the intermediate results of row X NOR row 1. Row 3 stores the intermediate results of row W NOR row 1. The result row R stores the result of row 2 NOR row 3, that is, the result of row X XNOR row W.

FIG. 6G illustrates an exemplary multi-bit multiplication operation that can be provided by the 3T1C DRAM calculating cell shape 201. In the upper block shown in FIG. 6G, row 1 stores the intermediate result of the inverse of row W (ie, ~W). Column 2 stores the intermediate result of the inverse of column X shifted to the left 2 ⁱ times (ie, ~X<<2 ⁱ ), where i is the index. Row 3 stores the intermediate results of row 1 NOR row 2, that is, PP _i =~W NOR~X<<2 ⁱ . In the lower region shown in FIG. 6G fast, column 1 store intermediate results of column PP ₀ SUM (sum) column PP _i (i.e., Σ PP _i). Row 2 stores the intermediate result of row 1 XNOR row W _sign . Row R stores the result of X*W.

FIG. 7 shows a block diagram of an exemplary embodiment of a DPU 700 including a random data area 715 according to the subject matter disclosed herein. The various components of the DPU 700 that have the same reference indicators as those of the components of the DPU 100 shown in FIG. 1 are similar, and the description of such similar components has been omitted here. The sub-array 102 of the DPU 700 includes a random data array 715 and a converter-to-stochastic array 716, and a (real) data cell array 106. Calculate the cell array 107 and the memory array on-chip shift array 108.

Each random data array 715 may include one or more random computing cells arranged in at least one row and at least one column. The number of rows in the random data array 715 is the same as the number of rows in the data cell array 106 and the calculation cell array 107. In one embodiment, the random data array 715 may include 2K rows and 16 columns. In another embodiment, the random data array 715 may include less than or more than 2K rows and/or less than or more than 16 columns. In the random data array 715, the existence probability of "1" and 2 ⁿ bits are used to represent the value of n bits. The random number generator in the converter-random array 716 can be used to convert real numbers into random numbers. The bit 1 counting operation can be used to convert random numbers back to real numbers.

Using random calculation methods, addition can be converted into multiple operations and multiplication can be converted into logical operations. For example, FIG. 8A shows a circuit that provides a random addition operation as a multiplexing operation, and FIG. 8B shows a circuit that provides a random multiplication operation as a sum logic operation. The traditional technology of random computing requires huge memory capacity; however, the subject disclosed in this article can be used to provide very efficient random computing because DRAM-style DPUs can perform large parallel operations and MUX operations. The random calculation using the DPU disclosed in this article also makes it possible to speed up complex operations in which deep learning is a typical application.

FIG. 9 shows a system architecture 900 including a DPU according to the subject matter disclosed herein. The system architecture 900 may include a hardware layer 910, a library and driver layer 920, a framework layer 930, and an application layer 940.

The hardware layer 910 may include a hardware device and/or have an embedded DPU (for example, DPU described herein). One embodiment of the device and/or component may be a Peripheral Component Interconnect Express (PCIe) device 911 that may include one or more embedded DPUs. Another embodiment of the device and/or component may be a dual in-line memory module (DIMM) 912 that may include one or more embedded DPUs. It should be understood that the hardware layer 910 of the system architecture 900 is not limited to rapid peripheral component interconnection devices and/or dual in-line memory modules, but may include System on a Chip (SOC) devices or may contain DPUs. Other memory type devices. The DPU that can be embedded in the device and/or component at the hardware layer 910 can be configured similar to the DPU 100 in FIG. 1 and/or similar to the DPU 700 in FIG. 7. In any embodiment, the specific computing cell array of the DPU may be configured to include a 3T1C formula computing cell shape 201 (FIG. 2A) or a 1T1C formula computing cell shape 202 (FIG. 2B).

The library and driver layer 920 of the system architecture 900 may include a DPU library 921, a DPU driver 922, and a DPU compiler 923. The DPU library 921 can be configured to provide optimal mapping functionality and resource allocation functionality for each sub-array in the DPU in the hardware layer 910 of different applications that can operate at the application layer 940. functionality), and scheduling functionality (scheduling functionality).

In one embodiment, the DPU library 921 may provide a high-level application programming interface (API) for the framework layer 930 that may include operations such as move, addition, and multiplication. For example, the DPU library 921 may also include the implementation of standard routines, such as but not limited to For accelerating the deep learning process, forward convolution and backward convolution layers, pooling layers, normalization layers, and activation layers. In one embodiment, the DPU library 921 may include an API-like function that maps the calculation of the entire convolutional layer of a convolution neural network (CNN). In addition, the DPU library 921 may include application programming interface functions for optimizing the mapping process of the convolutional layer calculation to the DPU.

The DPU library 921 may also include functions for mapping any individual or multiple parallelisms in a task (batch, output channel, pixel, input channel, convolution kernel) into a chip, The memory bank, sub-array, and/or memory array slice level corresponds to the DPU parallelism to optimize resource allocation application programming interface functions. In addition, the DPU library 921 may include application programming interface functions that provide optimal DPU configuration at initialization and/or runtime to make a weight between performance (ie, data movement flow) and power consumption. Other application programming interface functions provided by the DPU library 921 can include design-knob-type functions, such as setting the number of active sub-arrays of each memory bank, and the number of active sub-arrays of each active sub-array. The number of input feature maps, the partition of feature maps, and/or the reuse scheme of the convolution core. Some other application programming interface functions can provide additional functions by assigning specific tasks to each sub-array (for example, convolution calculation, channel sum up, and/or data dispatching). Optimize resource allocation. If the operand will To convert between integers and random numbers, the DPU library 921 includes application programming interface functions that meet precise constraints while minimizing costs. In the event that the accuracy is lower than expected, the DPU library 921 may include application programming interface functions that use additional bits to recalculate the value of the random representation, or offload tasks to other hardware (for example, the central processing unit) .

The DPU library 921 may also include application programming interface functions that simultaneously schedule multiple activated sub-arrays in the DPU and schedule data movement so that the data movement is hidden by computing operations.

Another aspect of the DPU library 921 includes an extended interface for further DPU development. In one embodiment, the DPU library 921 can use inverse OR and shift logic to provide an interface for directly programming functionality, so that standard operations (ie, addition, multiplication, maximum/minimum) can be provided. Value, etc.). The extended interface can also provide the following interface: the interface allows operations not specifically supported by the DPU library 921 to be offloaded to the system chip controller (not shown in the figure), the central processing unit/ Graphics processing unit (CPU/GPU) components, and/or central processing unit/tensor processing unit (CPU/TPU) components. Another aspect of the DPU library 921 provides application programming interface functions that use the DPU memory as a memory extension when the DPU memory is not used for calculation.

The DPU driver 922 can be configured to provide an interface connection between the DPU at the hardware layer 910, the DPU library 921, and an operating system (OS) at a higher layer to integrate the DPU hardware layer into a system. That is, the DPU driver 922 exposes the DPU to the system operating system and the DPU library 921. In one implementation In an example, the DPU driver 922 can provide DPU control during initialization. In one embodiment, the DPU driver 922 can send instructions to the DPU in the form of a DRAM-type address or a sequence of DRAM-type addresses and can control the movement of data in and out of the DPU. The DPU driver 922 can provide multiple DPU communications and handle DPU-CPU communications and/or DPU-GPU communications.

The DPU compiler 923 can compile the DPU code from the DPU library 921 into DPU instructions in the form of memory addresses, which are used by the DPU driver 922 to control the DPU. The DPU instruction generated by the DPU compiler 923 may be a single instruction that operates on one column and/or two columns in the DPU; vector instructions, and/or set vectors, instructions read during operation (read-on- operation instruction).

The framework layer 930 can be configured as a library and driver layer 920 and a hardware layer 910 to provide a user-friendly interface. In one embodiment, the frame layer 930 may provide a user-friendly interface compatible with various applications at the application layer 940 and make the DPU hard layer 910 transparent to the user. In another embodiment, the framework layer 930 may include adding a quantitation function to existing traditional methods (such as but not limited to Torch7-type applications and TensorFlow-type applications) The framework is extended. In one embodiment, the framework layer 930 may include adding quantitative functions to a training algorithm. In another embodiment, the framework layer 930 may prioritize the existing batch-normalization methods of division, multiplication, and square root and provide shift approximated methods of division, multiplication, and square root. method). In yet another embodiment, the framework layer 930 may provide an extension that enables the user to set the number of bits used for calculation. In yet another embodiment, the framework layer 930 provides a multi-DPU application programming interface that covers the capabilities of the DPU library and driver layer 920 to the framework layer 930 in the future, so that the user can use multiple graphics processing units in a similar manner The way to use multiple DPU at the hardware layer. Another feature of the framework layer 930 enables the user to assign functions to the DPU or graphics processing unit at the hardware layer 910.

The application layer 940 can include a variety of applications, such as but not limited to image tag processing, autonomous driving/piloting vehicle, and AlphaGo-type deep thinking application (AlphaGo-type deep-mind application), and/or speech research.

Those familiar with this technology will recognize that the novel concepts described in this article can be modified and changed in a variety of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but is limited by the scope of the following patent applications.

100‧‧‧DPU

101a, 101b‧‧‧Memory Bank

102a, 102b‧‧‧Sub-array

103‧‧‧Buffer

104‧‧‧System bus

105a, 105b‧‧‧Memory array chip/computing cell row

105n‧‧‧Memory array chip

106‧‧‧Data cell array

107‧‧‧Calculate cell array/calculate cell

108‧‧‧Shift Array/Memory Array On-chip shift array

109‧‧‧dotted line

110‧‧‧Decoder/Data Cell Array Decoder

111‧‧‧Decoder/Calculation Cell Array Decoder

112‧‧‧Shift Array/Memory Array Inter-chip Shift Array

113‧‧‧Memory array inter-chip forwarding array

114‧‧‧Controller/Sub-Array Controller

addr‧‧‧Address

Claims (20)

A dynamic random access memory (DRAM) processing unit (DPU), comprising: at least one computing cell array, including a plurality of DRAM type computing cells arranged in an array, the array having at least a first predetermined number of rows and A second predetermined number of columns, wherein the first predetermined number is greater than or equal to three and the second predetermined number is greater than or equal to three, each row is configured to provide a digital operation including performing a digital operation on the first column and the second column of the row The dynamic random access memory processing unit of the logic function operates and is configured to store the result of the logic function in the third column of the row, and the at least one computing cell array further includes a third predetermined number Shift lines, the third predetermined number is twice the first predetermined number, each shift line is coupled to the row of the computing cell via at least one corresponding first transistor, the shift line and The corresponding first transistor is configured to shift the content of the two columns of the calculation cell of the selected row by at least two rows in the right or left direction in the at least one calculation cell array; and the controller, Coupled to the at least one computing cell array to configure the at least one computing cell array to perform the dynamic random access memory processing unit operation. The dynamic random access memory processing unit according to the first item of the patent application, wherein the controller receives an instruction for the operation of the dynamic random access memory processing unit via an address bus. The dynamic random access memory processing unit described in the first item of the scope of patent application, wherein at least one row of the DRAM-type computing cells each includes a three-electric crystal Body and a capacitor (3T1C) type DRAM memory cell. In the dynamic random access memory processing unit described in item 3 of the scope of patent application, at least one row of the DRAM-type computing cell provides an inverse OR logic function. In the dynamic random access memory processing unit described in the first item of the patent application, the DRAM computing cells of at least one row each include a transistor and a capacitor (1T1C) DRAM memory cell. According to the dynamic random access memory processing unit described in item 5 of the scope of patent application, each DRAM-based computing cell further includes an arithmetic logic unit (ALU), and the arithmetic logic unit is coupled to the DRAM-based computing cell The bit line of the element, the arithmetic logic unit provides the logic function. The dynamic random access memory processing unit as described in item 6 of the scope of patent application, wherein the arithmetic logic unit provides an inverse OR logic function. The dynamic random access memory processing unit described in the first item of the patent application further includes: at least one memory cell array, including at least one DRAM-type memory cell arranged in the first predetermined number of rows , Each row of the DRAM-type memory cell of at least one data cell array corresponds to a row of the corresponding calculation cell array; and sense amplifiers, coupled to the calculation cells of each row, each sense amplifier includes an input And output, the input is electrically coupled to the read bit line of the calculation cell of the row, and the output is electrically coupled to the write bit of the calculation cell of the row Cell line, wherein the controller is further coupled to the at least one memory cell array to configure the at least one memory cell array to perform memory operations, and wherein the controller further flows through the address The bank receives instructions for the memory operation. The dynamic random access memory processing unit described in item 1 of the scope of the patent application further includes: at least one random computing cell array, including arrays arranged in the first predetermined number of rows and the second predetermined number of columns Each row of the DRAM-style random calculation cell of at least one data cell array corresponds to a row of the corresponding calculation cell array, and each row is configured to provide a first A random logic function for performing operations on the first data stream received by the row and the second data stream received by the second row and configured to store the data stream obtained by the random logic function in the third row Column, wherein the controller is further coupled to the at least one random calculation cell array to configure the at least one random calculation cell array to perform a random logic operation corresponding to the random logic function, and wherein The controller further receives an instruction for the random logic operation via an address bus. A dynamic random access memory (DRAM) processing unit (DPU), including: at least one computing cell array, including a plurality of DRAM type counters arranged in an array Calculating cell elements, the array has at least a first predetermined number of rows and a second predetermined number of columns, wherein the first predetermined number is greater than or equal to three and the second predetermined number is greater than or equal to three, and each row is configured to provide A logic function that performs digital operations on the first column and the second column of the row and is configured to store the result of the logic function in the third column of the row, the at least one computing cell array further includes A third predetermined number of shift lines, the third predetermined number is twice the first predetermined number, and each shift line is coupled to the row of the computing cell via at least one corresponding first transistor, so The shift line and the corresponding first transistor are configured to shift the content of the two columns of the calculation cell of the selected row by at least two rows in the right or left direction in the at least one calculation cell array At least one data cell array, including at least one DRAM-type memory cell arranged in the first predetermined number of rows, each row of the DRAM-type memory cell of the at least one data cell array and a corresponding The row correspondence of the calculation cell array; and a controller, coupled to the at least one calculation cell array to configure the at least one calculation cell array to perform dynamic random access memory processing unit operations, and is coupled to The at least one data cell array is used to perform memory operations. The dynamic random access memory processing unit described in claim 10, wherein the controller receives an instruction for the operation of the dynamic random access memory processing unit via an address bus. According to the dynamic random access memory processing unit described in item 10 of the scope of patent application, wherein at least one row of the DRAM-type computing cell includes three power Crystal and a capacitor (3T1C) type DRAM memory cell, and at least one row of the DRAM type computing cell provides an inverse OR logic function. According to the dynamic random access memory processing unit described in claim 10, the DRAM-type computing cells of at least one row each include a transistor and a capacitor (1T1C)-type DRAM memory cell, and Each DRAM type calculation cell further includes an arithmetic logic unit (ALU), the arithmetic logic unit is coupled to the bit line of the DRAM type calculation cell, and the arithmetic logic unit provides the logic function. The dynamic random access memory processing unit described in the scope of patent application, wherein the arithmetic logic unit provides an inverse OR logic function. The dynamic random access memory processing unit described in item 10 of the scope of the patent application further includes: at least one random computing cell array, including arrays arranged in the first predetermined number of rows and the second predetermined number of columns Each row of the DRAM-style random calculation cell of at least one data cell array corresponds to the row of the corresponding calculation cell array, and each row is configured to provide the first column of the row A random logic function that performs operations on the received first data stream and the second data stream received in the second row and is configured to store the data stream obtained by the random logic function in the third row of the row Wherein the controller is further coupled to the at least one random calculation cell array to configure the at least one random calculation cell array to perform random logic operations Calculation, and wherein the controller further receives an instruction for the random logic operation via an address bus. According to the dynamic random access memory processing unit described in item 15 of the scope of patent application, the DRAM-type random computing cells in at least one row each include a tri-transistor and a capacitor (3T1C)-type DRAM memory cell, Or a transistor and a capacitor (1T1C) type DRAM memory cell. A dynamic random access memory (DRAM) processing unit (DPU), comprising: at least one computing cell array, including a plurality of DRAM type computing cells arranged in an array, the array having at least a first predetermined number of rows and A second predetermined number of columns, wherein the first predetermined number is greater than or equal to three and the second predetermined number is greater than or equal to three, and each row is configured to provide digital operations on the first column and the second column of the row The logic function is configured to store the result of the logic function in the third column of the row, the at least one calculation cell array further includes a third predetermined number of shift lines, and the third predetermined number is Two times the first predetermined number, each shift line is coupled to the row of the computing cell via at least one corresponding first transistor, and the shift line and the corresponding first transistor are configured to In the at least one calculation cell array, the contents of the two columns of the calculation cells of the selected row are shifted by at least two rows in the right or left direction; at least one random calculation cell array includes the A first predetermined number of rows and a plurality of DRAM-style random computing cells of the second predetermined number of columns Each row of the DRAM-style random calculation cell of at least one data cell array corresponds to a row of the corresponding calculation cell array, and each row is configured to provide the first data string received for the first column of the row Flow and the random logic function of the second data stream received in the second row and configured to store the data stream obtained by the random logic function in the third row of the row; and a controller, coupled Connected to the at least one computing cell array to configure the at least one computing cell array to perform dynamic random access memory processing unit operations, and the controller is coupled to the at least one random computing cell array To perform a random logic operation corresponding to the random logic function. The dynamic random access memory processing unit according to the 17th patent application, wherein the controller receives an instruction for the operation of the dynamic random access memory processing unit via an address bus. The dynamic random access memory processing unit described in the 18th patent application, wherein the DRAM-type computing cells of at least one row each include a tri-transistor and a capacitor (3T1C)-type DRAM memory cell, and The DRAM computing cell in at least one row provides an inverse OR logic function. In the dynamic random access memory processing unit described in item 17 of the patent application, the DRAM-type random computing cells in at least one row each include a tri-transistor and a capacitor (3T1C)-type DRAM memory cell.

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