TWI713163B - Semiconductor package - Google Patents

Abstract

The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.

Description

Semiconductor packaging

The present invention relates to the field of semiconductor technology, in particular to a semiconductor package.

Semiconductor integrated circuit dies or chips are usually packaged to prevent external environmental pollution or damage. The package can provide physical protection, stability, and external connections to the die inside the package. In some cases, a Dynamic Random Access Memory (DRAM) package may be stacked on the bottom package to form a package-on-package (PoP) package.

However, the interposer substrate provided between the top package (ie DRAM package) and the bottom package, as well as the high-frequency interconnection traces and/or vias used to communicate with the DRAM chip, will affect the performance of the PoP package. This can have an adverse effect, especially when the bottom package includes a vulnerable radio-frequency (RF) chip.

In view of this, the present invention provides a semiconductor package that can reduce noise to meet the requirements of sensitivity attenuation (de-sense) to protect the signal stability of the package, especially the bottom package.

According to a first aspect of the present invention, a semiconductor package is disclosed, including: a bottom package, including a substrate, radio frequency die and system single die arranged side by side on the substrate, covering the radio frequency die and the system single die The molding compound of, and the intermediary on the molding compound; the connecting element is arranged on the upper surface of the substrate, wherein the connecting element surrounds the system single crystal grain; The signal interference shielding element is arranged between the radio frequency die and the system single die; and the top package is installed on the intermediate body.

The semiconductor package provided by the present invention includes a signal interference shielding element arranged between the radio frequency die and the system single die, which can prevent potential digital high-frequency digital signal interference from the circuit to reduce noise to meet sensitivity attenuation To protect the package, especially the signal stability of the bottom package.

1, 1a, 2, 3, 4: PoP package

10, 10a, 10b, 10c: bottom package

20: Top package

100: Package substrate

100a: upper surface

100b, 400b: bottom surface

104, PTH1, PTH2, PTH3: Through hole

110: molding compound

120: Intermediary

121: reroute traces

122: Fan-out/fan-in pad

B ₁ , B ₂ : bump

C ₁ , C ₂ , C ₃ , C ₄ , C ₅ , C _1a : connecting elements

D ₁ :RF die

D ₂ : SoC die

TB: terminal ball

301: Camera serial interface

302: Display serial interface

303: Universal flash memory interface

304: Serializer and deserializer interface

305: Universal Serial Bus Interface

311, 312, 313, 314: DDR interface

311a, 312a, 313a, 314a: high frequency digital signal trace

E ₁ , E ₂ , E ₃ , E ₄ , E ₅ : Edge

G ₁ , G ₂ : Ground plane

V1, V2, V3: Copper through holes

420: Molding compound RDL

422, 522: pad

400: Redistribution layer

500: core substrate

520: circuit layer

BL: build layer

Tr: Interconnect structure

C2a: The first signal interference shielding component

C2b: The second signal interference shielding component

The present invention can be understood more comprehensively by reading the following detailed description and embodiments. This embodiment is given with reference to the accompanying drawings, in which: Figure 1 is a schematic cross-section showing an exemplary PoP package according to an embodiment of the present invention Figure; Figure 2 is a perspective top view of the exemplary PoP package in Figure 1, showing the side-by-side arrangement of RF die and SoC (system-on-a-chip) die and the bottom of the PoP package The arrangement of the connection elements around the RF die and the SoC die in the package; Figure 3 is a perspective top view of a PoP package according to another embodiment of the present invention, showing the arrangement of the connection elements surrounding the RF die and the SoC die Figure 4 is a schematic partial top view showing the separate ground plane configuration of the exemplary PoP package in Figure 1; Figure 5 is a schematic partial top view showing the PoP package in Figure 1 with or without a separate ground plane Figure 6 is a schematic cross-sectional view of a PoP package according to another embodiment of the present invention; Figure 7 is a schematic cross-sectional view of a PoP package according to another embodiment of the present invention Figure; Figure 8 is a schematic cross-sectional view of a PoP package according to another embodiment of the present invention; Figure 9 is a perspective top view of the exemplary PoP package in Figure 8, showing the side-by-side arrangement of the RF die and SoC die and the connection elements around the RF die and SoC die in the bottom package of the PoP的Layout Package.

In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings that are a part of the present invention, and specific preferred embodiments in which the present invention can be practiced are shown through illustrations. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments can be utilized, and mechanical, structural, and programmatic modifications can be made without departing from the spirit and scope of the present invention. change. Therefore, the following detailed description should not be considered as having a limiting meaning, and the scope of the embodiments of the present invention is only limited by the scope of the appended patent application.

It should be understood that although the terms first, second, third, primary, secondary, etc. may be used in this embodiment to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or Or part should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teaching of the inventive concept, the first or primary element, component, region, layer or part discussed below may be referred to as a second or secondary element, component, region, layer or part.

This embodiment can use spatial relative terms, such as "below", "below", "below", "below", "above", "above" ", "above", etc., in order to describe the relationship between one element or feature and another element or feature in the figure. It should be understood that in addition to the directional orientations shown in the figures, the spatially relative terms are intended to include different orientations of devices in use or operation. For example, if the device in the figure is turned over, elements described as "below" or "below" or "below" other elements or features will be oriented "below" other elements or features ...Above" or "above". Therefore, the exemplary terms "below" and "below" can include directions of above and below. The device can be oriented in other ways (rotation 90 Degree or in other directions), and explain the spatial relative descriptors used in this article accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terms used here are only used for the purpose of describing specific embodiments, and are not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the", "said" are intended to also include the plural form, unless the context clearly dictates otherwise. It will be further understood that when used in this specification, the terms "including" and/or "comprising" designate the existence of the described features, wholes, steps, operations, elements and/or components, but do not exclude the existence or addition of one or more Other features, wholes, steps, operations, elements, components and/or combinations thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the related listed items and may be abbreviated as "/".

It should be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "adjacent to" another element or layer, it can be directly above the other element or layer, It is directly connected, directly coupled or directly adjacent to another element or layer, or there may be an intervening element or layer between the element or layer and another element or layer. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly coupled to" or "directly adjacent" to another element or layer, there are no intervening elements or layers.

Note: (i) the same features throughout the drawings will be denoted by the same reference signs, and they do not necessarily appear in the detailed description of each drawing, and (ii) a series of drawings may show different aspects of a single item , Each aspect is associated with various reference tags that may appear throughout the sequence, or may only appear in selected graphics of the sequence.

The present invention relates to a semiconductor chip package with reduced noise (less than the noise threshold level) to meet the sensitivity attenuation (de-sense) requirement, which is suitable for 5G (fifth generation mobile communications) or automotive applications. According to some embodiments, the semiconductor chip package may be a package-on-package (PoP) package, which includes a DRAM package (top package) stacked on an RF-SiP (Radio-Frequency System In Package) package (bottom package) ), but not limited to this. Can reduce the RF-SiP on the bottom The electromagnetic interference of the RF chip or die in the package, and can reduce the noise in the package from high-frequency digital transmission.

Please refer to Figures 1 and 2. Figure 1 is a schematic cross-sectional view of an exemplary PoP package according to an embodiment of the present invention. Figure 2 is a perspective top view of the exemplary PoP package in Figure 1, showing the side-by-side arrangement of RF (radio frequency) die and SoC (system-on-a-chip) die in the bottom package and the arrangement of RF die and The arrangement of the connection components around the SoC die.

As shown in FIG. 1, according to an exemplary embodiment, the PoP package 1 includes a bottom package 10 and a top package 20 stacked on the bottom package 10. According to an exemplary embodiment, the top package 20 may be a memory package, such as a dynamic random access memory (DRAM) package, with at least one packaged DRAM die, such as double data rate 4 (DDR4). ), low-power DDR4 (low-power DDR4, LPDDR4), double data rate 5 (double data rate 5, DDR5), low-power DDR5 (low-power DDR5, LPDDR5), etc. According to an exemplary embodiment, the bottom package 10 may include a package substrate 100 having an upper surface 100a and a bottom surface 100b. According to an exemplary embodiment, the RF die D1 and the SoC die D2 are mounted on the upper surface 100a of the package substrate 100 in a side-by-side manner.

According to an exemplary embodiment, the package substrate 100 may be a multilayer circuit board or a multilayer wiring board. For example, the packaging substrate 100 may be a two-layer, three-layer or four-layer circuit board, but is not limited thereto. According to an exemplary embodiment, the RF die D1 and the SoC die D2 may be flip chips, and are bonded to the package substrate 100 in a flip chip manner.

For example, the bumps B1 on the active surface of the RF die D1 are electrically connected to the corresponding pads 101 on the upper surface 100 a of the package substrate 100. For example, an antenna (not shown) or a system board (not shown) provided in a printed circuit board may penetrate the interconnection traces 103 and through holes 104 in the package substrate 100 and be provided on the bottom surface 100b of the package substrate 100 The terminal ball TB is electrically coupled to the RF die D1. For example, the bump B2 on the active surface of the SoC die D2 is electrically connected to the corresponding pad on the upper surface 100a of the package substrate 100 102. For example, signals from SoC die D2 or to SoC die D2 can be transmitted through interconnection traces 103 and through holes 104 in package substrate 100 and terminal balls TB provided on bottom surface 100b of package substrate 100.

According to an exemplary embodiment, the RF die D1, the SoC die D2 and the upper surface 100a of the packaging substrate 100 are encapsulated by the molding compound 110. According to an exemplary embodiment, as shown in FIGS. 1 and 2, a plurality of connecting elements C ₁ to C _{5 are} provided on the upper surface 100 a of the package substrate 100. For example, the connecting elements C ₁ to C ₅ may include Cu (copper)/tin (Sn) balls (Cu core solder balls), Cu pillars, Cu bumps, Cu through holes, through-molding plastic through holes, etc. According to an exemplary embodiment, the connecting elements C ₁ to C ₅ are surrounded by a molding compound 110. It should be understood that the number of rows/columns of the connecting elements C ₁ to C ₅ in Figure 2 is only for illustrative purposes. The connecting elements C ₁ to C ₅ may all be disposed on the upper surface 100 a of the package substrate 100. For example, the connecting elements C ₁ to C ₅ may be formed in the same process, so they are coplanar (commonly on the upper surface 100 a). In other embodiments described below, for example, vias V1-V3 or PTH1-PTH3, they can also be coplanar and can be formed in the same process.

According to an exemplary embodiment, as shown in FIG. 2, when viewed from above, the SoC die D2 may have a rectangular shape and may have four edges E1 to E4. The connection elements C1, C2, a part of the connection element C4 and a part of the connection element C5 are arranged around the RF die D1. The connection elements C2 and C3, the remaining connection elements C4 and the remaining connection elements C5 are arranged around the SoC die D2. According to an exemplary embodiment, at least the connecting element C2 directly arranged between the edge E1 of the SoC die D2 and the RF die D1 is grounded, the connecting element C2 can be used as a shielding ball, and the connecting element C2 can be called a signal interference shielding element . In this embodiment, it is convenient to describe that C1~C5 are all connecting elements. However, it is understandable that in the case of both connecting elements and signal interference shielding elements, the connecting elements should refer to C1, C3, C4 and C5, and signal interference The shielding element refers to C2. According to an exemplary embodiment, the connection elements C1, C2 and some of the connection elements C3 may be electrically coupled to the ground. According to an exemplary embodiment, some connecting elements C3 may be electrically coupled to the power source. It should be understood that the function of each connecting element C1~C5 can be referred to according to design requirements and layout design. set. In some embodiments, the connection element near the center of each row or column may be grounded. According to another embodiment, as shown in FIG. 3, the row (row or column) of the connecting element C1 (one or more) may be omitted. Therefore, in Figure 3, the PoP package 1a may only include the connecting elements C2 to C5. In addition, the connecting element C1 can also be grounded.

According to an exemplary embodiment, the connection elements C4 and C5 may be electrically coupled to the top package 20 through the interposer 120. The interposer 120 has rewiring traces 121 and/or fan-out/fan-in pads 122 that match the ball map of the top package 20. Matching may refer to components that can be connected to each other, but does not necessarily mean that the layout is completely consistent. The interposer 120 may include two or more metal layers, such as copper layers. The intermediary 120 may include a laminate material. For example, the intermediary body 120 may include a BT (Bismaleimide/Triazine, bismaleimide/triazine) laminate material. In another embodiment, the interposer 120 may be a Si (silicon) interposer and may include through silicon vias. It should be understood that the structure of the intermediary body 120 shown in the figure is only for illustrative purposes. In another embodiment, the interposer 120 may be a redistributed layer (RDL) interposer, which can make the package structure thinner, thereby making the package smaller and suitable for different needs.

According to an exemplary embodiment, the RF die D1 may be a millimeter wave (mmw) intermediate-frequency (IF) RF die, but is not limited thereto. According to an exemplary embodiment, the SoC die D2 may be a 5G processor die, but is not limited thereto. For example, the SoC die D2 may include interfaces such as a camera serial interface (CSI) 301 and/or a display serial interface (DSI) 302. These interfaces 301 and 302 are designed for high-bandwidth video input (such as CSI) and output (such as DSI). They can be set on the edges E3 and E4, respectively. The SoC die D2 may also include a Universal Flash Storage (UFS) interface 303, which is a JEDEC standard for high-performance mobile storage devices for next-generation data storage. According to a non-limiting exemplary embodiment, the UFS interface 303 may be arranged on the edge E2. SoC die D2 can also include ABB (analog baseband, analog baseband)/SerDes (Serializer and The Deserializer (serializer and deserializer) interface 304 and the universal serial bus (USB) 2.0/3.0 interface 305 can be arranged on the edge E1. The SoC die D2 may also include DDR interfaces 311 to 314, which are respectively arranged on the edges E3 and E4.

It is worth noting that the RF die D1 is arranged near the edge E1. Therefore, the DDR interfaces 311 to 314 are arranged on the edges E3 and E4. The edges E3 and E4 are different from the edge E1 adjacent to the RF die D1 and directly facing the edge E1 of the RF die D1, which can facilitate wiring (such as high-frequency digital signals). Traces 311a~314a), and reduce the possibility of noise or interference due to proximity. Preferably, when viewed from above, the high-frequency digital signal traces 311a~314a in the package substrate 100 are electrically connected to the DDR interfaces 311~314 on the edges E3 and E4, respectively, and do not cross the edge E1 and do not intersect the RF die. D1 overlaps (and certainly does not overlap with the edge E1), so that the possibility of coupling the high-frequency digital signal traces 311a to 314a with, for example, the RF die D1, etc., can be reduced, thereby reducing noise or interference. The high-frequency digital signal traces 311a to 314a can be connected to the connecting elements C4 and C5, and then connected to the interposer 120 via the connecting elements C4 and C5, and then connected to the top package 20. In addition, potential digital signal interference from the high-frequency digital signal traces 311a-314a can be blocked by the grounded connection element C2 disposed between the edge E1 of the SoC die D2 and the RF die D1. A row (row or column) of grounded connection components C2 (signal interference shielding components) inserted between the RF die D1 and the SoC die D2 can effectively reduce noise. The connecting elements C2 may also be two rows or three rows or more. The connecting element C2 can be formed with a plurality of arrangements as shown in Figure 2, or it can be a continuous (or integrally) elongated or rod-shaped or other continuous object. Of course, the connecting element C2 should be divided into two at this time A continuous object and electrically insulated between the two. Of course, considering the convenience of the manufacturing process, the shape and size of the connecting element can be freely selected according to requirements. In this embodiment, the high-frequency digital signal traces 311a~314a can pass between the SoC die D2 and the top package 20 to connect the components C4 and C5 (and of course the interposer 120 (the wiring, fan-out/fan-in soldering) The disk 122, etc.), the solder balls on the interposer 120, etc.) are electrically connected. Therefore, the connecting elements C4 and C5 may interfere with the RF die D1 when transmitting signals. In the present invention, the connecting element C2 is added, and the connecting element C2 is grounded, so that the connecting element C2 can be used to shield these interferences (and release the interference Out), so as to prevent potential digital high-frequency digital signal interference from the circuit (especially interference to the RF die D1) and ensure the normal operation of the package. In addition, in this embodiment, the connecting element C2 is disposed on the package substrate 100 (on the upper surface 100a) and in the molding compound 110, so as to shield the high-frequency digital signal traces 311a~314a, connecting elements C4 and C5. Interference. If the connecting element C2 is arranged in other positions, such as in the package substrate 100 or the intermediate body 120, interference from the high-frequency digital signal traces 311a to 314a and the connecting elements C4 and C5 cannot be shielded. In addition, the connection element C2 in this embodiment can also shield the interference from the connection element C3 that is also located on the packaging substrate 100 and in the molding compound 110 during operation. Therefore, the connection element C2 has the function of shielding different interferences to protect Stable packaging work.

Please refer to FIG. 4 and FIG. 5. FIG. 4 is a schematic partial top view showing the configuration of the separated ground plane of the exemplary PoP package in FIG. Figure 5 is a graph showing the relationship between noise and frequency of the PoP package in Figure 1 with or without a separate ground plane. As shown in Figure 4, the ground plane G1 that can be provided in the intermediary body 120 is electrically connected to the connecting element C1a and to the RF die D1 (part of the connecting element C1 may not be connected to the ground plane G1, but ground Or connected to the ground plane G2, etc.), so the ground plane G1 can be the ground plane of the RF die D1. The SoC die D2 can be connected to the ground plane G2 through wiring such as DRAM wiring (such as 311a-314a, etc.), so the ground plane G2 can be the ground plane of the DRAM and/or the SoC die D2. The ground plane G1 and the ground plane G2 in the intermediary body 120 are separated (for example, the ground planes G1 and G2 are parallel in the vertical direction and not electrically connected to each other; or the ground planes G1 and G2 are on the same layer but electrically insulated from each other), for example Physical separation, that is, electrically insulated from each other (no electrical connection). As shown in Figure 5, by providing such a configuration, the ground planes G1 and G2 are physically separated, so that the ground of the RF die D1 and the ground of the SoC die D2 are not directly connected, thereby avoiding the transmission of noise between each other , Further increase the shielding effect, reduce noise, noise can be reduced to -170dBm/Hz or even lower, especially to reduce the negative impact of SoC die D2 on RF die D1. At this time, since the RF die D1 and the SoC die D2 are not electrically connected, the interference between them is only the interference radiated into the space (such as air or molding compound, etc.), and this part of the interference will be caused by the grounded connection element C2 ( News Interference shielding element), so the solution in this embodiment (the connecting element C2 is provided between the RF die D1 and the SoC die D2 and the ground planes G1 and G2 are physically separated) can further shield the interference, greatly Reduce noise and interference to protect the stability of packaging work. In addition, the connecting element C2 may include a first signal interference shielding element C2a and a second signal interference shielding element C2b, wherein the first signal interference shielding element C2a is connected to the ground plane G1, and the second signal interference shielding element C2b is connected to the ground plane G2. The first signal interference shielding element C2a and the second signal interference shielding element C2b are electrically insulated from each other and are not electrically connected. Therefore, the ground planes G1 and G2 can be grounded independently of each other, thereby avoiding the mutual influence of the RF die D1 and the SoC die D2 (due to the ground connection), and reducing noise and interference.

In some embodiments, the ground planes G1 and G2 may also be provided in the package substrate 100. At this time, it is similar to the above-mentioned ground planes G1 and G2 being arranged in the intermediary body 120. The ground plane G1 of the package substrate 100 is physically separated from the ground plane G2, and it can achieve the same as the ground planes G1 and G2 arranged in the intermediary body 120. The effect of this greatly reduces noise and interference. That is to say, in this embodiment, the ground planes G1 and G2 may be provided only in the interposer 120, or only in the package substrate 100, or the ground planes G1 and G2 may be provided in both the interposer 120 and the package. In the substrate 100. When the ground planes G1 and G2 are both provided in the interposer 120 and the package substrate 100, the first signal interference shielding element C2a can also connect the ground plane G1 in the intermediary 120 with the ground plane G1 in the package substrate 100 In addition, the second signal interference shielding element C2b can also connect the ground plane G2 in the intermediate body 120 with the ground plane G2 in the package substrate 100. In this way, the ground planes G1 (in the interposer 120 and the package substrate 100) and G2 (in the interposer 120 and the package substrate 100) can be grounded independently of each other, thereby avoiding the RF die D1 and the SoC die D2 ( Because of the ground connection) and affect each other, reduce noise and interference. Of course, the ground plane G1 in the interposer 120 and the ground plane G1 in the package substrate 100 may not be connected, but are grounded separately; the ground plane G2 in the intermediary 120 and the ground plane G2 in the package substrate 100 may not be connected. Connected, but grounded separately, the above can be set according to requirements. When the ground planes G1 and G2 are both set in the interposer 120 and the package substrate 100 (of course, the interposer 120 The ground planes G1 and G2 in the neutral and package substrate 100 are separated), the effect of reducing noise and anti-interference is the best, so that the interference can be shielded from the upper and lower directions, which greatly reduces the noise (this effect You can refer to it as shown in Figure 5). Of course, the ground planes G1 and G2 can be provided only in the interposer 120, or only in the packaging substrate 100, to achieve better noise reduction and anti-interference effects.

In addition, in this embodiment, other methods can also be used, for example, when the ground planes G1 and G2 are both provided in the interposer 120 and the package substrate 100; the ground planes G1 and G2 in the interposer 120 are separated , And the ground planes G1 and G2 in the package substrate 100 are electrically connected (either integrated, or coupled to each other, that is, share the same ground plane); or the ground planes G1 and G2 in the intermediate body 120 are electrically connected (Either integrated or coupled to each other, that is, sharing the same ground plane), and the ground planes G1 and G2 in the package substrate 100 are separate. At this time, since at least one of the interposer 120 and the package substrate 100 has separate ground planes G1 and G2, the effect of reducing noise and interference can also be achieved. Of course, both the ground planes G1 and G2 in the interposer 120 and the package substrate 100 are separated (for example, physically separated, that is, electrically insulated) for the best effect. To facilitate understanding, the ground plane G1 located in the intermediate body 120 may be called the first ground plane, the ground plane G2 located in the intermediate body 120 may be called the second ground plane; the ground plane G1 located in the package substrate 100 may be called The third ground plane, the ground plane G2 located in the package substrate 100 may be referred to as the fourth ground plane. Of course, this is not a limitation. The ground plane G1 located in the package substrate 100 may be called the first ground plane, and the ground plane G2 located in the package substrate 100 may be called the second ground plane; the ground plane in the intermediary 120 The plane G1 may be referred to as a third ground plane, and the ground plane G2 located in the intermediate body 120 may be referred to as a fourth ground plane. Or the ground plane G1 becomes the first ground plane, and the ground plane G2 becomes the second ground plane. For clarity, the ground plane G1 in the intermediate body 120 may be referred to as the first ground plane in the intermediate body 120, and the ground plane G2 in the intermediate body 120 may be referred to as the second ground plane in the intermediate body 120; the package substrate 100 The ground plane G1 in the package substrate 100 may be referred to as the first ground plane, and the ground plane G2 in the package substrate 100 may be referred to as the second ground plane in the package substrate 100. Or other naming methods, these are just for convenience solution. As an example, the implementation in this paragraph can be described as that the first ground plane and the second ground plane in the intermediary 120 are physically separated, and the first ground plane and the second ground plane in the package substrate 100 are electrically connected or integrated. Or, the first ground plane and the second ground plane in the package substrate 100 are physically separated, and the first ground plane and the second ground plane in the intermediate body 120 are electrically connected or integrated. Therefore, in other words, as long as at least one of the package substrate 100 and the intermediate body 120 has ground planes G1 and G2 separated from each other in this embodiment, noise and interference can be reduced. Specifically, ground planes G1 and G2 separated from each other may be provided in both the packaging substrate 100 and the intermediate body 120; or only ground planes G1 and G2 separated from each other may be provided in the intermediate body 120 (or only in the packaging substrate 100). Ground planes G1 and G2 separated from each other are provided; or, ground planes G1 and G2 separated from each other are provided in the package substrate 100, and the ground planes G1 and G2 in the intermediary 120 are electrically connected (or integrated); Alternatively, the interposer 120 is provided with ground planes G1 and G2 separated from each other, and the ground planes G1 and G2 in the package substrate 100 are electrically connected (or integrated). The above methods can reduce noise and interference.

FIG. 6 is a schematic cross-sectional view showing a PoP package according to another embodiment of the present invention, in which the same numerical reference numerals represent the same elements, regions or layers. As shown in FIG. 6, the PoP package 2 includes a bottom package 10a and a top package 20 stacked on the bottom package 10a. The bottom package 10a may include a redistribution layer (RDL) 400, and the input/output pads on the RF die D1 and the SoC die D2 may be redistributed through the RDL 400 to form a pad BP on the bottom surface 400b, such as a ball grid The terminal ball TB of the ball grid array (BGA) ball is mounted on the corresponding pad BP. Similarly, the RF die D1 and the SoC die D2 are encapsulated by the molding compound 110, and the copper through holes V1 to V3 may be formed in the molding compound 110, and the copper through holes V1 to V3 are electrically connected to the molded RDL 420. The pad 422 for (connecting) the top package 20 is formed in the RDL 420 on the mold. The top package 20, such as the LPDDR4 or LPDDR5 DRAM package, can be electrically connected to the DDR interface of the SoC die D2 by molding the RDL 420, copper vias V1~V3 and RDL 400. As shown in Figure 2 or Figure 3, the layout of the copper vias V2 is similar to the connection element C2. The grounded copper via V2 can be used as a shielding element to prevent potential digital high-frequency digital signal interference from the circuit. Using RDL 400 can make The package structure is thinner, so that the package volume is smaller and suitable for different needs.

FIG. 7 is a schematic cross-sectional view showing a PoP package according to another embodiment of the present invention, in which the same numeral numbers represent the same elements, regions or layers. As shown in FIG. 7, similarly, the PoP package 3 includes a bottom package 10b and a top package 20 stacked on the bottom package 10b. The bottom package 10b may be an embedded die package. The RF die D1 and the SoC die D2 are embedded in the substrate and interconnected through the substrate manufacturing process to form a system-in-board package. For example, the RF die D1 and the SoC die D2 may be embedded in the core substrate 500. The core substrate 500 may include a copper clad laminate (CCL) substrate or an organic laminate substrate known in the art. A build-up layer BL (Build-up layer) such as high-density interconnect (HDI) traces and laser drilling and an interconnect structure Tr (interconnect structure) may be formed on the core substrate 500. The through holes PTH1 ˜PTH3 may be formed in the core substrate 500 of the bottom package 10 b, and the through holes PTH1 ˜PTH3 may be electrically coupled to the circuit layer 520. The pad 522 for (connecting) the top package 20 may be formed in the circuit layer 520. The top package 20 such as the LPDDR4 or LPDDR5 DRAM package can be electrically connected to the DDR interface of the SoC die D2 through the circuit layer 520, the through holes PTH1~PTH3 and the interconnect structure Tr of the substrate 500. The layout of the through holes PTH2 is similar to the connection element C2 shown in FIG. 2 or FIG. 3. The ground via PTH2 can be used as a shielding element to block potential digital signal interference from high-frequency digital signals.

Please refer to FIG. 8 and FIG. 9. FIG. 8 is a schematic cross-sectional view of a PoP package according to another embodiment of the present invention. Figure 9 is a perspective top view of the PoP package, showing the side-by-side arrangement of the RF die and SoC die in Figure 8 and the connection elements around the RF die and SoC die in the bottom package of the exemplary PoP的Layout Package.

As shown in FIG. 8, the PoP package 4 includes a bottom package 10c and a top package 20 stacked on the bottom package 10c. According to an exemplary embodiment, the top package 20 may be a memory package, such as a DRAM package having at least one packaged DRAM die, such as DDR4, LPDDR4, DDR5, LPDDR5, etc. According to an exemplary embodiment, the bottom package 10c may include a package substrate 100, and the package The substrate 100 has an upper surface 100a and a bottom surface 100b. According to an exemplary embodiment, the RF die D1 and the SoC die D2 are mounted on the upper surface 100a of the package substrate 100 in a side-by-side manner.

According to an exemplary embodiment, likewise, the package substrate 100 may be a multilayer circuit board or a multilayer wiring board. For example, the packaging substrate 100 may be a two-layer, three-layer or four-layer circuit board, but is not limited thereto. According to an exemplary embodiment, the RF die D1 and the SoC die D2 may be flip-chip chips, and may be bonded to the package substrate 100 in a flip-chip manner.

According to an exemplary embodiment, the RF die D1, the SoC die D2 and the upper surface 100a of the packaging substrate 100 are encapsulated by the molding compound 110. According to an exemplary embodiment, as shown in FIGS. 8 and 9, a plurality of connecting elements C2 to C5 are provided on the upper surface 100 a of the package substrate 100. For example, the connecting elements C2 to C5 may include Cu/Sn balls (Cu core solder balls), Cu pillars, Cu bumps, Cu through holes, through-molded through holes, and the like. According to an exemplary embodiment, the connecting elements C2 to C5 are surrounded by a molding compound 110. According to an exemplary embodiment, the connecting elements C2 to C5 may be electrically coupled to the top package 20 through the intermediary 120. The interposer 120 has rewiring traces and/or fan-out/fan-shaped pads that match the solder ball layout of the top package 20. The interposer 120 may include two or more metal layers, such as copper layers. The intermediary 120 may include a laminate material. For example, the intermediary 120 may include a BT (bismaleimide/triazine) laminate material. In another embodiment, the interposer 120 may be a Si interposer and may include through silicon vias. It should be understood that the structure of the intermediary body 120 shown in the figure is only for illustrative purposes.

The size of the packaging substrate 100 is larger than the upper interposer 120. Therefore, only the SoC die D2 is completely surrounded by the connecting elements C2 to C5. In addition, only the SoC die D2 overlaps the interposer 120. The high-frequency digital signal traces in the package substrate 100 that are electrically connected to the DDR interfaces on the edges E3 and E4, respectively, do not intersect the edge E1 and do not overlap the RF die D1. Using a smaller-sized intermediary body 120 can save the cost of the intermediary body 120. The grounded connection element C2 can be used as a shielding element to block potential digital signal interference from high-frequency digital signals.

Although the embodiments of the present invention and their advantages have been described in detail, it should be understood Yes, various changes, substitutions and alterations can be made to the present invention without departing from the spirit of the present invention and the scope defined by the scope of the patent application. The described embodiments are only for illustrative purposes in all aspects and are not used to limit the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: bottom package

20: Top package

100: Package substrate

100a: upper surface

100b: bottom surface

104: Through hole

110: molding compound

120: Intermediary

121: reroute traces

122: Fan-out/fan-in pad

B ₁ , B ₂ : bump

C ₁ , C ₂ , C ₃ : connecting components

D ₁ :RF die

D ₂ : SoC die

TB: terminal ball

Claims (8)

A semiconductor package includes: a bottom package, including a substrate, a radio frequency die and a system single die arranged side by side on the substrate, a molding compound covering the radio frequency die and the system single die, and the molding compound The connecting element is arranged on the upper surface of the substrate, wherein the connecting element surrounds the system single crystal grain; the signal interference shielding element is arranged between the radio frequency crystal grain and the system single crystal grain, and is grounded And a top package mounted on the intermediate body; wherein the connecting element and the signal interference shielding element are surrounded by the molding compound, and the connecting element is coplanar with the signal interference shielding element. The semiconductor package according to claim 1, wherein the top package is a memory package, and the memory package is a dynamic random access memory package having at least one packaged dynamic random access memory die, The radio frequency die is a millimeter wave intermediate frequency radio frequency die. The semiconductor package according to item 1 of the scope of patent application, wherein the connection element includes copper/tin balls, copper pillars, copper bumps, copper through holes or through-molded through holes. The semiconductor package according to item 1 of the scope of patent application, wherein the interposer includes rewiring traces and/or fan-out/fan-in pads matching the solder ball layout of the top package. The semiconductor package according to the first item of the scope of patent application, wherein the interposer includes a silicon interposer or a redistribution layer interposer. The semiconductor package according to claim 1, wherein the system single die includes a first edge and a second edge, the first edge is adjacent to the radio frequency die and directly faces the radio frequency die, and the first edge Two edges are arranged with double data rate interfaces, and the first edge is different from the second edge. The semiconductor package according to item 1 of the scope of patent application, which further includes a first ground plane and a second ground plane; the first ground plane and the second ground plane are physically separated; The radio frequency die is electrically coupled to the first ground plane, and the system single die is electrically coupled to the second ground plane. The semiconductor package according to item 7 of the scope of patent application, wherein the first ground plane and the second ground plane are both provided in the intermediary body and also in the package substrate.

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