CN112349702A

CN112349702A - Semiconductor package

Info

Publication number: CN112349702A
Application number: CN201910850132.6A
Authority: CN
Inventors: 林圣谋; 吴文洲; 刘兴治
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2019-08-07
Filing date: 2019-09-02
Publication date: 2021-02-09
Also published as: TW202107639A; TWI713163B

Abstract

The invention discloses a semiconductor package, comprising: a bottom package comprising a substrate, a radio frequency die and a system on die arranged in a side-by-side manner on the substrate, a molding compound covering the radio frequency die and the system on die, and an interposer on the molding compound; a connection element disposed on an upper surface of the substrate, wherein the connection element surrounds the system single die; a signal interference shielding element disposed between the radio frequency die and the system-on-die; and a top package mounted on the interposer. The signal interference shielding element can prevent potential digital high-frequency digital signal interference from the circuit, reduce noise to meet the requirement of sensitivity attenuation, and protect the stability of the signal of the package, particularly the bottom package.

Description

Semiconductor package

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor package.

Background

Semiconductor integrated circuit dies or chips are often packaged to prevent contamination or damage from the external environment, etc. The package may provide physical protection, stability, and external connections to the die inside the package. In some cases, Dynamic Random Access Memory (DRAM) packages may be stacked on a bottom package to form a package-on-package (PoP) package.

However, the interposer substrate disposed between the top package (i.e., the DRAM package) and the bottom package, as well as the high frequency interconnect traces and/or vias used to communicate with the DRAM chips, can adversely affect the performance of the PoP package, particularly when the bottom package includes a vulnerable radio-frequency (RF) chip.

Disclosure of Invention

Accordingly, the present invention provides a semiconductor package that can reduce noise to meet the de-sense requirement to protect the signal stability of the package, especially the bottom package.

According to a first aspect of the present invention, there is disclosed a semiconductor package comprising:

a bottom package comprising a substrate, a radio frequency die and a system on die arranged in a side-by-side manner on the substrate, a molding compound covering the radio frequency die and the system on die, and an interposer on the molding compound;

a connection element disposed on an upper surface of the substrate, wherein the connection element surrounds the system single die;

a signal interference shielding element disposed between the radio frequency die and the system-on-die; and

a top package mounted on the interposer.

The semiconductor package provided by the invention comprises a signal interference shielding element arranged between the radio frequency die and the system single die, and can prevent potential digital high-frequency digital signal interference from a circuit, reduce noise to meet the requirement of sensitivity attenuation, and protect the signal stability of the package, particularly a bottom package.

Drawings

Fig. 1 is a schematic cross-sectional view illustrating an exemplary PoP package according to one embodiment of the present invention;

fig. 2 is a perspective top view of the exemplary PoP package of fig. 1, showing a side-by-side arrangement of an RF die and an SoC (system-on-a-chip) die and an arrangement of connection elements around the RF die and the SoC die in a bottom package of the PoP package;

fig. 3 is a perspective top view of a PoP package showing the arrangement of connecting elements around an RF die and an SoC die according to another embodiment of the invention;

fig. 4 is a schematic partial top view illustrating a split ground plane configuration of the exemplary PoP package of fig. 1;

fig. 5 is a graph showing noise versus frequency for the PoP package of fig. 1 with or without a separate ground plane;

fig. 6 is a schematic cross-sectional view of a PoP package according to another embodiment of the invention;

fig. 7 is a schematic cross-sectional view of a PoP package according to yet another embodiment of the invention;

fig. 8 is a schematic cross-sectional view of a PoP package according to yet another embodiment of the invention;

fig. 9 is a perspective top view of the exemplary PoP package of fig. 8, showing a side-by-side arrangement of an RF die and an SoC die and an arrangement package of connection elements disposed around the RF die and the SoC die in a bottom package of the PoP.

Detailed Description

In the following detailed description of the embodiments of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

It will be understood that, although the present embodiments may use the terms first, second, third, primary, secondary, etc. to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first or major element, component, region, layer or section discussed below could be termed a second or minor element, component, region, layer or section without departing from the teachings of the present inventive concept.

The present embodiments may use spatially relative terms, such as "below …," "below …," "below …," "above …," "above …," etc., to facilitate describing one element or feature's relationship to another element or feature in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the directional orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below …" or "below …" or "below" other elements or features would then be oriented "above" or "over" … the other elements or features. Thus, the exemplary terms "below …" and "below" can include both an above and below orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items and may be abbreviated as "/".

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, directly connected to, directly coupled to or directly adjacent to the other element or layer or intervening elements or layers may be present between the element or layer and the other element or layer. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly adjacent to" another element or layer, there are no intervening elements or layers present.

Note that: (i) like features throughout the drawings will be referred to by like reference numerals and they do not necessarily appear in the detailed description of each figure, and (ii) a series of drawings may show different aspects of a single item, each aspect being associated with various reference labels that may appear throughout the sequence, or perhaps appearing only in selected graphics of the sequence.

The present invention relates to a semiconductor chip package with reduced noise (less than a noise threshold level) to meet a sensitivity attenuation (de-sense) requirement, which is suitable for 5G (fifth generation mobile communication) or automotive applications. According to some embodiments, the semiconductor chip Package may be a Package on Package (PoP) Package including, but not limited to, a DRAM Package (top Package) stacked on a RF-SiP (Radio-Frequency System In Package) Package (bottom Package). Electromagnetic interference to the RF chip or die in the bottom RF-SiP package may be mitigated and intra-package noise from high frequency digital transmissions may be reduced.

Referring to fig. 1 and 2, fig. 1 is a schematic cross-sectional view of an exemplary PoP package according to one embodiment of the invention. Fig. 2 is a perspective top view of the exemplary PoP package of fig. 1, showing a side-by-side arrangement of an RF (radio frequency) die and an SoC (system-on-a-chip) die in a bottom package and an arrangement of connection elements disposed around the RF die and the SoC die.

As shown in fig. 1, according to an exemplary embodiment, a PoP package 1 includes a bottom package 10 and a top package 20 stacked on the bottom package 10. According to an exemplary embodiment, the top package 20 may be a memory package, such as a Dynamic Random Access Memory (DRAM) package, having at least one packaged DRAM die, such as double data rate 4 (DDR 4), low power DDR4(low-power DDR4, LPDDR4), double data rate 5(double data rate 5, DDR5), low power DDR5(low-power DDR5, LPDDR5), and the like. According to an exemplary embodiment, the bottom package 10 may include a package substrate 100 having an upper surface 100a and a bottom surface 100 b. According to an exemplary embodiment, the RF die D1 and the SoC die D2 are mounted on the upper surface 100a of the package substrate 100 in a side-by-side manner.

According to an exemplary embodiment, the package substrate 100 may be a multilayer circuit board or a multilayer wiring board. For example, the package substrate 100 may be a two-layer, three-layer or four-layer circuit board, but is not limited thereto. According to an exemplary embodiment, the RF die D1 and the SoC die D2 may be flip chip (flip) chips and are flip chip bonded to the package substrate 100.

For example, bumps B1 on the active surface of RF die D1 are electrically connected to corresponding pads 101 on the upper surface 100a of package substrate 100. For example, an antenna (not shown) or a system board (not shown) disposed in a printed circuit board may be electrically coupled to the RF die D1 through the interconnect traces 103 and vias 104 in the package substrate 100 and the terminal balls TB disposed on the bottom surface 100b of the package substrate 100. For example, bumps B2 on the active surface of SoC die D2 are electrically connected to corresponding pads 102 on the upper surface 100a of the package substrate 100. For example, signals from SoC die D2 or to SoC die D2 may be transmitted through interconnect traces 103 and vias 104 in package substrate 100, and terminal balls TB disposed on bottom surface 100b of package substrate 100.

According to an exemplary embodiment, RF die D1, SoC die D2, and upper surface 100a of package substrate 100 are encapsulated by molding compound 110. According to an exemplary embodiment, as shown in fig. 1 and 2, a plurality of connection elements C1-C5 are disposed on the upper surface 100a of the package substrate 100. For example, the connection elements C1-C5 may include Cu (copper)/tin (Sn) balls (Cu core solder balls), Cu pillars, Cu bumps, Cu vias, through mold compound vias, and the like. According to an exemplary embodiment, the connecting elements C1-C5 are surrounded by a molding compound 110. It should be understood that the number of rows/columns of connecting elements C1-C5 in fig. 2 is for illustration purposes only. The connection elements C1-C5 may all be disposed on the upper surface 100a of the package substrate 100, for example, the connection elements C1-C5 may be formed in the same process so that they are coplanar (collectively on the upper surface 100 a). In other embodiments described below, such as through-holes V1-V3 or PTH1-PTH3, may also be coplanar and may be formed in the same process.

According to an exemplary embodiment, as shown in fig. 2, the SoC die D2 may have a rectangular shape and may have four edges E1-E4 when viewed from above. The connection elements C1, C2, a portion of the connection element C4, and a portion of the connection element C5 are disposed around the RF die D1. Connection elements C2 and C3, the remaining connection elements C4 and the remaining connection elements C5 are arranged around SoC die D2. According to an exemplary embodiment, at least the connection element C2 disposed directly between the edge E1 of the SoC die D2 and the RF die D1 is grounded, the connection element C2 may be used as a shielding ball, and the connection element C2 may be referred to as a signal interference shielding element. It is convenient to describe in this embodiment that C1-C5 are all connection elements, however, it is understood that in the case of having both connection elements and signal interference shielding elements, the connection elements shall refer to C1, C3, C4 and C5, and the signal interference shielding element to refer to C2. According to an exemplary embodiment, the connection elements C1, C2 and some of the connection elements C3 may be electrically coupled to ground. According to an exemplary embodiment, some of the connection elements C3 may be electrically coupled to a power source. It should be understood that the function of each connecting element C1-C5 may be dictated by design requirements and layout design. In some embodiments, the connecting elements near the center of each row or column may be grounded. According to another embodiment, as shown in fig. 3, the row(s) (row or column) of connecting elements C1 may be omitted. Thus, in fig. 3, the PoP package 1a may include only the connection elements C2 to C5. Furthermore, the connecting element C1 can also be connected to ground.

According to an exemplary embodiment, the connection elements C4 and C5 may be electrically coupled to the top package 20 through the interposer 120. The interposer 120 has rerouting traces 121 and/or fan-out/fan-in pads 122 that match the ball map of the top package 20. Where matching may mean that there are elements that may be connected to each other, and not necessarily that the arrangement is completely uniform. Interposer 120 may include two or more metal layers, such as copper layers. The interposer 120 may include a laminate material. For example, interposer 120 may include a BT (bismalimide/Triazine) laminate. In another embodiment, interposer 120 may be a Si (silicon) interposer and may include through-silicon vias. It should be understood that the structure of the interposer 120 shown in the figures is for illustration purposes only. In yet another embodiment, the interposer 120 may be a redistribution layer (RDL) interposer, which may allow the package structure to be thinner, thereby allowing the package to be smaller and more compact for different requirements.

According to an example embodiment, the RF die D1 may be a millimeter-wave (mmw) intermediate-frequency (IF) RF die, but is not limited thereto. According to an example embodiment, SoC die D2 may be a 5G processor die, but is not so limited. For example, SoC die D2 may include interfaces such as Camera Serial Interface (CSI) 301 and/or Display Serial Interface (DSI) 302. These

interfaces

301 and 302 are designed for high bandwidth video input (e.g., CSI) and output (e.g., DSI). They may be provided on the edges E3 and E4, respectively. SoC die D2 may also include Universal Flash Storage (UFS) interface 303, which is a JEDEC standard for high performance mobile Storage devices suitable for next generation data Storage. According to a non-limiting exemplary embodiment, UFS interface 303 may be disposed on edge E2. SoC die D2 may also include ABB (analog baseband)/SerDes (Serializer and Deserializer) interface 304 and Universal Serial Bus (USB) 2.0/3.0 interface 305, which may be disposed on edge E1. SoC die D2 may also include DDR interfaces 311-314 disposed on edges E3 and E4, respectively.

Notably, RF die D1 is disposed near edge E1. Thus, the DDR interfaces 311-314 are disposed on edges E3 and E4, and edges E3 and E4 are different from edge E1 which is adjacent to the RF die D1 and directly faces the RF die D1, which facilitates routing (e.g., high frequency digital signal traces 311a-314 a) and reduces the likelihood of noise or interference due to proximity. Preferably, when viewed from above, the high frequency digital signal traces 311a-314a in the package substrate 100 are electrically connected to the DDR interfaces 311-314 on the edges E3 and E4, respectively, and do not cross the edge E1 and do not overlap the RF die D1 (and certainly do not overlap the edge E1), so that the possibility of coupling the high frequency digital signal traces 311a-314a to, for example, the RF die D1 is reduced, thereby reducing noise or interference. The high frequency digital signal traces 311a-314a may be connected to connection elements C4 and C5, which in turn are connected to the interposer 120 via connection elements C4 and C5, which in turn are connected to the top package 20. In addition, potential digital signal interference from the high frequency digital signal traces 311a-314a may be blocked by the grounded connection element C2 disposed between the edge E1 of the SoC die D2 and the RF die D1. A row (row or column) of grounded connection elements C2 (signal interference shielding elements) interposed between RF die D1 and SoC die D2 may effectively reduce noise. The connecting elements C2 may also be in two or three or more rows. The connecting element C2 may be formed of multiple strips or bars or other continuous objects as shown in fig. 2, or may be continuous (or integral), in which case the connecting element C2 should be divided into two continuous objects and electrically insulated from each other. Of course, the shape, size, etc. of the connecting member can be freely selected according to the requirements in consideration of the convenience of the manufacturing process. In this embodiment, the SoC die D2 and the top package 20 can be electrically connected through the high frequency digital signal traces 311a-314a, the connection elements C4 and C5 (and of course the interposer 120 (routing, fan-out/fan-in pads 122, etc.), solder balls on the interposer 120, etc.), so that the connection elements C4 and C5 may interfere with the RF die D1 during signal transmission. In the present invention, the connection element C2 is added and the connection element C2 is grounded, so that the connection element C2 can be used to shield (and release) these interferences, thereby preventing potential digital high frequency digital signal interferences from the circuit (especially interferences to the RF die D1) and ensuring the proper operation of the package. In addition, the connecting element C2 is disposed on the package substrate 100 (on the upper surface 100 a) and in the molding compound 110 in this embodiment, so as to shield the interference from the high frequency digital signal traces 311a-314a, the connecting elements C4 and C5. If the connection element C2 is disposed at another position, for example, in the package substrate 100 or in the interposer 120, the interference from the high-frequency digital signal traces 311a to 314a, the connection elements C4, and C5 cannot be shielded. In addition, the connecting element C2 in this embodiment can also shield interference from the connecting element C3 and the like on the package substrate 100 and in the molding compound 110 during operation, so the connecting element C2 has the function of shielding different interference to protect the stability of the package operation.

Referring to fig. 4 and 5, fig. 4 is a schematic partial top view illustrating the configuration of the separated ground planes of the exemplary PoP package of fig. 1. Fig. 5 is a graph showing (in the case of) noise versus frequency for the PoP package of fig. 1 with or without a separate ground plane. As shown in fig. 4, ground plane G1, which may be disposed in interposer 120, is electrically connected to connection elements C1a and to RF die D1 (portions of connection elements C1 may not be connected to ground plane G1, but instead be grounded or connected to ground plane G2, etc.), so ground plane G1 may be the ground plane of RF die D1. SoC die D2 may be connected to ground plane G2 by a wire, such as a DRAM wire (e.g., 311a-314a, etc.), so ground plane G2 may be the ground plane of the DRAM and/or SoC die D2. The ground plane G1 in the interposer 120 is separated from the ground plane G2 (e.g., the ground planes G1 and G2 are parallel in the vertical direction and not electrically connected to each other; or the ground planes G1 and G2 are in the same layer but electrically isolated from each other), e.g., physically separated, i.e., electrically isolated from each other (not electrically connected). By providing such a configuration, as shown in fig. 5, the physical separation of ground planes G1 and G2 may allow the ground of RF die D1 and the ground of SoC die D2 to be not directly connected, thereby avoiding the transmission of noise therebetween, further increasing the shielding effect, reducing noise, which may be reduced to-170 dBm/Hz or even lower, particularly reducing the negative impact of SoC die D2 on RF die D1. At this time, since the RF die D1 and the SoC die D2 are not electrically connected, only the interference between them is the interference emitted into the space (e.g., air or molding compound, etc.), and this interference is shielded by the grounded connection element C2 (signal interference shielding element), so the scheme in this embodiment (the connection element C2 is disposed between the RF die D1 and the SoC die D2, and the ground planes G1 and G2 are physically separated) can further shield the interference, thereby greatly reducing noise and interference, and protecting the stability of the package operation. Further, the connection element C2 may include a first signal interference shielding element C2a and a second signal interference shielding element C2b, wherein the first signal interference shielding element C2a is connected to the ground plane G1 and the second signal interference shielding element C2b is connected to the ground plane G2. The first and second signal interference shielding elements C2a and C2b are electrically isolated from each other and not electrically connected. Therefore, the ground planes G1 and G2 can be grounded independently from each other, thereby avoiding the RF die D1 and the SoC die D2 from interfering with each other (due to the ground connection), and reducing noise and interference.

In some embodiments, ground planes G1 and G2 may also be disposed in the package substrate 100. . At this time, similar to the arrangement of the ground planes G1 and G2 in the interposer 120, the ground plane G1 of the package substrate 100 is physically separated from the ground plane G2, and the same effect as that of the arrangement of the ground planes G1 and G2 in the interposer 120 can be achieved, thereby greatly reducing noise and interference. That is, in the present embodiment, the ground planes G1 and G2 may be provided only in the interposer 120, or only in the package substrate 100, or the ground planes G1 and G2 may be provided in both the interposer 120 and the package substrate 100. When the ground planes G1 and G2 are disposed in both the interposer 120 and the package substrate 100, the first signal interference shielding element C2a may also connect the ground plane G1 in the interposer 120 with the ground plane G1 in the package substrate 100, and the second signal interference shielding element C2b may also connect the ground plane G2 in the interposer 120 with the ground plane G2 in the package substrate 100. In this way, the ground planes G1 (in the interposer 120 and in the package substrate 100) and G2 (in the interposer 120 and in the package substrate 100) can be grounded independently of each other, thereby avoiding the RF die D1 and the SoC die D2 from interfering with each other (due to the connection to ground) and reducing noise and interference. Of course, the ground plane G1 in the interposer 120 and the ground plane G1 in the package substrate 100 may not be connected, but may be grounded, respectively; the ground plane G2 in the interposer 120 and the ground plane G2 in the package substrate 100 may not be connected, but may be grounded, and both may be provided as required. When the ground planes G1 and G2 are disposed in both the interposer 120 and the package substrate 100 (of course, the ground planes G1 and G2 in the interposer 120 and the package substrate 100 are separated), the noise and interference reduction effect is best, so that the interference can be shielded from both the upper and lower directions, and the noise is greatly reduced (the effect can be seen with reference to fig. 5). Of course, the ground planes G1 and G2 may be disposed only in the interposer 120 or only in the package substrate 100, which may achieve better noise reduction and interference resistance.

In addition, in the present embodiment, other manners may also be adopted, for example, when the ground planes G1 and G2 are provided in both the interposer 120 and the package substrate 100; the ground planes G1 and G2 in the interposer 120 are separate, while the ground planes G1 and G2 in the package substrate 100 are electrically connected (either integral or coupled to each other, i.e., share a single ground plane); alternatively, the ground planes G1 and G2 in the interposer 120 are electrically connected (either integral or coupled to each other, i.e., share a ground plane), while the ground planes G1 and G2 in the package substrate 100 are separate. At this time, since at least one of the interposer 120 and the package substrate 100 has the separate ground planes G1 and G2, noise and interference can be reduced. Of course, it is most effective that the ground planes G1 and G2 in the interposer 120 and the package substrate 100 are separate (e.g., physically separate, i.e., electrically isolated). For ease of understanding, the ground plane G1 located in the interposer 120 may be referred to as a first ground plane, and the ground plane G2 located in the interposer 120 may be referred to as a second ground plane; the ground plane G1 located in the package substrate 100 may be referred to as a third ground plane, and the ground plane G2 located in the package substrate 100 may be referred to as a fourth ground plane. Of course, this is not a limitation, and the ground plane G1 in the package substrate 100 may be referred to as a first ground plane, and the ground plane G2 in the package substrate 100 may be referred to as a second ground plane; the ground plane G1 located in the interposer 120 may be referred to as a third ground plane, and the ground plane G2 located in the interposer 120 may be referred to as a fourth ground plane. Alternatively, the ground planes G1 may be the first ground plane and the ground planes G2 may be the second ground plane. For clarity, ground plane G1 in interposer 120 may be referred to as a first ground plane in interposer 120, and ground plane G2 in interposer 120 may be referred to as a second ground plane in interposer 120; the ground plane G1 in the package substrate 100 may be referred to as a first ground plane in the package substrate 100, and the ground plane G2 in the package substrate 100 may be referred to as a second ground plane in the package substrate 100. Or other nomenclature, which is used merely to facilitate understanding. By way of example, embodiments of this paragraph may be described as the first ground plane in the interposer 120 being physically separate from the second ground plane, the first ground plane in the package substrate 100 being electrically connected to or integral with the second ground plane; alternatively, the first ground plane and the second ground plane in the package substrate 100 are physically separated, and the first ground plane and the second ground plane in the interposer 120 are electrically connected or integrated. Therefore, in the present embodiment, as long as at least one of the package substrate 100 and the interposer 120 has the ground planes G1 and G2 separated from each other, noise and interference can be reduced. Specifically, ground planes G1 and G2 may be provided in both the package substrate 100 and the interposer 120, which are separated from each other; or the ground planes G1 and G2 separated from each other are provided only in the interposer 120 (or the ground planes G1 and G2 separated from each other are provided only in the package substrate 100); alternatively, ground planes G1 and G2 are provided in the package substrate 100 separately from each other, while ground planes G1 and G2 in the interposer 120 are electrically connected (or integral); alternatively, the ground planes G1 and G2 are provided in the interposer 120 separately from each other, and the ground planes G1 and G2 in the package substrate 100 are electrically connected (or integrated). Both the above approaches may reduce noise and interference.

Fig. 6 is a schematic cross-sectional view illustrating a PoP package according to another embodiment of the present invention, wherein like reference numerals denote like elements, regions, or layers. As shown in fig. 6, the PoP package 2 includes a bottom package 10a and a top package 20 stacked on the bottom package 10 a. The bottom package 10a may include a redistribution layer (RDL)400, and input/output pads on the RF die D1 and the SoC die D2 may be redistributed by the RDL400 to form pads BP on the bottom surface 400b, on which terminal balls TB, such as Ball Grid Array (BGA) balls, are mounted. Likewise, RF die D1 and SoC die D2 are encapsulated by molding compound 110, and copper vias V1-V3 may be formed in molding compound 110, with copper vias V1-V3 electrically connected to molded-on RDL 420. Pads 422 for (connecting) the top package 20 are formed in the molded-on RDL 420. The top package 20, such as an LPDDR4 or LPDDR5DRAM package, may be electrically connected to the DDR interface of SoC die D2 by over-molded RDL 420, copper vias V1-V3 and RDL 400. As shown in fig. 2 or 3, the layout of the copper via V2 is similar to the connecting element C2. The grounded copper via V2 may act as a shielding element that may prevent potential digital high frequency digital signal interference from the circuit. The RDL400 is adopted to enable the packaging structure to be thinner, so that the packaging volume is smaller, and the packaging structure is suitable for different requirements.

Fig. 7 is a schematic cross-sectional view illustrating a PoP package according to still another embodiment of the present invention, wherein like reference numerals denote like elements, regions, or layers. As shown in fig. 7, the PoP package 3 likewise includes a bottom package 10b and a top package 20 stacked on the bottom package 10 b. The bottom package 10b may be an embedded die package. RF die D1 and SoC die D2 are embedded in a substrate and interconnected by a substrate process to form a system-in-board (SoC-board) package. For example, RF die D1 and SoC die D2 may be embedded in core substrate 500. The core substrate 500 may include a Copper Clad Laminate (CCL) substrate or an organic laminate substrate known in the art. Build-up layers BL (Build-up layer) and interconnect structures tr (interconnect structure) such as high-density interconnect (HDI) traces and laser drilling may be formed on the core substrate 500. Through holes PTH1-PTH3 may be formed in the core substrate 500 of the bottom package 10b, and through holes PTH1-PTH3 may be electrically coupled to the circuit layer 520. Pads 522 for (connecting) the top package 20 may be formed in the circuit layer 520. Top package 20, such as LPDDR4 or LPDDR5DRAM package, may be electrically connected to the DDR interface of SoC die D2 through circuit layer 520, vias PTH1-PTH3 and interconnect structure Tr of substrate 500. The layout of the through-hole PTH2 is similar to connecting element C2 shown in fig. 2 or 3. The ground vias PTH2 may act as shielding elements that may block potential digital signal interference from high frequency digital signals.

Referring to fig. 8 and 9, fig. 8 is a schematic cross-sectional view of a PoP package according to another embodiment of the invention. Fig. 9 is a perspective top view of a PoP package showing the side-by-side arrangement of the RF die and SoC die in fig. 8 and the arrangement of the connection elements disposed around the RF die and SoC die in the bottom package of the exemplary PoP.

As shown in fig. 8, the PoP package 4 includes a bottom package 10c and a top package 20 stacked on the bottom package 10 c. According to an exemplary embodiment, the top package 20 may be a memory package, such as a DRAM package having at least one packaged DRAM die, such as DDR4, LPDDR4, DDR5, LPDDR5, and the like. According to an exemplary embodiment, the bottom package 10c may include a package substrate 100, the package substrate 100 having an upper surface 100a and a bottom surface 100 b. According to an exemplary embodiment, the RF die D1 and the SoC die D2 are mounted on the upper surface 100a of the package substrate 100 in a side-by-side manner.

According to an exemplary embodiment, the package substrate 100 may be a multilayer circuit board or a multilayer wiring board as well. For example, the package substrate 100 may be a two-layer, three-layer or four-layer circuit board, but is not limited thereto. According to an example embodiment, the RF die D1 and the SoC die D2 may be flip-chip chips and may be flip-chip bonded to the package substrate 100.

According to an exemplary embodiment, RF die D1, SoC die D2, and upper surface 100a of package substrate 100 are encapsulated by molding compound 110. According to an exemplary embodiment, as shown in fig. 8 and 9, a plurality of connection elements C2 through C5 are disposed on the upper surface 100a of the package substrate 100. For example, the connection elements C2-C5 may include Cu/Sn balls (Cu core solder balls), Cu posts, Cu bumps, Cu vias, through-mold vias, and the like. According to an exemplary embodiment, the connecting elements C2-C5 are surrounded by a molding compound 110. According to an exemplary embodiment, the connection elements C2-C5 may be electrically coupled to the top package 20 through the interposer 120. The interposer 120 has re-routed traces and/or fan-out/fan-out pads that match the solder ball layout of the top package 20. Interposer 120 may include two or more metal layers, such as copper layers. The interposer 120 may include a laminate material. For example, interposer 120 may include a BT (bismaleimide/triazine) laminate. In another embodiment, interposer 120 may be a Si interposer and may include through-silicon vias. It should be understood that the structure of the interposer 120 shown in the figures is for illustration purposes only.

The package substrate 100 is larger in size than the upper interposer 120. Therefore, only the SoC die D2 is completely surrounded by the connection elements C2 to C5. Furthermore, only SoC die D2 overlaps interposer 120. The high frequency digital signal traces in the package substrate 100 that are electrically connected to the DDR interfaces on edges E3 and E4, respectively, do not intersect edge E1 and do not overlap RF die D1. Using a smaller size interposer 120 may save the cost of the interposer 120. The grounded connection element C2 may act as a shielding element that may block potential digital signal interference from high frequency digital signals.

Those skilled in the art will readily observe that numerous modifications and variations of the apparatus and method may be made while maintaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor package, comprising:

a signal interference shielding element disposed between the radio frequency die and the system single die and grounded; and

a top package mounted on the interposer.

2. The semiconductor package of claim 1, wherein the top package is a memory package, wherein the memory package is a dynamic random access memory package having at least one packaged dynamic random access memory die, wherein the radio frequency die is a millimeter wave intermediate frequency radio frequency die.

3. The semiconductor package of claim 1, wherein the connection elements comprise copper/solder balls, copper pillars, copper bumps, copper vias, or through-mold vias.

4. The semiconductor package of claim 1, wherein the connection element and the signal interference shielding element are surrounded by the molding compound.

5. The semiconductor package of claim 4, wherein the connection element is coplanar with the signal interference shielding element.

6. The semiconductor package of claim 1, wherein the interposer comprises re-routing traces and/or fan-out/fan-in pads that match a solder ball layout of the top package.

7. The semiconductor package of claim 1, wherein the interposer comprises a silicon interposer or a redistribution layer interposer.

8. The semiconductor package of claim 1, wherein the system-on-die comprises a first edge and a second edge, the first edge being adjacent to and directly facing the RF die, the second edge being disposed with a double data rate interface, the first edge being different from the second edge.

9. The semiconductor package of claim 1, further comprising a first ground plane and a second ground plane; the first ground plane is physically separated from the second ground plane;

wherein the RF die is electrically coupled to the first ground plane and the system-on-die is electrically coupled to the second ground plane.

10. The semiconductor package of claim 9, wherein the first ground plane and the second ground plane are disposed in both the interposer and the package substrate.