TWI712041B - Erase method for multi-tier 3d memory - Google Patents

Abstract

Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.

Description

Erasing method of multi-level three-dimensional memory

The present invention relates to a method for erasing multi-tier three-dimensional memory.

With the increase in memory storage density, three-dimensional (3D) memory has now been developed. In a three-dimensional memory, plural character lines are grouped into multiple tiers, such as double tiers or triple tiers. Each character line can also be called a layer, because the character lines are arranged in a horizontal manner.

When the three-dimensional memory is erased, the unit is block. A block includes a plurality of unit cells. During the erasing operation, if all the unit cells of the selected block are lower than the erase verify voltage, the selected block is deemed to be erased successfully. However, during the erasing process, for the same selected block, the threshold voltage of some cells is already lower than the erase verification voltage, but the threshold voltage of other cells may not be lower than the erase verification voltage. If this is the case, the erasing voltage must be increased to lower the threshold voltage of the unit cells of the selected block. However, the increased erase voltage will also hold the cells whose threshold voltage has been lower than the erase verification voltage, which may cause further damage to the cells whose threshold voltage has been lower than the erase verification voltage.

Therefore, this case proposes a method of erasing multi-level three-dimensional memory in order to solve the above or other problems.

According to an example of this case, a method for erasing a multi-level three-dimensional memory is proposed. The multi-level three-dimensional memory includes a plurality of levels and a plurality of blocks, each of the levels includes a plurality of character lines, and the erasing method includes : When erasing one of the selected blocks of the blocks, in a current round, select at least one level from the levels to be erased by a first erase voltage; determine whether the at least one level is erased Verification; and if it is determined that the at least one level passes the erasure verification, in the next round, the at least one level that passed the erasure verification is prohibited from being erased.

According to an example of this case, a method for erasing a multi-level three-dimensional memory is proposed. The multi-level three-dimensional memory includes a plurality of levels and a plurality of blocks, each of the levels includes a plurality of character lines, and the erasing method includes : When erasing one of the selected blocks of these blocks, in a current round, select a first level group from the levels to be erased by a first erasing voltage, and from these levels Select a second-level group to prohibit being erased, wherein the group members of the first-level group and the second-level group do not overlap with each other; determine whether the selected first-level group passes Erase verification; and if it is determined that the selected first-level group passes the erase verification, in the next round, select a third-level group from the levels to be erased by a second erase voltage , And select a fourth-level group from these levels to prohibit being erased, wherein the group members of the third-level group and the fourth-level group do not overlap each other, and the third-level group includes The first level group.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

100: Three-dimensional memory

110: Three-dimensional memory array

120: Controller

SSL: String selection line

GSL: Overall selection line

DWT0, DWT1, DWB0, DWB1: Redundant character lines

WL0~WLY: character line

BL0~BLX: bit line

IP: isolation pad

T1~TN: level

310~357,410~437: steps

Figure 1 shows a functional block diagram of a three-dimensional memory according to an embodiment of the present application.

Figure 2 shows a schematic diagram of a three-dimensional memory array according to an embodiment of the present application.

FIG. 3A shows a schematic diagram of a character line grouping of a three-dimensional memory array according to an embodiment of the present application. Figures 3B to 3D show a flowchart of several erasing operations in Figure 3A.

FIG. 4A shows another schematic diagram of the character line grouping of the three-dimensional memory array according to an embodiment of the present application. Figures 4B to 4D show a flowchart of several erasing operations in Figure 4A.

FIG. 5 shows a top view of a three-dimensional memory array and its voltage application conditions according to an embodiment of the present case.

The technical terms in this specification refer to the customary terms in the technical field. If this specification describes or defines some terms, the explanation of this part of the terms is subject to the description or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

Please refer to FIG. 1, which shows a functional block diagram of a three-dimensional memory according to an embodiment of the present application. As shown in FIG. 1, the three-dimensional memory 100 according to the embodiment of the present application includes: a three-dimensional memory array 110 and a controller 120. Three-dimensional memory array 110 coupling To the controller 120. The controller 120 can control operations of the three-dimensional memory array 110, such as erasing operations, programming operations, and so on. The details of the erasing operation in the embodiment of this case will be explained below.

FIG. 2 shows a schematic diagram of a three-dimensional memory array 110 according to an embodiment of the present application. The three-dimensional memory array 110 includes: string select line SSL, global select line GSL, multiple redundant character lines (such as DWT0, DWT1, DWB0, DWB1, etc.), and multiple characters Lines (such as WL0~WLY, Y is a positive integer) and multiple bit lines (such as BL0~BLX, X is a positive integer). Among them, the character lines WL0~WLZ (Z is a positive integer) are grouped into the first tier T1, and the character lines WL(Z+1)~WLY are grouped into the second tier T2 , And an isolation pad IP is formed between the two levels T1 and T2, and the isolation pad IP is used to isolate the two levels. Of course, the second figure is used to illustrate a case of the character line grouping of the three-dimensional memory array in the embodiment of this case. In fact, if necessary, the character lines can be divided into more levels, and any two adjacent levels are separated from each other by isolation pads, which is also within the spirit of this case. As shown in Figure 2, the first level T1 and the second level T2 each include a plurality of character lines. In one embodiment, each of the first level T1 and the second level T2 includes 64 character lines. Therefore, the total word line of the three-dimensional memory array can be as high as 128 layers. Such a hierarchical operation is more advantageous for a three-dimensional memory array with more than 100 layers (that is, 100 character lines).

FIG. 3A shows a schematic diagram of a character line grouping of the three-dimensional memory array 110 according to an embodiment of the present application. Figures 3B to 3D show a flowchart of several erasing operations in Figure 3A.

As shown in FIG. 3A, the plural character lines of the three-dimensional memory array 110 are grouped into N levels T1 to TN, where N is a positive integer. That is, the character lines WL0~WLY in Figure 2 are grouped into N levels T1~TN, where the number of character lines included in each level can be the same or slightly different. In Figure 3A, the level T1 represents the bottom level, and the erase voltage VE (applied to the selected bit line BL) is applied to the bottom of the selected bit line BL, towards the selected bit line The top of the BL transmits. In Figure 3A, the erase voltage is applied from one side (applied to the bottom of the selected bit line BL).

Please refer to Figure 3B now. As shown in Figure 3B, during the erasing operation, in the first round (step 310), the first level T1 is erased by the erasing voltage VE (VE=VERS), and the remaining levels T2~TN are A prohibition voltage is applied to prohibit erasure, where VERS represents the reference erasure voltage.

In step 311, it is checked whether all the unit cells on all the character lines of the first level T1 have passed the erasure verification (that is, the respective thresholds of all the unit cells on all the character lines of the first level T1 are checked. Whether the voltage is lower than the erase verification voltage). If the check result of step 311 is yes, the flow continues to the next step. If the check result of step 311 is no, the process returns to step 310 to increase the erase voltage VE until all the cells on all the word lines of the first level T1 pass the erase verification.

In the second round (step 312), the second level T2 is erased by the erasing voltage VE (VE=VERS+△V), and the remaining levels T1 and T3~TN are applied with forbidden voltages to prohibit erasing. ,△V represents the erase voltage difference.

In step 313, it is checked whether all the cells on all the character lines of the second level T2 have passed the erasure verification. If the check result of step 313 is yes, then the flow Proceed to the next step. If the check result of step 313 is no, the flow returns to step 312 to increase the erasing voltage VE until all the cells on all the word lines of the second level T2 pass the erasing verification.

In the third round (step 314), the third level T3 is erased by the erasing voltage VE (VE=VERS+2*△V), and the remaining levels T1~T2 and T4~TN are applied with forbidden voltages to prohibit Wiped out.

In step 315, it is checked whether all the cells on all the character lines of the third level T3 have passed the erasure verification. If the check result of step 315 is yes, the flow continues to the next step. If the check result of step 315 is no, the flow returns to step 314 to increase the erase voltage VE until all the cells on all the word lines of the third level T3 pass the erase verification.

The above steps can be repeated.

In the Nth round (step 316), the Nth level TN is erased by the erasing voltage VE(VE=VERS+(N-1)*△V), and the remaining levels T1~T(N-1) are applied Prohibit voltage to prevent being erased.

In step 317, it is checked whether all the cells on all the character lines of the Nth level TN have passed the erasure verification. If the check result of step 317 is yes, the erase operation flow ends. If the check result of step 317 is no, the process returns to step 316 to increase the erase voltage VE until all the cells on all the word lines of the Nth level TN pass the erase verification.

Please refer to Figure 3C now. As shown in Figure 3C, during the erase operation, in the first round (step 330), all levels T1~TN are erased. VE(VE=VERS) erased.

In step 331, it is checked whether all the cells on all the character lines of the first level T1 have passed the erasure verification. If the check result of step 331 is yes, then the flow continues to the next step. If the check result of step 331 is no, the process returns to step 330 to increase the erasure voltage VE until all the cells on all the word lines of the first level T1 pass the erasure verification.

In the second round (step 332), the levels T2~TN are erased by the erasure voltage VE (VE=VERS+△V), and the first level T1 that has passed the erasure verification is applied with a prohibition voltage to prohibit erasure .

In step 333, it is checked whether all the cells on all the character lines of the second level T2 have passed the erasure verification. If the check result of step 333 is yes, the flow continues to the next step. If the check result of step 333 is no, the process returns to step 332 to increase the erase voltage VE until all the cells on all the word lines of the second level T2 pass the erase verification.

In the third round (step 334), levels T3~TN are erased by the erasing voltage VE (VE=VERS+2*△v), and the first level T1 and the second level T2 that have passed the erasure verification are erased Apply prohibition voltage to prohibit erasure.

In step 335, it is checked whether all the cells on all the character lines of the third level T3 have passed the erasure verification. If the check result of step 335 is yes, then the flow continues to the next step. If the check result of step 335 is no, the process returns to step 334 to increase the erase voltage VE until all the cells on all the word lines of the third level T3 pass the erase verification.

The above steps can be repeated.

In the Nth round (step 336), the Nth level TN is erased by the erasure voltage VE (VE=VERS+(N-1)*△V), and the remaining levels T1~T(N-1) that have passed the erasure verification ) Is applied with a prohibition voltage to prohibit erasure.

In step 337, it is checked whether all the unit cells on all the character lines of the Nth level TN have passed the erasure verification. If the check result of step 337 is yes, the erase operation flow ends. If the check result of step 337 is no, the process returns to step 336 to increase the erase voltage VE until all the cells on all the word lines of the Nth level TN pass the erase verification.

Please refer to Figure 3D now. As shown in Fig. 3D, during the erasing operation, in the first round (step 350), the Nth level TN (or, alternatively, the Nth level TN is selected as the first level group) is erased The voltage VE(VE=VERS) is erased, and the rest of the levels T1~T(N-1) are applied with a forbidden voltage to prohibit being erased (or, it can be said that the first level T1 to the (N-1) ) Level T(N-1) is selected as the second level group to be applied with a prohibition voltage to prohibit erasure). It can be seen from the above that the group members of the first-level group and the second-level group do not overlap with each other.

In step 351, it is checked whether all the unit cells on all the character lines of the Nth level TN have passed the erasure verification. If the check result of step 351 is yes, the flow goes to the next step. If the check result of step 351 is no, the flow returns to step 350 to increase the erase voltage VE until all the cells on all the word lines of the Nth level TN pass the erase verification.

In the second round (step 352), the Nth level TN and the N-1th level T(N-1) (Alternatively, it can be said that the Nth level TN and the N-1th level T(N-1) are selected as the third level group) to be erased voltage VE (VE=VERS-△V) The other levels T1~T(N-2) are applied with a prohibition voltage to prohibit the erasure (or, it can be called the first level T1 to the (N-2) level T(N-2) ) Is selected as the fourth level group to be applied with a prohibition voltage to prohibit erasure). It can be seen from the above that the group members of the third-level group and the fourth-level group do not overlap with each other.

In step 353, it is checked whether all the unit cells on all the character lines of the Nth level TN and the N-1th level T(N-1) have passed the erasure verification. If the check result of step 353 is yes, the flow continues to the next step. If the check result of step 353 is no, the process returns to step 352 to increase the erasing voltage VE until all the unit cells on all the character lines of the Nth level TN and the N-1th level T(N-1) pass Until the verification is erased.

In the third round (step 354), the Nth level TN, the N-1th level T(N-1) and the N-2th level T(N-2) are erased by the voltage VE (VE=VERS-2*△) V) is erased, and the remaining levels T1~T(N-3) are applied with a prohibition voltage to prohibit the erasure.

In step 355, it is checked whether all the unit cells on all the character lines of the Nth level TN, the N-1th level T(N-1) and the N-2th level T(N-2) have passed the erasure verification . If the check result of step 355 is YES, the flow continues to the next step. If the check result of step 355 is no, the process returns to step 354 to increase the erasing voltage VE until the Nth level TN, the N-1th level T(N-1) and the N-2th level T(N-2) All cells on all character lines of) have passed the erasure verification.

The above steps can be repeated.

In the Nth round (step 356), all levels T1~TN are erased voltage VE(VE=VERS-(N-1)*△V) is erased.

In step 357, it is checked whether all unit cells on all character lines of all levels T1 to TN have passed the erasure verification. If the check result of step 357 is yes, the erasure process ends. If the check result of step 357 is no, the process returns to step 356 to increase the erasing voltage VE until all the cells on all the word lines of all levels T1 to TN pass the erasing verification.

Taking the embodiment shown in Fig. 3B to Fig. 3C, the layers that have passed the erasure verification will not be erased again. Taking the example of the 3D drawing to see, for the levels that have passed the erasure verification, a gradually lower erasure voltage is applied. In this way, the level that has passed the erasure verification can be prevented from being further damaged by the erasure voltage applied in the subsequent rounds.

FIG. 4A shows another schematic diagram of character line grouping of the three-dimensional memory array 110 according to an embodiment of the present invention. Figures 4B to 4D show a flowchart of several erasing operations in Figure 4A. Different from Fig. 3A, in Fig. 4A, the erase voltage is applied from both sides of the selected bit line. That is, in Figure 4A, the erase voltage VE is respectively applied to the bottom and top of the selected bit line BL, and is transferred to the middle of the selected bit line BL. Therefore, in Figure 4A, TM represents the intermediate level, for example, M=(N+1)/2 (when N is a positive odd integer) or M=N/2 (when N is a positive even integer).

Please refer to Figure 4B and Figure 4C now. As shown in Figures 4B and 4C, during the erasing operation, in the first round (step 410), the first level T1 and the Nth level TN are erased by the erasing voltage VE (VE=VERS) In addition, the remaining levels T2~T(N-1) are applied with a prohibition voltage to prohibit erasure.

In step 411, check all of the first level T1 and the Nth level TN Whether all the unit cells on the character line have passed the erasure verification. If the check result of step 411 is yes, the flow continues to the next step. If the check result of step 411 is no, the process returns to step 410 to increase the erase voltage VE until all the cells on all the word lines of the first level T1 and the Nth level TN pass the erase verification.

In the second round (step 412), the second level T2 and the (N-1)th level T(N-1) are erased by the erasing voltage VE (VE=VERS+△V), and the remaining levels T1 T3~T(N-2) and TN are applied with a prohibition voltage to prohibit erasure.

In step 413, it is checked whether all the cell lines on all the character lines of the second level T2 and the (N-1)th level T(N-1) have passed the erasure verification. If the check result of step 413 is yes, the flow continues to the next step. If the check result of step 413 is no, the process returns to step 412 to increase the erasing voltage VE until all the unit cells on all the character lines of the second level T2 and the (N-1)th level T(N-1) All have passed the erasure verification.

In the third round (step 414), the third level T3 and the (N-2) level T(N-2) are erased by the erase voltage VE (VE=VERS+2*△V), and the rest Levels T1~T2, T4~T(N-3), T(N-1), and TN are applied with forbidden voltage to prevent being erased.

In step 415, it is checked whether all the unit cells on all the character lines of the third level T3 and the (N-2)th level T(N-2) have passed the erasure verification. If the check result of step 415 is yes, the flow continues to the next step. If the check result of step 415 is no, the process returns to step 414 to increase the erasing voltage VE until all the unit cells on all the character lines of the third level T3 and the (N-2)th level T(N-2) All have passed the erasure verification.

The above steps can be repeated.

In the Mth round (step 416), (1) If N is a positive odd number, then the The M level TM is erased by the erase voltage VE(VE=VERS+(M-1)*△V), while the rest of the levels T1~T(M-1) and T(M+1)~TN are prohibited The voltage is forbidden to be erased; or, (2) If N is a positive even number, then the M-th level TM and the (M+1)th level T(M+1) are erased by the voltage VE (VE=VERS+(M- 1) *△V) is erased, and the rest of the levels T1~T(M-1) and T(M+2)~TN are applied with forbidden voltage to prohibit being erased.

In step 417, it is checked whether (1) all the unit cells on all the character lines of the Mth level TM (if N is a positive odd number) have passed the erasure verification, or (2) the Mth level TM and the (M +1) Whether all the unit cells on all the character lines of level T(M+1) (if N is a positive even number) have passed the erasure verification. If the check result of step 417 is yes, the erase operation flow ends. If the check result of step 417 is no, the flow returns to step 416 to increase the erasing voltage VE until (1) whether all the unit cells on all the character lines of the M-th level TM (if N is a positive odd number) have passed Erasure verification, or (2) Mth level TM and (M+1)th level T(M+1) (if N is a positive even number) all cell lines on all character lines pass the erasure verification.

Please refer to Figure 4D now. As shown in Figure 4D, during the erasing operation, in the first round (step 430), the middle level is erased by the erase voltage VE (VE=VERS), while the rest of the levels are applied with a prohibition voltage to prohibit Wiped out. Among them, (1) if N is a positive odd integer, the intermediate level is the M-th level TM, (2) if N is a positive even integer, the intermediate level is the M-th level TM and the (M+1)-th level T(M +1). In this round, the level selected to be erased can also be referred to as the first level group, and the level selected not to be erased can also be referred to as the second level group.

In step 431, all crystals on all character lines in the middle level are checked. Whether all cells have passed the erasure verification. If the check result of step 431 is yes, the flow continues to the next step. If the check result of step 431 is no, the process returns to step 430 to increase the erasing voltage VE until all the cells on all the word lines in the middle level pass the erasing verification.

In the second round (step 432), the middle level and its first adjacent level are erased by the erasure voltage VE (VE=VERS-ΔV), and the rest of the levels are applied with a prohibition voltage to prohibit erasure. Among them, (1) If N is a positive odd number, the middle level is the Mth level TM, and the first adjacent level of the middle level refers to the (M-1)th level T(M-1) and the (M+ 1) Level T(M+1); (2) If N is a positive even number, the middle level is the Mth level TM and the (M+1)th level T(M+1), the first adjacent level of the middle level It refers to the (M-1)th level T(M-1) and the (M+2)th level T(M+2). In other words, the first adjacent level of the intermediate level refers to the previous level and the next level closest to the intermediate level. In this round, the level selected to apply the erasing voltage can also be called the third level group, and the level that is prohibited from applying the erasing voltage can also be called the fourth level group.

In step 433, it is checked whether all the unit cells on all the character lines of the middle level and its first adjacent level have passed the erasure verification. If the check result of step 433 is yes, the flow continues to the next step. If the check result of step 433 is no, the process returns to step 432 to increase the erasing voltage VE until all the cells on all the word lines of the middle level and its first adjacent level pass the erasing verification.

In the third round (step 434), the middle level, the first adjacent level of the middle level, and the second adjacent level of the middle level are erased by the erase voltage VE (VE=VERS-2*△V), and The rest of the levels are forbidden by applying forbidden voltage Stop being erased. Among them, (1) If N is a positive odd number, the middle level is the Mth level TM, and the first adjacent level of the middle level refers to the (M-1)th level T(M-1) and the (M+ 1) Level T(M+1), the second adjacent level of the middle level refers to the (M-2)th level T(M-2) and the (M+2)th level T(M+2); ( 2) If N is a positive even number, the middle level is the Mth level TM and the (M+1)th level T(M+1), and the first adjacent level of the middle level is the (M-1)th level T (M-1) and (M+2)th level T(M+2), the second adjacent level of the middle level refers to the (M-2)th level T(M-2) and (M+3)th level ) Level T (M+3). In other words, the second adjacent level of the middle level refers to the upper two levels and the lower two levels of the middle level. Other definitions can be deduced by analogy

In step 435, it is checked whether all the unit cells on all the character lines of the middle level, the first adjacent level of the middle level, and the second adjacent level of the middle level have passed the erasure verification. If the check result of step 435 is YES, the flow continues to the next step. If the check result of step 435 is no, the flow returns to step 434 to increase the erasing voltage VE until all the character lines on the middle level, the first adjacent level of the middle level, and the second adjacent level of the middle level are all The unit cells are all verified by erasure.

The above steps can be repeated.

In the Mth round (step 436), all levels T1~TN are erased by the erase voltage VE (VE=VERS-(M-1)*△V).

In step 437, it is checked whether all the unit cells on all the character lines of all levels T1 to TN have passed the erasure verification. If the check result of step 437 is yes, the erase operation flow ends. If the check result of step 437 is no, the flow returns to step 436 to increase the erasing voltage VE until all the character lines of all levels T1~TN All unit cells have passed the erasure verification.

In the embodiment shown in Figure 4B, erasing is prohibited for the layers that have passed erasing verification. Based on the embodiment shown in FIG. 4C, for the levels that have passed the erasure verification, a gradually lower erasure voltage is applied. In this way, the level that has passed the erasure verification can be prevented from being further damaged by the erasure voltage applied in the subsequent rounds.

FIG. 5 shows a top view of the three-dimensional memory array 110 and its voltage application conditions according to an embodiment of the present application. For the convenience of explanation, in Figure 5, the selected block (that is, the block selected for the erase operation) is framed by a dashed frame, and the circle represents the bit line BL. The table in Figure 5 shows the voltage application conditions of the selected and unselected blocks. In the table in Figure 5, "F" represents no voltage applied. It can be seen from FIG. 5 that the three-dimensional memory array 110 includes a plurality of blocks.

Taking example 1, for the selected block, the string selection line SSL, the overall selection line GSL, the redundant word lines (DWT0, DWT1, DWB0, DWB1) and the word lines of the unselected levels are applied with a fixed voltage ( For example, but not limited to, 8V~12V), and 0V is applied to the word lines of the selected level. Among them, the "selected level" represents the level(s) to be erased by the erase voltage, and the "unselected level" represents the level(s) erased by the unerased voltage. For example, taking Figure 3B as an example, in step 310, the first level T1 is the "selected level", and the remaining levels T2 to TN are "unselected levels". That is to say, taking Example 1, applying 0V to the word lines of the selected level can make the switches of the unit cells of the word lines of the selected level be turned on, so that the turned on These unit cells can be erased by the erase voltage. Similarly, taking Example 1, applying a fixed voltage to the word lines of the unselected level can make the unit cells of the word lines of the unselected level When these switches are turned off, the erase voltage will not have an effect on the disconnected unit cells, so as to prevent the unit cells that have passed the erase verification from being damaged by the erase voltage.

Taking Example 2, for the selected block, the string selection line SSL, the overall selection line GSL, and the redundant word lines DWT0 and DWB0 are not applied with voltage; the redundant word lines DWT1 and DWB1, and the unselected levels A fixed voltage (for example, but not limited to, 8V-12V) is applied to the word lines; 0V is applied to the word lines of the selected level.

Taking Example 3, for the selected block, string selection line SSL, global selection line GSL, redundant word lines DWT0 and DWB0 are not applied with voltage; redundant word lines DWT1 and DWB1 are applied with dynamic voltage ( The variable voltage is, for example, but not limited to, between (VE-V1) and (VE-V2), V1 may be 8V and V2 may be 12V); the word lines of unselected levels are applied with a fixed voltage ( For example, but not limited to, 8V~12V); 0V is applied to the character lines of the selected level.

Taking Example 4, for the selected block, the string selection line SSL, the overall selection line GSL, and the redundant word lines DWT0 and DWB0 are not applied with voltage; the redundant word lines DWT1 and DWB1, and those of the unselected level A variable voltage is applied to the character line (for example, but not limited to, the variable voltage is between (VE-V1) and (VE-V2), V1 may be 8V and V2 may be 12V); these selected levels 0V is applied to the word line.

To sum up, in the above-mentioned embodiments of the present case, whether the erasing voltage is applied unilaterally or the erasing voltage is applied bilaterally, a prohibition voltage is applied to the level that has passed the erasure verification to prohibit erasure, or the erasure has been passed. The level of the erasure verification is erased by the reduced erasure voltage. In this way, the level that has passed the erasure verification can be prevented from being further damaged by the erasure voltage applied in the subsequent rounds.

The embodiments of this case can be applied to three-dimensional flash memory, including but not limited to, vertical channel type (vertical channel type) three-dimensional flash memory, vertical gate type (vertical gate type) three-dimensional flash memory, and charge trapping Type (charge trapping type) three-dimensional flash memory, or floating gate type (floating gate type) three-dimensional flash memory.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

310~317: Step

Claims (7)

A method for erasing a multi-level three-dimensional memory. The multi-level three-dimensional memory includes a plurality of levels and a plurality of blocks. Each of the levels includes a plurality of character lines. The erasing method includes: erasing the areas When one of the blocks is selected as a block, in a current round, select at least one level from the levels to be erased by a first erase voltage; determine whether the at least one level passes the erase verification; and if it is determined that the at least one level One level passes the erasure verification. In the next round, the at least one level that passed the erasure verification is prohibited from being erased. Among them, the multi-level three-dimensional memory includes N levels, and N is a positive integer. In the round, the first level of one of the levels is selected to be erased by the first erasing voltage, and the second level to the Nth level of one of the levels is prohibited from being erased; and when determining the first level When a level passes the erasure verification, in the next round, the second level is erased by a second erasing voltage, and the first level, a third level to the Nth level are prohibited from being erased Erasing, wherein the second erasing voltage is higher than the first erasing voltage, and the first erasing voltage and the second erasing voltage are applied to one end of a plurality of bit lines of the multi-level three-dimensional memory. A method for erasing a multi-level three-dimensional memory. The multi-level three-dimensional memory includes a plurality of levels and a plurality of blocks. Each of the levels includes a plurality of character lines. The erasing method includes: erasing the areas When one of the blocks is selected, in a current round, select at least one level from these levels to be erased by a first erase voltage; Determine whether the at least one level passes the erasure verification; and if it is determined that the at least one level passes the erasure verification, in the next round, the at least one level that passed the erasure verification is prohibited from being erased; wherein, the multiple levels The three-dimensional memory includes N levels, and N is a positive integer. In the current round, all the N levels are erased by the first erase voltage; it is judged that one of the N levels is erased by the first level After verification, in the next round, one of the second to the Nth levels of the N levels is erased by a second erase voltage, and the first level is prohibited from being erased. The second erase voltage is higher than the first erase voltage, and the first erase voltage and the second erase voltage are applied to one end of a plurality of bit lines of the multi-level three-dimensional memory. A method for erasing a multi-level three-dimensional memory. The multi-level three-dimensional memory includes a plurality of levels and a plurality of blocks. Each of the levels includes a plurality of character lines. The erasing method includes: erasing the areas When one of the blocks is selected as a block, in a current round, select at least one level from the levels to be erased by a first erase voltage; determine whether the at least one level passes the erase verification; and if it is determined that the at least one level One level passes the erasure verification. In the next round, the at least one level that passed the erasure verification is prohibited from being erased. Among them, the multi-level three-dimensional memory includes N levels, and N is a positive integer. In the round, the first level and the Nth level of the N levels are erased by the first erasing voltage, and the second level to the (N-1) level of the N levels are prohibited Erased; after judging that the first level and the Nth level pass the erasure verification, in the next round, the second level and the (N-1)th level are affected by a second erasing voltage wipe For the first level, the Nth level, from a third level to a (N-2) level are prohibited to be erased, wherein the second erase voltage is higher than the first erase voltage , The first erase voltage and the second erase voltage are applied to two ends of a plurality of bit lines of the multi-level three-dimensional memory. A method for erasing a multi-level three-dimensional memory. The multi-level three-dimensional memory includes a plurality of levels and a plurality of blocks, wherein each of the levels includes a plurality of character lines. The erasing method includes: erasing the When one of the blocks is selected, in a current round, select a first level group from the levels to be erased by a first erasing voltage, and select a second level group from the levels Group to prohibit being erased, wherein the group members of the first-level group and the second-level group do not overlap with each other; determine whether the selected first-level group passes the erasure verification; and if It is determined that the selected first-level group passes the erasure verification. In the next round, a third-level group is selected from these levels to be erased by a second erasing voltage, and from these levels Select a fourth-level group to prohibit being erased, wherein the group members of the third-level group and the fourth-level group do not overlap each other, and the third-level group includes the first-level group group. The method for erasing multi-level three-dimensional memory according to claim 4, wherein the multi-level three-dimensional memory includes N levels, and N is a positive integer. In the current round, an Nth level is selected as the first The level group is erased by the first erasing voltage, and a first level to a (N-1)th level are selected as the second level group to prohibit erasure; and After judging that the first level group passes the erasure verification, in the next round, the Nth level and the (N-1)th level are selected as the third level group to be erased by the second level group. The first level to the (N-2)th level are selected as the fourth level group to prohibit erasing, wherein the second erasing voltage is lower than the first erasing The erase voltage, the first erase voltage and the second erase voltage are applied to one end of a plurality of bit lines of the multi-level three-dimensional memory. The method for erasing multi-level 3D memory as described in claim 4, wherein the multi-level 3D memory includes N levels, N is a positive odd integer, M=(N+1)/2, in the current round , Select an Mth level as the first level group to be erased by the first erasing voltage, and from a first level to a (M-1) level, and a (M+) level 1) Level to an Nth level is selected as the second level group to prohibit erasure; and after determining that the first level group passes the erasure verification, in the next round, the Mth level, The (M-1)th level and the (M+1)th level are selected as the third level group to be erased by the second erasing voltage, and the first level to the first (M- 2) Level, and a (M+2)th level to the Nth level should be selected as the fourth level group to prohibit erasing, wherein the second erasing voltage is lower than the first erasing voltage, The first erase voltage and the second erase voltage are applied to two ends of a plurality of bit lines of the multi-level three-dimensional memory. The erasing method of a multi-level three-dimensional memory according to claim 4, wherein the multi-level three-dimensional memory includes N levels, N is a positive even integer, M=N/2, In the current round, an Mth level and an (M+1)th level are selected as the first level group to be erased by the first erasing voltage, and a first level to a first level are selected (M-1) level, and a (M+2) level to an Nth level are selected as the second level group to prohibit erasure; after judging that the first level group has passed the erasure verification, In the next round, select the Mth level, the (M-1)th level, the (M+1)th level, and the (M+2)th level as the third level group to be selected by the The second erase voltage is erased, and the first level to the (M-2) level, the (M+3) level to the Nth level should be selected as the fourth level group to prohibit being Erasing, wherein the second erasing voltage is lower than the first erasing voltage, and the first erasing voltage and the second erasing voltage are applied to two ends of a plurality of bit lines of the multi-level three-dimensional memory .

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