TWI711117B - 異質接面雙極性電晶體及形成異質接面雙極性電晶體之方法 - Google Patents

異質接面雙極性電晶體及形成異質接面雙極性電晶體之方法 Download PDF

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TWI711117B
TWI711117B TW108117341A TW108117341A TWI711117B TW I711117 B TWI711117 B TW I711117B TW 108117341 A TW108117341 A TW 108117341A TW 108117341 A TW108117341 A TW 108117341A TW I711117 B TWI711117 B TW I711117B
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base layer
layer
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trench isolation
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TW202002161A (zh
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豈之 劉
夫厚爾 杰恩
詹姆士Ｗ 阿德金森
薩拉 麥克塔格
馬克 利維
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明是關於用於異質接面雙極性電晶體的裝置結構和製作方法。溝槽隔離區域，被配置以圍繞複數個活性區域，並且，集極，位在該活性區域的各者中。基極層，包括分別地配置在該活性區域上方的複數個第一區段和分別地配置在該溝槽隔離區域上方的複數個第二區段。該基極層的該第一區段含有單晶半導體材料，而該基極層的該第二區段含有多晶半導體材料。該基極層的該第二區段在垂直方向與該溝槽隔離區域隔開，以定義複數個凹口。複數個射極指，分別地配置在該基極層的該第一區段上。

Description

異質接面雙極性電晶體及形成異質接面雙極性電晶體之方法
本發明大致上是關於半導體裝置和積體電路製作，並且特別地是關於用於異質接面雙極性電晶體的裝置結構和其製作方法。
雙極性接面電晶體為包括射極、集極、以及配置在射極與集極之間的內部基極(intrinsic base)的三端電子裝置。在NPN雙極性接面電晶體中，射極和集極可由n型半導體材料組成，而內部基極可由p型半導體材料組成。在PNP雙極性接面電晶體中，射極和集極可由p型半導體材料組成，而內部基極可由n型半導體材料組成。在運作時，基極-射極接面是順向偏壓，基極-集極接面是逆向偏壓，而集極-射極電流可以由基極-射極電壓控制。
異質接面雙極性電晶體是雙極性接面電晶體的變體，其中，集極、射極、以及內部基極的至少二者是由具有不同能帶隙(energy bandgap)的半導體材料組成，其創造異質接面。舉例來說，異質接面雙極性電晶體的集極及/或射極可由矽組成，而異質接面雙極性電晶體的基極可由矽鍺(SiGe)組成，其具有能帶隙比矽的能帶隙窄的特性。
在一些例如功率放大器的應用中，異質接面雙極性電晶體的射極可包括多個射極指(emitter finger)。外部基極區域是配置在各個射極指對之間。這些外部基極區域貢獻裝置結構的寄生電容，其可能不利地影響裝置效能。
需要用於異質接面雙極性電晶體的改進結構和其製作方法。
在本發明的實施例中，提供用於異質接面雙極性電晶體的裝置結構。該裝置結構包括：複數個溝槽隔離區域，被配置以圍繞複數個活性區域；集極，在該活性區域的各者中；以及基極層，包括分別地配置在該活性區域上方的複數個第一區段和分別地配置在該溝槽隔離區域上方的複數個第二區段。該基極層的該第一區段含有單晶半導體材料，而該基極層的該第二區段含有多晶半導體材料。該基極層的該第二區段在垂直方向與該溝槽隔離區域隔開，以定義複數個凹口。複數個射極指分別地配置在該基極層的該第一區段上。
在本發明的實施例中，提供製作異質接面雙極性電晶體的方法。該方法包括：形成圍繞複數個活性區域的複數個溝槽隔離區域，該活性區域的各者包括集極；以及形成包括分別地配置在該活性區域上方且含有單晶半導體材料的複數個第一區段、以及分別地配置在該溝槽隔離區域上方且含有多晶半導體材料的複數個第二區段的基極層。該方法復包括選 擇性對於該基極層的該第二區段的各者的第二半導體層而移除該基極層的該第二區段的各者的第一半導體層，以定義配置在介於該第二半導體層與該溝槽隔離區域之間的垂直方向中的複數個凹口。該方法復包括形成分別地配置在該基極層的該第一區段上的複數個射極。
10‧‧‧基板
12‧‧‧溝槽隔離區域
13‧‧‧頂表面
14‧‧‧活性區域
16‧‧‧集極
18‧‧‧次集極
20‧‧‧集極接點區域
21‧‧‧介面
22‧‧‧基極層
24、26、28‧‧‧層、單晶層
25、27、29‧‧‧層、多晶層
31‧‧‧射極窗口
32‧‧‧射極指
34‧‧‧射極蓋
36‧‧‧蝕刻遮罩
38、40‧‧‧開口
39‧‧‧長孔
42‧‧‧凹口
44‧‧‧異質接面雙極性電晶體
48、50‧‧‧區段
60‧‧‧矽化層
62‧‧‧層間介電層
64‧‧‧接點
66‧‧‧表面
被併入並且構成此說明書的一部分的伴隨圖式例示本發明的各種實施例，並且連同上方給定的本發明的大致描述和下方給定的實施例的詳細描述，以解釋本發明的實施例。
第1-6圖為依據本發明的實施例在製程方法的連續製作階段的裝置結構的剖面視圖。
第4A圖為覆蓋第4圖的裝置結構的蝕刻遮罩的頂視圖，其中，第4圖大致上是沿著線4-4繪製。
第4B和4C圖為依據本發明的不同實施例類似於第4A圖的蝕刻遮罩的頂視圖。
第5A圖為裝置結構的頂視圖，其中，第5圖大致上是沿著線5-5繪製。
第5B圖為裝置結構大致上沿著第5A圖中的線5B-5B繪製的剖面視圖。
第7圖為依據本發明的不同實施例的第5圖的裝置結構的剖面視圖。
參考第1圖和依據本發明的實施例，基板10可由例如矽(Si)的單晶半導體材料組成。基板10的單晶半導體材料可包括在其頂表面處的磊晶層，並且磊晶層可用電性活性摻質予以摻雜，以改變其電性導電性。舉例來說，單晶矽的磊晶層可藉由磊晶生長製程而生長在基板10上，並且可在磊晶生長期間，以來自週期表的第V族的n型摻質(例如，磷(P)、砷(As)及/或銻(Sb))予以摻雜，以提供n型導電性。
溝槽隔離區域12形成在基板10中，並且經配置以圍繞基板10的活性區域14。溝槽隔離區域12可藉由依賴微影和乾蝕刻製程的淺溝槽隔離(STI)技術以定義基板10中的溝槽、沉積介電材料以填充溝槽、以及使用化學機械研磨(CMP)平坦化介電材料來形成。介電材料可例如為藉由化學氣相沉積(CVD)沉積的矽的氧化物(例如，二氧化矽(SiO2))。
集極16的區段配置在各個活性區域14中，並且可構成個別活性區域14的全部或一部分。集極16的電性導電性可例如藉由離子布植電性活性摻質(例如，n型摻質)進入活性區域14的中央部分而相對於基板10的電性導電性加以提昇。次集極18在外溝槽隔離區域12之下的基板10中側向地延伸，以為了將集極16耦接至配置在溝槽隔離區域12的外側的集極接點區域20。次集極18可藉由引進電性活性摻質(例如，來自週期表的第V族的摻質(例如，磷(P)、砷(As)及/或銻(Sb)))而在基板10的頂表面之下形成，以提供n型導電性。在實施例中，可藉由遮罩的高電流離子布植以布植一劑量的摻質然後接著進行高溫熱退火來形成次集極18。
基極層22是形成在活性區域14、溝槽隔離區域12和集極接點區域20上方的連續性膜。基極層22可包括多個區段48，其包括含有單晶半導體材料的多個層24、26、28，該多個層24、26、28是垂直對準於活性區域14的其中一者而堆疊設置，並且與個別活性區域14的單晶半 導體材料直接接觸。基極層22可復包括多個區段50，其具有含有多晶半導體材料的多個層25、27、29，該多個層25、27、29主要是堆疊配置在溝槽隔離區域12的其中一者的頂表面13上方並且分別地毗連單晶層24、26、28。
基極層22的區段48中的單晶層24是與基極層22的區段50中的多晶層25連續，基極層22的區段48中的單晶層26是與基極層22的區段50中的多晶層27連續，而基極層22的區段48中的單晶層28是與基極層22的區段50中的多晶層29連續。雖然基極層22在區段48和區段50中的厚度是顯示成相等，但這些厚度可不相同。基極層22的各個區段50中的多晶層25、27、29和鄰近的基極層22的區段48中的單晶層24、26、28之間的過渡沿著個別的介面發生，並且以虛線概略地指示。雖然介面是顯示成垂直指向，但介面可傾斜小於90°或大於90°的角度。介面的各者是直接地配置在介面21上方，各個溝槽隔離區域12沿著該介面21而毗連活性區域14的其中一者。
基極層22的單晶層26和多晶層27可由半導體材料組成(例如，包括組合在合金中的矽(Si)和鍺(Ge)的矽鍺(SiGe)，其中，矽的含量範圍為95原子百分比至50原子百分比，而鍺的含量範圍為5原子百分比至50原子百分比)。基極層22的單晶層26和多晶層27的鍺含量可跨越其個別厚度而呈均勻，或可跨越其個別厚度而呈遞變(graded)及/或步進(stepped)。基極層22的單晶層24和多晶層25可由缺少鍺的半導體材料組成，並且，在實施例中，可完全由矽(Si)組成。類似地，基極層22的單晶層28和多晶層29可由缺少鍺的半導體材料組成，並且，在實施例中，可完全由矽(Si)組成。在不同實施例中，基極層22的層24、25和基極層 22的層28、29的鍺含量(例如，1原子百分比)是顯著地少於基極層22的層26、27的鍺含量。
基極層22可使用非選擇性的低溫磊晶生長製程(例如，快速熱化學氣相沉積(RTCVD))加以形成，並且在低溫磊晶生長製程期間，經由控制沉積條件而調變基極層22的成分。單晶半導體材料(例如，單晶矽及/或單晶矽鍺)磊晶地生長在設置在區段48中及活性區域14的其中一者上的堆疊的單晶層24、26、28中。多晶半導體材料形成在設置在區段50中並且配置在溝槽隔離區域12上方的堆疊的多晶層25、27、29中。當在生長期間調變成分時，活性區域14的單晶半導體材料的結晶結構作為用於基極層22的單晶層24、26、28的生長的結晶模板，但溝槽隔離區域12不作為導致基極層22的多晶層25、27、29的形成的任何類型的結晶模板。在實施例中，基極層22可以特定濃度的來自週期表的第III族的p型摻質(例如，硼(B)及/或銦(In))加以摻雜，以提供p型導電性，並可在磊晶生長期間原位摻雜。
參考第2圖，其中，相同的元件符號是代表第1圖中的相同特徵，並且在本製程方法的後續製作階段中，一個或多個介電層30可形成在基極層22上，並使用光微影和蝕刻製程加以圖案化，以定義射極窗口31。各個射極窗口31與區段48的其中一者中的基極層22的單晶層24、26、28對準。
參考第3圖，其中，相同的元件符號是代表第2圖中的相同特徵，並且在本製程方法的後續製作階段中，射極指32和關聯的射極蓋34是藉由沉積半導體層(其填充射極窗口31並覆蓋介電層30)、沉積蓋層在所沉積的半導體層上、形成遮罩這些沉積的層的蝕刻遮罩在射極窗口31上方、以及以反應式離子蝕刻(RIE)蝕刻以圖案化射極指32和射極蓋34來形 成。射極指32可含有藉由化學氣相沉積(CVD)沉積的多晶半導體材料(例如，多晶矽(Si))。在實施例中，構成射極指32的半導體材料可由特定濃度的來自週期表的第V族的n型摻質(例如，磷(P)及/或砷(As))加以摻雜，以提供n型導電性。射極蓋34可由介電材料(例如，矽氮化物(Si3N4))組成。活性區域14和射極指32的數目可視裝置設計而變化。
基極層22的區段50中的多晶層27、29可以傳送來自週期表的第V族的p型摻質(例如，硼(B)及/或銦(In))的離子在給定布植條件下(例如，離子種類、離子劑量、離子動能、離子布植角度)加以布植，並且退火多晶層27、29以活性化摻質。多晶層27、29的布植可為異質接面雙極性電晶體提供低電阻的外部基極，其可用於後續製作階段中的基極接觸的形成。
參考第4、4A圖，其中，相同的元件符號是代表第3圖中的相同特徵，並且在本製程方法的後續製作階段中，藉由微影製程施加和圖案化蝕刻遮罩36，以定義與基極層22的區段50(參考第1圖，區段50配置在鄰近的射極指32之間和溝槽隔離區域12上方)對準的複數個開口38。開口40被接續地蝕刻，以延伸通過基極層22的各個區段50中的基極層22的多晶層25、27、29。在實施例中，開口40完全地延伸通過基極層22的多晶層25、27、29至基極層22的區段50的各者下面的特定溝槽隔離區域12。開口40是配置在射極指32的鄰近對之間。貫穿基極層22的多晶層25、27、29的開口40將獲取蝕刻遮罩36中的開口38的形狀、尺寸、配置等。形成延伸通過基極層22的多晶層25、27、29的開口40的蝕刻製程可為非等向性反應離子蝕刻(RIE)製程，其形成垂直或近乎垂直的側壁。
蝕刻遮罩36中的開口38與多晶層25、27、29中的開口40可具有不同形狀和配置。如第4A圖中所顯示的，開口38、40可配置成一列，並且開口38具有相等間隔。或者如第4B圖中所顯示的，開口38、40可配置成一列，並且開口38是成對以相等間隔配置。或者如第4C圖中所顯示的，可形成相等間隔的長孔39以取代開口38，長孔39也可配置成一列並且具有相等間隔。形成在多晶層25、27、29中的開口40將獲得長孔39的長橢圓形形狀。在不同實施例中，可選擇開口38及/或長孔39的這些形狀和配置的不同組合。開口38及/或長孔39的形狀和配置可根據例如製程效率、堅固性、及製造的容易度等因素而特別選擇。
參考第5、5A、5B圖，其中，相同的元件符號是代表第4圖中的相同特徵，並且在本製程方法的後續製作階段中，基極層22的多晶層25可從區段50(其中，區段50中的多晶層25、27、29被開口38以等向性蝕刻製程穿孔)的各者移除。等向性蝕刻製程的蝕刻化學經選擇而對於構成基極層22的多晶層27和基極層22的多晶層29的半導體材料選擇性的移除構成基極層22的多晶層25的半導體材料。如本文中所使用的，材料移除製程(例如，蝕刻)的術語「選擇性」意指，在適合的蝕刻劑選擇下，當暴露至材料移除製程時，對於目標材料的材料移除率(也就是，蝕刻率)大於對於至少另一種材料的移除率。蝕刻遮罩36可在接續於等向性蝕刻製程的實施後移除。
在實施例中，蝕刻並移除基極層22的各個區段50中的多晶層25的等向性蝕刻製程可為溼化學蝕刻製程。在實施例中，可使用含有鹼性物質(例如，鉀氫氧化物(KOH)或氨氫氧化物(NH4OH))的鹼性溶液蝕刻並移除多晶層25。基極層22的各個區段50中的多晶層27因為其鍺含量所引起的組成差異，所以沒有被溼化學蝕刻程序蝕刻，並且基極層22的各 個區段50中的多晶層29因為其p型摻雜及/或其缺少鍺含量，所以沒有被溼化學蝕刻程序蝕刻。保留基極層22的區段50中的多晶層29可確保低基極電阻得以維持。在實施例中，如果多晶層27的成分中的鍺濃度低，基極層22的各個區段50中的多晶層27也可部分地蝕刻。蝕刻製程可予以計時，並且基極層22的各個區段48中的單晶層24因為其單晶半導體材料中相對於多晶層25的多晶半導體材料中的相同成分具有較低的蝕刻率，使得各個區段48中的單晶層24不是沒有被蝕刻，就是僅以可忽略的程度被蝕刻。
基極層22的各個區段50中的多晶層25的移除形成凹口42，其高度等於移除的多晶層25的厚度。凹口42具有沿著射極指32的長度延伸的長度L。基極層22的區段50中的多晶層27、29定義被凹口42底切的半導體材料的橋件。
所導致的異質接面雙極性電晶體44的裝置結構具有垂直架構，其包括集極16的區段、射極指32、以及由基極層22的區段48中的單晶層24、26、28的單晶半導體材料所提供的內部基極區域。各個內部基極區域配置在介於射極指32的其中一者與對應的活性區域14中的集極16之間的垂直方向中，以定義異質接面雙極性電晶體44的個別p-n接面。
異質接面雙極性電晶體44的外部基極包括在基極層22的各個區段50中的多晶層27、29，其由凹口42的其中一者底切，並且配置在溝槽隔離區域12的其中一者上方。凹口42是配置在介於溝槽隔離區域12與基極層22的底切的區段50之間的垂直方向中，其中，多晶層27是配置在多晶層29與凹口42之間。凹口42的高度可大約等於基極層22的多晶層25的移除部分的厚度，並且可大於或等於基極層22的單晶層24的 厚度。因為選擇性蝕刻程序而在凹口42上方保存的基極層22的多晶層27、29提供外部基極中被凹口42底切的部分具有定義的厚度。
參考第6圖，其中，相同的元件符號是代表第5圖中的相同特徵，並且在本製程方法的後續製作階段中，隨後是中間製程(MOL)和後段製程(BEOL)，其包括形成用於與異質接面雙極性電晶體44耦接的互連結構的接點、通孔、以及打線。作為此製程的一部分，矽化層60可形成在基極層22的原封(intact)的區段50的多晶層29上以提供位在開口40之間並且圍繞開口40的橋件，而層間介電層62是形成在異質接面雙極性電晶體44上方。矽化層60可關閉通向凹口42的開口40。層間介電層62可含有由化學氣相沉積(CVD)沉積並平坦化的介電材料(例如，矽的氧化物(例如，二氧化矽(SiO2)))。藉由以微影製程和蝕刻製程圖案化層間介電層62中的接點開口，並接著以例如鎢(W)的導體填充接點開口，以形成接點64。
參考第7圖，其中，相同的元件符號是代表第6圖中的相同特徵，並且依據不同實施例，可藉由移除基極層22的單晶層24的單晶半導體材料的一部分和活性區域14的單晶半導體材料的一部分，來加長等向性蝕刻製程，以進一步放大各個凹口42。在實施例中，形成凹口42的等向性蝕刻製程可展現結晶取向相依性，其中，蝕刻製程的動能可依據結晶平面變化，並且特別地，可對於不同的低係數結晶平面變化。等向性蝕刻製程因為其動能的這些變化，可在基極層22的單晶層24的單晶半導體材料和活性區域14的單晶半導體材料的平面(111)中形成呈角度的表面66，並且此有角度的表面66的形成可在基極層22的單晶層24的單晶半導體材料中以小於基極層22的多晶層25的蝕刻率的蝕刻率進行。
各個凹口42包括配置在溝槽隔離區域12的其中一者上方的區段，其可具有均勻高度，並且在基極層22的多晶層27、29(也就是，外部基極)之下延伸至直接位於介面21上方之介面。各個凹口42也包括區段，其可具有均勻高度，並且相對於基極層22的多晶層27、29之下的區段是朝向活性區域14呈角度或傾斜。各個凹口42的區段的中心線的指向的改變是由第7圖中的點虛線表示。各個凹口42的呈角度的區段部分地延伸進入基極層22的單晶層26內，並且部分地延伸進入活性區域14的單晶半導體材料內至位在溝槽隔離區域12的頂表面13下方的深度。
上方所描述的方法是用於製作積體電路晶片。所導致的積體電路晶片可由製作者以原始晶圓形式(例如，具有多個未封裝晶片的單一晶圓形式)分佈成裸晶粒、或以封裝形式分佈。在後者的情況中，晶片是安裝在單一晶片封裝件(例如，具有引線以固定至主機板或其它高階承載件的塑膠承載件)中、或在多晶片封裝件(例如，具有表面互連和埋置互連的一者或兩者的陶瓷承載件)中。在任何情況中，晶片可整合至其它晶片、分離的電路元件、及/或其它訊號處理裝置，以作為中間產品或終端產品的部件。
本文中引用的術語「垂直」、「水平」、「側向」等是藉由範例、而非藉由限制的方式作出以建立參照系。本文所使用的術語「水平」和「側向」是指與半導體基板的頂表面平行的平面，不論其實際三維空間指向。術語「垂直」和「正交」是指與「水平」方向垂直的方向。「上方」和「下方」的術語指示元件或結構相對於彼此及/或相對於半導體基板的頂表面的定位，而不是指相對高度。
當特徵「連接」或「耦接」至另一個元件時，其可以是直接地連接或耦接至其它元件、或者可以存在一個或更多個中介元件。當特徵「直接地連接」或「直接地耦接」至另一個元件時，則不存在中介元件。當特徵「間接地連接」或「間接地耦接」至另一個元件時，則存在至少一個中介元件。
本發明的各種實施例的描述是為了例示的目的而呈現，而不意圖窮盡或限制所揭露的實施例。許多修飾和變化對於本領域中的熟習技術者將是顯而易見的，而不致於偏離所描述的實施例的範疇和精神。本文所使用的技術用語是為最佳解釋實施例的原理、針對市場中所發現的技術的實際應用或技術改進、或致能本領域中的其他通常技術者了解本文所揭露的實施例而選擇的。
10‧‧‧基板
12‧‧‧溝槽隔離區域
13‧‧‧頂表面
14‧‧‧活性區域
16‧‧‧集極
18‧‧‧次集極
20‧‧‧集極接點區域
21‧‧‧介面
22‧‧‧基極層
24、26、28‧‧‧層、單晶層
25、27、29‧‧‧層、多晶層
32‧‧‧射極指
34‧‧‧射極蓋
40‧‧‧開口
42‧‧‧凹口
44‧‧‧異質接面雙極性電晶體
50‧‧‧區段
60‧‧‧矽化層
62‧‧‧層間介電層
64‧‧‧接點

Claims (20)

  1. 一種用於異質接面雙極性電晶體之裝置結構，該裝置結構包含：複數個溝槽隔離區域，配置以圍繞複數個活性區域；集極，在該活性區域的各者中；基極層，包括分別地配置在該活性區域上方的複數個第一區段和分別地配置在該溝槽隔離區域上方的複數個第二區段，該基極層的該第一區段含有單晶半導體材料，該基極層的該第二區段含有多晶半導體材料，並且該基極層的該第二區段在垂直方向與該溝槽隔離區域隔開，以定義複數個凹口；以及複數個射極指，分別地配置在該基極層的該第一區段上。
  2. 如申請專利範圍第1項所述之裝置結構，其中，該基極層的該第二區段的各者包括配置在該溝槽隔離區域的其中一者上方的矽鍺層。
  3. 如申請專利範圍第2項所述之裝置結構，其中，該基極層的該第二區段的各者包括配置在該基極層的該第二區段的其中一者的該矽鍺層上方的矽層。
  4. 如申請專利範圍第2項所述之裝置結構，其中，該基極層的該第一區段的各者包括矽鍺層，該矽鍺層直接地配置在該活性區域的其中一者上方並且側向地毗連該基極層的該第二區段的一者或更多者的該矽鍺層。
  5. 如申請專利範圍第1項所述之裝置結構，其中，該基極層的該第一區段的各者包括在該活性區域的其中一者上的矽層，並且該凹口的 各者在該基極層的該第二區段的其中一者之下延伸至該基極層的該第一區段的其中一者的該矽層。
  6. 如申請專利範圍第5項所述之裝置結構，其中，該基極層的各第一區段的該矽層具有厚度，而該凹口的高度大於或等於該基極層的各第一區段的該矽層的該厚度。
  7. 如申請專利範圍第1項所述之裝置結構，其中，該基極層的該第一區段和該基極層的該第二區段沿著複數個第一介面毗連，該溝槽隔離區域沿著複數個第二介面毗連該活性區域，而該第一介面的各者直接地配置在該第二介面的其中一者上方。
  8. 如申請專利範圍第1項所述之裝置結構，其中，該基極層的該第一區段的各者包括配置在該活性區域的其中一者上的矽層，而該凹口的各者包括第一區段和第二區段，該凹口的各者之該第一區段在該基極層的該第二區段的其中一者之下延伸至該基極層的該第一區段的其中一者的該矽層，而該凹口的各者之該第二區段延伸進入該基極層的該第一區段的其中一者的該矽層和該活性區域的其中一者內。
  9. 如申請專利範圍第8項所述之裝置結構，其中，該凹口的各者的該第二區段相對於該凹口的各者的該第一區段呈角度。
  10. 如申請專利範圍第9項所述之裝置結構，其中，該溝槽隔離區域的各者具有頂表面，而該凹口的各者的該第二區段延伸至各溝槽隔離區域的該頂表面下方的深度。
  11. 如申請專利範圍第1項所述之裝置結構，其中，該基極層的該第二區段的各者包括複數個開口，而該開口延伸通過該基極層的該第二區段至該凹口。
  12. 如申請專利範圍第1項所述之裝置結構，進一步包含： 層間介電層，在該異質接面雙極性電晶體上方；以及複數個接點，延伸通過該層間介電層至該基極層的該第二區段。
  13. 一種形成異質接面雙極性電晶體之方法，該方法包含：形成圍繞複數個活性區域的複數個溝槽隔離區域，該活性區域的各者包括集極；形成包括複數個第一區段和第二複數個區段的基極層，該第一區段含有分別地配置在該活性區域上方的單晶半導體材料，而該第二複數個區段含有分別地配置在該溝槽隔離區域上方的多晶半導體材料；選擇性對於該基極層的該第二區段的各者的第二半導體層而移除該基極層的該第二區段的各者的第一半導體層，以定義複數個凹口，該凹口以垂直方向配置在介於該第二半導體層與該溝槽隔離區域之間；以及形成分別地配置在該基極層的該第一區段上的複數個射極。
  14. 如申請專利範圍第13項所述之方法，其中，選擇性對於該基極層的該第二區段的各者的該第二半導體層而移除該基極層的該第二區段的各者的該第一半導體層包含：形成延伸通過該基極層的該第二區段的各者至該溝槽隔離區域的複數個開口。
  15. 如申請專利範圍第14項所述之方法，其中，選擇性對於該基極層的該第二區段的各者的該第二半導體層而移除該基極層的該第二區段的各者的該第一半導體層進一步包含：在形成該開口在該第二區段的各者中後，等向性蝕刻該第一半導體層。
  16. 如申請專利範圍第15項所述之方法，其中，該第一半導體層是以溼化學蝕刻製程等向性蝕刻。
  17. 如申請專利範圍第16項所述之方法，其中，該第一半導體層是由矽組成，而該第二半導體層是由矽鍺組成。
  18. 如申請專利範圍第16項所述之方法，其中，該第一半導體層藉由該溼化學蝕刻製程完全地移除。
  19. 如申請專利範圍第13項所述之方法，其中，該基極層的該第一區段的各者包括在該個別的活性區域上的矽層，該凹口的各者包括在該基極層的該第二區段之下延伸的第一區段，並且進一步包含：形成延伸進入該基極層的該第一區段的該矽層和該個別的活性區域內的各凹口的第二區段，其中，各凹口的該第二區段相對於各凹口的該第一區段呈角度。
  20. 如申請專利範圍第13項所述之方法，其中，該基極層的該第二區段的各者包括配置在該第二半導體層上方的第三半導體層，該第一半導體層具有第一導電類型，並且進一步包含：摻雜該基極層的該第二區段的各者的該第三半導體層，以使該第三半導體層具有第二導電類型，其中，該基極層的該第二區段的各者的該第一半導體層選擇性對於該基極層的該第二區段的各者的該第三半導體層而被移除。
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