TWI710121B - Fabrication method of 3-dimensional flash memory device - Google Patents

Abstract

The present invention relates to a method for manufacturing a three-dimensional flash memory device, which performs high-pressure hydrogen heat treatment and wet heat treatment on a three-dimensional vertical flash memory device in a manner that can prevent an increase in leakage current and maintain record retention. The manufacturing method includes: A step of laminating a conductive layer and an insulating layer on a substrate in a multi-layer manner to form a laminated film; a step of forming etching holes in the laminated film; a step of removing the conductive layer and forming a blocking insulating film; and performing a wet high-pressure heat treatment on the blocking insulating film Steps; a step of forming a charge storage film on the blocking insulating film; a step of forming a tunnel insulating film on the charge storage film; a step of forming a channel along an etching hole; and a step of forming a gate electrode in the tunnel insulating film. In the present invention, high-pressure hydrogen heat treatment is performed on the blocking insulating film, the charge storage film, and the tunnel insulating film, so that problems caused by an increase in leakage current can be prevented, and the mobility of the channel can be improved.

Description

Manufacturing method of three-dimensional flash memory device

The present invention relates to a method for manufacturing a three-dimensional flash memory device, in particular to a three-dimensional vertical flash memory device subjected to high-pressure hydrogen heat treatment steps and wet high-pressure heat treatment in a manner that can prevent an increase in leakage current and maintain record retention. Manufacturing method of flash memory device.

Generally, flash memory devices are classified into NAND type and NOR type according to cell structure and operation.

In addition, according to the type of the charge storage layer (charge storage film) used in the unit cell, it is classified into a floating gate type memory device, a metal oxide nitrite semiconductor (MONOS) structure, or a nitrogen structure. Silicon oxide semiconductor (Silicon Oxide Nitride Oxide Semiconductor; SONOS) structure memory device.

Floating gate type memory devices are devices that use potential wells to achieve memory characteristics. Metal oxide nitrite semiconductors or silicon nitride semiconductors are used in the silicon nitride film as a dielectric film. The floating gate existing in the bulk or the floating gate existing in the interface between the dielectric film and the dielectric film realizes the memory characteristic. The aforementioned metal oxide nitrite semiconductor refers to a case where the control gate is formed of metal, and a silicon nitride semiconductor refers to a case where the control gate is formed of polysilicon.

In particular, compared with floating gate type flash memory, the advantage of silicon nitride semiconductor or metal oxide nitrite semiconductor type is that it has relatively easy scaling and improved endurance. And uniform threshold voltage distribution. However, when the thickness of the tunnel insulating film and the blocking insulating film is reduced for high integration, the characteristics are reduced in terms of recording retention and durability.

Recently, flash memory devices have been continuously expanded to achieve large-capacity, which has been used as storage memory in many fields, and mass production of 20nm-class 128Gbit products has been achieved. It is expected that floating gate technology ( floating gate technology) to expand to the level below 10nm.

Moreover, in order to achieve high integration of flash memory devices, from a two-dimensional structure to a three-dimensional structure, NAND flash memory devices can eliminate the need to form contacts in each storage cell (cell). In the case of ), the storage units are connected in a string form, so that a variety of three-dimensional structures in the vertical direction can be realized.

This three-dimensional and non-flash memory is formed in a form in which an N+ junction diffusion layer is arranged in a Si volume and used as a common source line. This structure has advantages, but due to the large resistance of the diffusion layer, the characteristics of the memory cell are degraded.

An example of this technique is disclosed in the following documents.

For example, Patent Document 1 below discloses a three-dimensional flash memory device including: a device forming substrate formed with through holes penetrating the upper surface and the lower surface; electrical conductors with gaps filled in the through holes The vertical channel is formed on the conductor and is formed in a shape extending along the upper direction of the device forming substrate; and the common source line is electrically connected to the conductor and is formed of a conductive material.

In addition, the following Patent Document 2 discloses the following three-dimensional semiconductor device, that is, comprising: a semiconductor substrate; a plurality of vertical channel structures arranged on the semiconductor substrate; a P-type semiconductor layer directly perpendicular to the plurality of vertical channel structures The channel structure is in contact with each other and is formed on the semiconductor substrate; and a common source line is formed on the semiconductor substrate between the plurality of vertical channel structures. The P-type semiconductor layer is simultaneously formed with the plurality of vertical channel structures and the The common source lines are connected.

In addition, the following Non-Patent Document 1 discloses the problem of the three-dimensional flash memory device, that is, the defect that remains in the polycrystalline silicon channel (polycrystalline silicon channel), so the problem of the hollow (Macaroni) Si channel based In the flash memory device, the driving current of the transistor is lacking.

[Prior Technical Literature]

[Patent Literature]

Patent Document 1: Korean Granted Patent Publication No. 10-1040154 (authorized on June 02, 2011).

Patent Document 2: Korean Granted Patent Publication No. 10-1489458 (authorized on January 28, 2015).

[Non-Patent Literature]

Non-Patent Document 1: Statistical spectroscopy of switching traps in deeply scaled vertical poly-Si channel for 3D memories, M. Toledano-Luque, IMEC, p.562, IEDM 2013.

However, in the prior art as described above, it has been confirmed that in a flash memory device based on a hollow (Macaroni) Si channel, in order to solve the defects remaining in the polysilicon channel, a high-pressure hydrogen heat treatment is used to increase the driving current. Get a maximum improvement of 10 times.

However, in the process of high-pressure hydrogen heat treatment, although the oxide layer/silicon (Si) interface is improved, in the flash memory, the composition ratio of the blocking oxide layer becomes lower, resulting in leakage current, which is recorded The problem of deterioration of preservation characteristics.

The present invention is to solve the above-mentioned problems. The object of the present invention is to provide a method for manufacturing a three-dimensional flash memory device that can prevent problems caused by an increase in leakage current and improve the mobility of the channel.

Another object of the present invention is to provide a method for manufacturing a three-dimensional flash memory device that can minimize the defect formation effect and prevent hydrogen penetration in the step of forming a blocking oxide layer.

In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a three-dimensional flash memory device, which is characterized by comprising: laminating a conductive layer and an insulating layer on a substrate in a multi-layer manner to form a laminated film; The step of etching the hole; the step of removing the conductive layer and forming a blocking insulating film; the step of performing a wet high-pressure heat treatment; the step of forming a charge storage film on the blocking insulating film; the step of forming a tunnel insulating film on the charge storage film The step of forming a channel in the above-mentioned etching hole; and the step of forming a gate electrode in the above-mentioned tunnel insulating film, in the method of manufacturing a three-dimensional flash memory device of the present invention, the above-mentioned blocking insulating film, charge storage film, tunnel The insulating film performs high-pressure hydrogen heat treatment.

In addition, the present invention is characterized in that, in the method of manufacturing a three-dimensional flash memory device of the present invention, the above-mentioned wet high pressure heat treatment is performed under 1-20 atmospheric pressure conditions.

Furthermore, the present invention is characterized in that, in the method of manufacturing a three-dimensional flash memory device of the present invention, the high-pressure hydrogen heat treatment is performed at a temperature of 350 to 450°C.

In addition, the present invention is characterized in that, in the method of manufacturing a three-dimensional flash memory device of the present invention, a nitrite protective film is formed on the charge storage film to prevent hydrogen from permeating into the blocking insulating film.

Furthermore, the present invention is characterized in that, in the manufacturing method of the three-dimensional flash memory device of the present invention, the above-mentioned high-pressure hydrogen heat treatment is performed under the conditions of 1 to 20 atmospheres.

As described above, the method for manufacturing a three-dimensional flash memory device according to the present invention has the following effect, that is, by performing an optimal hydrogen heat treatment for the three-dimensional flash memory device, the leakage current caused by the increase The problem can improve the mobility of the channel.

In addition, the method for manufacturing a three-dimensional flash memory device according to the present invention has the following effects, namely, ensuring the driving current by optimal interface passivation, and ensuring the recording of the device by maintaining the occlusion oxidation composition ratio Save the characteristics.

100‧‧‧Three-dimensional flash memory device

110‧‧‧Device support substrate

120‧‧‧Separation membrane

130‧‧‧Conductive film

140‧‧‧First lower side bump

145‧‧‧Second lower side bump

150‧‧‧The first upper side bump

155‧‧‧Second upper side bump

160‧‧‧Device forming substrate

165‧‧‧Through hole

167‧‧‧Through hole

170‧‧‧Conductor

172‧‧‧Conductor

180‧‧‧Insulation layer

181‧‧‧Block insulating film

182‧‧‧Upper insulation layer

183‧‧‧Charge Storage Film

184‧‧‧Tunnel insulating film

185‧‧‧Conductive layer

187‧‧‧Lower insulation layer

190‧‧‧Vertical Channel

195‧‧‧Bit Line

200‧‧‧Etched hole

A10, A20, S10~S60‧‧‧Step

FIG. 1 is a cross-sectional view for explaining the structure of a three-dimensional flash memory device applicable to the present invention.

2 is a partial cross-sectional view for explaining the vertical channel, the tunnel insulating film, the charge storage film, the blocking insulating film, and the gate shown in FIG. 1.

FIG. 3 is a flowchart for explaining the manufacturing method of the three-dimensional flash memory device shown in FIG. 2.

4 to 10 are cross-sectional views for explaining the processes of forming the tunnel insulating film, the charge storage film, and the blocking insulating film, respectively.

Through the descriptions and drawings in this specification, the above-mentioned objects, other objects, and novel features of the present invention will be described more clearly.

Hereinafter, the structure of the present invention will be explained based on the drawings.

FIG. 1 shows an example of the structure of a three-dimensional flash memory device applicable to the present invention.

The three-dimensional flash memory device 100 applicable to the present invention is roughly composed of a device part and a support part. The device part has a device forming substrate 160, a conductor 170, a conductor 172, a first upper bump 150, and a second upper bump 155 , The vertical channel 190, the lower insulating layer 187, the insulating layer 180, the conductive layer 185, the upper insulating layer 182, and the bit line 195. The supporting part has a device supporting substrate 110, a separation film 120, a conductive film 130, a first lower bump 140 and a second lower bump 145. The device part and the support part are connected by the first upper protrusion 150, the second upper protrusion 155, the first lower protrusion 140, and the second lower protrusion 145.

For example, the device support substrate 110 described above may be made of a silicon substrate, and a separation film 120 made of an insulating material and a conductive thin film 130 made of a conductive material are formed on the device support substrate 110. The conductive thin film 130 is patterned so as to correspond to the size and position of the through holes 165 and 167 formed in the device forming substrate 160. A first lower bump 140 and a second lower bump 145 made of a conductive substance are formed on the upper side of the patterned conductive film 130. The first lower bump 140 is electrically connected to the first upper bump 150, and the second lower bump 145 is electrically connected to the second upper bump 155 to connect the device part and the support part.

For example, the device forming substrate 160 described above can be made of a silicon substrate, and the device forming substrate 160 has through holes 165 and 167 penetrating the upper surface and the lower surface. The conductors 170 and 172 may be formed of a metal as a conductive material, and the gaps are filled in the through holes 165 and 167 formed in the device formation substrate 160. The conductor 170 with the gap filled in the through hole 165 is formed in the lower part of the vertical channel 190. The through hole 165 has a size of several μm to several tens of μm, and the vertical channel 190 is connected in a block unit. A first upper bump 150 and a second upper bump 155 made of a conductive material are formed under the conductors 170 and 172.

The conductive body 172 is used to receive an input external input signal on the upper side of the device forming substrate 160, and is electrically connected to the conductive film 130 by the second lower bump 145 and the second upper bump 155. That is, the conductive film 130, the second lower bump 145, the second upper bump 155, and the conductor 172 constitute a common source line so that the external signal input to the common source line is supplied to the vertical channel 190.

The vertical channel 190 may be formed of polysilicon (poly-Si) and formed on the conductor 170 to be formed in a shape extending long toward the upper side of the device forming substrate 160. The diameter of the vertical channel 190 can reach several tens of nm to several hundreds of nm. In addition, a bit line 195 made of a conductive material is formed on the upper portion of the vertical channel 190.

In addition, a plurality of laminated films (insulating layers 180 and conductive layers 185) in which insulating layers 180 and conductive layers 185 are alternately laminated are formed on the device formation substrate 160. The insulating layer 180 may be formed of silicon oxide (SiO ₂ ), and the conductive layer 185 may be formed of polysilicon (poly-Si). The insulating layer 180 and the conductive layer 185 may be formed with a thickness of several tens of nm. The insulating layer 180 and the conductive layer 185 are formed to surround the vertical channels 190, respectively. A lower insulating layer 187 made of an insulating material is formed under the laminated film (insulating layer 180, conductive layer 185), as if the conductor 170 and the conductive layer 185 are electrically separated. In addition, an upper insulating layer 182 made of an insulating material is formed on the upper portion of the laminated film (insulating layer 180 and conductive layer 185) to electrically separate the conductive layer 185 and the bit line 195 and protect the bit line 195.

In addition, as shown in FIG. 2, a tunnel insulating film 184 is formed between the vertical channel 190 and the above-mentioned laminated film (insulating layer 180 and conductive layer 185). The tunnel insulating film 184 may be formed of silicon oxide. Also, a charge storage film 183 and a blocking insulating film 181 are sequentially formed between the tunnel insulating film 184 and the conductive layer 185. The charge storage film 183 may be formed of a silicon nitride film (Si ₃ N ₄ ), and the blocking insulating film 181 may be formed of silicon oxide. Also, the tunnel insulating film 184, the charge storage film 183, and the blocking insulating film 181 can be formed to a thickness of several nm.

If a three-dimensional flash memory device is constructed, the conductive layer 185 can function as a control gate. Furthermore, by applying a potential to the bit line 195, the common source line, and the conductive layer 185, the charge can be stored or discharged in the charge storage film 183 in a charging or anti-electricity manner. Therefore, the tunnel insulating film 184, the charge storage film 183, and the blocking insulating film 181 can function as a storage unit. In addition, since the charge storage film 183 is electrically separated by the insulating layer 180, it is difficult for the charge stored in the charge storage film 183 to leak to the outside. If the flash memory is constructed in this form, there are memory cells equivalent to the number of conductive layers 185 in each vertical channel 190, so the degree of integration can be greatly increased.

After that, a method of manufacturing the tunnel insulating film 184, the charge storage film 183, and the blocking insulating film 181 that function as a storage unit will be described with reference to FIGS. 3 to 10.

3 is a flowchart for explaining the method of manufacturing the three-dimensional flash memory device shown in FIG. 2, and FIGS. 4 to 10 are for explaining the formation of the tunnel insulating film 184, the charge storage film 183, and the blocking insulating film 181, respectively Cross-sectional view of the process.

As shown in FIGS. 3 and 4, the conductive layer 185 and the insulating layer 180 are laminated in multiple layers on the conductor 170 and the lower insulating layer 187 provided on the device formation substrate to form a laminated film (step S10). Then, as shown in FIG. 5, an etching hole 200 is formed in the laminated film (step S20), and as shown in FIG. 6, the conductive layer 185 is removed.

Thereafter, as shown in Fig. 7, a blocking insulating film 181 is formed inside the removed conductive layer 185 (step S30).

The blocking insulating film 181 is used to prevent electrons from the tunnel insulating film 184 from leaking to the control gate during program operation.

In addition, it is prevented that electrons are prevented from moving from the control gate to the charge storage film 183 during the erasing operation. For this reason, it is preferable that the above-mentioned blocking insulating film 181 uses a high-k dielectric with a high dielectric constant. For example, it is preferably formed of a substance containing a high dielectric substance such as Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ , and YO ₂ . More preferably, hafnium silicate (Hf Silicate), zirconium silicate (Zr Silicate), yttrium silicate (Y Silicate) or lanthanide (Ln ) Metal silicate (Silicate) and so on.

After that, wet high-pressure heat treatment is performed on the above-mentioned blocking insulating film 181 (step A10).

In the wet high pressure heat treatment, the plurality of defects in the blocking insulating film 181 can be classified into point defects, line defects, plane defects, and the like. Fundamentally, elimination at high temperature is a process of increasing the energy of particles and moving high-temperature particles to energy-intensive defects to smooth out the defects.

In the case of performing the wet high-pressure heat treatment, the defects or oxygen pores of the blocked insulating layer are eliminated, and therefore, when the elimination operation is performed, the leakage current is reduced. That is, when the elimination operation is performed, the cathode electric field is applied by blocking the insulator, and even if the cathode electric field value increases, the gate leakage current is significantly lower than the case where the wet high-pressure heat treatment is not performed.

In the case of performing wet high-pressure heat treatment, multiple leakage current factors are eliminated, and the amount of electrons flowing into the blocking insulating layer is reduced, so that the elimination operation can be performed smoothly.

For wet high pressure heat treatment, when low temperature heat treatment is performed, water vapor is supplied under an inert gas atmosphere such as nitrogen or argon, and the heat treatment is performed in a high pressure atmosphere. Among them, the wet high-pressure heat treatment is performed under 1 to 20 atmospheres. However, preferably, it is performed at a temperature of 250° C. for 10 minutes in an atmosphere containing nitrogen at 10 atmospheres and steam at 2 atmospheres. Since the above-mentioned low-temperature heat treatment is performed in a high-pressure state, oxygen contained in the vapor penetrates into the blocking insulating film 181, and defects remaining in the blocking insulating film 181 are smoothed. Also, when performing low-temperature heat treatment, the gas pressure can reach 1 to 20 atmospheres. Next, as shown in FIG. 8, a charge storage film 183 is formed in the blocking insulating film 181 (step S40). The charge storage film 183 described above is used to store electrons passing through the tunnel insulating film 184 from the channel area. Also, preferably, the charge storage film 183 is formed of a silicon nitride film.

Preferably, the charge storage film 183 is made of a silicon nitride film (nitrite). Therefore, the charge storage film 183 forms a nitrite protective film to prevent the permeation of hydrogen or deuterium into the blocking insulating film 181 during high-pressure hydrogen heat treatment or deuterium heat treatment.

Next, as shown in FIG. 9, a tunnel insulating film 184 is formed in the charge storage film 183 (step S50).

Preferably, the tunnel insulating film 184 is formed of silicon oxide. In addition, the thickness of the tunnel insulating film 184 can be adjusted so that when the erasing action is performed, the charge can be easily moved to the channel area through the FN channel, and when the program is running, the charge can be easily stored in the charge. Layer inflow. Therefore, preferably, the thickness of the tunnel insulating film 184 is 5 nm or less.

After that, a channel is formed along the etching hole 200. Preferably, the channel is made of amorphous silicon as a material.

Then, as shown in FIG. 10, a gate electrode is formed in the tunnel insulating film 184 (step S60). Preferably, the gate electrode is formed of Ti, Ta, TaN, TiN or polysilicon. Word lines can be provided on such gate electrodes.

Next, a high-pressure hydrogen heat treatment is performed on the substrate on which the tunnel insulating film 184, the charge storage film 183, and the blocking insulating film 181 are formed (step A20).

More precisely, high-pressure hydrogen heat treatment is performed on the interface between the tunnel insulating film 184 and the channel.

High-pressure hydrogen heat treatment is a step of performing heat treatment in a hydrogen or deuterium atmosphere and under the conditions of 1 to 20 atmospheres. As a result, the electrical characteristics can be improved by passivating floating charges at the interface between the tunnel insulating film 184 and the channel.

As mentioned above, the invention of the present inventor has been specifically described based on the above-mentioned embodiments, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be implemented without departing from the scope of the gist.

[Industrial availability]

By using the manufacturing method of the three-dimensional flash memory device of the present invention, the drive current can be ensured by optimal interface passivation, and the record-saving characteristics of the device can be ensured by maintaining the occlusion oxidation composition ratio.

A10, A20, S10~S60‧‧‧Step

Claims (4)

A method for manufacturing a three-dimensional flash memory device includes the following steps: a step of laminating a conductive layer and an insulating layer on a substrate in a multi-layer manner to form a laminated film; a step of forming etching holes in the aforementioned laminated film; removing the aforementioned conductive layer and The step of forming a blocking insulating film; the step of performing wet high-pressure heat treatment on the aforementioned blocking insulating film; the step of forming a charge storage film on the aforementioned blocking insulating film; the step of forming a tunnel insulating film on the aforementioned charge storage film; along the aforementioned etching A step of forming a channel through a hole; and a step of forming a gate electrode in the aforementioned tunnel insulating film; performing high-pressure hydrogen heat treatment on the interface between the aforementioned tunnel insulating film and the aforementioned channel; wherein the aforementioned wet high-pressure heat treatment is performed under the conditions of 1 to 20 atmospheres . The method for manufacturing a three-dimensional flash memory device as described in claim 1, wherein the aforementioned high-pressure hydrogen heat treatment is performed at a temperature of 350°C to 450°C. The method for manufacturing a three-dimensional flash memory device described in claim 1, wherein the charge storage film is made of nitrite to prevent hydrogen from penetrating the blocking insulating film. The method for manufacturing a three-dimensional flash memory device described in claim 1, wherein the aforementioned high-pressure hydrogen heat treatment is performed under a condition of 1 to 20 atmospheres.

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