TWI710014B - Saw wafer method - Google Patents
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- TWI710014B TWI710014B TW108131774A TW108131774A TWI710014B TW I710014 B TWI710014 B TW I710014B TW 108131774 A TW108131774 A TW 108131774A TW 108131774 A TW108131774 A TW 108131774A TW I710014 B TWI710014 B TW I710014B
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Abstract
一種切割晶圓方法,特別是指一種能改善DAG(Dice After Gind)或DBG(Dice Before Gind)製程,透過本發明的技術可提升產品精度及產出效率高等多重優點。 A method of dicing wafers, especially refers to a method that can improve the DAG (Dice After Gind) or DBG (Dice Before Gind) process, and the technology of the present invention can improve the multiple advantages of product accuracy and high output efficiency.
Description
本發明關於一種切割晶圓方法,特別是指一種能改善DAG(Dice After Gind)或DBG(Dice Before Gind)製程,透過本發明的技術可提升產品精度及產出效率高等多重優點。 The present invention relates to a wafer dicing method, in particular to a method that can improve the DAG (Dice After Gind) or DBG (Dice Before Gind) process, and the technology of the present invention can improve the multiple advantages of product accuracy and high output efficiency.
在物聯網的應用中,如可穿戴設備朝「更小、更薄、更快速及更高效能」的需求,常見的穿戴設備如智能手環、智慧型行動裝置等已經成為日常生活常見的設備。 In the application of the Internet of Things, such as the demand for "smaller, thinner, faster and higher performance" of wearable devices, common wearable devices such as smart bracelets and smart mobile devices have become common devices in daily life .
積體電路的製造,乃從矽晶圓經過習知的製程後如黃光製程、蝕刻製程、薄膜製程及擴散製程等技術,最後積體電路的功能將晶圓切割、封裝、測試提供相關產品需求功能。 The manufacture of integrated circuits is based on silicon wafers that go through well-known processes such as yellow light process, etching process, thin film process and diffusion process. Finally, the function of integrated circuit will provide related products for wafer cutting, packaging and testing. Demand function.
附圖1為等離子體的研磨後切割(以下簡稱DAG製程,Dice After Gind),簡單來說將晶圓先貼上研磨膠帶後進行晶圓研磨減少其厚度達到表面平坦化,最後進行切割。 Fig. 1 is plasma grinding and dicing (hereinafter referred to as DAG process, Dice After Gind). Simply put, the wafer is first attached with a grinding tape and then the wafer is polished to reduce its thickness to flatten the surface, and finally dicing.
附圖2為等離子體的研磨前切割(以下簡稱DBG製程,Dice Before Gind),其目的是改善DAG製程的缺點,降低背面崩裂進而提高晶片抗折強度,另外因為是在研磨結束後分割形成晶粒,所以有望在加工薄型晶片時減小晶片破損的風險,目前在DBG製程中大多會採用DAF(Die Attach Film)的話,也有可能在SiP(System in Package)等薄型晶片積層的封裝製造方面全面採用DBG製 程。而DBG製程加上DAF雷射切割的製程主要先半切穿切割晶圓,貼附研磨膠帶進行背面研磨進行晶片研磨平坦。 Figure 2 is plasma cutting before polishing (hereinafter referred to as DBG process, Dice Before Gind), its purpose is to improve the shortcomings of the DAG process, reduce cracking on the back side and improve the flexural strength of the wafer, in addition, because it is divided to form crystals after the polishing is completed Therefore, it is expected to reduce the risk of chip breakage when processing thin wafers. At present, DAF (Die Attach Film) is mostly used in the DBG process, and it may also be comprehensive in the packaging and manufacturing of thin wafer stacks such as SiP (System in Package). Adopt DBG system Cheng. The DBG process plus DAF laser dicing process mainly first half-cut through the diced wafer, and attach a polishing tape for back polishing to polish the wafer flat.
如表1所示即是DAG製程與DBG製程製造所需要的站點與對應的設備:
利用DAG製程可以獲得產品的優點在於:1.價格便宜、2.普及性高、3.站點少與、4.產出效率高;但是DAG製程缺失在:1.無法有效改善崩裂問題、2.切割時Z軸精準度較差。 The advantages of using the DAG process to obtain products are: 1. Low price, 2. High popularity, 3. Fewer sites and 4. High output efficiency; But the DAG process is lacking in: 1. Cannot effectively improve the cracking problem, 2. .Poor accuracy of Z axis when cutting.
利用DBG製程可以獲得產品的優點在於:1.下切Z軸工作準度精確、2.有效改善正面崩裂與背面崩裂;但是DBG製程缺失在:1.產出效率低、2.普及性不高、3.設備價格昂貴、4.與DAG製程相較下站點較多增加額外的維修保養費用、5.消耗性材料昂貴(例如:雷射頭)。 The advantages of using the DBG process to obtain products are: 1. Accurate work accuracy of the down-cut Z-axis, 2. Effectively improve front cracking and back cracking; but the DBG process lacks: 1. Low output efficiency, 2. Low popularity, 3. The equipment is expensive, 4. Compared with the DAG process, there are more additional maintenance costs for the lower site, 5. The consumable materials are expensive (for example: laser head).
從上述可以得知DAG製程或DBG製程技術仍然有有改善空間。本案的發明人經過多年研究後終於開發出本案之切割晶圓方法。 From the above, it can be known that there is still room for improvement in DAG process or DBG process technology. After years of research, the inventor of this case finally developed the method of cutting wafers in this case.
本發明的主要目的在於提供一種切割晶圓方法,乃改善上述DAG製程與DBG製程的缺點,並兼具Z軸精度高與改善正面崩裂及背面崩裂的效果者。 The main purpose of the present invention is to provide a wafer dicing method that improves the shortcomings of the above-mentioned DAG process and the DBG process, and has both high Z-axis accuracy and the effects of improving front cracking and back cracking.
可達成上述目的的製造方式包含有:步驟1:將晶圓半切穿切割;步驟2:將研磨膠帶貼裝於晶圓;步驟3:進行晶圓背面研磨;步驟4:切割DAF膠帶貼裝;步驟5:表面保護膠帶剝離;步驟6:將晶圓透過切割設備全面切割。 The manufacturing methods that can achieve the above objectives include: Step 1: Half-cut through the wafer; Step 2: Place the polishing tape on the wafer; Step 3: Perform back grinding of the wafer; Step 4: Cut DAF tape placement; Step 5: Peel off the surface protection tape; Step 6: Cut the wafer through the cutting equipment.
在本發明的步驟1係利用迪斯科(DISCO)公司之切割設備(型號DFD6361)進行晶圓半切穿切割。 In step 1 of the present invention, a cutting device (model DFD6361) of DISCO is used to perform wafer half-cut through cutting.
在本發明的步驟2係採用琳得科(LINTEC)先進科技公司之全自動研磨用膠帶貼合機(型號RAD-3510F/12)將研磨膠帶貼裝於晶圓。 In step 2 of the present invention, a fully automatic polishing tape laminating machine (model RAD-3510F/12) from LINTEC Advanced Technology is used to attach the polishing tape to the wafer.
在本發明的步驟3採用迪斯科公司之研磨設備(型號DGP8761)進行晶圓背面研磨。 In step 3 of the present invention, a disco company's grinding equipment (model DGP8761) is used to perform wafer back grinding.
在本發明的步驟4、5採用迪斯科公司之研磨設備(型號DFM2800)進行DAF貼裝、切割框架黏貼裝置、表面保護膠膜剥離裝置一體化之裝置。 In steps 4 and 5 of the present invention, the disco company's grinding equipment (model DFM2800) is used to perform DAF mounting, cutting frame sticking device, and surface protective film peeling device integrated device.
在本發明的步驟6係利用迪斯科公司之切割設備(型號DFD6361)進行晶圓全面切割。 In step 6 of the present invention, the disco company's cutting equipment (model DFD6361) is used to perform overall wafer cutting.
在本發明的實施方式中,所述之半穿切割厚度為晶圓二分之一至三分之一厚度。 In the embodiment of the present invention, the thickness of the half-through cutting is one-half to one-third the thickness of the wafer.
據此,透過本發明的製程具有下列的優點: Accordingly, the process of the present invention has the following advantages:
1.本發明所使用的設備與DAG製程或DBG製程幾乎相同,因此替代性與共用性高。 1. The equipment used in the present invention is almost the same as the DAG process or the DBG process, so it is highly replaceable and common.
2.如表2所示,以本發明所製造的晶圓價格具有競爭力。 2. As shown in Table 2, the price of wafers manufactured by the present invention is competitive.
3.具備DBG製程下切Z軸精準度高,有效改善正面崩裂與背面崩裂。 3. Equipped with DBG process to cut down the Z axis with high accuracy, effectively improving front cracking and back cracking.
4.產出效率高增加業者獲利。 4. High output efficiency increases the profits of the industry.
附圖1為DAG製程示意圖。 Figure 1 is a schematic diagram of the DAG process.
附圖2為DBG製程示意圖。 Figure 2 is a schematic diagram of the DBG process.
附圖3為本發明製程示意圖。 Figure 3 is a schematic diagram of the manufacturing process of the present invention.
附圖4為本發明與習用技術相比較下的良率分析。 Fig. 4 is a yield analysis of the present invention compared with conventional technologies.
請參閱附圖3、4與表2,本發明切割晶圓方法其運用在積體電路(晶粒)切割時使用,其步驟包含有: Please refer to Figures 3, 4 and Table 2. The wafer dicing method of the present invention is used in the dicing of integrated circuits (die). The steps include:
步驟1:將晶圓半切穿切割;步驟1係利用迪斯科(DISCO)公司之切割設備(型號DFD6361)進行晶圓半切穿切割、又所述之半穿切割厚度為晶圓二分之一或三分之一的厚度。 Step 1: Half-cut through the wafer; Step 1 uses DISCO's cutting equipment (model DFD6361) to perform the half-cut through the wafer, and the thickness of the half-through cut is half or three of the wafer One part of the thickness.
步驟2:將研磨膠帶貼裝於晶圓;步驟2係採用琳得科(LINTEC)先進科技公司之全自動研磨用膠帶貼合機(型號RAD-3510F/12)將研磨膠帶貼裝於晶圓。 Step 2: Place the polishing tape on the wafer; Step 2 is to use the automatic polishing tape laminator (model RAD-3510F/12) of LINTEC Advanced Technology to attach the polishing tape to the wafer .
步驟3:進行晶圓背面研磨;步驟3採用迪斯科公司之研磨設備(型號DGP8761)進行晶圓背面研磨。 Step 3: Perform wafer back grinding; Step 3 uses disco company's grinding equipment (model DGP8761) to perform wafer back grinding.
步驟4:切割DAF膠帶貼裝。 Step 4: Cut the DAF tape for placement.
步驟5:表面保護膠帶剝離;步驟4、5採用迪斯科公司之研磨設備(型號DFM2800)進行DAF貼裝、切割框架黏貼裝置、表面保護膠膜剥離裝置一體化之裝置,其將步驟4、5合併於一站即可完成。 Step 5: Peel off the surface protective tape; Steps 4 and 5 use the disco company's grinding equipment (model DFM2800) for DAF placement, cutting frame pasting device, and surface protective film peeling device integration device, which combines steps 4 and 5 It can be done in one stop.
步驟6:將晶圓透過切割設備全面切割;利用迪斯科公司之切割設備(型號DFD6361)進行晶圓全面切割。 Step 6: Fully cut the wafer through the cutting equipment; use the disco company's cutting equipment (model DFD6361) to cut the whole wafer.
據此,透過本發明的製程具有下列的優點: Accordingly, the process of the present invention has the following advantages:
1.本發明所使用的設備與DAG製程或DBG製程幾乎相同,因此替代性與共用性高。 1. The equipment used in the present invention is almost the same as the DAG process or the DBG process, so it is highly replaceable and common.
2.如表2所示,以本發明所製造的晶元價格具有競爭力。 2. As shown in Table 2, the price of the wafer manufactured by the present invention is competitive.
3.本發明的製程具備DBG製程下切Z軸精準度高,有效改善正面崩裂與背面崩裂。 3. The process of the present invention has a DBG process with high precision of the Z-axis undercutting, which can effectively improve front cracking and back cracking.
4.產出效率高增加業者獲利。 4. High output efficiency increases the profits of the industry.
5.如附圖4所示,以DAG製程的產品良率約20%;以DBG製程的產品良率約99%;而透過本發明的製造步驟則有97.9%的產品良率,可以理解到建構生產線的價格可以降低,但是又能維持產品良率降低成本,讓業者獲利大幅提升。 5. As shown in Figure 4, the product yield rate of the DAG process is about 20%; the product yield rate of the DBG process is about 99%; and through the manufacturing steps of the present invention, the product yield rate is 97.9%, which can be understood The price of constructing a production line can be lowered, but it can maintain the product yield and reduce costs, so that the profits of the industry can be greatly increased.
綜上所述,本發明構成結構均未曾見於諸書刊或公開使用,誠符合發明專利申請要件,懇請 鈞局明鑑,早日准予專利,至為感禱。 In summary, the structure of the present invention has never been seen in books and periodicals or used publicly, and sincerely meets the requirements of an invention patent application. I sincerely ask Jun Bureau to approve the patent as soon as possible.
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US7420263B2 (en) * | 2004-03-02 | 2008-09-02 | Chippac, Inc. | DBG system and method with adhesive layer severing |
JP4434977B2 (en) * | 2005-02-02 | 2010-03-17 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
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US7420263B2 (en) * | 2004-03-02 | 2008-09-02 | Chippac, Inc. | DBG system and method with adhesive layer severing |
JP4434977B2 (en) * | 2005-02-02 | 2010-03-17 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
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