TWI710007B - Lithography apparatus and method to perform micro light emitting diode lithography - Google Patents

Abstract

A lithography apparatus is described having a substrate scanning system configured to scan a substrate, a pattern generator configured receive input signals and produce output signals related to a pattern and a light source connected to the pattern generator, wherein the light source is at least one array of micro light emitting diodes, wherein the array is configured to receive the signals from the pattern generator and repeat the pattern produced by the pattern generator.

Description

Lithography equipment and method for performing micro-light-emitting diode lithography

Several aspects of this disclosure are related to several maskless lithography systems. More particularly, several aspects of the present disclosure relate to several systems and methods for micro-light-emitting diode array lithography.

The advancement in light-emitting diode technology has continued to develop at a rapid pace in several industries. As an example, it is currently feasible to manufacture large arrays of light emitting diodes (LEDs) together with logic AND drivers on a single substrate. The traditional techniques currently used for maskless lithography use laser illumination, micro-mirror arrays, such as those available from Texas Instruments. The use of this device in combination with the lithography system has two inherent disadvantages. The first disadvantage is that the maximum frame rate is 20kHz. The second disadvantage is that the coherence of the irradiated beam combined with the grating characteristics of the mirror array conflicts with the telecentric requirement of the projection lens. The limited frame rate results in very slow scanning speed and/or low overall throughput. The limited frame rate may also produce fifty (50) or more different patterns for use Very complex software on every point on the substrate. In addition, the lack of telecentricity not only compromises on depth of field performance, but also compromises on overlay performance.

There is a need to provide an illumination system and method for the lithography system that does not conflict with the telecentric requirements.

There is also a need for illumination systems and methods for lithography systems that provide improved scan rates and greater overall yields of the included systems.

Compared with traditional systems, there is also a demand for lithography systems that provide increased depth of field performance.

Compared with traditional systems, there is also a demand for lithography systems that provide better coverage performance.

The following summary should not be regarded as limiting several aspects of this disclosure.

In a non-limiting embodiment, a lithography apparatus is disclosed and includes a substrate scanning system configured to scan a substrate; and one or more arrays of micro-light emitting diodes are imaged onto the substrate by a imaging system , Where the hard-wired logic is incorporated in the micro-light-emitting diodes of one or more arrays, and assembled to switch a logic signal in a scanning direction and assembled to use the logic signal to switch individual micro-light-emitting diodes Completely open or completely closed.

In another non-limiting embodiment, a method for performing micro-light-emitting diode lithography is disclosed and includes: placing a substrate on a platform, the platform being assembled to support the substrate; aligning the substrate on the platform with a mark; Utilize at least one array of micro light emitting diodes to illuminate the substrate on the platform; and remove the substrate from the platform.

Other aspects and advantages will be clearer through the description below and the scope of the attached patent application. In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

100: platform

101: Lithography equipment

102: substrate

104: substrate scanning system

106: micro light emitting diode

110: pattern generator

112: Computer

114: Flip-Flop

116: system clock

200, 300: method

202-206, 302-306: steps

In order to understand the above-mentioned features of the present disclosure in detail, the more specific description of the present disclosure briefly excerpted above can refer to several embodiments, and some of these embodiments are shown in the attached drawings. However, it is worth noting that for other equivalent embodiments of the present disclosure, the accompanying drawings only illustrate typical applications of the present disclosure and are not considered as a limitation of its scope.

FIG. 1 is a schematic diagram of the lithography device in an exemplary aspect described.

Figure 2 is a schematic diagram showing the approximate linear relationship between the relative exposure dose and the position of the line edge. The relative exposure dose is generated by the rows of diodes defining the edges.

Figure 3 is a plan and cross-sectional view of the LED array covered by the immersion lens.

Figure 4 is a schematic diagram showing how the logic state of the flip-flop performs 5 clock cycles.

Figure 5 is a schematic diagram showing how the internal and external logic contained in the LED row can be configured to transmit the exposure pattern from one end of the LED array to the other end in synchronization with the movement of the substrate.

Figure 6 is a layout diagram showing how two LED arrays can be positioned in a relay target plane to keep the line spacing.

Figure 7 is a schematic diagram showing how the position of the edge of the line can be moved by changing the relative exposure dose. The relative exposure dose is generated by the pixels at the edge of the line.

Figure 8 is a schematic diagram of an exemplary method for performing lithography operations in the illustrated aspect.

Figure 9 is a schematic diagram of an exemplary method for performing lithography operations in the illustrated aspect.

To facilitate understanding, the same reference numbers are used where feasible to indicate the same elements commonly used in the drawings. It will be understood that several elements disclosed in one embodiment can be advantageously utilized in other embodiments without any special citation.

In the following description, the reference system is achieved with several embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specific described embodiments. Instead, whether related to different embodiments or not, the combination of the following features and elements is expected to implement and realize the present disclosure. Furthermore, although the several embodiments of the present disclosure can achieve advantages over other possible solutions and/or conventional techniques, whether or not to achieve specific advantages through a given embodiment is not a limitation of this disclosure. Therefore, in addition to clearly stated in the scope of the patent application, the following aspects, features, embodiments and advantages are for illustration only, and are not regarded as elements or limitations of the scope of the patent application. Similarly, unless clearly stated in the scope of the patent application, references to "this disclosure" shall not be interpreted as the generalization of the subject matter of the invention disclosed herein, and shall not be regarded as elements within the scope of the attached patent application. Or limit.

Some embodiments will now be explained with reference to the drawings. For consistency, similar elements in several drawings will be quoted with the same numbers. In the following description, many details are presented to provide an understanding of several embodiments and/or features. However, it will be understood that with the general knowledge in this technical field, some embodiments can be implemented without many details, and many changes or adjustments from the described embodiments are feasible. As used here, the names "above" and "below", "above" and "below", "top" and "bottom", "upward" and "downward", and indicate above and below a given point or component Other similar names in the relative positions below are used in this description to more clearly describe specific embodiments.

The aspect expressed here is to provide LED solutions for lithography. This LED solution for lithography can provide frame diode modulation rates exceeding 1MHz when required, significantly exceeding the 20kHz maximum frame rate of the traditional micromirror system. In addition, the LED solution for lithography described here can provide incoherent illumination at 405 nm without interference that conflicts with the telecentric requirements of the projection system.

Although an exemplary system and method for LED solutions for lithography is proposed, those with ordinary knowledge in this technical field will understand that other feasible embodiments exist, and these embodiments are explained in the description provided here. Concept. In the example embodiment below, the specific method provided has simplified software requirements, in which the projected pattern for exposure on the substrate only needs to be calculated once, and the configuration described here is synchronized with the movement of the substrate to move the pattern Through LED array and hard-wired logic. Diffraction limited resolution and scale of each pixel The relationship between the inches makes it possible to precisely adjust the position of each pattern edge, and provides the use of resolution enhancement techniques, such as the establishment of auxiliary features to minimize rounded corners, and line truncation. ), and other proximity effects. The diffraction limit resolution and size of the pixel are defined by a single LED immersion element combined with accurate gray scale capability.

The method described here effectively couples the output of each LED to the substrate, and uses the output of each LED in a row to achieve the maximum exposure, which maximizes the exposure dose delivered by each diode. Although this configuration is capable of transmitting very precise gradual gray scales to the sub-pixels on the substrate, each diode system is completely turned on or completely turned off. For each diode, no complicated control circuit is needed to provide continuously variable output power.

Referring to FIG. 1, the lithography apparatus 101 is disclosed and has a platform 100, and the platform 100 supports a substrate 102. The substrate scanning system 104 is assembled to scan the substrate 102. The substrate scanning system 104 is assembled with several arrays of micro-light-emitting diodes 106. The individual micro-light-emitting diodes are automatically turned on and off in sequence to synchronize the movement of the substrate to transmit the exposure pattern from one end of the array to the other end. , And the exposure dose delivered by each sub-pixel is precisely controlled at the same time. The pattern generator 110 is also installed and connected to the computer 112. The system clock 116 synchronized with the scanning speed drives data to pass through the array of flip-flops 114. Each diode has an associated flip-flop logic circuit, and the logic state of the flip-flop logic circuit determines whether the individual micro light-emitting diodes are completely turned on or completely off. The rows of the diode are oriented in the scanning direction. Each row has one independently operated diode, two consecutively operated diodes, four consecutively operated diodes, 8 consecutively operated diodes, etc. to a total of 2 ⁿ -1, where n Will be an integer between 6 and 12. The hard line determines the sequence length of each group of diodes in a row.

As an illustrative example, suppose that a row contains 255 LEDs and is configured to include several groups of 1, 2, 4, 8, 16, 32, 64, and 128 diodes, two of each group The pole system is connected in order to operate. In order to provide the maximum possible exposure of the sub-pixels, a logic 1 must be sent to the first unconnected flip-flop, and after the first clock cycle, a logic 1 will be sent to the first flip-flop in the group 2 After the next two clock cycles, a logic 1 must be sent to the group of 4 flip-flops, and after the next 4 clock cycles, a logic 1 must be sent to the group of 8 flip-flops, etc. , Until a logic 1 is sent to the group of 128 flip-flops. This will generate accumulated exposure dose by 255 LEDs. By transmitting zero to replace the appropriate group of one to the flip-flop, it is possible to change the exposure dose from zero to 255 for each sub-pixel in the required exposure pattern. However, dealing with the delay between several inputs is tricky. Fortunately, this delay can be operated by a group of external flip-flops. The group of external flip-flops is driven by the same clock as the flip-flops included in the LED array. The purpose of the external flip-flop is to only delay the logic signal of the gray scale generated by the appropriate amount of time, so that the required synchronization between the exposure pattern and the substrate position is maintained.

In many cases, the substrate contains a pattern under the photoresist layer, and the next lithographic pattern must be accurately aligned with this pattern. The pattern is illuminated by a dark-field illuminator, which is surrounded by the objective lens The end is just above the substrate. The light diffracted from the characteristic edge on the substrate passes through the objective lens and back to the beam splitter, which is located just in front of the LED array where the camera is located. The pattern recognition software system is used to identify and calculate the position of the alignment mark currently on the substrate and the position of the target projected from the LED array to the substrate, and use this data to align the substrate in the subsequent exposure pattern. In the case where a single optical column can process the entire substrate in a reasonable length of time, as may be the case in integrated circuit IC packaging applications, two different assemblies are possible.

In one case, the optical column system remains fixed, and the substrate platform is designed to have sufficient degrees of freedom to provide substrate scanning, stepping, and angular orientation around a plane orthogonal to the substrate. The alternative is to provide a single-axis scanning capability in the substrate platform, and the ability to rotate the substrate in a small amount around an axis orthogonal to the plane of the substrate to align the pre-existing pattern in the scanning direction. If several columns are needed, due to time constraints, the best solution is to fix the optical column on the bridge so that it can step accurately orthogonal to the single scanning axis of the substrate platform.

In this case, not only is there no need to confirm that the image strips from each lens are seamlessly connected, but the last strip produced from one lens is seamlessly connected to the first strip of the image produced by adjacent lenses. No need to confirm. This system requires very small accumulated offset errors.

As an example, an array with several columns long enough to span the required field of view and several rows aligned in the scanning direction and a depth of 255 pixels will be described. If necessary, a high-bandwidth servo system is used to move the optical elements in the projection column to keep the position of the LED array fixed on the corresponding substrate position. The smallest The feature size is determined by the wavelength and numerical aperture (NA): (minimum feature=0.7 lambda/NA). Each minimum resolution feature is represented by a 3 x 3 array of LED pixels.

In the first approximation, the required exposure from a single pixel can be determined by covering the pixel grid on the required exposure pattern. The required gray scale is determined by the percentage of pixels covering the required exposure pattern. If the total exposure corresponds to exposure to 255 "on" pixels, and 60% of the pixels cover the required exposure pattern, then the required grayscale for the first approximation is (0.6)(255)=153 " On" pixels. Figure 7 shows the motion of the contour of the line edge when the intensity of the line defining the edge pixel increases from zero to the full exposure dose. For the first approximation, the value of the exposure threshold exceeding one level of the photoresist will be exposure.

Referring to Figure 2, the position of the line edge is provided by the first-order linear relationship and the exposure dose supplied by the pixels defining the line edge, and the line edge determines the edge position. In the example described, the exposure threshold is set to 50% of the maximum exposure dose (similar to the limit illustrated in Figure 7). This exposure threshold is consistent with chemically amplified resists that can be used. Grayscale systems provide good control over the position of edges, but square corners cannot be obtained because these systems require spatial frequencies far beyond the diffraction limit.

Compared with the traditional lithography system, the advantages of the proposed method and configuration are that the accurate exposure of the pixels in the pattern copied on the substrate only needs to be calculated once, and the hard-wired logic is synchronized with the scanning system to move this exposure The pattern crosses the entire substrate. The result is to simplify the underlying software and eliminate any pattern complexity that enhances the scanning speed limit.

Each pixel used in the system is a square emitter on a larger surrounding area. It also includes a logic flip-flop system and a power transistor, which can switch the LED on or off according to the logic state of the flip-flop.

This example provides a gray scale with an exposure range from 0 to 255 to generate each LED pixel on the target plane. In this case, the gray scale is stored in 8-byte groups, and its binary bits can be distributed to appropriate flip-flop strings included in the logic connected to the outside of each row. In other embodiments, rows of LEDs with lengths longer than 256 lengths selected as an example are feasible, for example, row lengths of 512, 1024, and 2048 are contemplated as non-limiting embodiments.

In essence, the configuration confirmed above the hard line greatly simplifies the software that needs to generate the projected pattern, because each pixel in each row only needs an 8-bit element, and because the pattern moves along the row, this is determined The state of all 255 pixels. Since each pixel on the LED moves synchronously with the corresponding point on the substrate, the calculation for proper exposure is performed once. Hard-wired logic ensures that the exposure dose for each pixel is provided appropriately. This assembly is efficient because the maximum exposure in the photoresist is produced by using each LED pixel in each row.

The micro LEDs are Lambertian emitters, which spread the light output at an angle of more than 180 degrees. Since efficiency is important to the overall system, it is only possible to capture light at an angle of 180 degrees to facilitate effective exposure of the photoresist layer by the lithography system. However, the immersion lens is arranged on top of each LED. This arrangement is reduced in two directions due to the refractive index of the immersion lens material In the emission angle, and also increase the appearance size of the LED by the same amount. In the exemplary embodiment, in the case where the 1.6 refractive index immersion lens array is arranged on top of the LED array, each LED is 6.25 square microns and separated from its nearest neighbor by 10 microns, the resulting output will be Shoots a continuous array that exceeds a cone angle of 77 degrees instead of a cone angle of 180 degrees.

The immersion lens system increases the total amount of light collected by 1.6 ² = 2.56 times. The higher refractive index of the immersion material is responsible for changing the emission angle. The lens on the top of the array preserves the gains achieved by the higher opacity and the transition back to air. In the exemplary embodiment, the LED emitting area only occupies 39% of the 10 by 10 micron area occupied by each LED. The remaining 61% can be used for other purposes, such as adding flip-flop logic and drive circuits. The light system output from adjacent LED pixels is not coherent (has an unstable phase relationship); therefore, there is no coherent interference effect and no grating effect between several pixels.

Figure 3 is a cross-sectional view (bottom part) through several LEDs and their individual immersion lenses. Although viewed from the top, the diodes are 10 square microns and densely stacked, there is ample space on the substrate to place the drivers and logic related to each LED.

In one embodiment, the logic of each column contained in the LED array and the related external logic are based on a series of clocked flip-flop circuits. This series of clocked flip-flop circuits are equipped with Remember 1 or 0 value. Each clock cycle causes the data stored in the flip-flop on the left to be transmitted to the flip-flop on the right when connected. The first flip-flop in a chain receives its input from the computer database. The brain database stores the required patterns to generate the required exposure patterns on the substrate. The logic state or bit flow along a single flip-flop chain and each successive clock cycle is shown in Figure 4. Since the clock cycle time is fixed, new and possible different states are provided to the flip-flops in the chain during each clock cycle. Each internal flip-flop is related to the individual micro light emitting diode, and this state determines whether the LED is turned on or off.

By measuring (in this example) the exposure dose of each of the 8 independent columns of LEDs in each row, an even higher degree of exposure dose correction can be achieved. This allows a simple computer program to produce a grayscale exposure that is closer to ideal anywhere in the entire grayscale range.

Failed LEDs can also be compensated by adding one or two additional LEDs and related flip-flops. However, each additional isolated flip-flop and LED combination system needs to add another character to the word group describing the gray scale.

In another exemplary embodiment, placing short flip-flops to link the start of the near scan reduces the number of flip-flops in the external logic chip to about half the number of LEDs in a row.

In the example where the scanning system needs to be bidirectional, the direction of the logic state is reversed, and the connection of the external and internal logic is changed. In this example, the previously described circuit is disabled, and a set of similar circuits is provided for scanning in the opposite direction. Figure 5 is a schematic diagram showing how the internal and external logic contained in an LED row can be configured to transmit the exposure pattern from one end of the LED array to the other end in synchronization with the movement of the substrate.

Typical arrays and design elements are illustrated and have appropriately defined attributes. In this typical array:

The above assumption can account for the 3 micron minimum feature spanned by the 3-LED pixel. The factor of pixel to minimum feature ratio of 3 is a conservative estimate of the required ratio to accurately locate the minimum feature and minimize the image smear caused by the moving substrate and the fixed LED array. In the illustrated embodiment, the maximum LED chip size is 26 by 33mm, which is the field of the stepping and scanning system. size). Depending on how many LED array chips are included in the illumination field, the target illumination field can also be a multiple of 26 by 33 mm. An example of a photo field containing two LED arrays of 26 by 33 mm is shown in Figure 6.

The number of LED configurations (chips) included in each target field can be selected based on economic considerations. In this example, the cost of the optical system increases with the square or cubic of the field, but the number of focusing and alignment systems required and the effort involved in testing and calibrating each optical system are saved. As an example, the system is modeled and includes 2 LED chips, each measuring 26 by 33 mm and obtaining a substrate illumination field of approximately 6.6 mm wide. In the scan direction. The positions of the two chips are staggered, so that the LED positions on each chip can be accurately abutted together after scanning, or even slightly overlapped.

The 26mm size of the proposed chip will carry a row containing as many as 2,600 LEDs. The closest number corresponding to 2 ⁿ -1 is 2,023=2 ¹¹ -1. This will shorten the size of the chip from 26mm to 20.23mm and increase the length of the block describing the gray scale to 11 bits.

By using the refractive index of the glass used to make the immersion lens, the immersion lens shown in Figure 3 changes the appearance size of each LED. Therefore, assuming that 1.6 is used as the refractive index of the glass array, the 6.26 square micrometer LED shows a 10 square micrometer LED. The cone angle of the shot is also from π steradian for Lambertian transmitter to π/(1.62)=1.227 steradian. Therefore, the net effect of the immersion lens is to reduce the total power required from the LED array and increase the proportion of that power delivered to the pupil of the optical relay. It is worth noting that the significant increase in the area of each LED from 6.25 square microns to 10 square microns is accurately offset by the reduction of the solid angle of the output radiation scattering. The total amount of radiation Pp from a single LED to the pupil is provided by the equation: Pp=(80W/cm ² )(.000625cm) ² (.0094) ² (1.6) ² =7.07 x 10 ^-9 Watts

When the magnification is -0.1, the pixel size area on the substrate is 1/100 of the pixel size on the LED array. The total power on the substrate from a single LED array is determined by the total number of pixels in the array (3,300 times 2,023) and therefore 0.04719 Watts. At the substrate, this power is distributed in an area of 2.023 times 3.3 mm or 0.0668 cm ² . The resulting intensity is 0.04719W/0.0668cm ² =0.707W/cm ² .

The exposure dose Ed is determined by the ratio of the length 1 of the diode array in the scanning direction to the scanning speed v times the power density: Ed=(1/v)(0.707W/cm ² )

The typical exposure dose used in flat panels is 30mJ/cm ² . Set Ed equal to this value and use equation (2) to solve for the scanning speed v to obtain: v=(0.707W/cm ² )(2.023cm)/(0.03Ws/cm ² )=47.7cm/s

If two LED arrays are used in each optical column, each of which is 3.3cm wide, the width of the pattern on the substrate is 6.6mm and each column can be exposed (0.66cm) (47.7cm/s)=31.5 cm ² /s. Each flat panel is 1.8m by 1.5m in area, and achieves a speed of 447.7cm/s and an acceleration of 1g, and then decelerates to zero at 1g. The acceleration/deceleration time is: acceleration and deceleration time=2(47.7cm /s)/(980cm/s ² )=0.0973s

Pattern exposure time=(180cm)/(47.7cm/s)=3.77s

Total time/time=3.77+0.0973=3.87s

If the total allotted time for the processing panel is one minute, and 15 seconds of the time includes loading/unloading and alignment, then 45 seconds can be used for exposure. During this period, each optical column can expose about 11 patterns, which are 7.26 cm wide. In order to expose a 1.5m wide panel, (150cm)/(7.26cm)=21 optical columns are required.

On the substrate plane, the scanning speed corresponding to 47.7cm/s and the clock frequency of 1 micron sub-pixel are (47.7x104 microns/s)/(1 micron)=477kHZ.

In the example where the pattern is accurately aligned with the pattern previously provided on the substrate, the substrate needs to be oriented to a fixed scanning direction very accurately, or several capabilities must be incorporated into the scanning system to change the scanning direction in a limited range and to change the scanning direction in the LED Corresponding correction in the orientation of the array, because each row in the array must be accurately aligned with the scanning direction. Another possible embodiment is to provide the ability for lateral displacement in each optical column by moving the lens or a small group of lenses laterally, or by moving the LED array laterally. The ability to have correction in each optical column provides the ability to correct local errors in the position of the pattern previously supplied to the substrate, including the distortion induced by the process in the substrate.

LED imaging system

The layout of a feasible imaging system capable of imaging two LED arrays is shown in Figure 6. The area of each LED array is 26 by 33 mm. This system has a magnification of -0.1, so that each of the 10μm ² pixels in the LED array is projected to 1μm ² on the LED. The 0.094 NA in the image plane is determined by the minimum feature size of 0.7λ divided by 3.0μm.

The large rectangular object system adjacent to the target plane is a possible position for the beam splitter to inspect the substrate. The performance of this system may be best represented by the Root Mean Square Optical Path Difference (RMS-OPD) and the field of view radius.

Since the "diffraction limit" is approximately 0.06λ, the optical correction system in this system far exceeds the diffraction limit in the entire spectral range from 399nm to 650nm. The exposure spectrum extending from 399 to 407nm is corrected to about 0.01λ RMS. The actual performance is most likely to be limited by manufacturing errors. This optical system is bi-telecentric, so that small changes in the position of the target and the image plane do not affect the magnification. Distortion may be the most severe aberration in most lithography systems.

The distortion in the exposed part of the spectrum (399-407nm) is essentially zero. The distortion in the 500-650nm spectral band applied for alignment is also zero to about half of the maximum field of view diameter. Therefore, providing alignment is done in the center of the field of view, and there should be no offset between exposure and alignment.

Referring to FIG. 8, a schematic diagram of an exemplary method 200 for performing a developing operation is presented. In this method, in step 202, the substrate is placed on the platform; the platform is assembled to move in at least one direction; in step 204, the lens in the projection system is positioned above the platform; and in step 206, an image is projected on the substrate and exposed to Substrate Several processes of the upper photoresist layer can be completed, wherein the patterned light beam projected from the projection system is generated by an array of micro light emitting diodes or several arrays of micro light emitting diodes.

Referring to FIG. 9, another example method 300 for performing lithography operations is presented. In this method, step 302 is to provide a substrate with a photoresist layer, and use light emitted from at least two arrays of micro light emitting diodes to perform exposure in step 304. In step 306, the micro light emitting diodes of the arrays The diode has individual micro-light-emitting diodes and a specific group of the individual micro-light-emitting diodes in the two arrays are exposed to the photoresist layer to form a pattern. According to the form of the photoresist, the exposed or unexposed part of the photoresist is then removed by the solvent in the subsequent developing operation.

In a non-limiting embodiment, a lithography apparatus is disclosed and includes a substrate scanning system assembled to scan a substrate; one or more arrays of micro-light emitting diodes are imaged onto the substrate by a imaging system , Where the hard-wired logic is incorporated in the micro-light-emitting diodes of one or more arrays, and assembled to switch a logic signal in a scanning direction and assembled to use the logic signal to switch individual micro-light-emitting diodes Completely open or completely closed.

In another non-limiting embodiment, the lithography device is assembled, in which the hard-wired logic in the micro light-emitting diodes connected to the one or more arrays is assembled to delay a gray scale related to a specific pattern element One of the logic signal applications.

In another non-limiting embodiment, the lithography device is further assembled to have an assembly to switch the configuration of the hard-wired logic. The hard-wired logic is assembled to delay the logic signal from reaching the hard-wired logic, and the hard-wired logic is combined in this OR Multiple arrays of micro light emitting diodes In the body, where the logic lies in scanning in a first or a second direction, it can be used.

In another non-limiting embodiment, the lithography device is further assembled and has an assembly to adjust the configuration of the hard-wired logic. The hard-wired logic is incorporated in the micro light-emitting diodes of the one or more arrays and assembled to switch The logic signal in a scanning direction causes the logic signal to switch to an opposite direction.

In another non-limiting embodiment, the lithography device is further equipped with a flip-flop circuit, equipped to store and transmit several logic states from one diode to the other, and delay the arrival of one of a logic signal .

In another non-limiting embodiment, the lithography device is further equipped with a system clock connected to each flip-flop, and one of the clock frequencies is directly related to the scanning speed.

In another non-limiting embodiment, the lithography device is assembled in which the hard-wired logic corresponding to each light-emitting diode in the array is merged with the light-emitting diodes in a space between the light-emitting diodes In the body substrate.

In another non-limiting embodiment, the lithography device is assembled in which the diodes in a ratio of 3:1 are cross-imaged on the substrate with a minimum feature size.

In another non-limiting embodiment, the lithography device is further equipped with an array of immersion lenses that optically contact the micro light emitting diodes of each array.

In another non-limiting embodiment, the lithography device is further equipped with an array of immersion lenses that optically contact the micro light emitting diodes of each array.

In another non-limiting embodiment, the lithography device is assembled, wherein the micro-light-emitting diode system of each array and a uniform distance between the micro-light-emitting diodes In a straight line, and aligned with the rows of micro light emitting diodes in each array aligned parallel to a scanning direction.

In another non-limiting embodiment, the lithography device is assembled, wherein the number of micro-luminescence diodes in the scanning direction is provided by an equation of m(2 ⁿ -1), where m and n are integers , And 2 ⁿ is the number of different gray levels that can be generated in a row.

In another non-limiting embodiment, the lithography device is assembled, wherein all the micro-light-emitting diodes in at least one of the one or more arrays are square.

In another non-limiting embodiment, the lithography device is assembled, wherein the number of interconnected micro light-emitting diodes in each row in one or more arrays is represented by an integer power including two.

In another non-limiting embodiment, the lithography device is further equipped with a detector array located in a focal plane of a substrate and assembled with 2 ⁿ light emitting diodes in each row of the micro light emitting diodes in each array An exposure dose produced by each group of the body can be measured.

In another non-limiting embodiment, the lithography device is further equipped with an imaging system, including a beam splitter and a camera. The camera inspects a pattern on a substrate produced in a previous lithography step and from a Or a plurality of arrays of micro-light-emitting diodes projected and reflected from an alignment pattern of the substrate; and a pattern recognition system to identify a specific pattern on the substrate and projected from the one or more arrays of micro-light-emitting diodes Align the patterns and measure their relative positions.

In another non-limiting embodiment, the lithography device is further equipped with a fixed optical column, including an imaging system; a platform, which accurately measures and moves freely in a scanning and transverse scanning directions; and a clamping The clamping piece is fixed on the platform, and the clamping piece can be used to rotate and attach the substrate in a small angle range; and an alignment position correction system to move the platform on which the substrate is fixed to a position, and the projected pattern is scanned During this period, the previous pattern included on the substrate will be aligned in this position.

In another non-limiting embodiment, the lithography device is further equipped with an optical column including an imaging system, the optical column is fixed on a bridge, and the bridge is assembled to move in the transverse scanning direction.

In another non-limiting embodiment, the lithography device is further assembled with a platform, which is assembled to move in a scanning direction; a clamping piece is fixed on the platform, and the clamping piece can be used to rotate and attach A small angular range of the substrate; and an alignment position correction system that moves the platform on which the substrate is fixed and the imaging system is fixed on a bridge to a position, and a pattern is projected in this position during scanning It is compliant with a previous pattern included on the substrate.

In another non-limiting embodiment, a method for performing micro-light-emitting diode lithography is disclosed and includes placing a substrate on a platform, the platform is assembled to support the substrate; aligning the substrate on the platform with a mark; Utilize at least one array of micro light emitting diodes to illuminate the substrate on the platform; and remove the substrate from the platform.

In another non-limiting embodiment, this method can be implemented, in which the irradiated substrate is through a hard-wired logic, which is incorporated in at least one array of micro-light-emitting diodes, and the logic is assembled to switch in One logic in one scan direction The signal and assembly use logic signals to convert individual micro light-emitting diodes to fully open or fully close.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: platform

101: Lithography equipment

102: substrate

104: substrate scanning system

106: micro light emitting diode

110: pattern generator

112: Computer

114: Flip-Flop

116: system clock

Claims (20)

A photolithography device includes: a substrate scanning system assembled to scan a substrate; and one or more arrays of micro light emitting diodes, which are imaged onto the substrate by an imaging system, in which hard-wired logic is integrated in The one or more arrays of micro light emitting diodes are assembled to switch a logic signal in a scanning direction, and assembled to use the logic signal to switch the individual micro light emitting diodes to fully open or completely close . The lithography device described in claim 1, wherein the hard-wired logic in the micro light-emitting diodes connected to the one or more arrays is assembled to delay the gray level of a specific pattern element One application of this logic signal. For example, the lithography device described in item 2 of the scope of patent application further includes: an assembly to switch the configuration of the hard-wired logic, the hard-wired logic is assembled to delay the logical signal from reaching the hard-wired logic, and the hard-wired logic is combined In the one or more arrays of micro light emitting diodes, the hard-wired logic can be used when scanning in a first or a second direction. The lithography device described in item 2 of the scope of patent application further includes: an assembly to adjust the configuration of the hard-wired logic, the hard-wired logic is incorporated in the one or more arrays of micro light-emitting diodes, and the assembly By switching the logic signal in the scanning direction, the logic signal is switched to an opposite direction. For example, the lithography device described in item 1 of the scope of patent application further includes: a flip-flop circuit, which is assembled to store and transmit a plurality of logic states from one micro-light emitting diode to the other, and delay the logic signal One arrived. The lithography device described in item 5 of the scope of the patent application further includes: a system clock connected to each of the flip-flop circuits, wherein a clock frequency is directly related to the scanning speed. The lithography device described in item 1 of the scope of patent application, wherein the hard-wired logic corresponding to each micro-light-emitting diode in the one or more arrays is merged in a space between the micro-light-emitting diodes In the substrate. The lithography device described in item 1 of the scope of patent application, wherein the micro light-emitting diodes in a ratio of 3:1 are cross-imaged on the substrate with a minimum feature size. The lithography equipment described in the first item of the scope of the patent application further includes: an array of immersion lenses, optically contacting each of the one or more arrays of micro light emitting diodes. The lithography device described in item 1 of the scope of patent application, wherein each of the one or more arrays of micro light emitting diode systems is aligned with a uniform distance between the micro light emitting diodes and parallel to the scan The micro light emitting diodes of each row in the one or more arrays aligned in the direction are aligned together. The lithography device described in item 10 of the scope of patent application, wherein the number of the micro light emitting diodes in the scanning direction is provided by an equation of m(2 ⁿ -1), where m and n are integers , And 2 ⁿ is the number of different gray levels that can be generated in a row. The lithography device described in item 1 of the scope of patent application, wherein all the micro-light-emitting diodes of at least one of the one or more arrays The system is square. According to the lithography device described in claim 1, wherein the number of interconnected micro light-emitting diodes in each row in the one or more arrays is represented by an integer power including 2. The lithography equipment described in the first item of the scope of patent application further includes: a detector array located in a focal plane of a substrate and assembled in each row of the micro light emitting diode of the one or more arrays An exposure dose produced by each group of 2 ⁿ micro-luminescence diodes can be measured. The lithography apparatus described in the first item of the scope of the patent application further includes: the imaging system includes a beam splitter and a camera, and the camera inspects a pattern on the substrate generated in a previous lithography step and An alignment pattern projected from the one or more arrays of micro light emitting diodes and reflected from the substrate; and a pattern recognition system that recognizes a specific pattern on the substrate and the micro light emission from the one or more arrays The alignment patterns projected by the diodes and their relative positions are measured. The lithography equipment described in item 15 of the scope of patent application further includes: a fixed optical column containing the imaging system; a platform that accurately measures and moves freely in the scanning direction and a cross-scanning direction; A clamping piece fixed on the platform, the clamping piece can be used to rotate and attach the substrate in a small angle range; and an alignment position correction system to move the platform on which the substrate is fixed to a position In this case, the projected alignment pattern will be aligned to the previous pattern included on the substrate in the position during scanning. The lithography apparatus described in the first item of the patent application further includes: an optical column including the imaging system, the optical column is fixed on a bridge, and the bridge is assembled to move in a transverse scanning direction. For example, the lithography equipment described in item 15 of the scope of the patent application further includes: a platform assembled to move in the scanning direction; a clamping piece fixed on the platform, the clamping piece can be used to rotate and attach A small angle range of the substrate; and an alignment position correction system that moves the platform on which the substrate is fixed and the imaging system is fixed on a bridge to a position, and the projected alignment pattern is scanned In the meantime, the position will be aligned with the previous pattern included on the substrate. A method for performing micro-luminescence diode lithography includes: placing a substrate on a platform that is assembled to support the substrate; aligning the substrate on the platform with a mark; using at least one array of micro-luminescence The diode irradiates the substrate on the platform; and removes the substrate from the platform. The method described in claim 19, wherein the irradiating the substrate is through a hard-wired logic, the hard-wired logic is incorporated in the at least one array of micro light-emitting diodes, and the hard-wired logic is assembled A logic signal in a scanning direction is switched and assembled to use the logic signal to switch the individual micro light emitting diodes to be completely open or completely closed.

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