TWI530986B - System and method for manufacturing three dimensional integrated circuit - Google Patents

Description

Method and system for lithography process of 3D stacked integrated circuit

The present invention relates to the manufacture of integrated circuits. In particular, the present invention relates to a system and method for fabricating a three-dimensional (3-D) integrated circuit.

This application is a continuation of the US Official Patent Application No. 12/475,114 filed on May 29, 2009, and claims the priority of the official patent application in accordance with Article 120 of the US Patent Law. The U.S. Patent Application Serial No. 12/475,114 claims priority to U.S. Patent Application Serial No. 12/337,504, filed on December 17, 2008, and the U.S. Patent Application Serial No. 12/337,504 claims 2008 The priority of the US Provisional Patent Application No. 61/099, 495, "Optical Imaging Writing System", filed on September 23, 2009. The present application also claims priority to U.S. Provisional Patent Application Serial No. 61/379,732, filed on Sep. 3, 2010. The entire disclosure of U.S. Patent Application is incorporated herein by reference.

Thanks to the rapid advancement of semiconductor integrated circuit (IC) technology, the process of dynamic matrix liquid crystal television (AMLCD TV) and computer display has made great progress. In recent years, the size of LCD TVs and computer monitors has been continuously enlarged, but the price has gradually become popular.

In the case of semiconductor ICs, each technology generation is defined by the critical dimensions (CD) in the circuit design rules. With the evolution of the technology generation, the target value of the key dimension of the new generation IC is gradually reduced, and the tolerance of error is more strict. In the case of flat panel displays (FPDs), however, each generation of technology is categorized according to the physical dimensions of the substrates used in the process. For example, FPD entered the sixth generation (G6), eighth generation (G8) and tenth generation (G10) in 2005, 2007 and 2009 respectively, and the corresponding substrate size (mm x mm) was 1500x1800, 2160x2460 respectively. And 2880x3080.

Whether it is a semiconductor IC or an FPD substrate, the challenge of the lithography process is how to increase the size of the product on the one hand and make the product more affordable on the other hand; but the process of the two is quite different. One of the major challenges in the IC industry is the formation of small critical dimensions on wafers 300 mm in diameter, with the goal of maximizing the number of transistors installed and enabling better performance of wafers of the same size. However, one of the major challenges in the FPD industry is to maximize the size of the rectangular substrate that can be processed, because the larger the FPD substrate that can be processed on the production line, the larger the TV or display that can be manufactured, and the lower the cost. In order to improve performance, LCD TVs and displays are generally designed with relatively complex thin film transistors (TFTs), but the critical size target values of TFTs remain within the same specifications. From a certain point of view, one of the main challenges of the FPD process is to provide reasonable cost-effectiveness in the unit time output of subsequent generations. One of the important considerations is that the process yield is at a profit level. At the same time maintain the appropriate process window.

Conventional lithography techniques for fabricating FPD have evolved from the lithography process for fabricating ICs. Most of the lithography exposure tools used in FPD substrates are step-wise and/or scanning projection systems, in which the projection ratio from the reticle to the substrate is two to one (reduced) and one to one. In order to project the reticle pattern onto the substrate, the reticle itself must be manufactured in accordance with acceptable critical dimensions. The mask process of the FPD is similar to that of the semiconductor IC, except that the size of the mask used to fabricate the semiconductor IC is about 150 mm (about 6 inches) per side, and the mask used to make the FPD is The size of each side can be about eight times the size of each of the aforementioned sides in one example, that is, more than one meter per side.

Please refer to FIG. 1a, which shows a conventional architecture of a projection exposure tool for scanning a reticle pattern onto an FPD substrate. The exposure source used in this architecture is primarily a high voltage short arc mercury (Hg) lamp. The incident illumination light is reflected by the mirror 102, passes through the mask 104 and the projection lens 106 in sequence, and finally reaches the FPD substrate 108. However, in order to perform the lithography process for the FPD of the new generation with the conventional mask-type exposure tool architecture shown in Fig. 1a, it is necessary to solve the problem of increasing the size of the reticle. Taking the eighth generation FPD as an example, the size of the mask is about 1080 mm x 1230 mm, and the area of the eighth generation substrate is four times. Since the critical dimensions of TFTs are in the range of 3 microns ± 10%, how to control the critical dimensions of TFTs on the eighth generation of substrates over two meters on each side is a challenge; compared to 300 mm in diameter. The lithography on the wafer is used to print advanced IC patterns and control their specifications. The former is more difficult. The problem that the FPD industry has to solve is how to construct a reticle exposure tool for the new generation FPD in a cost-effective manner while retaining acceptable lithography process capability limits (also known as process windows).

If one wants to reduce the inconsistency of key dimensions in the FPD exposure area, one of the methods is to use a multiple exposure method in which the nominal exposure is composed of a plurality of exposure components distributed in appropriate proportions, and each exposure component uses a preselected wavelength. The illumination is matched with the corresponding projection lens to complete the scanning and stepping. Such exposure tools must contain more than one projection lens, but only with a single illumination source, since a high output power short arc mercury lamp illumination source in kilowatts (KW) must be used. As for the way to select the exposure wavelength, a suitable filter is attached to the light source. In one example, this multi-wavelength exposure method can reduce the negative impact of critical dimension uniformity on the eighth generation substrate, so that relatively inexpensive lenses and illumination devices can be used.

When using multi-wavelength exposure, the critical size target value and critical dimension uniformity must be set for the mask itself. In one example, the critical dimension error tolerance of the TFT reticle is less than 100 nanometers, which is much less than the error tolerance required for the nominal target value of the reticle key size of 3 microns. This makes it easier to control the process window of the FPD lithography process for processes using the existing exposure tool architecture. However, the stricter requirements for the critical dimension specifications of the FPD reticle will make the mask set that was originally costly more expensive. In some cases, the cost of producing key masks for the eighth generation of FPDs is extremely high and the lead time is very long.

Another problem with conventional methods is that it is not easy to perform helium density control when using a large reticle. When using a large reticle for multiple exposure lithography, even if you start with a flawless reticle, you may end up with harmful flaws. If the process is flawed, not only will the yield be affected, but the cost of the mask will also increase.

Figure 1b depicts another architecture of a conventional exposure tool. As shown in FIG. 1b, the exposure tool includes a light source 110, a first projection lens 112, a reticle 114, a second projection lens 116, a wafer 118, and a wafer platform 120. The light source 110 can be controlled to pass light through the first projection lens 112 to the reticle 114, wherein the reticle contains a pattern to be imaged on the wafer 118. Part of the light will be blocked by the reticle 114, and some of the light will pass through the reticle 114 and penetrate the second projection lens 116, causing the wafer 118 to be exposed. Light passing through the reticle 114 will expose a particular area of the wafer 118, resulting in a set of pattern images corresponding to the IC design pattern formed on the reticle 122.

Please note that the wafer is fixed on the wafer platform 120, and the wafer platform can be moved under the control of the arrow in the direction indicated by the arrow. In a conventional stepping system, the light source 110 can be blue visible light or near ultraviolet light, and the first projection lens 112, the reticle 114 and the second projection lens 116 are fixed, and the wafer 118 and the crystal are fixed. The wafer platform 120 is movable to expose different areas of the wafer 118. This stepper system can be used to fabricate designs with resolutions of up to 1 to 3 microns, such as small-sized masks, light-emitting diodes (LEDs), and flat-panel displays from the fourth and earlier generations. In a conventional scanning system, the light source 110, the first projection lens 112, and the second projection lens 116 are fixed, and the reticle 114, the wafer 118, and the wafer platform 120 for fixing the wafer are movable. In order to expose different areas on the wafer 118. Compared to stepper systems, scanning systems are more efficient at handling large-size reticle and flat panel displays, but they are also more expensive. Scanning systems are mostly used to make flat-panel displays of the sixth or new generation of substrates.

Figures 1c to 1e illustrate various ways in which conventional exposure tools secure the reticle, and how conventional exposure tools align the reticle for exposure. In Fig. 1c, the reticle 130 is held in contact with the substrate wafer 132, so the system is generally referred to as a contact alignment system. In Fig. 1d, the reticle 130 is fixed adjacent to the substrate wafer 132, so the system is generally referred to as a proximity alignment system. Conventional contact alignment systems and proximity alignment systems are mostly used in the manufacture of printed circuit boards, touch panels (25 to 40 microns), light-emitting diodes (3 to 5 microns), and solar panels (>100 microns). Disadvantages of the contact alignment system and the proximity alignment system include the inability to process high resolution design patterns, warped wafers, or substrates larger than 4 inches.

FIG. 1e illustrates a conventional projection alignment system in which a projection lens 131 is further disposed between the reticle 130 and the substrate wafer 132. This system is mostly used to make circuits from 5 to 10 microns. Such a projection alignment system is more suitable for manufacturing a color filter of a flat panel display with a large-sized photomask, but a large-sized photomask is expensive. Therefore, if a higher mask cost cannot be accepted, it would be cost-effective to manufacture a printed circuit board and a light-emitting diode with a projection alignment system.

Figure 2 illustrates a conventional architecture for an exposure tool for fabricating a reticle. In this exposure tool architecture, illumination light 202 directed at beam splitter 204 will be partially reflected and passed through Fourier lens 208 to illuminate spatial light modulator (SLM) 206. After the imaged light is reflected, it passes through the Fourier lens 208, the beam splitter 204, the Fourier filter 210, and the reduction lens 212, and finally reaches the blank mask substrate 216. The mask data 214 is electronically transmitted to the spatial light modulator 206 to set the micromirror pixels. The reflected light produces a bright spot on the blank mask substrate 216, and a dark spot is formed on the blank mask substrate 216 where there is no reflected light. The reticle material pattern can be transferred to the blank reticle substrate 216 by controlling and arranging the reflected light.

Note that in this exposure tool architecture, the illumination path is flexed for vertical injection into the spatial light modulator. The curved illumination path and the exposure imaging path form a T-shape. In addition to using high-power illumination sources, such exposure systems must also use projection lenses with high reduction ratios to improve the accuracy and precision of reticle pattern writing. Basically, the lens reduction ratio is about 100 to 1. When using a projection lens with a high reduction ratio, the exposure area produced by a single spatial light modulator wafer is very small. The physical size of the spatial light modulator is about one centimeter, and after being reduced by a factor of 100, the write area of the spatial light modulator is about 100 microns. If you want to write a whole eighth-generation FPD mask with this extremely small write area, it takes a long time.

Another conventional method is to sequentially illuminate a spatial light modulator with multiple laser beams. This multi-beam is reflected by a single illumination laser source through a rotating polygon mirror. Multiple illumination beams can produce multiple exposures at specific times, thereby increasing the reticle write speed. In one example, it takes about 20 hours to write an eighth generation FPD reticle in this way. Due to the long write time, the cost of controlling the machine and maintaining its mechanical and electronic operations is also increased, which in turn increases the cost of its FPD reticle. If this exposure tool is applied to the FPD reticle of the tenth generation or newer generation, the manufacturing cost is likely to be higher.

In order to reduce the cost of the reticle when making a small number of prototypes, another conventional method uses an exposure tool architecture with a transparent spatial light modulator as a reticle. This method reads the reticle pattern into the spatial light modulator to visualize the desired reticle pattern so that a solid reticle is not required. In other words, the function of this transparent space light modulator can replace the physical mask, thereby saving the cost of the mask. As far as the architecture of the exposure tool is concerned, this method is basically the same as the reticle projection system. However, if compared with a solid reticle, the image quality of the spatial light modulator reticle is low and does not meet the pattern specifications of the FPD process.

U.S. Patent No. 6,906,779 (hereinafter referred to as the '779 patent) discloses another conventional method of manufacturing a display which utilizes a roll-to-roll process for simultaneous lithographic exposure of a mesh substrate. In short, the '779 patent exposes the reticle pattern onto a roll of substrate. Another conventional scrolling lithography process can be found in Se Hyun Ahn et al., "Hight-Speed Roll-to-Roll Nanoprinting on Flexible Plastic Substrate". Substrates)" ( Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim , " Advanced Materials ", 2008, 20, pp. 2044-2049) (hereinafter referred to as Ahn).

However, the two conventional methods described above are limited to a reticle of a predetermined size, and the reticle size is substantially limited to the size of the flexible display that can be manufactured. Another problem with the conventional methods described in the '759 patent and the Ahn article is that in order to achieve proper lithographic printing, the rolled substrate must be flattened during exposure. As a result, the flatness of the surface of the substrate will be inferior to that of a hard glass substrate used in general LCD TV screens. When such a reticle lithography technique is applied, the depth of focus (DOF) is limited due to the unevenness of the surface of the substrate. Therefore, it is difficult to form a TFT pattern having a critical dimension of 5 μm or less by the above-mentioned conventional methods. If the resolution of the TFT display is to be at a certain level, the critical dimension of the TFT mask should be about 3 microns.

The above-mentioned challenges that may arise in the manufacture of future generations of FPDs are due to the fact that the FPD industry does not need to reduce costs, and one of the main motivations is to make the process of the new generation products cost-effective. The lithography technology must maintain output efficiency on the one hand, and ensure that the product yield is improved from generation to generation. To achieve this goal, it is necessary to increase the process window of the lithography process and reduce the process 瑕疵 to accommodate the increasing number of FPD substrates. As mentioned above, the existing exposure tool architecture has many disadvantages, one of which is related to the use of the reticle, that is, the reticle size is too large, resulting in the manufacture of the reticle being inconsistent. As the size of the reticle is bound to continue to increase to meet the needs of future generations of FPD, this shortcoming will become more serious. Therefore, there is a need for an improved imaging writing system to solve many of the problems of conventional tools and methods.

The present invention relates to a variety of systems and methods for applying a reticle data pattern to a substrate in a lithography process. In one embodiment, an imaging system of the present invention includes a plurality of spatial light modulator (SLM) imaging units, wherein each SLM imaging unit includes one or more illumination sources, one or more alignment sources, one or more a projection light source and a plurality of micromirrors that project light from the one or more illumination sources to a corresponding one or more projection lenses. The imaging system further includes a controller for controlling the SLM imaging units, and the controller can respectively adjust the SLM imaging units by writing the reticle data into a lithography process of each of the SLM imaging units.

In another embodiment, a method of fabricating a three-dimensional integrated circuit includes the steps of: providing an imaging writing system having a plurality of SLM imaging units, wherein the SLM imaging units are arranged in one or more parallel arrays; receiving One or more reticle data to be written into the three-dimensional integrated circuit; processing the reticle data to form a plurality of partition reticle data patterns corresponding to the one or more layers in the three-dimensional integrated circuit; assigning one or more The SLM imaging units are responsible for processing the mask data patterns of the respective regions; and controlling the SLM imaging units to write the pattern of the mask masks in parallel to the one or more layers of the three-dimensional integrated circuit.

The step of assigning one or more SLM imaging units to process the mask data patterns of each partition includes at least one of the following: scaling the pattern of the mask mask data according to the SLM imaging units, wherein each of the partition masks The data pattern has a corresponding scaling correction action; according to the SLM imaging units, the alignment state correction is performed on the pattern mask data patterns, wherein each of the partition mask material patterns has a corresponding alignment state correction action; The SLM imaging unit performs a viewpoint spacing correction on the partition mask data patterns, wherein each of the partition mask data patterns has a corresponding viewpoint spacing correction action; according to the SLM imaging units, the partition mask data patterns are Performing a rotation factor correction, wherein each of the partition mask data patterns has a corresponding rotation factor correction action; and performing deformation correction of the substrate mask patterns according to the SLM imaging units, wherein each of the partition mask data patterns is There is a corresponding substrate deformation correction action. The step of controlling the SLM imaging units includes exposing each of the SLM imaging units with a corresponding partitioned mask data pattern independent of other SLM imaging units in the imaging writing system.

In another embodiment, a method of fabricating a plurality of design patterns in parallel on a printed circuit board (PCB) includes the steps of providing an imaging writing system having a plurality of SLM imaging units, wherein the SLM imaging units are Arranging into one or more parallel arrays; providing a printed circuit board having a plurality of regions divided, wherein each region includes a design pattern to be manufactured; receiving reticle data to be written into the plurality of regions of the printed circuit board; a mask material, wherein a plurality of patterned mask data patterns corresponding to the plurality of regions of the printed circuit board are formed; assigning one or more SLM imaging units to process each of the partition mask material patterns, wherein the assigning comprises performing at least the following One of: scaling correction, alignment state correction, viewpoint spacing correction, rotation factor correction, and substrate warpage correction; and controlling the SLM imaging units to write the pattern mask data patterns in parallel to the printed circuit board The plural area.

In another embodiment, a method of fabricating a partial wafer includes the steps of: providing an imaging writing system having a plurality of SLM imaging units, wherein the SLM imaging units are arranged in one or more parallel arrays; Or a plurality of wafers to be processed; receiving reticle data, wherein the reticle data is for writing to the substrate of the one or more partial wafers; processing the reticle data to form a plurality of zonal mask data patterns The partitioned mask data pattern corresponds to the substrate of the one or more partial wafers; assigning one or more SLM imaging units to process each of the partitioned mask data patterns, wherein the assigning comprises performing at least one of the following : scaling correction, alignment correction, viewpoint spacing correction, rotation factor correction, and substrate warpage correction; and controlling the SLM imaging units to write the partition mask data patterns in parallel to the one or more partial crystals Round substrate.

In another embodiment, a method of fabricating a plurality of light emitting diodes (LEDs) in parallel includes the steps of: providing an imaging writing system having a plurality of SLM imaging units, wherein the SLM imaging units are arranged in one or more Parallel arrays; providing one or more substrates corresponding to the LEDs to be manufactured; receiving reticle data, wherein the reticle data is for writing the one or more substrates corresponding to the LEDs; processing the reticle Data to form a plurality of partitioned mask data patterns corresponding to the one or more substrates of the LEDs; assigning one or more SLM imaging units to process the mask data patterns of the respective partitions; The SLM imaging units are controlled to write the patterned mask data patterns in parallel to the one or more substrates of the LEDs.

The step of processing the reticle data includes at least one of: processing the reticle data to form a plurality of zonal reticle data patterns, wherein the zonal reticle data patterns correspond to the one or more substrates of the LEDs And the same design; and processing the reticle data to form a plurality of zonal reticle data patterns, wherein the zonal reticle data patterns correspond to the one or more substrates of the LEDs, and are different designs . The step of controlling the SLM imaging unit includes at least one of: detecting a deformation condition of each local area on a substrate of each SLM imaging unit, and adjusting a focus of the corresponding SLM imaging unit according to a deformation condition of each partial area on each substrate; Detecting a rotation error of each local area on a substrate related to each SLM imaging unit, thereby determining a rotation correction factor corresponding to the partition mask data pattern, and applying the rotation correction factor to each partial region of each SLM imaging unit related substrate The mask mask data pattern is detected; and the pattern distortion caused by the deformation of the substrate in each local area on the substrate of each SLM imaging unit is detected, thereby determining the pattern correction factor of the corresponding mask mask data pattern, and applying the pattern correction factor A mask reticle data pattern corresponding to each partial region of each SLM imaging unit related substrate.

In another embodiment, a method of performing an automated optical inspection includes the steps of: providing an imaging writing system having a plurality of SLM imaging units, wherein the SLM imaging units are arranged in one or more parallel arrays; providing one or a plurality of patterned substrates to be inspected; dividing the one or more patterned substrates into a plurality of regions; receiving reference mask data corresponding to the one or more patterned substrates; processing the reference mask data to form a plurality of And zoning the reticle data pattern corresponding to the plurality of regions of the one or more patterned substrates; and acquiring, by the SLM imaging unit, the information of the plurality of regions of the one or more patterned substrates And comparing the information of the plurality of regions with the corresponding plurality of partition mask data patterns to generate inspection results; and storing the inspection results in a memory device.

The step of analyzing the information of the plurality of regions includes: checking whether the plurality of regions of the one or more patterned substrates are different from the corresponding plurality of partial mask mask patterns; and if the one or more patterned substrates are The difference is found in one or more regions, and the one or more regions are identified in the one or more patterned substrates for repair.

The step of checking the difference includes at least one of the following: using the corresponding plurality of partition mask data patterns as a reference object, and checking whether the plurality of regions of the one or more patterned substrates have a substrate pattern distortion, if the one or more The substrate pattern is distorted in one or more regions of the patterned substrate, the one or more regions are identified in the one or more patterned substrates for repair; and the plurality of patterned substrates are inspected Whether the region contains additional circuit components that should not be present on the substrate, and if one or more patterned circuit components are found in one or more regions of the one or more patterned substrates, the one or more patterned substrates Identifying the one or more regions for repair; checking whether the plurality of regions of the one or more patterned substrates are missing circuit elements that should appear on the substrate, if one of the one or more patterned substrates or Identifying the missing circuit component in the plurality of regions, identifying the one or more regions in the one or more patterned substrates for repair; and inspecting the one or more patterned substrates Whether the foreign particles are present in the plurality of regions and do not affect the pattern, and if the foreign particles are found in one or more regions of the one or more patterned substrates, the one or more of the one or more patterned substrates are identified Area for repair.

The method of performing an automated optical inspection further includes the steps of: recoating the substrate photoresist on the one or more regions identified as being repairable by the one or more patterned substrates; Performing reconstruction of the pattern on the one or more regions identified as being repaired by the patterned substrate; using the SLM imaging units, re-examining the one or more of the one or more patterned substrates is identified as The area to be repaired; and the results of the inspections are updated based on the information obtained from the re-inspection.

The method of performing an automated optical inspection further comprises the steps of: recoating the substrate photoresist on the plurality of regions of the one or more patterned substrates; performing on the plurality of regions of the one or more patterned substrates Reconstruction of the pattern; re-examining the plurality of regions of the one or more patterned substrates using the SLM imaging units; and updating the inspection results based on the information obtained from the re-examination.

The present invention provides a system and method for fabricating a three-dimensional (3-D) integrated circuit. The following description is made to enable those skilled in the art to make and use the invention. The descriptions of the specific embodiments and the manner of application are for illustrative purposes only, and those skilled in the art can readily appreciate various modifications and combinations of the examples. The basic principles described herein are also applicable to other embodiments and applications without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the examples described and illustrated herein, but the broadest scope of the principles and technical features described herein.

In the following detailed description, a portion of the content is presented through a flowchart, a logical block diagram, and other illustrations of information processing steps that can be performed in a computer system. In this document, any program, computer-executable steps, logic blocks and processes, etc., are a self-consistent sequence of one or more steps or instructions for the purpose of achieving a predetermined result. These steps refer to the steps of actually manipulating physical quantities, and the physical quantities include electrical, magnetic or radio signals that can be stored, transferred, combined, compared, and otherwise manipulated in a computer system. In this document, the signals are sometimes referred to as bits, values, elements, symbols, characters, terms, numbers, or the like. The performer of each step can be a hardware, a soft body, a firmware, or a combination of the above.

Embodiments of the present invention use a spatial projection device based on a spatial light modulator (SLM). There are two types of SLM image projection methods available, one is through a digital micromirror device (DMD), and the other is through a grating light valve (GLV) device. Both devices can be fabricated by MEMS. to make.

FIG. 3 illustrates an example of a digital micromirror device in accordance with an embodiment of the present invention. In this example, reference numeral 302 is a single DMD wafer, and reference numeral 304 is an enlarged simplified view of the DMD wafer. If you want to use the DMD as a spatial light modulator, tilt the micromirrors in the DMD to a fixed angle (mostly about ±10° or ±12°). DMD's micromirrors are extremely reflective against incident illumination. Each micromirror can be tilted (as indicated by reference numeral 306) by the underlying transistor controller or maintained at the original position (as indicated by reference numeral 308). In one embodiment, the distance between the DMDs can be about 14 microns, and the distance between the micromirrors can be about 1 micron. The number of pixels on a single DMD wafer can be 1920 x 1080 micromirror pixels, which is compatible with high definition television (HDTV) display specifications.

Figure 4 illustrates a DMD projection system in accordance with an embodiment of the present invention. In this example, the micromirror has three states: 1) a "start" state 402 with an inclination of about +10°; 2) a "flat" state 404 without tilting; and 3) a "closed" tilt angle of about -10°. State 406. In Fig. 4, the position of the light source 408 is at an angle of -20° to the DMD. When the light source emits a light beam, the micromirror in the "on" state (or "1" in the binary) will reflect the light beam. It passes directly through the projection lens 410, thus forming a bright spot on the display substrate. For the "flat" state and the "off" state (or "0" in the binary), the reflected beam will be deflected (the angles are about -20 ° and -40 ° respectively) and fall on the Outside the concentrating cone of the projection lens. In other words, the reflected light from the micromirrors of the latter two states does not pass through the projection lens 410, and therefore, a dark spot will be formed on the display substrate. Since the reflected light of the micromirror cannot be visually decomposed, we can combine a set of projected bright and dark points in appropriate proportions to form a gray scale. This method uses millions of shades of gray and color to project a realistic image.

Please note that the higher-order diffracted light from the "flat" state micromirror and the second-order diffracted light from the "off" state micromirror can still enter the concentrating cone of the projection lens and produce a flash that we are not happy with. , which reduces image contrast. In accordance with an embodiment of the present invention, a high intensity illumination source for precise aiming and focusing can be utilized to increase the diffraction efficiency of the pixels, thereby optimizing the projection optical design of the DMD imaging writing system.

According to other embodiments of the invention, GLV is another method of projecting images. The top layer of the GLV device is a linearly aligned layer of material, also known as a ribbon, which has excellent reflectivity. In one embodiment, the strip members may have a length of from 100 to 1000 microns, a width of from 1 to 10 microns, and a pitch of 0.5 microns. Basically, the GLV imaging mechanism utilizes a steerable dynamic diffraction grating that acts like a phase modulator. The GLV device can comprise a total of six strip-like elements that are alternately flexed to form a dynamic diffraction grating.

Fig. 5 is a cross-sectional view showing an example of a specular reflection state and a diffraction state of a GLV device in the embodiment of the present invention. When the GLV strip elements are coplanar (as indicated by reference numeral 502), the incident light will produce a specular reflection, i.e., the number of diffraction orders is zero. When the incident light strikes a set of alternatingly folded strip-like elements (as indicated by reference numeral 504), the intense ±1 order diffracted light and the weaker 0-order diffracted light will form a diffractive pattern. If one of the 0-level diffracted light and the ±1-level diffracted light is filtered out, a highly contrasted reflected image can be produced. In other words, if the objective lens recaptures all of the 0 or ±1 diffracted light, no image will be formed. The difference between GLV and DMD is that the entire image formed in the GLV field of view is constructed by scanning one by one, because the linearly arranged strip-shaped element grating can form a linear diffraction image at a time.

As can be seen from the related descriptions in Figures 1 and 2, in order to meet the production requirements per unit time, it is necessary to match the high-power illumination source used in the conventional system. In one example, a high pressure short arc mercury lamp having a power in the range of kilowatts is used, and in another example a high power excimer laser is used. Due to the use of high power illumination sources, the illumination path must be from a distance to reduce the heat generated and must be flexed to produce the appropriate illumination. This design divides the illumination system and the SLM imaging system into two separate units, and the optical path is perpendicular to the lens.

To overcome the limitations of conventional systems and methods, the improved exposure tool architecture of the present invention avoids the use of high power illumination sources. The present invention provides a collinear imaging system in which each imaging unit includes an SLM, an illumination source, an alignment source, an electronic controller, and an imaging lens. If the system uses a low-power light-emitting diode (LED) and a diode laser illumination source, the exposure processing amount per unit time is low, but if the number of imaging units is increased, the exposure processing amount per unit time can be increased. One advantage of using a small SLM imaging unit is that the units can be constructed into arrays of different sizes to facilitate different imaging applications. In an application example, more than 1000 of the above-described small SLM imaging units are arrayed, and the write processing amount per unit time is higher than that of the existing multi-wavelength photomask exposure tool architecture.

Figure 6 illustrates an example of a small SLM imaging unit in accordance with an embodiment of the present invention. In this example, the small SLM imaging unit includes a spatial light modulator 602, a set of micromirrors 604, one or more illumination sources 606, one or more alignment sources 608, and a projection lens 610. Illumination source 606 can employ a blue or near-ultraviolet LED or a diode laser having a wavelength of less than 450 nanometers. The alignment source 608 can employ a non-photochemical laser source or LED to penetrate the lens for focus and alignment adjustment. The projection lens 610 can employ a lens having a reduction ratio of 5X or 10X. As shown in FIG. 6, both the illumination source 606 and the alignment source 608 are located outside of the concentrating cone of the projection lens. In this embodiment, a commercially available lens having a numerical aperture NA of 0.25 and a resolution of about 1 micron can be used. A lower NA value ensures a better depth of focus (DOF). In a lithography process example, the target size of the photoresist is 1 micron and the lens NA is 0.25, which is greater than 5.0 microns. The resolution and depth of focus are calculated according to the Rayleigh criterion:

Minimum graph resolution = k ₁ (λ / NA)

Depth of field = k ₂ (λ/NA ² )

Where k ₁ and k ₂ are process capability factors and λ is the exposure wavelength. In an example of a lithography process using phenolic resin chemical photoresist, k _{1 is} between 0.5 and 0.7, and k ₂ is between 0.7 and 0.9.

To meet the small form factor requirements, the illumination source can be a blue light, a near-ultraviolet LED, or a semiconductor diode laser. In addition to achieving sufficient illumination intensity, one design example of the present invention uses multiple illumination sources that surround the SLM and are close to the SLM surface. The SLM can be a DMD or GLV with a suitable optical lens design. In one example, the target illumination intensity target value at the substrate is in the effective actinic exposure wavelength, up to 10 to 100 milliwatts per square centimeter.

In this example of an exposure tool architecture, the electronic control board housings of each small imaging system conform to a specified small form factor. For ventilation and heat dissipation, this enclosure is located on top of the SLM and away from the illumination source. The physical size of a single small SLM imaging unit depends on the imaging performance required and the commercially available components available, such as projection lenses, LED or diode laser illumination sources, and diode lasers for focusing/alignment, components Both must have their cooling space. Alternatively, custom components can be used to further reduce the form factor of the physical dimensions of a single SLM imaging unit. A custom SLM imaging unit with a 2D cross-sectional dimension as small as 5 cm x 5 cm; an SLM imaging unit consisting of commercially available off-the-shelf components with a 2D cross-sectional dimension of approximately 10 cm x 10 cm.

For the tenth generation FPD process, a typical substrate size is 2880 mm x 3130 mm. If a small SLM imaging unit is used, the entire system may contain hundreds of small SLM imaging units arranged in parallel arrays. FIG. 7 illustrates an example of a parallel array of SLM imaging units in accordance with an embodiment of the present invention. In this example, 600 to 2400 SLM imaging unit parallel arrays (702, 704, 706, 708, etc.) are simultaneously imaged for writing, and each parallel array may comprise a plurality of SLM imaging units.

According to an embodiment of the present invention, an example of a known unit time processing amount of an SLM mask writing system (for example, exposure of a 1300 mm x 1500 mm photomask for 20 hours) can be performed when calculating the exposure processing amount per unit time. As a starting point for calculation. The amount of processing per unit time depends on the illumination intensity of the plane in which the substrate is located. In this example, if the illumination intensity is 50 milliwatts per square centimeter (the LED or diode laser source can provide this illumination intensity), the nominal exposure energy is 30 millijoules per square centimeter - second, then the exposure time is About 0.6 seconds. In another example, the exposure tool is a high-power illumination source such that the illumination intensity at the substrate is at least 200 milliwatts per square centimeter; the unit time processing of the reticle step/scan system is approximately 50 wafers per hour. The eighth generation of FPD substrates. In one example, if both high-power and low-power illumination sources are taken into account, the estimated throughput per unit time is 25 to 100 substrates per hour, depending on the density of the SLM imaging units in each parallel array. The economics of this array of parallel exposure architectures have a competitive advantage.

Figure 8 is a plan view of a parallel array of SLM imaging units shown in Figure 7. In this example, each column or row may represent a parallel array of SLM imaging units, and each parallel array may include a plurality of SLM imaging units 802. The yield of the lithography process is closely related to the process window. In this case, the process window refers to a combination of the focus setting range and the exposure amount setting range that can be printed in accordance with the specifications of the specifications. In other words, the more flexible the process window is, the more relaxed the allowable out-of-focus setting and/or the exposure setting. Larger process windows help increase product yield. However, as the substrate size increases from generation to generation, the process window of the lithography process becomes smaller and smaller, mainly because the larger and thinner substrate materials are more likely to bend and sag. In order to solve this problem, the thickness and surface uniformity of the substrate material must be strictly regulated. In the case of a reticle type exposure tool, if the exposure area is larger than about two meters on one side, it is not only costly to maintain the uniformity and focus control of the whole area, but also technically difficult. The exposure tool must be able to perform partial and overall optimization of focus and illumination to implement the process window settings.

The parallel array exposure system shown in Figure 8 solves the above problem because each small SLM imaging unit can be locally optimized to produce optimal illumination and focus in its individual exposure areas. This ensures that the exposed areas of each SLM imaging unit have a better process window, and the optimization of each SLM imaging unit improves the overall process window.

Figure 9 is a comparison of a process window of a conventional single lens projection system with a partially optimized process window of an array imaging system in accordance with an embodiment of the present invention. The conventional single lens projection system 902 on the left side of Figure 9 must be adjusted to a compromise focal plane 904 as shown by the dotted line. The solid line 906 in the figure represents the actual cross-sectional shape of the substrate surface, the double-arrow line segment 908 represents the optimal focus setting range when the single lens is patterned, and the double-circle line segment 910 represents the maximum variation range of the substrate surface cross-sectional shape corresponding to each imaging lens. And the two dotted lines represent the upper and lower limits of the focus range, respectively.

As shown in Fig. 9, for the conventional single lens projection system, the bending amplitude of the large-sized substrate in the figure may have exceeded the focusing range of the lens, and the center point of the focus setting range may be barely applied to the peak of the curved section of the substrate. Department and Valley, thus limiting the overall process window. The improved projection system shown on the right side of Fig. 9 uses an array of imaging units, wherein the focus 914 of the imaging unit 912 can be individually adjusted for individual imaging zones, thus each focus setting range (e.g., double rounded line segment 916) All shown) are properly located within the upper and lower limits of the focus control. In addition to fine-tuning the focus of each imaging zone, each imaging unit can also adjust its illumination to make the illumination uniformity better than the single lens system to adjust the illumination. Therefore, the use of an array of imaging unit systems provides a better process window.

FIG. 10 illustrates a method for optimizing local unevenness of a substrate in an embodiment of the present invention. An area of uneven surface shape of the substrate has been detected in this example, as indicated by reference numeral 1002. A fine-tuning optimization method applies a focus averaging procedure to a local uneven exposure region corresponding to an SLM imaging unit and a region corresponding to the SLM imaging unit in the vicinity of the SLM imaging unit. The more imaging units that can be included in this averaging procedure near the uneven area, the better the overall optimization. Those skilled in the art will recognize that the imaging system of the present invention may also utilize other averaging techniques to improve image uniformity across the substrate.

In one embodiment, a thin film transistor (TFT) based liquid crystal display (LCD) uses the reticle data format described below. Please note that although we can use the hierarchical data stream format GDSII to deliver the mask data to the manufacturer, this mask data format may not be suitable for the parallel SLM imaging system of this case. If you want to flatten the hierarchical mask data, you can use the commercially available CAD software program, but the mask data needs to be further processed after it is flattened. The array parallel imaging writing system of this case can form a high quality image if it is matched with a suitable reticle data structure.

For the array parallel imaging writing system of the present case, after the reticle data structure is flattened, it needs to be divided into blocks of a predetermined size to be properly or evenly transmitted to each SLM imaging unit. The information in the reticle data structure not only specifies the placement of the reticle data blocks relative to their corresponding imaging units, but also how the images across multiple imaging units should be segmented. If it is desired to identify whether the data placement position has been fine-tuned, the related mask data structure of the adjacent mask data block corresponding to the adjacent imaging unit can be examined.

FIG. 11 is a diagram showing an application manner of a reticle data structure in an embodiment of the present invention. In this example, a hierarchical reticle profile containing a multilayer reticle data instance 1102 is first flattened to form a flattened reticle material 1104. The flattened reticle material 1104 is then divided into a plurality of partitioned reticle material patterns, wherein a portion of the reticle material pattern is represented by a shaded area 1106 in the figure. This shaded area 1106 also appears in the nine-square grid, which is divided by a dotted line below the 11th figure, and becomes the square in the center. There must be sufficient overlap of the reticle pattern between adjacent imaging units (ie, the horizontal and vertical strip portions 1108 in the figure) to ensure uniform patterning of the pattern around the border. Each of the squares in the nine squares represents a pattern of masked mask data that will be imaged by one or more SLM imaging units. According to an embodiment of the invention, the partition mask data comprises a first set of identification elements and a second set of identification elements, wherein the first set of identification elements is used to identify a state of excessive micro-mirror pixels in an SLM imaging unit (run-in conditions) And the second set of identification elements is used to identify the micro-mirror pixel-run state in an SLM imaging unit. If there are too many pixels in the area between the two SLM imaging units, it is a state in which the micromirror pixels are excessive; if there is insufficient pixel in the area between the two SLM imaging units, the micromirror pixels are insufficient. Each of the zone mask data patterns is transmitted to the corresponding SLM imaging unit for processing, and the associated sector mask material pattern is written by each SLM imaging unit into a predetermined overlapping area. Each SLM imaging unit is referenced to the adjacent SLM imaging unit at the time of writing, ensuring that the image fusion degree and uniformity conform to the design criteria. The masked mask data pattern can be optimized for parallel total exposure, thereby increasing the consistency of key dimensions of the image. The use of parallel plus total exposure reduces various process variables that are detrimental to critical dimensional consistency. When the total exposure is performed, if the number of exposures of the micromirror pixels is sufficient, Gaussian spots generated by using the diode laser can be removed.

Figure 12 illustrates a parallel array sum exposure method in accordance with an embodiment of the present invention. In this method, the mask data is first sent to each SLM imaging unit column by column, and then the array of micromirror pixels corresponding to each column of mask data is sequentially illuminated, starting from one end of each column of micromirror pixels, and the second illumination is performed. To the other end. In one example, the method begins at block 1201 by first illuminating one of its lowest row of micromirror pixels; then moving to block 1202, illuminating its penultimate column of micromirror pixels; then, in block 1203, illuminating Its third last column of micromirror pixels. The method continues to process blocks 1204, 1205, 1206, and 1207, and illuminates the corresponding columns of micromirror pixels, and then proceeds to block 1208 to illuminate the last column of micromirror pixels in the example (ie, one of the topmost mirrors of block 1208). Prime). The process of illuminating the micromirror pixels in a column by column will be repeated to complete the corresponding exposure operation, thereby writing the pattern to the substrate. Since the illuminating micromirror is very fast, the feature pattern can be exposed multiple times through the fast column-by-column illumination procedure until the nominal exposure is reached. In a word, this pattern writing process is formed by combining individual exposures of a plurality of micromirror pixels. We can use the same total exposure program and move the substrate platform at a coordinated speed and direction to complete the writing of the entire substrate.

The column-by-column loop mode shown in Fig. 12 is only an example. If the image forming unit is to sequentially perform local or detailed exposure in the parallel total exposure, other loop modes may be employed. In other embodiments, the row/column row/column can also be performed in a sequential manner to effectively complete the parallel total exposure. In addition, other methods of summing up may be developed, such as a program of column-by-column illumination by two adjacent SLM imaging units, or multiple columns of data as a starting column, respectively, in multiple directions, thereby increasing micro The effect of shadow printing, but may need to be further moved with the platform.

If the array parallel exposure method is used in mass production, a certain degree of redundancy or tolerance can be built in to prevent process interruption. In other words, once the exposure control routine detects a failure of an SLM imaging unit, the failed imaging unit will be turned off and its mask data will be reallocated to one or more adjacent imaging units for the adjacent The imaging unit completes the exposure task and finally removes the exposed substrate. This exposure correction process will continue until the entire batch of substrates has completed exposure. The entire process will continue until the imaging performance and throughput per unit time are acceptable.

Figure 13 is a diagram showing a method of forming redundancy in an image writing system in an embodiment of the present invention. In this example, imaging unit 212 is turned off as soon as it is found to be faulty. Among the eight adjacent imaging units, the imaging unit 212 may be replaced. In this case, the area originally occupied by the imaging unit 212 is not required to be written until the other areas are exposed.

If two adjacent SLM imaging units are image-distorted due to substrate warpage or sag, a micro-scale mismatch boundary (between local and local) will be formed between the two SLM imaging units. This mismatch boundary is indicated by reference numeral 1402 in Fig. 14, in which the data pattern is partially out of the frame line area, and the pattern fusion in the overlap area is optimized. Figure 14 illustrates a wedge boundary fusion method in accordance with an embodiment of the present invention. As shown in Fig. 14, this method turns on the micromirror pixels at the end of the selected boundary 1404, and the boundary end 1404 overlaps with the adjacent imaging unit write region 1406, so that the two regions match each other. Those skilled in the art should be able to understand that other methods can be used to selectively open the micromirror pixels at the desired location for boundary fusion purposes.

According to some embodiments of the present invention, the effect of fusion can also be achieved if the selected micromirror pixels between adjacent overlapping boundaries are turned on in an alternating or complementary manner. According to other embodiments of the present invention, if the pixel of the selected position is turned on when performing the total exposure program of the line-by-line illumination, the fusion effect is better.

In addition, in order to achieve the predetermined alignment accuracy of the array parallel imaging system of the present case, the method of the present invention sequentially divides the alignment program into a plurality of precision levels. The first alignment level emphasizes the overall alignment accuracy, while the next alignment level narrows the target to mid-level accuracy. The method of this case uses this bottom-up procedure to achieve the required level of precision.

In one example, there are three levels of accuracy: the placement of the unit lens, the fine adjustment of the lens center, and the manipulation of the micromirror imaging data. Figure 15 is a diagram showing a method of arranging SLM imaging units in an array in an embodiment of the present invention. This method can control the overall placement accuracy of a plurality of SLM imaging units 1502 within a few millimeters. The position of the projection lens assembly in each SLM imaging unit is then electronically adjusted to achieve micron-level accuracy. To achieve this, a laser (or other non-actinic alignment source) can be used to align the center of the lens to a known reference position on the platform. Finally, the micromirror is controlled to achieve the alignment accuracy of the nanometer level.

According to an embodiment of the invention, the exposure alignment program may comprise the following steps:

(1) Calibrate the lens centers of the SLM imaging units in the array using known reference locations on the platform. In this way, a set of mathematical array grid points can be established with reference to the solid lens array.

(2) When writing the first mask layer, since no alignment marks are printed on the substrate, the substrate is mechanically aligned and mainly relies on the accuracy of the platform.

(3) The substrate obtains alignment marks throughout the substrate via the previous mask layer, and such alignment marks can be detected by the corresponding SLM imaging unit. In this way, a grid map can be created with reference to the actual image position on the substrate.

(4) Compare the two grid maps (the grid map of the SLM imaging unit itself and the lithography alignment marker map measured from the substrate), and then establish a paired mathematical model that can guide the movement of the platform.

(5) In one example, an array of 2400 SLM imaging units is constructed for a tenth generation substrate, and the maximum horizontal (X) or vertical (Y) movement distance of the platform is about 120 mm, and the moving distance is also included. The calculation of the grid map pairing. Please note that the moving distance of this platform is very short. Therefore, compared with the reticle type exposure tool, when the 10th generation substrate is imaged, the moving distance of the platform must reach the full width and the full length of the substrate. The method of this case has technical advantages. . Due to the considerable weight of the tenth generation substrate, if the distance of the platform load is shortened, the accuracy of the system operation can be improved.

(6) In order to fine-tune the alignment accuracy to the sub-micron level, the method of the present invention incorporates the correction factor into the reticle data transmitted to the corresponding imaging unit. In other words, the correction factors of the imaging units may differ from each other depending on the relative positions of the imaging units on the substrate. In addition, the correction factor may vary with the substrate due to the different warpage conditions of the substrates. The bending condition of each substrate can be detected before exposure.

FIG. 16 is a diagram showing an example of a maskless image writing system for manufacturing a flexible display according to an embodiment of the present invention. As shown in FIG. 16, the reticle imaging writing system 1600 is comprised of one or more SLM imaging unit arrays, wherein a single SLM imaging unit is designated by reference numeral 1602. The one or more SLM imaging unit arrays can be formed into a particular shape, such as a circle, as desired for a particular application. In another embodiment, the matte imaging writing system can be used to fabricate a non-flexible display.

Figure 17 illustrates an SLM imaging unit in accordance with an embodiment of the present invention. The SLM imaging unit includes a blue and red diode laser 1702, an aperture 1704, a lens 1706, a spherical mirror 1708, a DMD 1710 mounted on a printed circuit board 1712, a beam dump 1714, a beam splitter 1716, Charge coupled device (CCD) camera 1718 and lens assembly 1720. The blue and red diode laser 1702 further includes a red laser diode (non-actinic) 1722 and four blue laser diodes (actinic) 1723, 1724, 1725 and 1726. The arrangement of the laser diodes can be as shown in Fig. 17. The red laser diode located in the center is non-actinic, mainly used for alignment or aiming at the initial focus setting. For the four actinic blue laser diodes, it is used for exposure. The number and arrangement of the laser diodes can also be designed differently depending on the package size of the laser diode, as long as the illumination intensity is uniform. In another example, the actinic illumination can also be transmitted using a fiber optic bundle. In this case, each laser diode system is irradiated to one end of the fiber bundle, and then the optical fiber is transmitted by the optical fiber to the other end of the fiber bundle to emit light. In other embodiments, the LED can also be substituted for the diode laser. With this design, multiple blue LEDs can be brought closer together to provide uniform illumination intensity, and multiple red LEDs can be placed separately for alignment and initial focus. In this example, the light emitted by the blue and red LED laser 1702 sequentially passes through the aperture 1704 and the lens 1706, then illuminates the spherical mirror 1708, and is reflected by the spherical mirror 1708 to the DMD 1710. The DMD can utilize its different states of micromirrors to reflect light directly to the beam collecting device 1714, or to illuminate the substrate via the lens assembly 1720. The image formed on the substrate will be reflected upward, through lens 1720 and beam splitter 1716, and finally to CCD camera 1718.

Figure 18 is a diagram showing a roll-type matte lithography method using a linear array of SLM imaging units in an embodiment of the present invention. In this example, the SLM imaging units 1802 are arranged in a single linear array, as shown in FIG. The substrate 1804 can be moved along the substrate moving direction (X direction) under the control of the person, and the linear array of the SLM imaging unit 1802 can be moved under the control of the substrate on the plane of the substrate 1804 along the plane perpendicular to the substrate. The direction of the direction (Y direction) moves back and forth. The exposure of the linear array of SLM imaging units can be adjusted to simultaneously process a particular area of substrate 1804 as the substrate is scrolled. In this way, the linear array of SLM imaging units can be controlled to image a substrate larger than the linear array of SLM imaging units. The image writing system shown in Fig. 18 can not only control the SLM imaging unit to move along the moving direction of the substrate, but also move it perpendicular to the moving direction of the substrate, so that the patent No. 779 and the Ahn article can be broken. The conventional method limits the size of the physical reticle.

Figure 19 is a diagram showing a scroll-type matte lithography method using a two-dimensional array of SLM imaging units in an embodiment of the present invention. Figure 19 depicts a two-dimensional array 1902 of SLM imaging units in a top view, with each circle representing an SLM imaging unit. Similar to the example shown in Fig. 18, the substrate 1904 in Fig. 19 can be moved in the X direction under the control of the human, and the two-dimensional array 1902 of the SLM imaging unit can be under the control of the substrate on the plane of the substrate 1904. Up, reciprocating in the Y direction. The exposure of the two-dimensional array of the SLM imaging unit can be adjusted to simultaneously process a specific area of the substrate 1904 as the substrate is rolled, so that the two-dimensional array of the SLM imaging unit can be controlled to be larger than the SLM imaging. Substrate imaging of a two-dimensional array of cells. Therefore, the image writing system shown in Fig. 19 can overcome the limitations of the physical mask size by the conventional methods described in the '759 patent and the Ahn article. Note that in some embodiments, the two-dimensional array of SLM imaging units can be arranged in an interlaced or non-interlaced manner.

FIG. 20 is a diagram showing a method for imaging a plurality of substrates of different sizes by using a maskless lithography method according to an embodiment of the invention. Similar to the method shown in Fig. 19, the image writing system of Fig. 20 also uses a two-dimensional array 2002 of SLM imaging units. The SLM imaging unit 2D array 2002 can automatically receive and process imaging data continuously under the control of ours. Therefore, if the imaging writing system seamlessly loads different TFT mask data, it can switch different substrate designs. In contrast, the conventional methods described in the '779 patent and the Ahn article must be discontinued in order to replace the different masks. In the example shown in FIG. 20, the substrate includes substrate design patterns of different sizes, as indicated by reference numerals 2006, 2008, 2010, 2012, and 2014, and the SLM imaging unit two-dimensional array 2002 can process the substrate immediately when the substrate is scrolled. Such as the substrate design pattern of different sizes.

Figure 21 is a diagram showing a method of positioning each SLM imaging unit according to a local condition of the surface of the substrate in the embodiment of the present invention. The method of this example is to examine the unevenness of the substrate surface 2104 during exposure and adjust the SLM imaging unit linear array 2102 accordingly. Fig. 21 shows the unevenness of the substrate 2104 in an exaggerated manner, thereby highlighting the advantage of the method of adjusting each SLM imaging unit to an optimum height. By adjusting the optimum height of each SLM imaging unit, the focus can be adjusted to the depth of focus required for a predetermined resolution critical size of 1 to 5 microns when autofocusing. The details of the method will be described later.

In one example, a TFT-based PV panel is printed for lithography, and the minimum footprint may exceed 50 microns. Within the scope of this lithography, we often see inkjet printing as a lower cost option. However, one of the main disadvantages of the inkjet printing method is that the ink mist droplets may cause defects, which is a side effect of the droplet ink flow. The inkjet printing method is not as clean as the lithography process, or it can be used for the lithographic printing reticle pattern, but it is not suitable to form the circuit driving line component; the inkjet printing method is mainly suitable for the information reading of the non-circuit driving line. take. When manufacturing active TFT components by reel lithography, the scalable SLM imaging cell array is still a better reticle-based lithography solution due to higher component yield. This method completes the maskless imaging by magnifying the projection; in detail, the exposure lens of the SLM imaging unit is not a reduction objective lens but an amplification objective lens, which can enlarge the product image size from 25 micrometers under the control of our own. To hundreds of microns.

One of the methods to monitor and adjust the focus of the SLM imaging unit during exposure is to maintain optimal focus throughout the substrate that is not necessarily absolutely flat. FIG. 22 illustrates a method for detecting pixel focus in an embodiment of the present invention. If you want to monitor the focus, you can use the lens-capable surveillance camera to capture the image in the exposure, then analyze the captured dark and dark pixel image and compare it with the expected exposure pattern to obtain a relative measure of the degree of defocus. The example shown in Fig. 22 is a pair of light and dark pixels (2202 and 2204) and their quasi-focus (2206 and 2208) and out-of-focus state (2210). In the transition pattern of the light and dark junction, the dark pixel of the alignment focus exhibits a relatively large contrast transition pattern, and the pair of off-focus dark and dark pixels exhibit a fuzzy transition pattern, wherein the degree of the blur transition can be mapped The degree of defocusing. In other examples, we can monitor and analyze the spatial frequency in an image. Since the focus error preferentially lowers the higher spatial frequency, after capturing the image, we only need to compare the loss of the high-frequency component in the image to evaluate the degree of defocus. Another method is to monitor and analyze the image contrast of a set of light and dark patterns, where the image with the best focus setting has the highest contrast and the loss of contrast corresponds to the degree of out of focus.

Although the above method can effectively monitor the size of the focus error, it cannot specify the direction of the error. In order to solve this problem, the system of the present invention can continuously change the focus position within a range centered on the target focus under the control of the software, and simultaneously update the position of the target focus to maintain the best focus state. We only need to balance the error between the two ends of the range, so that we can adjust to the best focus state sensitively, but it is best to avoid deliberately defocusing the exposed image. To achieve this, the focus of the camera can be disturbed in a controlled manner, but the focus of the exposure image is not changed; for example, if a surveillance camera with a penetrable lens is used, the effective optical path between the camera and the objective lens can be changed. In terms of the first-order approximation, changing the focal length of the lens on the camera side (f ₂ in the 23a diagram) is the same as the effect of changing the same ratio f ₁ . To cause this change in focus, the camera can be vibrated back and forth, or the image can be reflected by a vibrating mirror, or as shown in Figure 23a, the light can be passed through a turntable having a plurality of thicknesses and/or refractive indices. Different sectors of the sector create the desired changes in the effective path length. The above-mentioned turntable is the first optical path difference (OPD) modulator 2316 and the second OPD modulator 2326 in the drawing. In addition, the image can be reflected by a disk with a mirror having a plurality of sector portions of different heights.

FIG. 23a illustrates an example of an apparatus for instantly detecting the focus of an SLM imaging unit in an embodiment of the present invention. As shown in Figure 23a, the device includes an imaging source 2302, a beam splitter 2304, an objective lens 2306, and a housing 2308 of the objective lens 2306. One of the imaging light sources 2302, such as shown in FIG. 17, includes elements 1702 through 1714. The device also includes a first photographic sensor 2310 (hereinafter also referred to as a camera or sensor), a first motor 2312, a first refracting disk 2314, and a first OPD modulator 2316. The first OPD modulator 2316 can be formed by a circular optical device 2317 that can have a plurality of sectors (as indicated by reference numeral 2318). Each of the sector portions is made of a material having a different refractive index, or is made of a material having the same refractive index but different thicknesses, wherein the different thicknesses can form an optical path difference.

Another method of determining the direction of focus adjustment is to use two cameras to capture images at different path lengths, as shown in Figures 23b and 23c. 23b and 23c illustrate two other examples of devices that can instantly detect the focus of the SLM imaging unit in the embodiment of the present invention. In addition to the components shown in FIG. 23a, the two device examples further include a second photographic sensor 2322 (hereinafter also referred to as a camera or sensor) and a second OPD modulator 2326. Figure 23c also includes a third OPD modulator 2330. The configuration of the second and third OPD modulators 2326, 2330 can be similar to the first OPD modulator 2316. When the two photographic sensors 2310 and 2322 are used, the two OPD modulators 2316 and 2326 having different refractive indexes can be correspondingly arranged to determine the focus adjustment direction. In another embodiment, the implementation of the two different OPD modulators 2316 and 2326 merely sets the corresponding cameras 2310 and 2322 at different distances.

The examples shown in Figures 23b and 23c respectively examine the images of the first photographic sensor and the second photographic sensor, thereby comparing and analyzing the focus adjustment direction, and then adjusting the focus setting so that the two photographic sensors measure The degree of defocus is equal, so that the best focus state is determined by the optical path difference between the two photographic sensors. The first and second photographic sensors observe the substrate through complementary focus offsets to determine the direction of the target focus. Alternatively, the focus is not adjusted by moving the objective lens above, but the third OPD modulator 2330 is placed over the outer casing 2308 of the objective lens 2306 to adjust the focus by changing the effective optical path length.

The immediate monitoring and adjustment of focus includes the following steps:

1) Set the distance between the substrate surface and the objective lens within the focus range.

2) First, the image is imaged with non-photochemical illumination and the image is captured. This step does not cause any damage to the photosensitive material for exposure. In other words, the initial focus is set with non-optical illumination, and then the objective lens is adjusted to achieve the best focus.

3) Once the exposure platform starts moving in the moving direction (X direction) of the substrate, the actinic exposure is started.

4) Monitor the captured image under actinic illumination and adjust the objective lens.

5) Please note that each time the focus adjustment is based on the optimal exposure status of the above exposure position, but it is used for the next exposure position.

6) According to the optical path difference measurement of f1 and f2, determine the focusing amplitude of the objective lens.

As mentioned above, we can use one or more cameras to monitor the writing of images in real time during the exposure process. Each image pattern is exposed by a plurality of DMD micromirror pixels through a micromirror pixel total exposure method. This exposure method originally had a large focus error margin during the initial exposure phase because the exposure provided by each micromirror pixel is only a small fraction of the total exposure energy required; then, when performing pixel total exposure, The focus of each SLM imaging unit can be adjusted instantly. This focus error margin is especially important when writing a separate "hole" pattern surrounded by dark areas (as shown in Figure 24) or a separate "island" pattern surrounded by bright areas. The feature pattern lacks image change during the process of setting the disturbance focus of the person, so it is not easy to set the optimal focus state in the initial stage, and the optimal focus state can be determined after multiple exposures.

In another example, the aforementioned autofocus mechanism can be used for "focus plus exposure" to increase the overall depth of focus. FIG. 25 is a diagram showing a method for improving the depth of focus by a pixel total exposure method in an embodiment of the present invention. In the example shown in Figure 25, we can dynamically adjust the optimal exposure setting during the pixel total exposure, so that the pixel total exposure can be achieved through different optimal focus states in the depth of focus range. In this manner, the final image pattern is jointly exposed using a plurality of focus settings 2502, and the focus settings 2502 will also expand the overall final depth of focus 2504.

26a and 26b illustrate a method of joining adjacent imaging regions using overlapping regions in an embodiment of the present invention. Figure 26a shows two adjacent imaging regions 2602, 2606 and their corresponding SLMs 2604, 2608. The area between two adjacent imaging regions 2602 and 2606 is defined as an overlap region 2610. The imaging range of the SLM 2604 can span the theoretical boundary 2612 and extend to the user-defined boundary 2614 (dashed line) within the imaging zone 2606, while the imaging range of the SLM 2608 can also span the theoretical boundary 2612 and extend to another within the imaging zone 2602 The user customizes the border 2616 (dashed line). Since the overlap region 2610 is simultaneously encompassed within the imaging ranges of the SLMs 2604 and 2608, the method can utilize one of the two adjacent imaging regions to compensate for inconsistencies in another region, such as a mismatch in position or a difference in exposure. .

Figure 26b shows two other adjacent imaging regions 2622, 2626 and their corresponding SLMs 2624, 2628. In this example, the two SLMs and their corresponding imaging zones are horizontally set instead of the vertical settings as shown in Figure 26a. Although the orientation of the overlapping regions in Figures 26a and 26b is different, similar techniques can be applied. In other embodiments, the horizontal overlap region may be treated differently than the vertical overlap region. Similar to Fig. 26a, the region between two adjacent imaging regions 2622, 2626 is defined as an overlap region 2630, wherein the imaging range of the SLM 2624 can span the theoretical boundary 2632 and extend to a user-defined boundary 2634 within the imaging region 2626 (dashed line The imaging range of the SLM 2628 can also span the theoretical boundary 2632 and extend to another user-defined boundary 2636 (dashed line) within the imaging zone 2622.

If imaged within the overlap region 2630, the imaging intensities of the two SLMs 2624 and 2628 can be decremented toward each other. The fold line 2638 and the fold line 2639 (dashed line) schematically show the image intensities of the SLMs 2624 and 2628, respectively. In the overlap region 2630, the intensity of the SLM 2624 is ramped from full strength to zero, while the intensity of the SLM 2628 is ramped from zero to full strength. Note that in this example, a good imaging effect can be produced if the theoretical boundary is substantially aligned with the actual transition of the imaging zone (eg, the distance between the two is within 50 nm).

Automated Optical Inspection (AOI) can be applied to the fabrication of integrated circuits (ICs), printed circuit boards (PCBs), and flat panel displays (FPDs). In the current state of the art ultra-large integrated circuit (VLSI) process, the critical line width in its design specification has reached a fraction of the deep ultraviolet (DUV) exposure wavelength, about 193 nm. AOI is a key step in the manufacturing process to ensure the production yield of PCBs, FPDs and similar line-width electronic devices. For example, AOI can be used to check line widths, capture particles that are much smaller than the target line width, detect contamination on the substrate surface, and find missing, distorted, or redundant patterns.

AOI can determine whether a PCB meets product quality specifications in a variety of ways. The first method compares the image obtained by the AOI with the image of a known reference pattern (also known as the PCB Gold Reference Standard). The second method compares the captured image pattern with known and pre-stored good PCB images and inferior PCB images. The third method is derived from the second method and uses statistical pattern matching techniques. In detail, the comparison method of the third method includes a known gold reference standard and a plurality of inferior PCB images with different degrees of inequality, so that statistical determination can be performed under the condition that slight deviation is allowed.

For PCBs and electronic devices that use similar substrates and similar linewidth grades, the main purpose of AOI is to help users quickly determine the root cause of failures, so as to correct them early, avoiding the same problems with a large number of boards, and also quickly eliminate them. Unable to use the parts to ensure the overall quality of the product. Subject to cost, resource and time factors, if not for specific engineering purposes, PCB defects are rarely repaired. In general production lines, such products may be marked as obsolete.

In the case of FPDs and electronic devices using similar substrates and similar line width grades, the purpose of implementing AOI is also to perform various inspections such as detecting particles, contamination conditions, and pattern defects that should not occur. Among various types of patterns, mura (Japanese "plaque") refers to a beat interference pattern that is low in contrast but visually perceptible and affects visual effects. Other types of patterns include pattern missing, extra pattern, or both; all three of them cause pattern distortion.

The AOI's hardware mechanism can be configured differently when dealing with very large substrates. For example, a camera that is originally mounted on a fast-moving XY orbital platform in an overhead manner for scanning and capturing images of different positions of the substrate can be arranged in a row in a horizontal direction, and the manner in which the entire substrate is scanned is The substrate is moved horizontally in a direction perpendicular to the column camera and passes completely through the column camera from below. When the substrate is moved in a single-line axial manner, the moving speed can be kept consistent with the image capturing rate, and the position can be maintained within the focal length of the sub-camera. In addition, each camera can capture tens of thousands of scan line images, and each pixel line can have 8 bit pixels, other details will not be described in detail. In one example, a TFT color filter panel product having a line width of 8 to 10 microns can be inspected using a 7.5 micron camera. If the line width to be inspected is narrower, for example, to inspect a TFT array of 1 to 3 microns, a higher resolution camera can be used. In this case, the line width will be close to the illumination wavelength, so the algorithm for data volume and image processing must also be adjusted.

If a high-resolution panel product is used for visual communication, any visually visible defects will result in failure to ship. However, as the number of substrates required to manufacture new generations of products has grown, and the price of substrate materials has also increased, it is necessary for us to repair all panels that have been detected by AOI, rather than scrapping high-priced substrate materials. Therefore, 瑕疵 repair has become an important process step for FPD and similar electronic devices.

Taking the substrate of the tenth generation FPD as an example, a solution is to find the location of the crucible through the AOI, and then repair the pattern to remove the crucible. Due to the large size of the substrate, which can reach 2.88x3.08 meters, it is very difficult to repair it manually. It is best to automate the repair with a robot. We can set up robots to automate various flaw repair processes, such as removing surface foreign particles, removing unwanted patterns by laser etching or strong airflow, and locally depositing process-compatible films in sparse patterns to fill in missing areas. Part of the pattern. The above steps can all be performed by the software algorithm. The AOI can provide precise position, define the area to be repaired, identify the type of pattern (such as missing or redundant), and compare it with the predetermined reference pattern. Therefore, the problem to be dealt with later is how to get the missing pattern. And the distortion pattern in the excess pattern is used to reconstruct the desired pattern.

After the distortion pattern is found, if the reconstruction of the pattern is to be performed by the laser removal method and the local thin film deposition method, in the primary image processing, it is necessary to identify which portions of the pattern are missing and/or an unnecessary pattern is present. . To this end, an SLM imaging unit can be used to capture the image and correlate the captured image with the original mask pattern. In particular, image scanning can be performed using an array of SLM imaging units, but the SLM imaging units only capture pattern images without actually exposing. Alternatively, a single SLM imaging unit can be installed in an AOI system. After the AOI system completes the analysis of the 瑕疵 type and determines that it is necessary to perform subsequent 瑕疵 inspection and classification, the SLM imaging unit that commands the additional setting performs the above actions. In the left diagram of Figure 28c, element 2810 has been determined to be a 瑕疵, in particular, an extra pattern between two parallel rectangles 2812. In the right side of Figure 28c, 瑕疵2810 has been removed from the original reticle after being judged (indicated by the white area between the dashed lines).

In accordance with an embodiment of the present invention, another method of reconstructing a pattern after AOI utilizes an SLM imaging unit to repair the pattern in a localized area where defects occur without masking. This imaging method must be combined with partial or total recoating of the photoresist. If partial recoating is required, the photoresist is applied only to a portion of the area and is then developed. However, if there are multiple patterns on the substrate to be reconstructed, it is preferable to re-coat the entire substrate.

This method is similar to the lithography process of single-line axial movement, except that only the 瑕疵 pattern needs to be imaged again for the purpose of pattern reconstruction. This method can be re-patterned with a single SLM imaging unit or an SLM imaging unit array, the first step of which is to align the patterned regions, as in the SLM imaging unit. In the case of this partial imaging method, however, the alignment action is aligned with the previous mask layer, rather than the mask pattern being written in parallel as in the first lithography exposure. In detail, the pattern of the mask layer that has been etched is aligned when the pattern is reconstructed, and therefore, the aligned mask pattern may be different in appearance from the original mask pattern, depending on the process conditions actually experienced by it. set. When reconstructing the pattern, the process conditions must be taken into consideration to make the reconstructed pattern more closely match the surrounding pattern. In other words, the process correction factor must be included in the re-imaging, for example, to enlarge or reduce the reconstructed pattern area.

In Fig. 28d, the left side top pattern has been added with a known process correction factor, and the right side pattern shows the image alignment correlation of the 瑕疵 pattern, that is, the pattern actually seen at the position of the 瑕疵 and the previously captured 瑕疵 pattern. compared to. The small dark area 2820 located in the center of the right figure shows that the alignment is very high, so the position of the ( (ie, the position of the pattern reconstruction) can be accurately determined. After incorporating the process condition factor into the reconstructed image, a maskless exposure can be performed to complete the reconstruction of the partial pattern.

27a and 27b illustrate a method of measuring and using the viewpoint spacing between centers of adjacent SLM imaging units in an embodiment of the present invention. In the embodiment shown in Figure 27a, four SLMs in a row are used. Viewpoint Spacing (IOD) is the vector value distance between two adjacent SLM centers. For example, IOD-x is the distance between the centers of both SLM 2702 and SLM 2704; likewise, IOD-y is the distance between the centers of both SLM 2702 and SLM 2706. In Figure 27b, the entire imaging region is divided into a plurality of sub-regions in a grid, such as sub-regions 2708, 2710, 2712, and 2714. Each sub-region corresponds to an imaging region of an SLM. In this example, the viewpoint spacing between the two SLMs used to image subfields 2708 and 2710 is measured as IOD-x, and the viewpoint spacing between the two SLMs used to image subfields 2710 and 2714 is measured as IOD-y. . Once the IOD between the corresponding SLMs in the system is measured, the system can use this message to calibrate and generate mask data to control the exposure of each SLM in the system. Through the application of IOD, even if each SLM is not located in the center of its imaging area, the system can use the IOD to prepare the mask data to compensate for any alignment errors of the SLM in the system.

28a and 28b illustrate a method of measuring and correcting an alignment state of an imaging writing system in an embodiment of the present invention. In Figure 28a, part of the SLM is rotated, for example SLM 1 and SLM 3 are slightly turned to the right, SLM 5, 6, 8 are slightly turned to the left, and SLM imaging units 7, 9 are turned slightly to the right (all The magnitude of the rotation is exaggerated in the figure). These rotational errors can be detected and determined in conventional system settings or system maintenance operations. In this example, the rotation correction factor is measured as θ _SLM . Once the θ _SLM of each SLM in the system is measured, the system can use this information to calibrate and generate reticle data to control the exposure of each SLM in the system. Through the application of the rotation correction factor, even if the orientation of each SLM relative to its imaging area is not completely accurate, the system can use the rotation correction factor to prepare the reticle data, thereby compensating for any error in the orientation of the SLM. For example, SLM #7 2803's rotation correction factor for its imaging zone is measured as θ _SLM . When preparing the reticle data, the system incorporates these rotational correction factors and produces aligned reticle data 2804.

Figure 28b illustrates a pattern recognition isomorphic alignment method in an embodiment of the present invention. In this exemplary method, a plurality of predetermined patterns may be used as landmarks, and an image of the alignment target is captured based on the pattern recognition. For example, a plus sign (+) 2805 can be used along the edge of the imaging zone as the boundary identification. In addition, the existing design pattern (ie, E and F in the figure) 2807 may indicate the corners of the image area between adjacent SLMs. According to an embodiment of the invention, the SLM can simultaneously find an alignment target. Once the alignment target is used, the system can determine a set of correction factors, such as offset, rotation correction, and scaling factor. If there are enough additional alignment marks, the correction of nonlinear distortion (such as axis bending or keystone distortion) can be calculated. The system can generate reticle data to utilize the above-described correction factor to align the desired pattern 2808 with the actual measurement position of the alignment mark.

Over the past four decades, the design dimensions of complementary metal-oxide-semiconductor (CMOS) have been shrinking under Moore's Law, enabling IC component manufacturers to move within the same die area as component generations change. Add more and more versatile or transistor, while increasing the operating frequency of components and reducing overall wafer cost. But the economic benefits have finally reached the limit. As the technical difficulty of shrinking the CMOS size has become higher and higher, if the next generation of components smaller than 20 nm is to be manufactured, the capital investment required is not affordable to the general industry. As far as the lithography exposure tool is concerned, the expected upgrade cost may be expected by the industry leader. In order to achieve the goal of improving system efficiency and miniaturization in a lower cost manner, or in order to implement the concept of "beyond Moore's Law", the industry began to focus on system integration ten years ago instead of simply increasing the transistor density.

Recently, three-dimensional packaging technology realized through through-hole via (TSV) interconnection has provided a way to reduce the size of Moore's Law. Three-dimensional packaging technology makes heterogeneous integration feasible, enabling us to integrate components such as radio frequency (RF), logic, memory and MEM sensors in a space-constrained package. The three-dimensional packaging technology is different from the system single-chip (SOC) and the concept of "beyond Moore's Law"; the system single-chip system continuously increases the number of transistors in the two-dimensional wafer area, and the concept of "beyond Moore's Law" must Reduce the design size to the extreme. The capital investment threshold for 3D packaging technology is low, and the economic benefits are attractive for manufacturers of next-generation consumer devices such as smart mobile devices. In fact, the above devices have long been one of the main driving forces of 3D packaging technology. Driven by strong market demand, despite the global economic downturn, the industry has rapidly developed the various manufacturing tools, processes and technologies required for integrated packaging in 3D systems.

There are two types of three-dimensional packaging technology, one is called "three-dimensional 矽 (Si) integration", and the other is called "three-dimensional IC integration", both of which are based on 矽 through holes, but each has different levels of manufacturing difficulty. The three-dimensional germanium integration technology, also known as wafer bonding, provides better electrical performance and lower energy consumption. The height and weight of the product are also lower, and the output per unit time is higher.

Three-dimensional IC integration techniques can be used to increase the density of CMOS image sensors within digital cameras. To achieve this, three-dimensional IC interconnection technology can be used with the through hole. Memory-related applications can also use 3D stacking technology to reduce the footprint of the product while meeting the stringent requirements for increased memory density. 29a to 29d are diagrams showing a parallel manufacturing method of a three-dimensional integrated circuit without a mask in the embodiment of the present invention. Figure 29a shows three ways to form a through-hole, namely via-first, via-middle and via-last; as the name implies, the three represent 矽The via is formed before the IC is manufactured, during the manufacturing process, and after the fabrication is completed. In the example of Figure 29a, all three types of through-holes are shown in cross-section. Regardless of the type of through-hole (dark gray), the via pattern is first formed by lithography, and then a deep trench is etched on the germanium substrate, and a conductive metal such as copper is filled in the trench. . Then, the back surface of the substrate is polished to gradually thin the substrate, so that the through hole is exposed on the back surface of the substrate. In this way, the exposed vias can be directly connected to another wafer having a matching via design.

The design rules for the through hole are determined by "diameter/pitch" and "aspect ratio" (ie, the ratio of depth to diameter). In one example, the diameter/pitch ratio can be 50/250 microns and the aspect ratio is 5:1. In another example, the diameter/pitch ratio can be reduced to 10/100 micron with an aspect ratio of 10:1; or a diameter/pitch ratio of 5/50 microns with an aspect ratio of 16:1; or a diameter/pitch ratio It is 3/50 micron with an aspect ratio of 16:1; or a diameter/pitch ratio of 1/20 micron with an aspect ratio of 20:1. In terms of the lithography forming technique and the etching technique, the above diameter/pitch ratio is a reasonable range, but the deep trench coating technique is difficult to match the ratio. In order to provide a mature manufacturing process, it is necessary to improve existing development processes, such as improving the electrical reliability of through-hole forming technology, improving the handling of thin wafers with severe bending/warping, improving thermal energy management efficiency, and improving Test methods for stacking wafers, etc.

One method is to combine the tantalum via process with the semiconductor process. However, the grain yield may be negatively affected. For example, if a wafer with many good grains must be scrapped after the completion of the drilling process, the grain yield will be greatly affected. Another method is to bond directly to another wafer, but the other wafer may be designed by another manufacturer and is not necessarily fabricated by a compatible semiconductor process.

Yet another method is to fabricate IC wafers in a conventional process and independently test them to interconnect with other wafers. This method uses a passive interposer with a via hole and attaches the IC wafer to the interposer before packaging. The interposer may be a substrate material made of tantalum or glass, and its shape/size is similar to that of a wafer or a rectangular glass substrate. The role of the interposer is to carry an IC with a large number of output/input terminals and high-density routing lines (from the package to the PCB). Such a passive interposer is not provided with an active component and can be separately manufactured by a foundry or an external package.

Figure 29b is a cross-sectional view of an interposer embodiment in which an application specific integrated circuit (ASIC) logic die is placed adjacent to a dynamic random access memory (DRAM) wafer stack and bonded to the same passive interposer. Another type of through hole can be used between the memory chips of the DRAM stack.

If you want to form a pattern on the active interposer, even if the pattern of the via hole is formed on the IC device wafer, you can use the SLM array (Array of SLMs, hereinafter referred to as AOS) without the reticle direct imaging tool with the integrated component manufacturer. (IDM) or foundry has both exposure tools and exposures in a mix-n-match manner, with a certain level of output per unit time. In the process of drilling holes in the process, a mask step should be performed after the photomask layer of the transistor and the tungsten contact is disposed, and then a plurality of copper interconnects are formed to provide a larger pitch from the through hole to the through hole. An interconnect structure having a diameter of 3 to 5 microns is formed in the through hole. As for the post-drilling process, the wafer is thinned, the wafer is temporarily bonded to the carrier, and then the via is formed by etching from the back side of the wafer until etching to the barrier layer; The diameter of the holes is between 8 and 10 microns.

The third generation of double data rate synchronous dynamic random access memory (DDR3 DRAM) for mobile devices must be downsized and reduced in power consumption. In the case of a memory IC, a 10 to 50 micron thick coffin can be provided with a via having an aspect ratio (AR) of 5:1 to 10:1, and a copper interconnect is formed in the via hole by electroplating; In other words, the via diameter is 2 to 5 microns. This diameter range roughly corresponds to the diameter of the through hole that can be made by IDM and the foundry.

If you want to form a pattern of through-holes through a passive interposer, you can do it by the Sealing Foundry (OSAT). The final coffin target thickness of such an interposer can range from 100 to 140 microns. If the thickness of the interposer is reduced to less than 100 microns, the hard tantalum wafer will become a flexible tantalum foil. As far as the through hole diameter is concerned, if the aspect ratio is 5:1, the imaging target of the through hole diameter may be about 20 to 30 microns. An enamel interposer comprises a redistribution layer (RDL) composed of coated copper wires, wherein the line width and the pitch of the coated copper wires are respectively close to the diameter and the pitch of the corresponding 矽 via holes.

The above line width and diameter are all within the scope of the AOS maskless direct imaging capability at 405 nm exposure wavelength. The interposer can be used in a variety of ways, for example, through the interposer to enable previously obsolete components to be applied to boards that are difficult to redesign. If OSAT wants to compete with the foundry or IDM in the commercial application of the intermediation layer, it can provide rapid design, prototyping, and small-scale production of mass media, and rearrange it through the intermediation layer. The way of routing lines makes the complex substrate conform to the standard size; in addition, there are other related services. In performing the above operations, the AOS maskless direct imaging technology of this case provides a fast transition, which is unmatched by conventional mask-type exposure tools (including stepper systems and mask alignment systems).

The AOS reticle direct imaging system of the present invention provides a proper alignment function when handling ultra-thin substrates with deformed defects such as bending and warping. Through the method disclosed herein, the AOS maskless direct imaging system of the present invention can efficiently "stretch" the mask material to match the existing substrate pattern for local alignment. The conventional reticle lithography technology does not have this function.

In another method, the AOS maskless direct imaging system of the present invention is used to form a pupil via pattern on an active enamel interposer. In order to optimize the thermal and electrical properties of the 3D IC integrated components, or to be in the research or development stage, or in the split design for different application purposes for the same wafer, the through holes are on the active die. The setup method is for experimental design (DOE). The AOS reticle direct imaging system of this case can achieve this purpose efficiently, so there is no need to order any reticle for this purpose.

Figure 29c is a configuration diagram of a two-dimensional integrated circuit. As shown in this example, each block (ie, A, B, C, D, E, F, G) in the configuration diagram represents a portion of the integrated circuit and its corresponding area on a wafer. The line segments extending between blocks A and C, between blocks A and E, and between blocks C and G represent the routing lines required for the blocks to communicate with each other, respectively. Those skilled in the art will appreciate that in an integrated circuit with billions of transistors, the routing of communication signals between blocks is very complicated, and the design is very difficult. The problems involved include resistance-capacitor delay effects. Crosstalk interference, energy consumption and form factor all have a direct impact on the cost of the integrated circuit.

The system and method disclosed in the present invention can solve the design problem of the system single chip in the figure 29c, especially for the three-dimensional bonding of the die to the die, the die to the wafer, and the wafer to the wafer, so as to be more effective. The method of manufacturing a three-dimensional integrated circuit. As shown in Fig. 29d, the integrated circuits can be arranged in three dimensions, thereby greatly shortening the routing length of communication signals between the blocks. In this example, blocks A and C are located in the first layer of the integrated circuit, and blocks B, D, E, F, and G are located in the second layer of the integrated circuit. It will be apparent to those skilled in the art that the number of layers in the integrated circuit can be more than two layers to achieve the specific design and cost objectives of the integrated circuit. Extending between blocks A and E, between blocks A and D, between blocks A and F, between blocks C and B, between blocks C and F, and between blocks C and G The vertical line represents the communication signal routing between different layer blocks in the integrated circuit. Since these routing lines are arranged in three dimensions, their length has been greatly shortened. In other embodiments, the analog circuit and the digital circuit can be separated into different layers of the three-dimensional integrated circuit. In other embodiments, the power and ground planes of the circuit can also be divided into different layers of the three-dimensional integrated circuit.

If a three-dimensional integrated circuit is fabricated by a conventional method, a reticle is required for each layer of the integrated circuit, but it is often necessary to perform multiple iterations in the design process to meet design standards of functions, performance, and cost. In other words, in the design and verification process, the reticle corresponding to each layer of the integrated circuit may need to be modified, thereby increasing the development cost and development time of the integrated circuit. However, if the imaging writing system of the present invention is used, the formation of the circuit design patterns of the layers does not require the use of a photomask. In addition, if the multi-wafer direct imaging method of the imaging writing system of the present invention is employed, the plurality of layers in the integrated circuit can be manufactured in parallel, thereby reducing the development cost of the integrated circuit and shortening the development time.

According to an embodiment of the present invention, the image writing system of the present invention can be used for the "first drilling" process of the through hole to facilitate the bonding of the three-dimensional integrated circuit chip. The maskless method of the present invention can replace the conventional filling step using a photomask, which is the second step in the processing step (process 1) before the front end processing (FEOL), or the processing step after the front stage processing. The third step in (Step 2). Similarly, the image writing system of the present invention can be used for the "post-drilling" process of the through-holes to facilitate the bonding of the three-dimensional integrated circuit chips. The maskless method of the present invention can replace the conventional filling step using a photomask, which is the third step in the processing step (step 3) before the BEOL process, or the processing step after the post-stage process. The fifth step in (Step 4).

Please note that since the through-hole reticle pattern of the through-hole is mostly of a critical dimension different from that of other reticle patterns, the flexibility of the reticle-free method in this case can be of great benefit, because the conventional method is used. The economics of making through-hole mask patterns with state-of-the-art exposure tools is very low. In contrast, the use of state-of-the-art exposure tools to form a mask layer in the front-end process is economical. As mentioned above, the imaging writing system of the present invention can perform scaling correction, viewpoint spacing correction and rotation factor correction in the imaging process, thereby reducing product development costs and shortening product development time.

Figure 30 is a diagram showing a multi-wafer direct imaging method in an embodiment of the present invention. In the example shown in FIG. 30, a 3x6 SLM array is used to parallelize two wafers having a diameter of 300 mm, wherein the first wafer 3002 can be imaged by a first set of 3x3 SLM arrays, and the second wafer 3004 can be second. Group 3x3 SLM array imaging. Through this method, each wafer may comprise different design patterns or different layers of a three-dimensional integrated circuit. In addition, each SLM can be imaged for different types of vias. Furthermore, each SLM can be used to perform different image stitching operations, scaling corrections, viewpoint spacing corrections, and rotation factor corrections.

According to an embodiment of the invention, the SLM array of the present invention can process a plurality of wafers in parallel. For example, a 3x3 SLM array can image nine 2-inch wafers without image bonding. Each of the two wafers is directly imaged by a corresponding SLM, and the imaging writing system of the present invention can control each The SLM is used to expose nine wafers in parallel. Similar to the example in Figure 30, each SLM can also perform different image stitching operations, scaling corrections, viewpoint spacing corrections, and rotation factor corrections. In another method, a 3x3 SLM array can be used to image nine 2吋 PCBs, each PCB is directly imaged by a corresponding SLM, and the imaging writing system of the present invention can control each SLM to make the nine PCBs parallel. exposure. As will be appreciated by those skilled in the art, the SLM array can be adapted to different manufacturing needs, for example, a 4x6, 5x5 or 12x12 SLM array can be used for a plurality of correspondingly arranged 2 turns of wafer or PCB parallel imaging.

In the example shown in Figure 30, the AOS reticle direct imaging system can be arranged in a plurality of 300 mm wafer or rectangular interposer substrates (which can be used for active or passive 矽 through-hole interposer) exposure. In the case of an active interposer, the wafer loading can be designed to be compatible with a reticle exposure system. In the case of a rectangular interposer substrate, since the resolution and alignment accuracy are low, it can be manually loaded in addition to being automatically loaded by the machine. Such an AOS exposure system can load more than one wafer or substrate on the same exposure platform for simultaneous scanning exposure, depending on the amount of output per unit time required. The example shown in Figure 30 is a parallel exposure of two wafers.

During wafer loading, the orientation of the wafer must be identified before loading the wafer at the specified location. Each SLM can independently perform the function of "area alignment" for its corresponding exposure area. Once the under-alignment correction factor for each region is calculated, it can be applied to the reticle data corresponding to each SLM. Please note that the use of this method does not require precise pre-alignment operations for each wafer, as long as each alignment target is within the field of view of the corresponding alignment camera, or within a few square millimeters. . However, since the reticle data of each SLM imaging unit can be individually subjected to under-alignment correction, alignment correction can be performed subsequently. Through the above functions, the AOS maskless direct imaging system of this case can expose a plurality of wafers. In the process of AOS exposure for multiple wafers, all substrates are on the same exposure platform, so AOS can perform physical scanning by orientation and distance. Since the reticle data containing the correction factor can be applied to each SLM separately before exposure, the resulting wafer pattern is the same as that formed by a single physical reticle. Figure 28b is an illustration of the method. As shown in Figure 28b, we can perform regional alignment correction for the reticle data corresponding to each SLM imaging unit in the same wafer. In addition, two different wafers may have different pre-alignment errors, such as the pre-alignment error of the first wafer is (θ _x1 , θ _y1 ), and the pre-alignment error of the second wafer is (θ _x2 , θ _y2 The two errors can be corrected separately and then applied to the mask data to correct the mask data. Please note that we can also use a similar method to expose AOS to a rectangular substrate and control and apply correction factors as needed. The reticle data corresponding to each SLM imaging unit can also receive regional alignment corrections.

The booming high-brightness LED (HB-LED) market is benefited from backlighting applications for a variety of displays, including handheld devices, televisions, computer monitors, and advertising billboards. One way to reduce the cost of manufacturing LED chips is to use larger wafers, such as wafers from 2 to 6 to 6 to 6 wafers. However, the high-brightness LED epitaxial wafer process is different from the germanium-based IC process. The former is made of sapphire or tantalum carbide, and then deposited by metal organic chemical vapor deposition (MOCVD). film. Gallium nitride is a hardband semiconductor material that is hard, mechanically stable, has high heat capacity, and has high thermal conductivity. The lattice constant of gallium nitride does not match sapphire or tantalum carbide. Although the gallium nitride film deposited on the substrate has crack resistance, the wafer is seriously warped and bent, and the larger the substrate size, the more serious the problem of wafer warpage. For example, a gallium nitride film on a 2 吋 sapphire wafer can cause warpage and bending of the wafer by 20 to 25 microns, and a gallium nitride film on a 4 Å sapphire wafer can cause warpage of the wafer to be more than 100 microns. And bending, as for 6-inch wafers, the flatness range often exceeds 250 microns. In contrast, the flatness range of a 6-inch epitaxial wafer may be only a few microns. Therefore, the above problems are a big challenge when increasing the wafer of high-brightness LEDs.

The current mainstream wafer size for manufacturing LED chips is 2吋. If a wafer for LED wafers with a diameter greater than 2 turns is to be fabricated in a cost-effective manner using a lithography process, the lithographic tools used must not only have the necessary resolution but also have sufficient depth of focus. This depth of focus must at least cover the typical warpage and bending amplitude of the sapphire wafer with the gallium nitride film in each exposure range. In the case of poor wafer flatness, whether the alignment between layers is high enough is also an important consideration. Therefore, conventional contact alignment systems are not suitable for fabricating wafers larger than 2 Å for use with high brightness LED wafers.

Figure 31 illustrates a maskless scanning exposure system in accordance with an embodiment of the present invention. As shown in Fig. 31, the exposure range of the system is small, so that the focus can be tracked in a more flexible manner according to the surface condition of the substrate for scanning exposure. This system is also highly tolerant of severely warped and curved sapphire wafers.

Please note that such a maskless scanning exposure system can be arranged in an array to separately scan for a plurality of wafers on the same platform. Alternatively, such a maskless scanning exposure system can be arranged in a mutual engagement, and a large size wafer is exposed in parallel.

If you want to scan and scan multiple wafers on the same platform, you must first place all the wafers in individual positions. At this time, each wafer will have a unique rotation error. After a rough pre-alignment step in the wafer loading process, the above-mentioned rotation error can be adjusted to a preset limit. Then, if you want to expose the mask without alignment, you must scan the alignment marks on each wafer (as shown in Figure 28b) to determine the actual pattern range.

In addition to the pattern rotation (as shown in Figure 28a), each wafer may also become warped or bent due to the apparent mismatch of lattice constants in each heat treatment cycle, resulting in pattern shift or distortion. Each of the maskless scanning exposure units (ie, the SLM imaging unit) can independently determine the pattern correction factor of the mask data, and apply the pattern correction factors to the mask data corresponding to each SLM imaging unit.

As mentioned above, a linear array of SLM arrays (AOS) can simultaneously perform a maskless scanning exposure in parallel on the same platform. To this end, each SLM in the SLM array has the same reticle data, but the reticle data for each SLM contains a unique set of correction factors corresponding to the wafer to be exposed. In another example, an SLM array comprising two SLMs can process the same wafer, wherein the steps of wafer mapping and mask data correction are substantially the same, except that the two SLM imaging units are identical here. Wafer exposure.

The AOS maskless scanning exposure system of the present invention has many advantages, which not only can track the focus with the substrate surface in a more efficient manner, but also apply different mask correction patterns to the wafers to be exposed. In addition, since the system can simultaneously expose a plurality of wafers in parallel, the throughput per unit time of the manufacturing system is multiplied by the number of wafers simultaneously exposed, and the correction of the mask pattern of each wafer is not affected therebetween. Please note that in the process of loading the wafer on the exposure platform, the AOS maskless scanning exposure system of this case is quite tolerant to the pre-alignment error, which can be within a few millimeters, or in each SLM imaging unit. The image of the camera is aligned within the limits of the image capture. It is best to use the robot's wafer loading and unloading mechanism, but if necessary, a skilled operator can manually load the wafer to perform AOS maskless scanning exposure.

In one method, the SLM array of the present invention can be parallel imaging of a plurality of patterned sapphire substrate (PSS) light emitting diodes (LEDs). Since each SLM can expose a PSS LED wafer, the throughput per unit time is very high. For example, if a 5x5 SLM array is used and the exposure time per PSS LED is one minute, then 25 wafer exposures per minute can be achieved, ie 1500 wafers per hour. These unit time outputs exceed the level at which the PSS LEDs are manufactured using conventional exposure tools. Please note that the above PSS LED process tends to subject the wafer to high stress, which in turn causes the substrate to warp significantly; typically, the warpage of each wafer is about 100 microns. In addition, each batch of wafers may have different substrate warpage characteristics, which is difficult to handle in the process if using conventional exposure tools, because conventional proximity alignment systems are not suitable for handling warpage. The substrate, while the conventional stepping system will add additional cost associated with the reticle. In order to solve this problem, the imaging writing system of the present invention can independently control the focus of each SLM, thereby generating an optimal imaging effect in a local area corresponding to each SLM. Such a method of solving the problem of substrate warpage by means of adjusting the focus is shown in Figs. 9 and 21.

32a and 32b illustrate a method of imaging directly on a portion of a wafer substrate in an embodiment of the present invention. Figure 32a is a homomorphic alignment exposure performed by a 1x3 SLM array. In this method, the imaging pattern can be separately exposed by each SLM. Note that this function of processing some of the wafers is especially useful when manufacturing gallium arsenide (GaAs) wafers because gallium arsenide wafers are more susceptible to cracking than germanium wafers. If a conventional tool is used, it is difficult to process part of the wafer because the mask may not be used with some wafers. Even if the mask can be used with some wafers, the two are not easily aligned with each other. However, if we use the imaging writing system of this case, we can control each SLM separately when imaging part of the wafer, and compensate for the scaling, IOD and rotation factor correction. In this way, some wafers can be exposed without precise alignment. Similarly, Figure 32b illustrates how parallel isomorphic alignment exposure can be performed on a two-part wafer using a 1x2 SLM array, wherein each wafer is exposed by a corresponding SLM. Please note that in the example shown in Figure 32b, the two wafers do not have to be aligned with each other, and the two wafers can have their own offset angles, which can be used by the SLM during the exposure process. To compensate. The 32c and 32d drawings illustrate a method for directly imaging a design pattern of different shapes in the embodiment of the present invention. In detail, the design pattern 3202 of the cardioid flexible substrate in FIG. 32c can be directly imaged by a 1×4 SLM array without a photomask, and the rectangular design pattern 3204 of the curved flexible substrate in FIG. 32d can be A 2x4 SLM array is directly imaged without a reticle. In the above example, we can program each SLM and compensate for items such as warpage, scaling, IOD, and rotation factor correction.

Figures 33a and 33b illustrate a method of manufacturing a maskless mask in an embodiment of the present invention. In particular, Figure 33a is a conventional manufacturing method using a photomask, and Figure 33b is a maskless manufacturing method using the imaging writing system of the present invention. In Fig. 33a, the conventional manufacturing method receives the finalized product design pattern in block 3302, and then performs mask factory preparation, mask writing, and mask inspection and repair in blocks 3304, 3306, and 3308, respectively. The operations of blocks 3304 to 3308 are collectively referred to as mask factory operations. If 瑕疵 is found in block 3308, the 瑕疵 can be repaired, and sometimes the reticle write operation of block 3306 is repeated, thereby adding additional cost (indicated by $ in the figure), which includes the materials used. Cost, and the time cost of preparing a new reticle in block 3306. After completing the mask factory operation, the reticle will undergo a quality control test in block 3310. If an error is found during the test, the mask must be reworked. In other words, it must be returned to block 3306 to create a new mask, which will add more cost (indicated by $$). The added cost includes material cost and weight. The time cost of the reticle. Block 3312 is for product manufacturing verification. If a functional or performance problem is discovered during verification, the product may have to be redesigned, that is, the process must be repeated and the finalized product design pattern re-proposed in Box 3302. The increased cost of this situation is higher (indicated by $$), and the actual amount can reach millions of dollars. If the product successfully passes the manufacturing verification of block 3312, the mass production program of block 3314 can be entered.

In Figure 33b, the maskless manufacturing process receives the finalized product design pattern in block 3302. Then, in accordance with an embodiment of the present invention, the imaging writing system of the present invention will receive and process the design data for subsequent imaging and parallel exposure using an SLM array. In the process of processing design data for imaging, the imaging writing system of the present invention can perform alignment state correction, scaling correction, wafer warpage correction, viewpoint spacing correction, and rotation factor correction for each SLM. The correction operation is based on parameters of a specific area on the substrate, and each SLM system receives control to perform the correction operations.

Block 3312 of Figure 33b is identical to the corresponding block in Figure 33a and is a product manufacturing verification. If a functional or performance problem is discovered after verification, the product may have to be redesigned, i.e., the above process must be repeated, and the finalized product design pattern is resubmitted in block 3302. At this time, since the physical mask is not used, and the mask factory operation (blocks 3304 to 3308) or the reticle quality control operation is not required, the time course of the re-shaping mask will be better than that shown in Fig. 33a. The manufacturing process is short and the product development cost is also low (as indicated by the dashed lines in blocks 3312 to 3302). If the product manufacturing verification of block 3312 is successfully completed, the mass production program of block 3314 can be entered.

In accordance with an embodiment of the present invention, the imaging writing system of the present invention can perform an automated optical inspection of an integrated circuit in which the SLM array can capture an image of the substrate as shown in Figures 23a through 23c. For example, the sensors 2310 and 2322 can capture one or more images of a certain area of the substrate, and the substrate represents a portion of the integrated circuit that is inspected. Each image captured will be analyzed to find patterns of anomalies, such as flaws and foreign particles that should not appear. In one embodiment, the imaging writing system of the present invention can perform the following three checks: 1) finding the difference between the substrate and the mask database; 2) finding the distortion associated with the substrate pattern; and 3) finding the substrate Foreign particles. Compared with the conventional inspection method, the advantages of automatic optical inspection by the imaging writing system of the present invention are numerous. First, because the SLM array can align the reticle database in parallel, the system's throughput per unit time is extremely high. Secondly, the image writing system of the present invention can perform image bonding, so that the comparison of the substrate pattern and the mask database can be performed for a large design pattern. Furthermore, each SLM can independently inspect a specific area of the substrate, so that it can be more effective in various situations in the area, such as alignment state correction, scaling correction, IOD correction, rotation factor correction, and substrate warpage. Corrected. This automated optical inspection technology is suitable for very large substrates such as the tenth generation and newer generation flat panel displays.

The embodiments of the present invention are not only applicable but also beneficial to the lithography process of the FPD and its reticle (that is, forming a unique original size pattern or a precise replica thereof on the glass substrate), and are also suitable for the integrated circuit and computer generation. Large-scale imaging display applications such as full-scale images (CGH), PCBs, and other microscale and mesoscale.

Embodiments of the present invention are also applicable and advantageous for lithographic processes without a reticle. For example, a predetermined reticle data pattern can be directly written to the substrate, thereby eliminating the cost of the reticle and eliminating related problems. Embodiments of the present invention enable the exposure tool to perform a maskless exposure and have a throughput per unit time that exceeds the level required for the tenth generation and above substrates. More importantly, the design of the present invention improves the process window, thereby ensuring the yield of the lithography process.

Although the embodiments of the present invention have been described above by the various functional units and the present invention, it is obvious that the functions may be distributed between different functional units and processors in any suitable manner without departing from the spirit and scope of the invention. For example, functions performed by different processors or controllers may be performed by the same processor or controller. Thus, when reference is made to a particular functional unit, it refers to a suitable means of providing the described functionality, rather than a specific logical or physical structure or organization.

The invention can be embodied in any suitable form, including hardware, software, firmware, or any combination thereof. Portions of the present invention can be implemented as computer software executable by one or more data processors and/or digital signal processors, as desired. The elements, functions, and logic of the elements of any embodiment of the invention may be implemented in any suitable manner. The functions may be implemented in a single unit or in a plurality of units, or as part of other functional units. Thus, the invention can be a single unit, or can be in the

It will be apparent to those skilled in the art that the embodiments disclosed herein may be modified and combined in various ways, while still retaining the basic mechanism and method of the present invention. For ease of explanation, the foregoing has been described with respect to specific embodiments. However, the above description does not exhaust all possible embodiments, and the invention is not limited to the specific forms disclosed herein. Those who are familiar with the art may refer to the above descriptions, or may consider various modifications and variations. The invention has been described with respect to the specific embodiments and embodiments of the invention, and the invention may be

1, 3, 5, 6, 7, 8, 9. . . SLM

102. . . Mirror (previous technique)

104. . . Photomask (prior art)

106. . . Projection lens (prior art)

108. . . FPD substrate (prior art)

110. . . Light source (prior art)

112. . . First projection lens (prior art)

114. . . Photomask (prior art)

116. . . Second projection lens (prior art)

118. . . Wafer (prior art)

120. . . Wafer platform (prior art)

122. . . Mask projection imaging area (prior art)

130. . . Photomask (prior art)

131. . . Projection lens (prior art)

132. . . Substrate wafer (prior art)

202. . . Illumination light (prior art)

204. . . Beam splitter (prior art)

206. . . Space light modulator (prior art)

208. . . Fourier lens (prior art)

210. . . Fourier filter (prior art)

212. . . Reduced lens (previous technique)

214. . . Mask data (previous technology)

216. . . Blank reticle substrate (prior art)

302, 304. . . Digital Micromirror Device (DMD) or Spatial Light Modulator Chip (SLM)

306. . . Tilted micromirror

308. . . Micromirror that maintains its original position

402. . . Startup state

404. . . Flat state

406. . . Disabled

408. . . light source

410. . . Projection lens

502. . . Coplanar grating light valve (GLV) ribbon component

504. . . Alternately curved grating light valve (GLV) strip element

602. . . Space light modulator

604. . . Micromirror

606. . . Illumination source

608. . . Aligning light source

610. . . Projection lens

702, 704, 706, 708. . . Parallel array of SLM imaging units

802. . . SLM imaging unit

902. . . Single lens projection system (prior art)

904. . . Compromise focal plane (prior art)

906. . . Actual cross-sectional shape of the substrate surface (prior art)

908. . . Single lens is the best focus setting range for pattern imaging (prior art)

910. . . The maximum variation range of the cross-sectional shape of the substrate surface corresponding to each imaging lens (previous technique)

912. . . Imaging unit

914. . . focus

916. . . Depth of focus setting range

1002. . . An area of uneven surface of the substrate

1102. . . Mask data example

1104. . . Flattening mask data

1106. . . Partition mask material pattern

1108. . . Mask pattern overlap

1201 to 1208. . . Part of the SLM imaging block

1402. . . Mismatched boundary

1404. . . End of boundary

1406. . . Imaging unit write area

1502. . . SLM imaging unit

1600. . . Two-dimensional array type maskless image writing system

1602. . . SLM imaging unit

1702. . . Blue light and red light diode laser

1704. . . Orifice

1706. . . lens

1708. . . Spherical mirror

1710. . . Digital Micromirror Device (DMD) or Spatial Light Modulator Chip (SLM)

1712. . . A printed circuit board

1714. . . Beam collecting device

1716. . . Beam splitter

1718. . . CCD camera

1720. . . Lens assembly

1722. . . Red laser diode

1723, 1724, 1725, 1726. . . Blue laser diode

1802. . . SLM imaging unit

1804. . . Flexible roll substrate

1902. . . SLM imaging unit two-dimensional array

1904. . . Flexible roll substrate

2002. . . SLM imaging unit two-dimensional array

2006, 2008, 2010, 2012, 2014. . . Different "mask data" design patterns

2102. . . SLM imaging unit linear array

2104. . . Substrate surface

2202, 2204. . . Light and dark pixels

2206, 2208. . . Bright and dark pixels in the quasi-focus state

2210. . . Light and dark pixels in out-of-focus state

2302. . . Imaging light source

2304. . . Beam splitter

2306. . . Objective lens

2308. . . shell

2310. . . First photographic sensor

2312. . . First motor

2314. . . First refractive disk

2316. . . First optical path difference modulator

2317. . . Circular optical device

2318. . . Sector

2322. . . Second photographic sensor

2326. . . Second optical path difference modulator

2330. . . Third optical path difference modulator

2502. . . Different focus settings

2504. . . Final depth of focus

2602. . . Imaging area

2604. . . Space light modulator

2606. . . Imaging area

2608. . . Space light modulator

2610. . . Overlapping area

2612. . . Theoretical boundary

2614, 2616. . . User-defined border

2622. . . Imaging area

2624. . . Space light modulator

2626. . . Imaging area

2628. . . Space light modulator

2630. . . Overlapping area

2632. . . Theoretical boundary

2634, 2636. . . User-defined border

2638, 2639. . . Polyline

2702, 2704, 2706. . . Center point of SLM

2708, 2710, 2712, 2714. . . Each SLM imaging area

2802. . . SLM #7 direct imaging area

2803. . . SLM #7

2804. . . Mask data

2805. . . "+" boundary identifier

2806. . . Measured pattern

2807. . . Corner of the imaging area between adjacent SLMs

2808. . . Required pattern

2810. . . defect

2812. . . Parallel rectangle

2820. . . Small dark area

3002. . . First wafer

3004. . . Second wafer

3202. . . Heart-shaped flexible substrate design pattern

3204. . . Curved rectangular design pattern of flexible substrate

A, B, C, D, E, F, G. . . Design functional blocks in the integrated circuit

A more complete understanding of the technical features and advantages of the present invention will be apparent from the description of the appended claims. In the figure:

Figures 1a through 1e illustrate various conventional exposure tools for making integrated circuits, printed circuit boards, and flat panel displays.

Figure 2 illustrates a conventional architecture of an exposure tool for fabricating a reticle.

FIG. 3 illustrates a digital micromirror device (DMD) or spatial example in accordance with an embodiment of the present invention.

Figure 4 illustrates a DMD projection system in accordance with an embodiment of the present invention.

Fig. 5 is a view showing a grating light valve (GLV) device according to an embodiment of the present invention, and simultaneously showing an example of a specular reflection state and a diffraction state.

FIG. 6 illustrates an example of a small spatial light modulator (SLM) imaging unit in accordance with an embodiment of the present invention.

FIG. 7 illustrates an example of a parallel array of SLM imaging units in accordance with an embodiment of the present invention.

Figure 8 is a plan view of a parallel array of SLM imaging units shown in Figure 7.

The right side of Figure 9 illustrates how the array processing system of the embodiment of the present invention can be used to optimize the local process window, while the left side is a conventional single lens projection system.

FIG. 10 illustrates a method for optimizing local unevenness of a substrate in an embodiment of the present invention.

FIG. 11 is a diagram showing an application manner of a reticle data structure in an embodiment of the present invention.

Figure 12 illustrates a parallel array sum exposure method in accordance with an embodiment of the present invention.

Figure 13 is a diagram showing a method of forming redundancy in an image writing system in an embodiment of the present invention.

Figure 14 illustrates a wedge boundary fusion method in accordance with an embodiment of the present invention.

Figure 15 is a diagram showing a method of arranging SLM imaging units in an array in an embodiment of the present invention.

FIG. 16 is a diagram showing an example of a two-dimensional array type image writing system for manufacturing a flexible display without a photomask according to an embodiment of the present invention.

Figure 17 illustrates an SLM imaging unit in accordance with an embodiment of the present invention.

Figure 18 is a diagram showing a roll-type matte lithography method using a linear array of SLM imaging units in an embodiment of the present invention.

Figure 19 is a diagram showing a scroll-type matte lithography method using a two-dimensional array of SLM imaging units in an embodiment of the present invention.

FIG. 20 is a diagram showing a method for imaging a same flexible reel-type substrate by using a matte lithography method for a plurality of products due to different reticle data sizes.

Figure 21 is a diagram showing a method of positioning each SLM imaging unit according to a local condition of the surface of the substrate in the embodiment of the present invention.

FIG. 22 illustrates a method for detecting pixel focus in an embodiment of the present invention.

23a to 23c illustrate three examples of devices for instantly detecting the focus of an SLM imaging unit in an embodiment of the present invention.

Figure 24 is a diagram showing an example of an imaging pattern suitable for a pixel total exposure method in an embodiment of the present invention.

FIG. 25 is a diagram showing a method for improving depth of focus (DOF) by a pixel total exposure method in an embodiment of the present invention.

26a and 26b illustrate a method of joining adjacent imaging regions using overlapping regions in an embodiment of the present invention.

27a and 27b illustrate a method of measuring and utilizing the viewpoint spacing between centers of adjacent SLM imaging units in an embodiment of the present invention.

28a and 28b illustrate a method of measuring and correcting an alignment state of an imaging writing system in an embodiment of the present invention.

Figures 28c and 28d illustrate the method of determining the component 及 in the embodiment of the present invention and determining the location of the 瑕疵 using alignment affinity.

29a to 29d are diagrams showing a parallel manufacturing method of a three-dimensional integrated circuit without a mask in the embodiment of the present invention.

Figure 30 illustrates one or more wafer direct imaging methods in an embodiment of the invention.

Figure 31 illustrates a maskless scanning exposure system in accordance with an embodiment of the present invention.

32a and 32b illustrate a method of parallel manufacturing of a mask without a mask in an embodiment of the present invention.

32c and 32d illustrate a method for directly imaging a design pattern of a flexible substrate of different shapes in an embodiment of the present invention.

Figures 33a and 33b illustrate a method of manufacturing a maskless mask in an embodiment of the present invention.

In the present specification, the same elements are denoted by the same reference numerals.

Figure 30 illustrates an embodiment of the present invention,

3002. . . First wafer

3004. . . Second wafer

Forming one or more parallel arrays in a non-mask parallel exposure manner, receiving the boring mask reticle data, and adopting respective scaling correction, alignment state correction, viewpoint spacing correction, rotation factor correction, and substrate deformation correction, etc. Synchronous formation of one or more layers of correlated 矽 borehole imaging on one or more wafers. A method in which each of the transistor design functional blocks is connected and manufactured by a three-dimensional integrated circuit.

Claims (16)

A method of fabricating a three-dimensional integrated circuit comprising the steps of: providing an imaging writing system, wherein the imaging writing system comprises a plurality of spatial light modulator (SLM) imaging units, the plurality of SLM imaging units being arranged in a Or a plurality of parallel arrays; receiving reticle data, wherein the reticle data is for writing one or more layers of the three-dimensional integrated circuit; processing the reticle data to form one or more layers corresponding to the three-dimensional integrated circuit The plurality of partition mask data patterns, wherein the step of processing the mask data comprises: arranging one or more of the one or more configuration blocks disposed in the one or more layers of the three-dimensional integrated circuit, and identifying the through holes for use Routing a communication signal between the one or more configuration blocks in the one or more layers of the three-dimensional integrated circuit; assigning one or more of the SLM imaging units to process each of the partitioned mask data patterns; and controlling the A plurality of SLM imaging units, wherein the plurality of partition mask data patterns are written in parallel to the one or more layers of the three-dimensional integrated circuit. The method of claim 1, wherein the step of assigning one or more of the SLM imaging units comprises: scaling the plurality of partitioned mask data patterns according to the plurality of SLM imaging units, wherein each of the plurality of SLM imaging units The partitioned mask data patterns all have a corresponding scaling correction. The method of claim 1, wherein the step of assigning one or more of the SLM imaging units further comprises: performing alignment state correction on the plurality of partitioned mask data patterns according to the plurality of SLM imaging units, wherein Each of the zone reticle data patterns has a corresponding alignment state correction; and subsequent alignment state corrections are performed in the multiple exposures of the zone reticle material pattern. The method of claim 1, wherein the step of assigning one or more of the SLM imaging units further comprises: performing a viewpoint spacing correction on the plurality of partitioned mask data patterns according to the plurality of SLM imaging units, wherein each The partition mask data pattern has a corresponding correction of the viewpoint spacing, wherein the step of performing the viewpoint spacing correction comprises: measuring the viewpoint spacing between the plurality of SLM imaging units, and calibrating the plurality of partitions by using the viewpoint spacing A mask data pattern for controlling exposure of each SLM imaging unit; and compensating for errors in alignment of the plurality of SLM imaging units. The method of claim 1, wherein the step of assigning one or more of the SLM imaging units further comprises: performing a rotation factor correction on the plurality of partitioned mask data patterns according to the plurality of SLM imaging units, wherein each The partition mask data pattern has a corresponding rotation factor correction, and wherein the step of performing the rotation factor correction comprises: detecting a rotation error of the plurality of SLM imaging units, in the plurality of SLM imaging units Each of the SLM imaging units measures a rotation correction factor and calibrates the plurality of partitioned mask data patterns to control exposure by the plurality of SLM imaging units. The method of claim 1, wherein the step of assigning one or more of the SLM imaging units further comprises: performing substrate deformation correction on the plurality of partitioned mask data patterns according to the plurality of SLM imaging units, wherein each The partitioned mask data patterns each have a corresponding correction of substrate deformation. The method of claim 1, wherein the step of controlling the plurality of SLM imaging units comprises: for each of the SLM imaging units, causing a corresponding one of the partitioned mask data patterns to be independent of other portions of the imaging writing system The SLM imaging unit is exposed. A system for fabricating a three-dimensional integrated circuit comprising: a plurality of spatial light modulator (SLM) imaging units, the plurality of SLM imaging units being arranged in one or more parallel arrays; and a configuration to control the plurality of SLM images a controller of the unit, wherein the controller includes: logic for receiving the reticle data, wherein the reticle data is for writing one or more layers of the three-dimensional integrated circuit; logic for processing the reticle data, Forming a plurality of partial mask reticle data patterns corresponding to the one or more layers in the three-dimensional integrated circuit, wherein the logic for processing the reticle data comprises: arranging one of the one or more configuration blocks disposed on the three-dimensional product In the one or more layers of the body circuit, and for identifying the through hole Logic for routing communication signals between the one or more configuration blocks in the one or more layers of the three-dimensional integrated circuit; logic for assigning one or more of the SLM imaging units, assigning one or more The SLM imaging unit is responsible for processing each of the partition mask data patterns; and logic for controlling the plurality of SLM imaging units, and writing the plurality of partition mask data patterns in parallel to the one or more layers of the three-dimensional integrated circuit . The system of claim 8 wherein the logic for assigning one or more of the SLM imaging units comprises: scaling the plurality of partitioned mask data patterns according to the plurality of SLM imaging units Logic, wherein each of the partitioned mask data patterns has a corresponding scaling correction. The system of claim 8, wherein the logic for assigning one or more of the SLM imaging units further comprises: aligning the plurality of partitioned mask data patterns according to the plurality of SLM imaging units The logic of the correction, wherein each of the partitioned mask data patterns has a corresponding correction of the alignment state. The system of claim 8, wherein the logic for assigning one or more of the SLM imaging units further comprises: performing a viewpoint spacing correction on the plurality of partitioned mask data patterns according to the plurality of SLM imaging units The logic, wherein each of the partition mask data patterns has a corresponding correction of the viewpoint spacing. The system of claim 8, wherein the logic for assigning one or more of the SLM imaging units further comprises: performing a rotation factor correction on the plurality of partitioned mask data patterns according to the plurality of SLM imaging units The logic, wherein each of the partitioned mask data patterns has a corresponding correction of the rotation factor. The system of claim 8, wherein the logic for assigning one or more of the SLM imaging units further comprises: performing substrate deformation correction on the plurality of partitioned mask data patterns according to the plurality of SLM imaging units The logic, wherein each of the partitioned mask data patterns has a corresponding correction of substrate deformation. The system of claim 8, wherein the logic for controlling the plurality of SLM imaging units comprises: for each of the SLM imaging units, causing a corresponding one of the partitioned mask data patterns to be independent of the imaging writing system The logic of exposure of other SLM imaging units. A method of fabricating a partial wafer, comprising the steps of: providing an imaging writing system, wherein the imaging writing system comprises a plurality of spatial light modulator (SLM) imaging units, the plurality of SLM imaging units being arranged in one or a plurality of parallel arrays; providing one or more partial wafers to be processed; receiving reticle data, wherein the reticle data is for writing to the substrate of the one or more partial wafers; Processing the reticle data to form a plurality of zonal reticle data patterns corresponding to the one or more partial wafers; assigning one or more of the SLM imaging units to process Each of the partitioned mask data patterns, wherein the assigning comprises performing at least one of: scaling correction, alignment state correction, viewpoint spacing correction, rotation factor correction, or substrate deformation correction, wherein one or more of the SLMs are assigned The processing unit is configured to process the mask material pattern of each of the partitions, and: performing alignment state correction on the plurality of partition mask data patterns according to the plurality of SLM imaging units, wherein each of the partition mask material patterns has a corresponding pair Correction of a quasi-state, and subsequent alignment state correction in multiple exposures of the masked mask data pattern; and controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns in parallel to the one or more The substrates of the partial wafers. A method of fabricating a plurality of designs in parallel on a printed circuit board (PCB), comprising the steps of: providing an imaging writing system, wherein the imaging writing system comprises a plurality of spatial light modulator (SLM) imaging units, A plurality of SLM imaging units are arranged in one or more parallel arrays; a printed circuit board is provided, wherein the printed circuit board has been divided into a plurality of regions, and each of the regions includes a design to be manufactured; receiving the mask data, wherein the Mask data is used to write the plurality of areas of the printed circuit board; Processing the reticle data to form a plurality of partial reticle material patterns corresponding to the plurality of regions of the printed circuit board; assigning one or more of the SLM imaging units to process each of the reticle material patterns, wherein The assigning includes performing at least one of: scaling correction, alignment state correction, viewpoint spacing correction, rotation factor correction, or substrate deformation correction, wherein assigning one or more of the SLM imaging units is responsible for processing each of the partitioned masks The data pattern includes: performing alignment state correction on the plurality of partition mask data patterns according to the plurality of SLM imaging units, wherein each of the partition mask material patterns has a corresponding alignment state correction, and in the partition Subsequent alignment state correction is performed in multiple exposures of the mask data pattern; and the plurality of SLM imaging units are controlled to write the plurality of partition mask data patterns in parallel to the plurality of regions of the printed circuit board.