TWI709950B - Display control signal processing circuit, source drive circuit and display device - Google Patents

Abstract

A display control signal processing circuit has: a data receiving and output unit for receiving an input data signal and generating an output data signal according to the input data signal; a multi-clock signal generating unit for performing processing on the input data signal A clock recovery process to generate a base frequency signal, and generate a plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases according to the base frequency signal; a multiplexer is used to generate a The dynamic control of the selection signal, each time one of the plurality of candidate clock signals is selected to generate an output clock signal; and a selector for generating a time-varying digital signal driven by the base frequency signal to determine the selection signal content.

Description

Display control signal processing circuit, source drive circuit and display device

The present invention relates to the technical field of display driving chips, in particular to a display control signal processing circuit, a source driving circuit including the display control signal processing circuit, and a display device including the source driving circuit.

Please refer to FIG. 1, which shows a block diagram of a conventional display control signal processing circuit. As shown in FIG. 1, a display control signal processing circuit 1'located in a source driver is coupled to a display controller 2'commonly called Timing Controller (Tcon), and the display control signal processing circuit 1'includes: a clock The recovery unit 13' is used to perform a clock recovery process on an input data signal Data_IN transmitted from the display controller 2'to generate an output clock signal CLK_OUT; and a data recovery unit 14' is used to output the clock signal Under the control of CLK_OUT, a data recovery process is performed on the input data signal Data_IN to generate an output data signal Data_OUT.

In more detail, after receiving the input data signal Data_IN, the clock recovery unit 13' correspondingly generates a base frequency signal as an output clock signal CLK_OUT, so that the data recovery unit 14' is controlled by the output clock signal CLK_OUT according to the input The data signal Data_IN generates the output data signal Data_OUT. When the display needs to support high-resolution specifications, the display control signal processing circuit 1'and the display controller 2'must use a high-speed transmission interface to transmit data. However, as far as the display control signal processing circuit 1'is concerned, the output clock signal CLK_OUT has the problem of electromagnetic interference (Electric Magnetic Interruption, EMI). In particular, the output clock signal CLK_OUT generated by the clock signal generating unit 11' usually has a fixed frequency, and electromagnetic interference (EMI) often occurs at the base frequency or multiplier of the fixed frequency.

In order to reduce electromagnetic interference, conventionally, a technical solution using a multi-phase output clock signal to reduce the peak energy of the spectrum has been proposed. Please refer to FIG. 2, which shows a block diagram of another conventional display control signal processing circuit. As shown in FIG. 2, a display control signal processing circuit 1'located in a source driver is coupled to a display controller 2'commonly known as Timing Controller (Tcon), and displays the control signal The signal processing circuit 1'includes: a multi-phase clock signal generating unit 16' for performing a clock recovery processing procedure on an input data signal Data_IN transmitted from the display controller 2'to generate a base frequency signal and Frequency signal generates a multi-phase output clock signal CLK_OUT (which has N phases: CLK_1-CLK_N); and a data recovery unit 14' for performing a data on the input data signal Data_IN under the control of the base frequency signal The processing procedure is returned to generate an output data signal Data_OUT.

However, the multi-phase output clock signal of Figure 2 is still at a fixed frequency, and there is still room for improvement in terms of reducing electromagnetic wave interference (Electric Magnetic Interruption, EMI).

Therefore, there is an urgent need for a novel display control signal processing circuit in the art.

An object of the present invention is to provide a display control signal processing circuit located in a source driving circuit, which can generate a display data control clock with a time-varying duty cycle or a time-varying duty cycle and a time-varying phase to When the source drive circuit drives a pixel array, it effectively reduces electromagnetic interference (EMI) to the outside world.

Another object of the present invention is to provide a source driving circuit, which can generate a display data control clock with a time-varying duty cycle or a time-varying duty cycle and a time-varying phase through an internal display control signal processing circuit , In order to effectively reduce electromagnetic interference to the outside world when the source driving circuit drives a pixel array.

Another object of the present invention is to provide a display device, which can generate a display data control with a time-varying duty cycle or a time-varying duty cycle and a time-varying phase by a display control signal processing circuit of a source driving circuit The clock pulse effectively reduces electromagnetic interference to the outside when the source drive circuit drives a pixel array.

In order to achieve the above objective, a display control signal processing circuit is proposed, which has: a data receiving and output unit for receiving an input data signal and generating an output data signal according to the input data signal; a multi-clock signal generating unit , Used to perform a clock recovery process on the input data signal to generate a base frequency signal, and generate a different duty cycle or a different duty based on the base frequency signal A plurality of candidate clock signals with different phases; a multiplexer for dynamic control of a selection signal, each time one of the plurality of candidate clock signals is selected to generate an output clock signal; and a selection The device is used to generate a time-varying number according to the driving of the base frequency signal to determine the content of the selection signal.

In one embodiment, the selector is a pseudo-random selector, and the time-varying number is a random number.

In one embodiment, the selector is an up-counting selector, and the time-varying number is a number that increases periodically.

In one embodiment, the selector is a down-counting selector, and the time-varying code is a periodically decreasing code.

To achieve the above objective, the present invention further provides a source drive circuit, which has a display control signal processing circuit and a digital-to-analog conversion circuit, the digital-to-analog conversion circuit is used to control an output clock signal to convert an output data signal Converted into a pixel voltage to drive a pixel array, and the display control signal processing circuit has: a data receiving and output unit for receiving an input data signal and generating the output data signal according to the input data signal; A multi-clock signal generating unit for performing a clock recovery processing procedure on the input data signal to generate a base frequency signal, and generating different duty cycles or different duty cycles and different phases according to the base frequency signal A plurality of candidate clock signals; a multiplexer for generating the output clock signal by selecting one of the plurality of candidate clock signals according to the dynamic control of a selection signal; and a selector for A time-varying number is generated according to the driving of the fundamental frequency signal to determine the content of the selection signal.

In one embodiment, the selector is a pseudo-random selector, and the time-varying number is a random number.

In one embodiment, the selector is an up-counting selector, and the time-varying number system A number that increases periodically.

In one embodiment, the selector is a down-counting selector, and the time-varying code is a periodically decreasing code.

In order to achieve the above objective, the present invention further provides a display device having a display controller and the aforementioned source driving circuit and pixel array, wherein the display controller is used to provide the input clock signal and the input data signal.

In possible embodiments, the display device may be a liquid crystal display device, an organic light emitting diode display device, or a micro light emitting diode display device.

<The present invention>

1: Display control signal processing circuit

2: display controller

11: Data receiving and output unit

12: Multiple clock signal generation unit

13: Multiplexer

14: selector

121: Multi-phase clock signal generator

122: Multi-duty cycle clock signal generator

100: Source drive circuit

110: Display control signal processing circuit

120: Digital analog conversion circuit

200: display device

210: display controller

220: Source drive circuit

230: pixel array

<Learning>

1’: Display control signal processing circuit

2’: Display Controller

13’: Clock recovery unit

14’: data recovery unit

16’: Multi-phase clock signal generating unit

FIG. 1 shows a block diagram of a conventional display control signal processing circuit.

FIG. 2 shows a block diagram of another conventional display control signal processing circuit.

FIG. 3 is a block diagram of an embodiment of the display control signal processing circuit of the present invention.

4 is a block diagram of an embodiment of a multi-clock signal generating unit of the display control signal processing circuit of FIG. 3. FIG.

FIG. 5 shows a block diagram of an embodiment of the source driving circuit of the present invention.

FIG. 6 is a block diagram of an embodiment of the display device of the present invention.

In order to enable your reviewer to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred specific embodiments are attached as follows.

Please refer to FIG. 3, which shows a block diagram of an embodiment of the display control signal processing circuit of the present invention. As shown in FIG. 3, a display control signal processing circuit 1 (located in a source driving circuit) is used to couple to a display controller 2, which is commonly known as Timing Controller (Tcon), to generate according to an input data signal Data_IN An output clock signal CLK_OUT and an output data signal Data_OUT. The display control signal processing circuit 1 includes: a data receiving and outputting unit 11, a multi-clock signal generating unit 12, a multiplexer 13, and a selector 14.

The data receiving and outputting unit 11 can be a data buffer for The input data signal Data_IN generates the output data signal Data_OUT.

The multi-clock signal generating unit 12 performs a clock recovery process on the input data signal Data_IN to generate a base frequency signal CLK, and generates complex numbers with different duty cycles or different duty cycles and different phases according to the base frequency signal Candidate clock signals (CLK_1, CLK_2,..., CLK_N). Since the duty cycle control circuit is well-known (for example, a voltage controlled duty cycle circuit), it is not intended to be further described here.

The multiplexer 13 is used for dynamic control of a selection signal SEL (which can be a serial signal or a parallel signal), and each time one of a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) is selected to generate an output clock Signal CLK_OUT.

The selector 14 is used to generate a time-varying number according to the driving of the base frequency signal CLK to determine the content of the selection signal SEL. In a possible embodiment, the selector 14 is a pseudo-random selector, and the time-varying number is a random number; or the selector 14 is an up-counting selector, and the time-varying number is a number that increases periodically ; Or the selector 14 is a down-counting selector, and the time-varying number is a periodically decreasing number.

In the actual operation, when the selector 14 is the pseudo-random selector, corresponding to N pulses of the base frequency signal CLK, N is an integer greater than 1, and the output clock signal CLK_OUT of the multiplexer 13 is N pulses The pulse has a randomly varying duty cycle. Therefore, the energy of the output clock signal CLK_OUT can be evenly distributed in a wide frequency band, thereby effectively reducing the electromagnetic wave interference to the outside; when the selector 14 is the up-counting selector described above , Corresponding to the N pulses of the base frequency signal CLK, N is an integer greater than 1, and the N pulses of the output clock signal CLK_OUT of the multiplexer 13 will have N different duty cycles. Therefore, the energy of the output clock signal CLK_OUT is It can be evenly distributed in a wide frequency band, thereby effectively reducing the electromagnetic wave interference to the outside; and when the selector 14 is the aforementioned down-counting selector, corresponding to N pulses of the fundamental frequency signal CLK, N is an integer greater than 1. The N pulses of the output clock signal CLK_OUT of the multiplexer 13 will have N different duty ratios. Therefore, the energy of the output clock signal CLK_OUT can be evenly distributed in a wide frequency band, thereby effectively reducing electromagnetic interference to the outside world .

Please refer to FIG. 4, which shows the multiple clock signals of the display control signal processing circuit of FIG. 3 A block diagram of an embodiment of the generating unit 12. As shown in FIG. 4, the multi-clock signal generating unit 12 includes a multi-phase clock signal generator 121 and a multi-duty cycle clock signal generator 122, wherein the multi-phase clock signal generator 121 is used for the base frequency signal CLK A plurality of phase-shifted clock signals (CLK_1', CLK_2',...,CLK_N') with different phases are generated, and the multi-duty cycle clock signal generator 122 is used to make the phase-shifted clock signal (CLK_1) controlled by the selection signal SEL. ',CLK_2',...,CLK_N') further have different duty cycles, thereby generating candidate clock signals (CLK_1, CLK_2,..., CLK_N). The selector 14 is used to generate a time-varying number according to the driving of the base frequency signal CLK to determine the content of the selection signal SEL. In a possible embodiment, the selector 14 is a pseudo-random selector, and the time-varying number is a random number; or the selector 14 is an up-counting selector, and the time-varying number is a number that increases periodically ; Or the selector 14 is a down-counting selector, and the time-varying number is a periodically decreasing number.

In addition, although in the embodiment of FIG. 4, the multi-phase clock signal generator 121 is used to perform the phase shift modulation operation first, and then the multi-duty cycle clock signal generator 122 is used to perform the duty cycle modulation operation, but the present invention does not Not limited to this, the multi-duty clock signal generator 122 may be used to perform the duty-cycle modulation operation first, and then the multi-phase clock signal generator 121 may be used to perform the phase-shift modulation operation.

Based on the above description, the present invention further provides a source driving circuit. Please refer to FIG. 5, which shows a block diagram of an embodiment of the source driving circuit of the present invention. As shown in FIG. 5, a source driving circuit 100 includes a display control signal processing circuit 110 (implemented by the display control signal processing circuit 1 shown in any one of FIGS. 2-4) and a digital-to-analog conversion circuit 120, in which, The digital-to-analog conversion circuit 120 is used to convert the output data signal Data_OUT into a pixel voltage V _P under the control of the output clock signal CLK_OUT to drive a pixel array. Since the energy of the output clock signal CLK_OUT can be evenly distributed in a wide frequency band, the electromagnetic wave interference of the source driving circuit 100 to the outside can be effectively reduced.

In addition, the present invention further provides a display device. Please refer to FIG. 6, which shows a block diagram of an embodiment of the display device of the present invention. As shown in FIG. 6, a display device 200 includes a display controller 210, a source drive circuit 220 (implemented by the source drive circuit 100 of FIG. 5), and a pixel array 230, where the display controller 210 is used In order to provide the input clock signal CLK_IN and the input data signal Data_IN, the source driver circuit 220 is used to convert the output data signal Data_OUT (generated based on the input data signal Data_IN) under the control of the output clock signal CLK_OUT (generated based on the input clock signal CLK_IN) A pixel voltage V _{P is used} to drive a pixel array. Since the energy of the output clock signal CLK_OUT in the source driving circuit 220 can be evenly distributed in a wide frequency band, the electromagnetic interference of the display device 200 to the outside can be effectively reduced.

In addition, among possible display devices, the display device 200 may be a liquid crystal display device, an organic light emitting diode (OLED) display device, or a micro light emitting diode (Micro LED) display device.

In addition, in order to verify the efficacy of the present invention, the inventor of the present case integrated the display control signal processing circuit 1 into a source driver chip as an experimental group, and used the source driver that did not include the display control signal processing circuit 1 of the present invention. The chip served as a control group. The experiment found that compared with the control group, the electromagnetic interference (EMI) of the experimental group was significantly reduced by 21.5%.

In this way, the above system has completely and clearly described the technical solution of the present invention; and from the above, it can be seen that the present invention has the following advantages:

(1) The display control signal processing circuit of the present invention can generate a display data control clock with a time-varying duty cycle or a time-varying duty cycle and a time-varying phase, so that when the source driving circuit drives a pixel array Effectively reduce electromagnetic interference (EMI) to the outside world.

(2) The source drive circuit of the present invention can generate a display data control clock with a time-varying duty cycle or a time-varying duty cycle and a time-varying phase through an internal display control signal processing circuit, so that the source The pole drive circuit effectively reduces electromagnetic interference to the outside world when driving a pixel array.

(3) The display device of the present invention can generate a display data control clock with a time-varying duty ratio or a time-varying duty ratio and a time-varying phase through a display control signal processing circuit of a source driving circuit, so as to The source drive circuit effectively reduces electromagnetic interference to the outside when driving a pixel array.

It must be emphasized that the foregoing disclosures in this case are preferred embodiments, and any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those who are familiar with the art will not deviate from the patent of this case. Right category.

In summary, regardless of the purpose, means and effect of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. I implore the examiner to investigate and grant the patent as soon as possible. Society is for the best prayer.

1: Display control signal processing circuit

2: display controller

11: Data receiving and output unit

12: Multiple clock signal generation unit

13: Multiplexer

14: selector

Claims (6)

A display control signal processing circuit, which has: a data receiving and output unit for receiving an input data signal and generating an output data signal according to the input data signal; a multi-clock signal generating unit for the input data signal Perform a clock recovery process to generate a base frequency signal, and generate a plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases according to the base frequency signal; a multiplexer for Dynamic control of a selection signal, each time one of the plurality of candidate clock signals is selected to generate an output clock signal; and a selector for generating a time-varying digital according to the driving of the base frequency signal to determine the selection signal The content; where the selector is an up-counting selector, and the time-varying number is a number that increases periodically. A display control signal processing circuit, which has: a data receiving and output unit for receiving an input data signal and generating an output data signal according to the input data signal; a multi-clock signal generating unit for the input data signal Perform a clock recovery process to generate a base frequency signal, and generate a plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases according to the base frequency signal; a multiplexer for Dynamic control of a selection signal, each time one of the plurality of candidate clock signals is selected to generate an output clock signal; and a selector for generating a time-varying digital according to the driving of the base frequency signal to determine the selection signal The content; where the selector is a down-counting selector, and the time-varying number is a periodically decreasing number. A source drive circuit, which has a display control signal processing circuit and a digital-to-analog conversion circuit, the digital-to-analog conversion circuit is used to control an output clock signal The material signal is converted into a pixel voltage to drive a pixel array, and the display control signal processing circuit has: a data receiving and output unit for receiving an input data signal and generating the output data according to the input data signal Signal; a multi-clock signal generating unit for performing a clock recovery processing procedure on the input data signal to generate a base frequency signal, and according to the base frequency signal to generate a different duty cycle or a different duty cycle and have different A plurality of candidate clock signals of phase; a multiplexer for dynamic control of a selection signal, each time one of the plurality of candidate clock signals is selected to generate the output clock signal; and a selector, It is used to generate a time-varying number according to the driving of the base frequency signal to determine the content of the selection signal; wherein, the selector is an up-counting selector, and the time-varying number is a number that increases periodically. A source driving circuit has a display control signal processing circuit and a digital-to-analog conversion circuit. The digital-to-analog conversion circuit is used to convert an output data signal into a pixel voltage under the control of an output clock signal to drive a pixel voltage. Pixel array, and the display control signal processing circuit has: a data receiving and output unit for receiving an input data signal and generating the output data signal according to the input data signal; a multi-clock signal generating unit for Perform a clock recovery process on the input data signal to generate a base frequency signal, and generate a plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases according to the base frequency signal; A selector for generating the output clock signal by selecting one of the plurality of candidate clock signals according to the dynamic control of a selection signal; and a selector for generating the output clock signal according to the driving of the base frequency signal The variable number is used to determine the content of the selection signal; wherein the selector is a down-counting selector, and the time-varying number is a periodically decreasing number. A display device having a display controller, such as the third to fourth patent application The source driving circuit and pixel array according to any one of the clauses, wherein the display controller is used to provide the input clock signal and the input data signal. The display device described in item 5 of the scope of patent application is a display device selected from the group consisting of a liquid crystal display device, an organic light emitting diode display device, and a micro light emitting diode display device.

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