TWI707333B - Display control signal processing circuit, source drive circuit and display device - Google Patents

Display control signal processing circuit, source drive circuit and display device Download PDF

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TWI707333B
TWI707333B TW108130334A TW108130334A TWI707333B TW I707333 B TWI707333 B TW I707333B TW 108130334 A TW108130334 A TW 108130334A TW 108130334 A TW108130334 A TW 108130334A TW I707333 B TWI707333 B TW I707333B
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display
clock signal
processing circuit
display control
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TW202109497A (en
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周士勛
蘇嘉偉
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大陸商北京集創北方科技股份有限公司
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一種顯示控制信號處理電路,具有:一資料接收及輸出單元,用以接收一輸入資料信號並依該輸入資料信號產生一輸出資料信號;一多時鐘信號產生單元,用以依一輸入時鐘信號產生具不同占空比或具不同占空比且具不同相位的複數個候選時鐘信號;以及一多工器,用以依一選擇信號的動態控制,每次由所述複數個候選時鐘信號中擇一以產生一輸出時鐘信號。 A display control signal processing circuit has: a data receiving and output unit for receiving an input data signal and generating an output data signal according to the input data signal; a multi-clock signal generating unit for generating an input clock signal A plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases; and a multiplexer for dynamic control of a selection signal, each time being selected from the plurality of candidate clock signals One to generate an output clock signal.

Description

顯示控制信號處理電路、源極驅動電路及顯示裝置Display control signal processing circuit, source drive circuit and display device
本發明係關於顯示驅動芯片之技術領域,尤指一種顯示控制信號處理電路、包含該顯示控制信號處理電路的一種源極驅動電路、以及包含該源極驅動電路的一種顯示裝置。The present invention relates to the technical field of display driving chips, in particular to a display control signal processing circuit, a source driving circuit including the display control signal processing circuit, and a display device including the source driving circuit.
請參照圖1,其繪示一習知顯示控制信號處理電路的方塊圖。如圖1所示,位於一源極驅動器內之一顯示控制信號處理電路1’耦接俗稱為Timing Controller (Tcon)的一顯示控制器2’,且顯示控制信號處理電路1’包括:一時鐘信號產生單元11’,用以接收傳送自該顯示控制器2’的一輸入時鐘信號CLK_IN;以及一資料緩衝單元12’,用以接收傳送自該顯示控制器2’的一輸入資料信號Data_IN。Please refer to FIG. 1, which shows a block diagram of a conventional display control signal processing circuit. As shown in FIG. 1, a display control signal processing circuit 1'located in a source driver is coupled to a display controller 2'commonly called Timing Controller (Tcon), and the display control signal processing circuit 1'includes: a clock The signal generating unit 11' is used to receive an input clock signal CLK_IN transmitted from the display controller 2'; and a data buffer unit 12' is used to receive an input data signal Data_IN transmitted from the display controller 2'.
更詳細地說明,在接收所述輸入時鐘信號CLK_IN之後,時鐘信號產生單元11’即對應地產生一基頻信號以作為一輸出時鐘信號CLK_OUT,使得資料緩衝單元12’在輸出時鐘信號CLK_OUT的控制下依輸入資料信號Data_IN產生一輸出資料信號Data_OUT。當顯示器需要支援高解析度規格時,顯示控制信號處理電路1’和顯示控制器2’之間即須使用高速傳輸介面來傳輸資料。然而,就顯示控制信號處理電路1’而言,其輸出時鐘信號CLK_OUT會有產生電磁波干擾(Electric Magnetic Interruption, EMI)的問題。特別是,該時鐘信號產生單元11’所產生的輸出時鐘信號CLK_OUT通常具有固定頻率,而電磁波干擾(EMI)常發生在其固定頻率的基頻或倍頻之上。In more detail, after receiving the input clock signal CLK_IN, the clock signal generating unit 11' accordingly generates a base frequency signal as an output clock signal CLK_OUT, so that the data buffer unit 12' controls the output clock signal CLK_OUT Next, an output data signal Data_OUT is generated according to the input data signal Data_IN. When the display needs to support high-resolution specifications, the display control signal processing circuit 1'and the display controller 2'must use a high-speed transmission interface to transmit data. However, as far as the display control signal processing circuit 1'is concerned, the output clock signal CLK_OUT has the problem of electromagnetic interference (Electric Magnetic Interruption, EMI). In particular, the output clock signal CLK_OUT generated by the clock signal generating unit 11' usually has a fixed frequency, and electromagnetic interference (EMI) often occurs at the base frequency or multiplier of the fixed frequency.
為解決上述問題,本領域亟需一種新穎的顯示控制信號處理電路。In order to solve the above problems, a novel display control signal processing circuit is urgently needed in the art.
本發明之一目的在於提供一種位於一源極驅動電路內之顯示控制信號處理電路,其可產生具有時變占空比之一顯示資料控制時脈,以在該源極驅動電路驅動一畫素陣列時有效地降低對外界之電磁波干擾(EMI)。An object of the present invention is to provide a display control signal processing circuit located in a source drive circuit, which can generate a display data control clock with a time-varying duty cycle to drive a pixel in the source drive circuit Array effectively reduces electromagnetic interference (EMI) to the outside world.
本發明之另一目的在於提供一種源極驅動電路,其可藉由內部之一顯示控制信號處理電路產生具有時變占空比之一顯示資料控制時脈,以在該源極驅動電路驅動一畫素陣列時有效地降低對外界之電磁波干擾。Another object of the present invention is to provide a source drive circuit, which can generate a display data control clock with a time-varying duty cycle through an internal display control signal processing circuit to drive a source drive circuit Pixel array effectively reduces electromagnetic interference to the outside world.
本發明之又一目的在於提供一種顯示裝置,其可藉由一源極驅動電路之一顯示控制信號處理電路產生具有時變占空比之一顯示資料控制時脈,以在該源極驅動電路驅動一畫素陣列時有效地降低對外界之電磁波干擾。Another object of the present invention is to provide a display device, which can generate a display data control clock with a time-varying duty cycle by a source driving circuit and a display control signal processing circuit, so that the source driving circuit When driving a pixel array, it effectively reduces electromagnetic interference to the outside world.
為達成上述目的,一種顯示控制信號處理電路乃被提出,其具有:In order to achieve the above objective, a display control signal processing circuit is proposed, which has:
一資料接收及輸出單元,用以接收一輸入資料信號並依該輸入資料信號產生一輸出資料信號;A data receiving and output unit for receiving an input data signal and generating an output data signal according to the input data signal;
一多時鐘信號產生單元,用以依一輸入時鐘信號產生具不同占空比或具不同占空比且具不同相位的複數個候選時鐘信號;以及A multiple clock signal generation unit for generating a plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases according to an input clock signal; and
一多工器,用以依一選擇信號的動態控制,每次由所述複數個候選時鐘信號中擇一以產生一輸出時鐘信號。A multiplexer is used to generate an output clock signal by selecting one of the plurality of candidate clock signals each time according to the dynamic control of a selection signal.
在一實施例中,所述之顯示控制信號處理電路進一步具有一偽隨機選擇器以依該輸入時鐘信號的驅動產生一隨機數碼以決定該選擇信號的內容。In one embodiment, the display control signal processing circuit further has a pseudo-random selector to generate a random number according to the driving of the input clock signal to determine the content of the selection signal.
在一實施例中,所述之顯示控制信號處理電路進一步具有一向上計數選擇器以依該輸入時鐘信號的驅動以遞增的方式產生一動態數碼以決定該選擇信號的內容。In one embodiment, the display control signal processing circuit further has a count-up selector to generate a dynamic number in an incremental manner according to the driving of the input clock signal to determine the content of the selection signal.
在一實施例中,所述之顯示控制信號處理電路進一步具有一向下計數選擇器以依該輸入時鐘信號的驅動以遞減的方式產生一動態數碼以決定該選擇信號的內容。In one embodiment, the display control signal processing circuit further has a count-down selector to generate a dynamic number in a decremental manner according to the driving of the input clock signal to determine the content of the selection signal.
為達上述目的,本發明進一步提出一種源極驅動電路,其具有一顯示控制信號處理電路及一數位類比轉換電路,該數位類比轉換電路係用以依一輸出時鐘信號的控制將一輸出資料信號轉成一畫素電壓以驅動一畫素陣列,且該顯示控制信號處理電路具有:To achieve the above objective, the present invention further provides a source drive circuit, which has a display control signal processing circuit and a digital-to-analog conversion circuit, the digital-to-analog conversion circuit is used to control an output clock signal to convert an output data signal Converted to a pixel voltage to drive a pixel array, and the display control signal processing circuit has:
一資料接收及輸出單元,用以接收一輸入資料信號並依該輸入資料信號產生所述的輸出資料信號;A data receiving and output unit for receiving an input data signal and generating the output data signal according to the input data signal;
一多時鐘信號產生單元,用以依一輸入時鐘信號產生具不同占空比或具不同占空比且具不同相位的複數個候選時鐘信號;以及A multiple clock signal generation unit for generating a plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases according to an input clock signal; and
一多工器,用以依一選擇信號的動態控制,每次由所述複數個候選時鐘信號中擇一以產生所述的輸出時鐘信號。A multiplexer is used for generating the output clock signal by selecting one of the plurality of candidate clock signals according to the dynamic control of a selection signal.
在一實施例中,該顯示控制信號處理電路進一步具有一偽隨機選擇器以依該輸入時鐘信號的驅動產生一隨機數碼以決定該選擇信號的內容。In one embodiment, the display control signal processing circuit further has a pseudo-random selector to generate a random number according to the driving of the input clock signal to determine the content of the selection signal.
在一實施例中,該顯示控制信號處理電路進一步具有一向上計數選擇器以依該輸入時鐘信號的驅動以遞增的方式產生一動態數碼以決定該選擇信號的內容。In one embodiment, the display control signal processing circuit further has an up-count selector to generate a dynamic number in an incremental manner according to the driving of the input clock signal to determine the content of the selection signal.
在一實施例中,該顯示控制信號處理電路進一步具有一向下計數選擇器以依該輸入時鐘信號的驅動以遞減的方式產生一動態數碼以決定該選擇信號的內容。In one embodiment, the display control signal processing circuit further has a count-down selector to generate a dynamic number in a decremental manner according to the driving of the input clock signal to determine the content of the selection signal.
為達上述目的,本發明進一步提出一種顯示裝置,其具有一顯示控制器以及如前述之源極驅動電路和畫素陣列,其中,該顯示控制器係用以提供該輸入時鐘信號及該輸入資料信號。In order to achieve the above objective, the present invention further provides a display device having a display controller and the aforementioned source driving circuit and pixel array, wherein the display controller is used to provide the input clock signal and the input data signal.
在可能的實施例中,所述之顯示裝置可為液晶顯示裝置、有機發光二極體顯示裝置或微發光二極體顯示裝置。In possible embodiments, the display device may be a liquid crystal display device, an organic light emitting diode display device, or a micro light emitting diode display device.
為使  貴審查委員能進一步瞭解本發明之結構、特徵、目的、與其優點,茲附以圖式及較佳具體實施例之詳細說明如後。In order to enable your reviewer to further understand the structure, features, purpose, and advantages of the present invention, the drawings and detailed descriptions of preferred specific embodiments are attached as follows.
第一實施例First embodiment
請參照圖2,其繪示本發明顯示控制信號處理電路之第一實施例的方塊圖。如圖2所示,一顯示控制信號處理電路1(位於一源極驅動電路中)係用以耦接一顯示控制器2,即俗稱的Timing Controller (Tcon),以依一輸入資料信號Data_IN產生一輸出資料信號Data_OUT及依一輸入時鐘信號CLK_IN產生一輸出時鐘信號CLK_OUT。顯示控制信號處理電路1包括:一資料接收及輸出單元11、一多時鐘信號產生單元12、一多工器13以及一偽隨機選擇器(Pseudo random selector)14a。Please refer to FIG. 2, which shows a block diagram of the first embodiment of the display control signal processing circuit of the present invention. As shown in FIG. 2, a display control signal processing circuit 1 (located in a source drive circuit) is used to couple to a display controller 2, which is commonly known as Timing Controller (Tcon), to generate according to an input data signal Data_IN An output data signal Data_OUT and an output clock signal CLK_OUT are generated according to an input clock signal CLK_IN. The display control signal processing circuit 1 includes: a data receiving and outputting unit 11, a multi-clock signal generating unit 12, a multiplexer 13, and a pseudo random selector 14a.
資料接收及輸出單元11可為一資料緩衝器(Data buffer) ,用以依輸入資料信號Data_IN產生輸出資料信號Data_OUT。The data receiving and outputting unit 11 can be a data buffer for generating an output data signal Data_OUT according to the input data signal Data_IN.
多時鐘信號產生單元12係用以依輸入時鐘信號CLK_IN產生具不同占空比的複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)。由於占空比的控制電路已屬習知(例如電壓控制占空比電路),故在此不擬對其做進一步敘述。The multi-clock signal generating unit 12 is used to generate a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) with different duty cycles according to the input clock signal CLK_IN. Since the duty cycle control circuit is well-known (for example, a voltage controlled duty cycle circuit), it is not intended to be further described here.
多工器13係用以依一選擇信號SEL(可為串列信號或並行信號)的動態控制,每次由複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)中擇一以產生輸出時鐘信號CLK_OUT。The multiplexer 13 is used for dynamic control of a selection signal SEL (which can be a serial signal or a parallel signal), and each time one of a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) is selected to generate an output clock Signal CLK_OUT.
偽隨機選擇器14a係用以依輸入時鐘信號CLK_IN的驅動產生一隨機數碼以決定選擇信號SEL的內容。The pseudo-random selector 14a is used to generate a random number according to the driving of the input clock signal CLK_IN to determine the content of the selection signal SEL.
於操作時,對應輸入時鐘信號CLK_IN的N個脈衝,N為大於1的整數,輸出時鐘信號CLK_OUT的N個脈衝會有隨機變化的占空比,因此,輸出時鐘信號CLK_OUT的能量即可平均分配在一寬頻帶內,從而有效降低對外界的電磁波干擾。During operation, corresponding to the N pulses of the input clock signal CLK_IN, N is an integer greater than 1, and the N pulses of the output clock signal CLK_OUT will have a randomly varying duty cycle. Therefore, the energy of the output clock signal CLK_OUT can be evenly distributed In a wide frequency band, thereby effectively reducing electromagnetic interference to the outside world.
另外,在可能的變化實施例中,多時鐘信號產生單元12可依輸入時鐘信號CLK_IN產生具不同占空比且具不同相位的複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)。由於相位的控制電路已屬習知,故在此不擬對其做進一步敘述。In addition, in a possible variant embodiment, the multi-clock signal generating unit 12 can generate a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) with different duty cycles and different phases according to the input clock signal CLK_IN. Since the phase control circuit is well-known, it will not be described further here.
第二實施例Second embodiment
請參照圖3,其繪示本發明顯示控制信號處理電路之第二實施例的方塊圖。如圖3所示,一顯示控制信號處理電路1(位於一源極驅動電路中)係用以耦接一顯示控制器2,即俗稱的Timing Controller (Tcon),以依一輸入資料信號Data_IN產生一輸出資料信號Data_OUT及依一輸入時鐘信號CLK_IN產生一輸出時鐘信號CLK_OUT。顯示控制信號處理電路1包括:一資料接收及輸出單元11、一多時鐘信號產生單元12、一多工器13以及一向上計數選擇器14b。Please refer to FIG. 3, which shows a block diagram of a second embodiment of the display control signal processing circuit of the present invention. As shown in FIG. 3, a display control signal processing circuit 1 (located in a source driving circuit) is used to couple to a display controller 2, which is commonly known as Timing Controller (Tcon), to generate according to an input data signal Data_IN An output data signal Data_OUT and an output clock signal CLK_OUT are generated according to an input clock signal CLK_IN. The display control signal processing circuit 1 includes: a data receiving and outputting unit 11, a multi-clock signal generating unit 12, a multiplexer 13, and an up counting selector 14b.
資料接收及輸出單元11可為一資料緩衝器(Data buffer) ,用以依輸入資料信號Data_IN產生輸出資料信號Data_OUT。The data receiving and outputting unit 11 can be a data buffer for generating an output data signal Data_OUT according to the input data signal Data_IN.
多時鐘信號產生單元12係用以依輸入時鐘信號CLK_IN產生具不同占空比的複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)。由於占空比的控制電路已屬習知(例如電壓控制占空比電路),故在此不擬對其做進一步敘述。The multi-clock signal generating unit 12 is used to generate a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) with different duty cycles according to the input clock signal CLK_IN. Since the duty cycle control circuit is well-known (for example, a voltage controlled duty cycle circuit), it is not intended to be further described here.
多工器13係用以依一選擇信號SEL(可為串列信號或並行信號)的動態控制,每次由複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)中擇一以產生輸出時鐘信號CLK_OUT。The multiplexer 13 is used for dynamic control of a selection signal SEL (which can be a serial signal or a parallel signal), and each time one of a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) is selected to generate an output clock Signal CLK_OUT.
向上計數選擇器14b係用以依輸入時鐘信號CLK_IN的驅動以遞增的方式產生一動態數碼以決定選擇信號SEL的內容。The up-count selector 14b is used to generate a dynamic number in an incremental manner according to the driving of the input clock signal CLK_IN to determine the content of the selection signal SEL.
於操作時,對應輸入時鐘信號CLK_IN的N個脈衝,N為大於1的整數,輸出時鐘信號CLK_OUT的N個脈衝會有N個不同的占空比,因此,輸出時鐘信號CLK_OUT的能量即可平均分配在一寬頻帶內,從而有效降低對外界的電磁波干擾。During operation, corresponding to the N pulses of the input clock signal CLK_IN, N is an integer greater than 1, and the N pulses of the output clock signal CLK_OUT will have N different duty cycles. Therefore, the energy of the output clock signal CLK_OUT can be averaged Allocate in a wide frequency band to effectively reduce electromagnetic interference to the outside world.
另外,在可能的變化實施例中,多時鐘信號產生單元12可依輸入時鐘信號CLK_IN產生具不同占空比且具不同相位的複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)。由於相位的控制電路已屬習知,故在此不擬對其做進一步敘述。In addition, in a possible variant embodiment, the multi-clock signal generating unit 12 can generate a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) with different duty cycles and different phases according to the input clock signal CLK_IN. Since the phase control circuit is well-known, it will not be described further here.
第三實施例The third embodiment
請參照圖4,其繪示本發明顯示控制信號處理電路之第三實施例的方塊圖。如圖4所示,一顯示控制信號處理電路1(位於一源極驅動電路中)係用以耦接一顯示控制器2,即俗稱的Timing Controller (Tcon),以依一輸入資料信號Data_IN產生一輸出資料信號Data_OUT及依一輸入時鐘信號CLK_IN產生一輸出時鐘信號CLK_OUT。顯示控制信號處理電路1包括:一資料接收及輸出單元11、一多時鐘信號產生單元12、一多工器13以及一向下計數選擇器14c。Please refer to FIG. 4, which shows a block diagram of a third embodiment of the display control signal processing circuit of the present invention. As shown in FIG. 4, a display control signal processing circuit 1 (located in a source driving circuit) is used to couple to a display controller 2, which is commonly known as Timing Controller (Tcon), to generate according to an input data signal Data_IN An output data signal Data_OUT and an output clock signal CLK_OUT are generated according to an input clock signal CLK_IN. The display control signal processing circuit 1 includes: a data receiving and outputting unit 11, a multi-clock signal generating unit 12, a multiplexer 13, and a down counting selector 14c.
資料接收及輸出單元11可為一資料緩衝器(Data buffer) ,用以依輸入資料信號Data_IN產生輸出資料信號Data_OUT。The data receiving and outputting unit 11 can be a data buffer for generating an output data signal Data_OUT according to the input data signal Data_IN.
多時鐘信號產生單元12係用以依輸入時鐘信號CLK_IN產生具不同占空比的複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)。由於占空比的控制電路已屬習知(例如電壓控制占空比電路),故在此不擬對其做進一步敘述。The multi-clock signal generating unit 12 is used to generate a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) with different duty cycles according to the input clock signal CLK_IN. Since the duty cycle control circuit is well-known (for example, a voltage controlled duty cycle circuit), it is not intended to be further described here.
多工器13係用以依一選擇信號SEL(可為串列信號或並行信號)的動態控制,每次由複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)中擇一以產生輸出時鐘信號CLK_OUT。The multiplexer 13 is used for dynamic control of a selection signal SEL (which can be a serial signal or a parallel signal), and each time one of a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) is selected to generate an output clock Signal CLK_OUT.
向下計數選擇器14c係用以依輸入時鐘信號CLK_IN的驅動以遞減的方式產生一動態數碼以決定選擇信號SEL的內容。The down-counting selector 14c is used to generate a dynamic number in a decremental manner according to the driving of the input clock signal CLK_IN to determine the content of the selection signal SEL.
於操作時,對應輸入時鐘信號CLK_IN的N個脈衝,N為大於1的整數,輸出時鐘信號CLK_OUT的N個脈衝會有N個不同的占空比,因此,輸出時鐘信號CLK_OUT的能量即可平均分配在一寬頻帶內,從而有效降低對外界的電磁波干擾。During operation, corresponding to the N pulses of the input clock signal CLK_IN, N is an integer greater than 1, and the N pulses of the output clock signal CLK_OUT will have N different duty cycles. Therefore, the energy of the output clock signal CLK_OUT can be averaged Allocate in a wide frequency band to effectively reduce electromagnetic interference to the outside world.
另外,在可能的變化實施例中,多時鐘信號產生單元12可依輸入時鐘信號CLK_IN產生具不同占空比且具不同相位的複數個候選時鐘信號(CLK_1, CLK_2,…, CLK_N)。由於相位的控制電路已屬習知,故在此不擬對其做進一步敘述。In addition, in a possible variant embodiment, the multi-clock signal generating unit 12 can generate a plurality of candidate clock signals (CLK_1, CLK_2,..., CLK_N) with different duty cycles and different phases according to the input clock signal CLK_IN. Since the phase control circuit is well-known, it will not be described further here.
依上述的說明,本發明進一步提出一源極驅動電路。請參照圖5,其繪示本發明之源極驅動電路之一實施例方塊圖。如圖5所示,一源極驅動電路100包含一顯示控制信號處理電路110(由圖2-4中任一所示之顯示控制信號處理電路1實現)及一數位類比轉換電路120,其中,數位類比轉換電路120係用以依輸出時鐘信號CLK_OUT的控制將輸出資料信號Data_OUT轉成一畫素電壓V P以驅動一畫素陣列。由於輸出時鐘信號CLK_OUT的能量可平均分配在一寬頻帶內,故可有效降低源極驅動電路100對外界的電磁波干擾。 Based on the above description, the present invention further provides a source driving circuit. Please refer to FIG. 5, which shows a block diagram of an embodiment of the source driving circuit of the present invention. As shown in FIG. 5, a source driving circuit 100 includes a display control signal processing circuit 110 (implemented by the display control signal processing circuit 1 shown in any one of FIGS. 2-4) and a digital-to-analog conversion circuit 120, in which, The digital-to-analog conversion circuit 120 is used to convert the output data signal Data_OUT into a pixel voltage V P under the control of the output clock signal CLK_OUT to drive a pixel array. Since the energy of the output clock signal CLK_OUT can be evenly distributed in a wide frequency band, the electromagnetic wave interference of the source driving circuit 100 to the outside can be effectively reduced.
另外,本發明進一步提出一顯示裝置。請參照圖6,其繪示本發明之顯示裝置之一實施例方塊圖。如圖6所示,一顯示裝置200包含一顯示控制器210、一源極驅動電路220(由圖5之源極驅動電路100實現)及一畫素陣列230,其中,顯示控制器210係用以提供輸入時鐘信號CLK_IN及輸入資料信號Data_IN,源極驅動電路220係用以依輸出時鐘信號CLK_OUT(依輸入時鐘信號CLK_IN產生)的控制將輸出資料信號Data_OUT(依輸入資料信號Data_IN產生)轉成一畫素電壓V P以驅動一畫素陣列。由於源極驅動電路220內的輸出時鐘信號CLK_OUT的能量可平均分配在一寬頻帶內,故可有效降低顯示裝置200對外界的電磁波干擾。 In addition, the present invention further provides a display device. Please refer to FIG. 6, which shows a block diagram of an embodiment of the display device of the present invention. As shown in FIG. 6, a display device 200 includes a display controller 210, a source drive circuit 220 (implemented by the source drive circuit 100 of FIG. 5), and a pixel array 230, where the display controller 210 is used In order to provide the input clock signal CLK_IN and the input data signal Data_IN, the source driver circuit 220 is used to convert the output data signal Data_OUT (generated based on the input data signal Data_IN) under the control of the output clock signal CLK_OUT (generated based on the input clock signal CLK_IN) A pixel voltage V P is used to drive a pixel array. Since the energy of the output clock signal CLK_OUT in the source driving circuit 220 can be evenly distributed in a wide frequency band, the electromagnetic interference of the display device 200 to the outside can be effectively reduced.
另外,在可能的顯示裝置中,顯示裝置200可為液晶顯示裝置、有機發光二極體(OLED)顯示裝置或微發光二極體(Micro LED)顯示裝置。In addition, among possible display devices, the display device 200 may be a liquid crystal display device, an organic light emitting diode (OLED) display device, or a micro light emitting diode (Micro LED) display device.
另外,為了證實本發明之功效,本案發明人將顯示控制信號處理電路1整合在一顆源極驅動芯片中以作為實驗組,並使用未包含本發明之顯示控制信號處理電路1的源極驅動芯片作為對照組。實驗發現,相較於對照組,實驗組的電磁波干擾(EMI)大幅降低21.5%。In addition, in order to verify the efficacy of the present invention, the inventor of the present case integrated the display control signal processing circuit 1 into a source driver chip as an experimental group, and used the source driver that did not include the display control signal processing circuit 1 of the present invention. The chip served as a control group. The experiment found that compared with the control group, the electromagnetic interference (EMI) of the experimental group was significantly reduced by 21.5%.
如此,上述係已完整且清楚地說明本發明之技術方案;並且,經由上述可得知本發明具有下列優點:In this way, the above system has completely and clearly described the technical solution of the present invention; and from the above, it can be seen that the present invention has the following advantages:
(1)本發明之顯示控制信號處理電路可產生具有時變占空比之一顯示資料控制時脈,以在該源極驅動電路驅動一畫素陣列時有效地降低對外界之電磁波干擾(EMI)。(1) The display control signal processing circuit of the present invention can generate a display data control clock with a time-varying duty cycle, so as to effectively reduce electromagnetic interference (EMI) to the outside world when the source drive circuit drives a pixel array. ).
(2)本發明之源極驅動電路可藉由內部之一顯示控制信號處理電路產生具有時變占空比之一顯示資料控制時脈,以在該源極驅動電路驅動一畫素陣列時有效地降低對外界之電磁波干擾。(2) The source drive circuit of the present invention can generate a display data control clock with a time-varying duty cycle through an internal display control signal processing circuit, so as to be effective when the source drive circuit drives a pixel array Ground to reduce electromagnetic interference to the outside world.
(3)本發明之顯示裝置可藉由一源極驅動電路之一顯示控制信號處理電路產生具有時變占空比之一顯示資料控制時脈,以在該源極驅動電路驅動一畫素陣列時有效地降低對外界之電磁波干擾。(3) The display device of the present invention can generate a display data control clock with a time-varying duty cycle by a source driving circuit and a display control signal processing circuit to drive a pixel array in the source driving circuit Effectively reduce electromagnetic interference to the outside world.
必須加以強調的是,前述本案所揭示者乃為較佳實施例,舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者,俱不脫本案之專利權範疇。It must be emphasized that the foregoing disclosures in this case are preferred embodiments, and any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those who are familiar with the art will not deviate from the patent of this case. Right category.
綜上所陳,本案無論目的、手段與功效,皆顯示其迥異於習知技術,且其首先發明合於實用,確實符合發明之專利要件,懇請  貴審查委員明察,並早日賜予專利俾嘉惠社會,是為至禱。In summary, regardless of the purpose, means and effects of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. Please check it out and grant the patent as soon as possible. Society is for the best prayer.
<本發明><The present invention>
1:顯示控制信號處理電路1: Display control signal processing circuit
2:顯示控制器2: display controller
11:資料接收及輸出單元11: Data receiving and output unit
12:多時鐘信號產生單元12: Multiple clock signal generation unit
13:多工器13: Multiplexer
14a:偽隨機選擇器14a: pseudo-random selector
14b:向上計數選擇器14b: Up counting selector
14c:向下計數選擇器14c: Down-count selector
100:源極驅動電路100: Source drive circuit
110:顯示控制信號處理電路110: Display control signal processing circuit
120:數位類比轉換電路120: Digital analog conversion circuit
200:顯示裝置200: display device
210:顯示控制器210: display controller
220:源極驅動電路220: Source drive circuit
230:畫素陣列230: pixel array
<習知><Acquaintances>
1’:顯示控制信號處理電路1’: Display control signal processing circuit
2’:顯示控制器2’: Display Controller
11’:時鐘信號產生單元11’: Clock signal generating unit
12’:資料緩衝單元12’: Data buffer unit
圖1繪示一習知顯示控制信號處理電路的方塊圖。 圖2繪示本發明顯示控制信號處理電路之第一實施例的方塊圖。 圖3繪示本發明顯示控制信號處理電路之第二實施例的方塊圖。 圖4繪示本發明顯示控制信號處理電路之第三實施例的方塊圖。 圖5繪示本發明之源極驅動電路之一實施例方塊圖。 圖6繪示本發明之顯示裝置之一實施例方塊圖。 FIG. 1 shows a block diagram of a conventional display control signal processing circuit. 2 is a block diagram of the first embodiment of the display control signal processing circuit of the present invention. FIG. 3 is a block diagram of a second embodiment of the display control signal processing circuit of the present invention. 4 is a block diagram of a third embodiment of the display control signal processing circuit of the present invention. FIG. 5 shows a block diagram of an embodiment of the source driving circuit of the present invention. FIG. 6 is a block diagram of an embodiment of the display device of the present invention.
1:顯示控制信號處理電路 1: Display control signal processing circuit
2:顯示控制器 2: display controller
11:資料接收及輸出單元 11: Data receiving and output unit
12:多時鐘信號產生單元 12: Multiple clock signal generation unit
13:多工器 13: Multiplexer
14a:偽隨機選擇器 14a: pseudo-random selector

Claims (10)

  1. 一種顯示控制信號處理電路,其具有: 一資料接收及輸出單元,用以接收一輸入資料信號並依該輸入資料信號產生一輸出資料信號; 一多時鐘信號產生單元,用以依一輸入時鐘信號產生具不同占空比或具不同占空比且具不同相位的複數個候選時鐘信號;以及 一多工器,用以依一選擇信號的動態控制,每次由所述複數個候選時鐘信號中擇一以產生一輸出時鐘信號。 A display control signal processing circuit, which has: A data receiving and output unit for receiving an input data signal and generating an output data signal according to the input data signal; A multiple clock signal generation unit for generating a plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases according to an input clock signal; and A multiplexer is used to generate an output clock signal by selecting one of the plurality of candidate clock signals each time according to the dynamic control of a selection signal.
  2. 如申請專利範圍第1項所述之顯示控制信號處理電路,其進一步具有一偽隨機選擇器以依該輸入時鐘信號的驅動產生一隨機數碼以決定該選擇信號的內容。For example, the display control signal processing circuit described in item 1 of the scope of patent application further has a pseudo-random selector to generate a random number according to the driving of the input clock signal to determine the content of the selection signal.
  3. 如申請專利範圍第1項所述之顯示控制信號處理電路,其進一步具有一向上計數選擇器以依該輸入時鐘信號的驅動以遞增的方式產生一動態數碼以決定該選擇信號的內容。For example, the display control signal processing circuit described in item 1 of the scope of patent application further has an up-count selector to generate a dynamic number in an incremental manner according to the driving of the input clock signal to determine the content of the selection signal.
  4. 如申請專利範圍第1項所述之顯示控制信號處理電路,其進一步具有一向下計數選擇器以依該輸入時鐘信號的驅動以遞減的方式產生一動態數碼以決定該選擇信號的內容。For example, the display control signal processing circuit described in item 1 of the scope of patent application further has a count-down selector to generate a dynamic number in a decremental manner according to the driving of the input clock signal to determine the content of the selection signal.
  5. 一種源極驅動電路,其具有一顯示控制信號處理電路及一數位類比轉換電路,該數位類比轉換電路係用以依一輸出時鐘信號的控制將一輸出資料信號轉成一畫素電壓以驅動一畫素陣列,且該顯示控制信號處理電路具有: 一資料接收及輸出單元,用以接收一輸入資料信號並依該輸入資料信號產生所述的輸出資料信號; 一多時鐘信號產生單元,用以依一輸入時鐘信號產生具不同占空比或具不同占空比且具不同相位的複數個候選時鐘信號;以及 一多工器,用以依一選擇信號的動態控制,每次由所述複數個候選時鐘信號中擇一以產生所述的輸出時鐘信號。 A source driving circuit has a display control signal processing circuit and a digital-to-analog conversion circuit. The digital-to-analog conversion circuit is used to convert an output data signal into a pixel voltage under the control of an output clock signal to drive a pixel voltage. Pixel array, and the display control signal processing circuit has: A data receiving and output unit for receiving an input data signal and generating the output data signal according to the input data signal; A multiple clock signal generation unit for generating a plurality of candidate clock signals with different duty cycles or with different duty cycles and different phases according to an input clock signal; and A multiplexer is used for generating the output clock signal by selecting one of the plurality of candidate clock signals according to the dynamic control of a selection signal.
  6. 如申請專利範圍第5項所述之源極驅動電路,其中該顯示控制信號處理電路進一步具有一偽隨機選擇器以依該輸入時鐘信號的驅動產生一隨機數碼以決定該選擇信號的內容。According to the source driving circuit described in item 5 of the patent application, the display control signal processing circuit further has a pseudo-random selector to generate a random number according to the driving of the input clock signal to determine the content of the selection signal.
  7. 如申請專利範圍第5項所述之源極驅動電路,其中該顯示控制信號處理電路進一步具有一向上計數選擇器以依該輸入時鐘信號的驅動以遞增的方式產生一動態數碼以決定該選擇信號的內容。The source driving circuit described in item 5 of the scope of patent application, wherein the display control signal processing circuit further has an up-counting selector to generate a dynamic number in an incremental manner according to the driving of the input clock signal to determine the selection signal Content.
  8. 如申請專利範圍第5項所述之源極驅動電路,其中該顯示控制信號處理電路進一步具有一向下計數選擇器以依該輸入時鐘信號的驅動以遞減的方式產生一動態數碼以決定該選擇信號的內容。The source driving circuit as described in item 5 of the scope of patent application, wherein the display control signal processing circuit further has a down-counting selector to generate a dynamic number in a decreasing manner according to the driving of the input clock signal to determine the selection signal Content.
  9. 一種顯示裝置,其具有一顯示控制器、如申請專利範圍第5至8項中任一項所述之源極驅動電路及畫素陣列,其中,該顯示控制器係用以提供該輸入時鐘信號及該輸入資料信號。A display device having a display controller, the source drive circuit and pixel array according to any one of the 5th to 8th items of the scope of patent application, wherein the display controller is used to provide the input clock signal And the input data signal.
  10. 如申請專利範圍第9項所述之顯示裝置,其係由液晶顯示裝置、有機發光二極體顯示裝置和微發光二極體顯示裝置所組成的群組所選擇的一種顯示裝置。The display device described in item 9 of the scope of patent application is a display device selected from the group consisting of a liquid crystal display device, an organic light emitting diode display device, and a micro light emitting diode display device.
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TW200951911A (en) * 2008-03-20 2009-12-16 Anapass Inc Display device and method for transmitting clock signal during blank period
TW201434017A (en) * 2013-02-20 2014-09-01 Novatek Microelectronics Corp Display driving apparatus and method for driving display panel
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