TWI708527B - Circuit board - Google Patents

Abstract

A circuit board includes a flexible substrate, a first conductive pattern layer, and at least one drive chip. The flexible substrate includes a central area, a test area, and two sprocket areas. The test area surrounds the central area, and two sprocket areas are located outside the opposite sides of the test area. The first conductive pattern layer includes a plurality of test pads, a plurality of input pads, a plurality of output pads, and a circuit pattern. The circuit pattern is located in the central area. The input pads and the output pads are located in the central area and respectively adjacent to the two opposite second edges of the central area. The test pads are located within the test area and respectively adjacent to the two opposing first edges of the central area. The driving chip is located in the central area and electrically connected to the first conductive pattern layer.

Description

Circuit board

The invention relates to a circuit structure, especially a circuit board.

The design of current display devices is developing towards a high-resolution trend. In the pursuit of high resolution, more and more drive chips or other electronic components are required on the circuit board, and the layout of the drive circuit is becoming more and more complicated. Therefore, the display device is more sensitive to the drive chip or other electronic components. The requirements for component protection are becoming increasingly stringent.

Generally speaking, a display device includes a display panel, a circuit board, and a system circuit board. The circuit structure of a commonly used circuit board is to arrange the driving chip and other electronic components on the circuit board, and the circuit board is electrically connected to the display panel through a plurality of output pads and is electrically connected to the system circuit board through a plurality of input pads. There are a plurality of test pads on the circuit board. However, these test pads are arranged on the adjacent sides of the plurality of output pads and output pads and are close to the display panel side and the system circuit board side, respectively. Therefore, the lines of the output pads and the output pads The layout needs to reserve space to set up these test pads. In this way, the pitch between the test pad and the plurality of input pads and output pads is dense.

An embodiment of the present invention provides a circuit board, which includes a flexible substrate, a first conductive pattern layer, and at least one driving chip. The flexible substrate has a first surface and a second surface opposite to the first surface. The soft base material includes the central area, the test area and the second transmission area. The central area has two first edges and two second edges, the two first edges are opposite to each other and the two second edges are opposite to each other, and each The first edge and each second edge are connected to each other. The test area surrounds the two first edges and the two second edges of the central area, and the two transmission areas are respectively located outside the opposite sides of the test area and correspond to the two first edges of the central area. The first conductive pattern layer is located on the first surface and includes a plurality of test pads, a plurality of input pads, a plurality of output pads, and a circuit pattern. The circuit pattern is located in the central area. The input pads and the output pads are located in the central area and are respectively adjacent to the two second edges of the central area. These test pads are located in the test area and are respectively adjacent to the two first edges of the central area. The driving chip is located on the first surface and in the central area, and the driving chip is electrically connected to the first conductive pattern layer.

In summary, in the circuit board of the embodiment of the present invention, these test pads are located in the test area instead of in the bonding area and are adjacent to the input pads and the output pads. Compared with the conventional test pads located adjacent to the plurality of input pads and output pads, the embodiment of the present invention can improve the problem of dense pitch between the plurality of test pads and the plurality of input pads and output pads. Therefore, the conventional test pad occupies additional layout space of the input pad and the output pad.

100: circuit board

110: Flexible substrate

111: first surface

112: second surface

120: first conductive pattern layer

121: test pad

122: input pad

123: output pad

124: circuit pattern

125: chip pad

130: driver chip

140: second conductive pattern layer

150: Protective paint

ACF: Anisotropic conductive adhesive

CF: Color filter substrate

D: Distribution range

H: Transmission hole

ITO: Line

L1: first edge

L11: first line segment

L12: second line segment

L2: second edge

M1: Central District

M11: Line area

M12: junction area

M2: test area

M3: Transmission area

TS: Thin film transistor substrate

PL: display panel

PCB: system circuit board

V: Through hole

FIG. 1 is a top view of a circuit board according to an embodiment of the invention.

2 is a schematic cross-sectional view of the circuit board corresponding to the A-A section line of FIG. 1.

3 is a schematic cross-sectional view of the circuit board corresponding to the line B-B in FIG. 1.

4 is a side view of a circuit board disposed on a display panel according to an embodiment of the invention.

Fig. 5 is a bottom view of a circuit board according to an embodiment of the invention.

Fig. 6 is a bottom view of a circuit board according to another embodiment of the invention.

FIG. 7 is a top view of a circuit board according to another embodiment of the invention.

FIG. 8 is a top view of a circuit board according to another embodiment of the invention.

FIG. 9 is a top view of a circuit board according to another embodiment of the invention.

FIG. 10 is a top view of a circuit board according to another embodiment of the invention.

FIG. 11 is a top view of a circuit board according to another embodiment of the invention.

FIG. 12 is a top view of a circuit board according to another embodiment of the invention.

FIG. 13 is a top view of a circuit board according to another embodiment of the invention.

FIG. 1 is a top view of a circuit board according to an embodiment of the invention. 2 is a schematic cross-sectional view of the circuit board corresponding to the A-A section line of FIG. 1. 3 is a schematic cross-sectional view of the circuit board corresponding to the line B-B in FIG. 1. Please refer to FIGS. 1, 2 and 3, the circuit board 100 includes a flexible substrate 110, a first conductive pattern layer 120 and at least one driving chip 130. The first conductive pattern layer 120 is disposed on the flexible substrate 110, and the driving chip 130 is disposed on the first conductive pattern layer 120.

The flexible substrate 110 has a first surface 111 and a second surface 112 opposite to the first surface 111. The viewing angle depicted in FIG. 1 is the viewing angle of looking down on the first surface 111. The flexible substrate 110 includes a central area M1, a test area M2, and a second transmission area M3. The test area M2 surrounds the central area M1, and the two transmission areas M3 are respectively located outside the opposite sides of the test area M2.

As shown in FIG. 1, the central area M1 has two first edges L1 and two second edges L2. The two first edges L1 are opposite to each other and the two second edges L2 are opposite to each other, and each first edge L1 and each second edge L2 are connected to each other. The central area M1 has a circuit area M11 and two junction areas M12. The two junction areas M12 are located on two opposite sides of the circuit area M11 and are respectively adjacent to the two second edges L2. The test area M2 has a frame shape and surrounds the two first edges L1 and the two second edges L2 of the central area M1. The two transmission areas M3 are respectively located at the two first edges L1 of the central area M1 on opposite sides of the test area M2.

Please refer to FIG. 4, which is a side view of a circuit board disposed on a display panel according to an embodiment of the present invention. FIG. 4 corresponds to the B-B section line in FIG. In the subsequent assembly process of the display device, the circuit board 100 can be processed to cut the test area M2 and the second transmission area M3, that is, cut along each first edge L1 and each second edge L2, leaving only the central area M1. Generally speaking, the display device roughly includes a display panel PL, a circuit board 100 and a system circuit board PCB, and the display panel PL includes a color filter substrate CF and a thin film transistor substrate TS. One end of the central area M1 located on the first surface 111 of the flexible substrate 110 can be electrically connected to the line ITO of the thin film transistor substrate TS of the display panel PL by an anisotropic conductive adhesive ACF, and is located on the first surface of the flexible substrate 110 The other end of the central area M1 of the surface 111 can be electrically connected to the system circuit board PCB.

In one embodiment, the flexible substrate 110 has a plurality of transmission holes H located in the transmission area M3, and the flexible substrate 110 can use these transmission holes H and the rollers (not shown in the figure) of the transmission machine (Shown) engage to drive the flexible substrate 110 to move. In one embodiment, the flexible substrate 110 is an insulating sheet with flexibility. In another embodiment, the flexible substrate 110 is an insulating sheet with light permeability. The material of the flexible substrate 110 is, for example, but not limited to, polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), polycarbonate (polycarbonate). , PC), or a combination of at least two of the above materials, or other suitable materials.

The first conductive pattern layer 120 is located on the first surface 111 of the flexible substrate 110. The first conductive pattern layer 120 includes a plurality of test pads 121, a plurality of input pads 122, a plurality of output pads 123 and a circuit pattern 124.

The test pads 121 are located in the test area M2 and are respectively adjacent to the two first edges L1 of the test area M2. In other words, some of the test pads 121 are adjacent to the two first edges L1 One of them, and another of the test pads 121 is adjacent to the other of the two first edges L1. In one embodiment, the test pads 121 can be electrically connected to the driving chip 130 through the traces of the circuit pattern 124 (not shown in the figure). These test pads 121 can receive external electrical signals to perform electrical testing of the circuit pattern 124, the driving chip 130 and/or the display panel PL. In an implementation aspect, some of the test pads 121 are a plurality of output test pads for outputting electrical signals for testing; and, some of the test pads 121 are a plurality of input test pads for receiving external telecommunications number.

The input pads 122 and the output pads 123 are located in the central area M1 and are respectively adjacent to the two second edges L2 of the central area M1. In one implementation, as shown in FIG. 1, these input pads 122 are located in the central area M1 adjacent to the bonding area M12 of the system circuit board, and these output pads 123 are located in the central area M1 adjacent to the bonding area of the display panel PL Area M12. In an implementation aspect, the input pads 122 and the output pads 123 are gold fingers.

In one embodiment, the circuit pattern 124 is located in the circuit area M11 of the central area M1. Wherein, since the circuit pattern 124 is covered by the protective paint 150 (detailed structure will be described later), the circuit pattern 124 is omitted in FIG. 1.

At least one driving chip 130 is located on the first surface 111 of the flexible substrate 110 and located in the central area M1. The driving chip 130 is electrically connected to the first conductive pattern layer 120. In one embodiment, as shown in FIG. 1, the number of driving chips 130 is two. However, it should be noted that the number of driving chips 130 shown in FIG. 1 is only an example, not a limitation of the embodiment of the present invention.

In one embodiment, as shown in FIGS. 1, 2 and 3, the circuit board 100 further includes a second conductive pattern layer 140. The second conductive pattern layer 140 is located on the second surface 112 of the flexible substrate 110. The second conductive pattern layer 140 is electrically connected to the first conductive pattern layer 120. In a mode of implementation As shown in FIG. 3, the flexible substrate 110 has a through hole V, and the through hole V connects the first surface 111 and the second surface 112. In one embodiment, the second conductive pattern layer 140 is electrically connected to the first conductive pattern layer 120 through the conductive pillars in the through holes V.

In one embodiment, the second conductive pattern layer 140 is electrically connected to a plurality of test pads 121, so as to transmit external electrical signals to the test pads 121 and/or electrical signals sent by the test pads 121 Transmit to the outside world. Here, the distribution range D of the second conductive pattern layer 140 at least corresponds to the distribution range of the test pads 121.

In an implementation aspect, FIGS. 5 and 6 are both bottom views of the circuit board according to an embodiment of the present invention, and the viewing angles shown in FIGS. 5 and 6 are the viewing angles looking down on the second surface 112. Among them, the distribution range D of the second conductive pattern layer 140 is represented by a dotted chain line. In addition, in order to clearly show that the distribution range D of the second conductive pattern layer 140 on the second surface 112 corresponds to all the elements on the first surface 111 In relation to this, all elements located on the first surface 111 are represented by dashed lines. Referring to FIGS. 3 and 5, since these test pads 121 are located on the first surface 111 and are located in the test area M2, similarly, the second conductive pattern layer 140 is located on the second surface 112 and the second conductive pattern layer 140 The distribution range D of is at least in the test area M2.

Further, referring to FIGS. 3 and 6, the distribution range D of the second conductive pattern layer 140 may be more located in the circuit area M11 depending on the circuit design. In addition, the second conductive pattern layer 140 may not cover the bonding area M12 on the PCB side of the corresponding system circuit board, that is, the distribution range D of the second conductive pattern layer 140 does not overlap the bonding area M12 on the PCB side of the corresponding system circuit board. Here, when the circuit board 100 is assembled with the display panel PL and the system circuit board PCB and the appearance inspection is performed to detect depressions, protrusions, short circuits, etc., the bonding area M12 of the second surface 112 of the circuit board 100 can be directly moved to the first The appearance of the input pad 122 and the circuit board 100 can be detected by viewing the surface 111 Then, the line of sight will not be blocked by the line ITO.

The shapes of the first edge L1 and the second edge L2 of the central area M1 can have various embodiments. In one embodiment, as shown in FIG. 1, each first edge L1 and each second edge L2 are straight lines. Here, the top view shape of the central area M1 may be a rectangle.

In one embodiment, each first edge L1 only has a first line segment L11 that is concave toward the inside of the circuit area M11, and each second edge L2 is a straight line. In other words, the top view shape of the central area M1 is approximately an hourglass shape. In one embodiment, as shown in FIG. 7, the first line segment L11 may be V-shaped, and the tip of each first line segment L11 is directed to the circuit area M11 and is opposite to each other. In one embodiment, as shown in FIG. 8, the first line segment L11 may be U-shaped, and the protruding ends of each first line segment L11 all point to the circuit area M11 and are opposite to each other.

In an embodiment, as shown in FIG. 9, the first line segment L11 may be arc-shaped, and the arc ends of each first line segment L11 all point to the line area M11 and are opposite to each other.

In an implementation aspect, please refer to FIGS. 7, 8 and 9, some of the test pads 121 are adjacent to one of the first line segments L11, and some of the test pads 121 are adjacent to the other of the first line segments L11. A line segment L11. In other words, the test pads 121 are respectively distributed in the recesses of the first line segment L11 facing the inner line area M11.

In one embodiment, each first edge L1 has a first line segment L11 and two second line segments L12. The first line segment L11 is recessed toward the inside of the circuit area M11, and the two second line segments L12 are perpendicular to the second edge L2 and are respectively connected to the first line segment L11 and one of the second edges L2. In other words, the top view shape of the central area M1 is also similar to an hourglass shape.

In one embodiment, as shown in FIG. 10, the first line segment L11 may be V-shaped, and the tip of each first line segment L11 is directed to the circuit area M11 and is opposite to each other. In a mode of implementation 11, the first line segment L11 may be U-shaped, and the protruding ends of each first line segment L11 all point to the line area M11 and are opposite to each other. In one embodiment, as shown in FIG. 12, the first line segment L11 may be arc-shaped, and the arc ends of each first line segment L11 all point to the line area M11 and are opposite to each other.

In an implementation aspect, please refer to FIG. 10, FIG. 11 and FIG. 12, some of the test pads 121 are adjacent to one of the first line segments L11, and some of the test pads 121 are adjacent to the other of the first line segments L11. A line segment L11. In other words, the test pads 121 are respectively distributed in the recesses of the first line segment L11 facing the inner line area M11.

In an implementation aspect, please refer to FIG. 10, FIG. 11, and FIG. 12. The input pads 122 and the output pads 123 are gold finger patterns, so the width of each junction area M12 is approximately equivalent to the input pads 122 or For the pad lengths of the output pads 123, the length of each second line segment L12 is greater than or equal to the width of each bonding area M12. Here, this design can maintain the range of the junction area M12.

In one embodiment, as shown in FIG. 13, the first conductive pattern layer 120 further includes a plurality of die pads 125, and the die pads 125 are located in the circuit region M11 of the central region M1. In one embodiment, the chip pads 125 are internal pins of the driver chip 130 or conductive bumps. In one embodiment, at least one of the chip pads 125 is electrically connected to at least one of the input pads 122, and at least one of the chip pads 125 is electrically connected to at least one of the output pads 123.

In one embodiment, as shown in FIGS. 1 to 12, to protect the first conductive pattern layer 120 in the circuit area M11, the circuit board 100 further includes a protective paint 150. The protective paint 150 is located in the circuit area M11 and covers the circuit pattern 124. In one implementation aspect, the protective paint 150 is a solder mask or solder resist commonly known as green paint and ink (Solder Mask or Solder Resist) to avoid the circuit pattern 124 Scratches that cause short circuits and/or open circuits.

In one embodiment, as shown in FIG. 13, in order to avoid electrical insulation, the protective varnish 150 does not cover the chip pads 125, nor does it cover the input pads 122 and output pads 123.

In summary, in the circuit board of the embodiment of the present invention, these test pads are located in the test area instead of in the bonding area and are adjacent to the input pads and the output pads. Compared with the conventional test pads located adjacent to the plurality of input pads and output pads, the embodiment of the present invention can improve the problem of dense pitch between the plurality of test pads and the plurality of input pads and output pads. Therefore, the conventional test pad occupies additional layout space of the input pad and the output pad.

Although the technical content of the present invention has been disclosed in the preferred embodiments as above, it is not intended to limit the present invention. Anyone who is familiar with this technique and makes some changes and modifications without departing from the spirit of the present invention should be covered by the present invention Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

100: circuit board

110: Flexible substrate

111: first surface

121: test pad

122: input pad

123: output pad

130: driver chip

150: Protective paint

H: Transmission hole

L1: first edge

L2: second edge

M1: Central District

M11: Line area

M12: junction area

M2: test area

M3: Transmission area

Claims (10)

A circuit board includes: a flexible substrate having a first surface and a second surface opposite to the first surface. The flexible substrate includes a central area, a test area and two transmission areas. The central area has Two first edges and two second edges, the two first edges are opposite to each other and the two second edges are opposite to each other, and each of the first edges and each of the second edges are connected to each other, and the test area surrounds the central area The two first edges and the two second edges, the two transmission areas are respectively located outside the opposite sides of the test area and corresponding to the two first edges of the central area; a first conductive pattern layer is located on the first surface, The first conductive pattern layer includes a plurality of test pads, a plurality of input pads, a plurality of output pads, and a circuit pattern. The circuit pattern is located in the central area, the input pads and the output pads are located in the central area and are respectively Adjacent to the two second edges of the central area, the test pads are located in the test area and respectively adjacent to the two first edges of the central area; and at least one drive chip is located on the first surface and located in the central area , The at least one driving chip is electrically connected to the first conductive pattern layer. The circuit board according to claim 1, wherein the central area has a circuit area and two bonding areas located on two opposite sides of the circuit area, the two bonding areas are respectively adjacent to the two second edges, and the input pads are located in one of them In one bonding area, the output pads are located in the other bonding area, and the circuit pattern is located in the circuit area. The circuit board according to claim 1, further comprising a second conductive pattern layer, the second conductive pattern layer is located on the second surface, the flexible substrate has a through hole, and the second conductive pattern layer The through hole is electrically connected to the first conductive pattern layer. The circuit board according to claim 1, wherein the first conductive pattern layer further includes a plurality of chip pads, the chip pads are located in the central area, and at least one of the chip pads is electrically connected to the inputs At least one of the pads, and at least one of the chip pads is electrically connected to at least one of the output pads. The circuit board according to claim 2, wherein each of the first edges has at least one first line segment that is concave toward the direction of the circuit area. The circuit board according to claim 2, wherein each of the first edges has at least one first line segment recessed in the direction of the circuit area and two second line segments perpendicular to the second edge, each of the second edges The line segment is connected to the at least one first line segment and one of the second edges, and the length of each second line segment is greater than or equal to the width of each joining area. The circuit board according to claim 5 or 6, wherein the number of the at least one first line segment is two, some of the test pads are adjacent to one of the two first line segments, and one of the test pads Others are adjacent to the other of the two first line segments. The circuit board according to claim 2, further comprising a protective paint, which is located in the circuit area and covers the circuit pattern. The circuit board according to claim 2, further comprising a second conductive pattern layer, and the second conductive pattern layer is located on the second surface and does not cover at least one of the bonding areas. The circuit board according to claim 2, further comprising a second conductive pattern layer, and the second conductive pattern layer is located on the circuit area and the test area on the second surface.

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