TWI706460B - Plasma etching method - Google Patents

Plasma etching method Download PDF

Info

Publication number
TWI706460B
TWI706460B TW105138041A TW105138041A TWI706460B TW I706460 B TWI706460 B TW I706460B TW 105138041 A TW105138041 A TW 105138041A TW 105138041 A TW105138041 A TW 105138041A TW I706460 B TWI706460 B TW I706460B
Authority
TW
Taiwan
Prior art keywords
plasma
frequency power
film
gas
plasma etching
Prior art date
Application number
TW105138041A
Other languages
Chinese (zh)
Other versions
TW201721739A (en
Inventor
高山航
冨永翔
五十嵐義樹
Original Assignee
日商東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東京威力科創股份有限公司 filed Critical 日商東京威力科創股份有限公司
Publication of TW201721739A publication Critical patent/TW201721739A/en
Application granted granted Critical
Publication of TWI706460B publication Critical patent/TWI706460B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本發明之目的在於將於氧化矽膜與氮化矽膜之界面產生之階差去除。 本發明提供一種電漿蝕刻方法，其包含：第1步驟，其係使用第1高頻電源所輸出之第1高頻電力自包含含氟氣體之第1處理氣體生成電漿，並利用所生成之電漿對氧化矽膜與氮化矽膜之積層膜進行蝕刻；及第2步驟，其係於上述第1步驟之後，使用上述第1高頻電力自包含含溴氣體之第2處理氣體生成電漿，並利用所生成之電漿對上述積層膜進行蝕刻。The purpose of the present invention is to remove the step difference generated at the interface between the silicon oxide film and the silicon nitride film. The present invention provides a plasma etching method comprising: a first step of generating plasma from a first processing gas containing a fluorine-containing gas using first high-frequency power output from a first high-frequency power supply, and using the generated plasma The plasma etches the laminated film of the silicon oxide film and the silicon nitride film; and the second step, which is after the first step, is generated from the second process gas containing bromine-containing gas using the first high-frequency power Plasma is used to etch the above-mentioned laminated film using the generated plasma.

Description

電漿蝕刻方法Plasma etching method

本發明係關於一種電漿蝕刻方法。The invention relates to a plasma etching method.

已知有如下方法，即，於製造3D-NAND(Not AND，反及)快閃記憶體等三維積層半導體記憶體時，藉由進行電漿蝕刻，而對氧化矽膜與氮化矽膜之積層膜進行蝕刻，從而形成高縱橫比之孔(hole)或溝槽(槽)。 於該方法中，於氧化矽膜之蝕刻速度與氮化矽膜之蝕刻速度不同之情形時，會於氧化矽膜與氮化矽膜之界面產生階差(紋狀凹凸構造)。若如此般產生階差，則例如於之後之步驟中形成於孔或溝槽之膜容易剝離等而可靠性降低。 因此，先前，例如使用NF3 氣體與CH3 F氣體之混合氣體進行電漿蝕刻，藉此，一面抑制階差之產生一面對積層膜進行蝕刻(例如參照專利文獻1)。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特開2015-144158號公報The following method is known. When manufacturing three-dimensional laminated semiconductor memory such as 3D-NAND (Not AND) flash memory, plasma etching is performed to reduce the gap between the silicon oxide film and the silicon nitride film. The laminated film is etched to form holes or trenches (grooves) with a high aspect ratio. In this method, when the etching rate of the silicon oxide film is different from the etching rate of the silicon nitride film, a step difference (striated uneven structure) occurs at the interface between the silicon oxide film and the silicon nitride film. If a step difference occurs in this way, for example, the film formed in the hole or groove in a subsequent step will easily peel off, and the reliability will decrease. Therefore, conventionally, plasma etching is performed using, for example, a mixed gas of NF 3 gas and CH 3 F gas, whereby the layered film is etched while suppressing the generation of steps (for example, refer to Patent Document 1). [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open No. 2015-144158

[發明所欲解決之問題] 然而，於上述方法中，雖然於積層膜之蝕刻時產生之階差得到抑制，但未揭示產生階差之情形時將階差去除之方法。因此，於上述方法中，於因對氧化矽膜與氮化矽膜之積層膜進行蝕刻而於氧化矽膜與氮化矽膜之界面產生階差之情形時，蝕刻形狀變差。 針對上述課題，於一態樣中，本發明之目的在於將於氧化矽膜與氮化矽膜之界面產生之階差去除。 [解決問題之技術手段] 為了解決上述課題，根據一態樣，提供一種電漿蝕刻方法，其包含：第1步驟，其係使用第1高頻電源所輸出之第1高頻電力自包含含氟氣體之第1處理氣體生成電漿，並利用所生成之電漿對氧化矽膜與氮化矽膜之積層膜進行蝕刻；及 第2步驟，其係於上述第1步驟之後，使用上述第1高頻電力自包含含溴氣體之第2處理氣體生成電漿，並利用所生成之電漿對上述積層膜進行蝕刻。 [發明之效果] 根據一態樣，可將於氧化矽膜與氮化矽膜之界面產生之階差去除。[Problem to be Solved by the Invention] However, in the above method, although the step difference generated during the etching of the laminated film is suppressed, the method of removing the step difference when the step difference occurs is not disclosed. Therefore, in the above method, when a step difference occurs at the interface between the silicon oxide film and the silicon nitride film due to the etching of the laminated film of the silicon oxide film and the silicon nitride film, the etching shape becomes worse. In view of the above-mentioned problems, in one aspect, the object of the present invention is to remove the step difference generated at the interface between the silicon oxide film and the silicon nitride film. [Technical Means to Solve the Problem] In order to solve the above-mentioned problems, according to one aspect, a plasma etching method is provided, which includes: a first step, which uses the first high-frequency power output from the first high-frequency power source to self-contain The first process gas of the fluorine gas generates plasma, and the generated plasma is used to etch the laminated film of the silicon oxide film and the silicon nitride film; and the second step, which is after the first step, uses the first 1 High-frequency power generates plasma from the second process gas containing bromine-containing gas, and the above-mentioned laminated film is etched by the generated plasma. [Effects of the Invention] According to one aspect, the step difference generated at the interface between the silicon oxide film and the silicon nitride film can be removed.

以下，參照圖式對用以實施本發明之形態進行說明。再者，於本說明書及圖式中，對於實質上相同之構成，藉由標註相同之符號而省略重複之說明。 [電漿蝕刻裝置之整體構成] 首先，基於圖1對本發明之一實施形態之電漿蝕刻裝置進行說明。圖1係表示本實施形態之電漿蝕刻裝置之縱截面之一例之圖。 電漿蝕刻裝置1包含例如表面經氧化鋁膜處理(陽極氧化處理)之包含鋁之圓筒形之腔室10。腔室10接地。 於腔室10之內部設置有載置台12。載置台12例如由鋁(Al)或鈦(Ti)、碳化矽(SiC)等材質構成，且經由絕緣性之保持部14支持於支持部16。藉此，載置台12設置於腔室10之底部。 於腔室10之底部設置有排氣管26，排氣管26與排氣裝置28連接。排氣裝置28包含渦輪分子泵或乾式泵等真空泵，將腔室10內之處理空間減壓至特定之真空度，並且將腔室10內之氣體引導至排氣通路20及排氣口24，進行排氣。於排氣通路20安裝有用以控制氣體之流動之擋板22。 於腔室10之側壁設置有閘閥30。藉由閘閥30之開閉而進行晶圓W自腔室10之搬入及搬出。 於載置台12，經由匹配器33連接有用以生成電漿之第1高頻電源31，且經由匹配器34連接有用以將電漿中之離子提取至晶圓W之第2高頻電源32。例如，第1高頻電源31對載置台12施加適於在腔室10內生成電漿之第1頻率、例如100 MHz之第1高頻電力HF(電漿生成用之高頻電力)。第2高頻電源32對載置台12施加適於將電漿中之離子提取至載置台12上之晶圓W之低於第1頻率之第2頻率、例如3.2 MHz之第2高頻電力LF(偏壓電壓產生用之高頻電力)。第2高頻電力LF例如與第1高頻電力HF同步地施加。如此，載置台12載置晶圓W，並且具有作為下部電極之功能。 於載置台12之上表面設置有用以利用靜電吸附力保持晶圓W之靜電吸盤40。靜電吸盤40係將包含導電膜之電極40a夾入至一對絕緣層40b(或絕緣片)之間而成者，於電極40a，經由開關43連接有直流電壓源42。靜電吸盤40藉由來自直流電壓源42之電壓而利用庫侖力將晶圓W吸附保持於靜電吸盤上。於靜電吸盤40設置有溫度感測器77，測定靜電吸盤40之溫度。藉此，測定靜電吸盤40上之晶圓W之溫度。 於靜電吸盤40之周緣部，以包圍載置台12之周圍之方式配置有聚焦環18。聚焦環18例如由矽或石英形成。聚焦環18以提高蝕刻之面內均一性之方式發揮功能。 於腔室10之頂壁設置有氣體簇射頭38作為接地電位之上部電極。藉此，將自第1高頻電源31輸出之第1高頻電力HF電容性地施加至載置台12與氣體簇射頭38之間。 氣體簇射頭38包含具有多個氣體通氣孔56a之電極板56、及將電極板56可裝卸地支持之電極支持體58。氣體供給源62經由氣體供給配管64自氣體導入口60a向氣體簇射頭38內供給處理氣體。處理氣體於氣體擴散室57擴散，並自多個氣體通氣孔56a導入至腔室10內。於腔室10之周圍配置有呈環狀或同心圓狀地延伸之磁鐵66，藉由磁力控制上部電極與下部電極之電漿生成空間中所生成之電漿。 亦可於靜電吸盤40埋入加熱器75。加熱器75亦可貼附於靜電吸盤40之背面而代替埋入至靜電吸盤40內。自交流電源44輸出之電流經由饋電線而供給至加熱器75。藉此，加熱器75對載置台12進行加熱。 於載置台12之內部形成有冷媒管70。自冷卻器單元71供給之冷媒(以下，亦稱作「鹽水(Brine)」)於冷媒管70及冷媒循環管73中循環而使載置台12冷卻。 藉由該構成，載置台12藉由特定溫度之鹽水於載置台12內之冷媒管70中流動而冷卻。藉此，將晶圓W調整為所需之溫度。又，氦氣(He)等傳熱氣體經由傳熱氣體供給管線72而供給至靜電吸盤40之上表面與晶圓W之背面之間。 控制部50包含CPU(Central Processing Unit，中央處理單元)51、ROM(Read Only Memory，唯讀記憶體)52、RAM(Random Access Memory，隨機存取記憶體)53及HDD(Hard Disk Drive，硬磁驅動器)54。CPU51按照由ROM52、RAM53或HDD54之記錄部中記錄之配方所設定之程序，進行蝕刻等電漿蝕刻。又，記錄部中記錄有下述之資料表等各種資料。控制部50對利用加熱器75之加熱機構或利用鹽水之冷卻機構之溫度進行控制。 於進行電漿蝕刻時，控制閘閥30之開閉，將晶圓W搬入至腔室10內並載置於靜電吸盤40上。閘閥30於搬入晶圓W後關閉。腔室10內之壓力藉由排氣裝置28而減壓至設定值。藉由對靜電吸盤40之電極40a施加來自直流電壓源42之電壓，而將晶圓W靜電吸附於靜電吸盤40上。 繼而，自氣體簇射頭38呈簇射狀地向腔室10內導入特定之氣體，並對載置台12施加特定功率之電漿生成用之第1高頻電力HF。所導入之氣體藉由第1高頻電力HF而進行游離及解離，藉此生成電漿，藉由電漿之作用對晶圓W實施蝕刻等電漿蝕刻。亦可對載置台12施加偏壓電壓產生用之第2高頻電力LF。電漿蝕刻結束後，將晶圓W搬出至腔室10外。 [電漿蝕刻方法] 其次，基於圖2對使用含氟氣體之氧化矽膜(SiO2 )與氮化矽膜(SiN)之積層膜之蝕刻進行說明。圖2係說明蝕刻前後之積層膜之剖面形狀之圖，圖2(a)表示蝕刻前之積層膜之概略剖面，圖2(b)表示蝕刻後之積層膜之概略剖面。 如圖2(a)所示，於晶圓W上形成有氧化矽膜201與氮化矽膜202交替地積層複數層而成之積層膜200，於積層膜200上形成有具有開口300a之遮罩膜300。晶圓W例如為矽晶圓。遮罩膜300例如為多晶矽膜、有機膜、非晶形碳膜、氮化鈦膜。 如圖2(b)所示，若將遮罩膜300作為蝕刻遮罩，藉由自包含含氟氣體之第1處理氣體生成之電漿對積層膜200進行蝕刻，則於積層膜200形成孔200h。此時，存在如下情形，即，於形成於積層膜200之孔200h之側壁200sw，於氧化矽膜201與氮化矽膜202之界面產生階差(紋狀凹凸構造)。其原因在於，於蝕刻時，氧化矽膜201被蝕刻之速度(蝕刻速度)與氮化矽膜202被蝕刻之速度(蝕刻速度)不同。若如此般於氧化矽膜201與氮化矽膜202之界面產生階差，則於在形成孔200h之後之步驟中於孔200h形成膜之情形時，所形成之膜容易剝離等而可靠性降低。此種氧化矽膜201與氮化矽膜202之界面之階差於在晶圓W之溫度為-30℃以下之極低溫環境下進行蝕刻之情形時容易產生。再者，第1處理氣體亦可包含含氫氣體。 作為一例，對藉由以下文所示之極低溫環境下之製程條件對氧化矽膜201與氮化矽膜202之積層膜200進行蝕刻而形成之孔200h之形狀進行說明。製程條件如下所述。 ・冷卻器單元之設定溫度：-60℃ ・氣體：氫(H2 )/四氟化碳(CF4 )/三氟甲烷(CHF3 ) ・壓力：60 mTorr(8.0 Pa) ・第1高頻電力HF：2500 W、連續波 ・第2高頻電力LF：4000 W、脈衝波、頻率0.3 kHz、工作比55% 圖3係說明於氧化矽膜與氮化矽膜之界面產生之階差之圖，下圖表示將上圖中之區域A放大之剖面。 如圖3所示，於將遮罩膜300作為蝕刻遮罩，藉由自包含含氟氣體之第1處理氣體生成之電漿對積層膜200進行蝕刻之情形時，於形成於積層膜200之孔200h之側壁200sw產生階差。 因此，以下，對可將於積層膜200之蝕刻時於氧化矽膜201與氮化矽膜202之界面產生之階差去除的第1實施形態及第2實施形態之電漿蝕刻方法進行說明。 ＜第1實施形態＞ 基於圖4對第1實施形態之電漿蝕刻方法進行說明。圖4係表示第1實施形態之電漿蝕刻方法之一例之流程圖。 如圖4所示，於本實施形態之電漿蝕刻方法中，首先，將晶圓表面之溫度控制為-30℃以下之極低溫(步驟S2)。繼而，將包含含氟氣體之第1處理氣體供給至腔室10內(步驟S4)。例如，供給包含H2 /CF4 /CHF3 之處理氣體。 繼而，使用第1處理氣體對氧化矽膜201與氮化矽膜202之積層膜200進行蝕刻(步驟S6：第1步驟)。具體而言，自第1高頻電源31輸出(接通)第1高頻電力HF，對載置台12施加電漿生成用之高頻電力。又，自第2高頻電源32輸出(接通)第2高頻電力LF，對載置台12施加偏壓電壓產生用之高頻電力。此時，第1高頻電力HF及第2高頻電力LF可為連續波，亦可為脈衝波。第1步驟之執行時間(特定時間)根據形成於積層膜200之孔200h之深度、第1高頻電力HF之輸出、第2高頻電力LF之輸出等而規定。經過特定時間時，將第1高頻電力HF及第2高頻電力斷開(步驟S8)。 繼而，將向包含含氟氣體之第1處理氣體中添加含溴氣體所得之第2處理氣體供給至腔室10內(步驟S10)。例如，供給包含H2 /CF4 /CHF3 /溴化氫(HBr)之處理氣體。 繼而，使用第2處理氣體對氧化矽膜201與氮化矽膜202之積層膜200進行蝕刻(步驟S12：第2步驟)。具體而言，自第1高頻電源31輸出(接通)第1高頻電力HF，對載置台12施加電漿生成用之高頻電力。又，自第2高頻電源32輸出(接通)第2高頻電力LF，對載置台12施加偏壓電壓產生用之高頻電力。此時，第1高頻電力HF可為連續波，亦可為脈衝波，第2高頻電力LF較佳為連續波。第2步驟之執行時間(特定時間)根據第1高頻電力HF之輸出、第2高頻電力LF之輸出等而規定。經過特定時間時，將第1高頻電力HF及第2高頻電力斷開(步驟S14)。 藉由以上步驟於積層膜200形成孔200h。 再者，於本實施形態中，於第1步驟後暫時將第1高頻電力HF及第2高頻電力LF斷開，然後於第2步驟中再次將第1高頻電力HF及第2高頻電力LF接通，但並不限定於此。例如，亦可於第1步驟後不將第1高頻電力HF及第2高頻電力LF斷開而繼續進行第2步驟。 具體而言，以下文所示之製程條件將遮罩膜300作為蝕刻遮罩而對氧化矽膜201與氮化矽膜202之積層膜200進行電漿蝕刻。製程條件如下所述。 (第1步驟) ・冷卻器單元之設定溫度：-60℃ ・氣體：H2 /CF4 /CHF3 ・壓力：60 mTorr(8.0 Pa) ・第1高頻電力HF：2500 W、連續波 ・第2高頻電力LF：4000 W、脈衝波、頻率0.3 kHz、工作比55% (第2步驟) ・冷卻器單元之設定溫度：-60℃ ・氣體：H2 /CF4 /CHF3 /HBr ・壓力：60 mTorr(8.0 Pa) ・第1高頻電力HF：2500 W、連續波 ・第2高頻電力LF：5500 W、連續波 此時，作為比較例，於第2步驟中不添加HBr，除此以外，藉由與第1實施形態同樣之步驟進行電漿蝕刻。製程條件如下所述。 (第1步驟) ・冷卻器單元之設定溫度：-60℃ ・氣體：H2 /CF4 /CHF3 ・壓力：60 mTorr(8.0 Pa) ・第1高頻電力HF：2500 W、連續波 ・第2高頻電力LF：4000 W、脈衝波、頻率0.3 kHz、工作比55% (第2步驟) ・冷卻器單元之設定溫度：-60℃ ・氣體：H2 /CF4 /CHF3 ・壓力：60 mTorr(8.0 Pa) ・第1高頻電力HF：2500 W、連續波 ・第2高頻電力LF：5500 W、連續波 圖5係說明第1實施形態之電漿蝕刻之效果之圖，下圖表示將上圖中之區域A放大之剖面。具體而言，圖5(a)表示於第1步驟後進行本實施形態之第2步驟之蝕刻後之積層膜200之剖面，圖5(b)表示於第1步驟後進行比較例之第2步驟之蝕刻後之積層膜200之剖面。 如圖5(a)所示，藉由在第2步驟中使用包含HBr之第2處理氣體作為蝕刻氣體而對積層膜200進行蝕刻，可將於第1步驟中產生之於氧化矽膜201與氮化矽膜202之界面產生之階差去除。其原因在於，藉由在第2步驟中添加HBr，而矽自積層膜200被擊出，並以含矽物之形式堆積於在氧化矽膜201與氮化矽膜202之界面產生之階差之凹部，並且將階差之凸部削落，從而使階差平坦化。此時，就促進階差之凸部之削落之觀點而言，較佳為於第2步驟中施加第2高頻電力LF，特佳為第2高頻電力LF大於第1高頻電力HF。又，藉由添加HBr，可縮小氧化矽膜201之蝕刻速度與氮化矽膜202之蝕刻速度之差。因此，於第2步驟中，與第1步驟相比不易於氧化矽膜201與氮化矽膜202之界面產生階差。 又，於第1步驟中不添加HBr地對積層膜200進行蝕刻。因此，可不使遮罩膜300相對於積層膜200之選擇比(遮罩選擇比)降低而於積層膜200形成孔200h。 相對於此，如圖5(b)所示，於在第2步驟中未添加HBr作為蝕刻氣體之情形時，幾乎未看出於氧化矽膜201與氮化矽膜202之界面產生之階差有所改善。 再者，於本實施形態中，將第2步驟中之腔室10內之壓力設為60 mTorr(8.0 Pa)，但腔室10內之壓力亦可為60 mTorr(8.0 Pa)以下，例如亦可為25 mTorr(3.3 Pa)、15 mTorr(2.0 Pa)。藉由使第2步驟中之腔室10內之壓力降低，可使形成於積層膜200之孔200h之底部之直徑(底部CD(Critical Dimension，臨界尺寸))擴大。其結果，除了可將於氧化矽膜201與氮化矽膜202之界面產生之階差去除以外，亦可提高形成於積層膜200之孔200h之側壁200sw之垂直性。 如以上所說明般，於第1實施形態之電漿蝕刻方法中，於使用包含含氟氣體之第1處理氣體之電漿對積層膜200進行蝕刻後，使用包含含溴氣體之第2處理氣體之電漿對積層膜200進行蝕刻。藉此，可將於氧化矽膜201與氮化矽膜202之界面產生之階差去除。 ＜第2實施形態＞ 對第2實施形態之電漿蝕刻方法進行說明。於第1實施形態中，對第2步驟中所使用之第2處理氣體為向第1步驟中所使用之第1處理氣體中添加含溴氣體所得之處理氣體的形態進行了說明。相對於此，於第2實施形態中，對第2步驟中所使用之第2處理氣體為向與第1步驟中所使用之第1處理氣體不同之處理氣體中添加含溴氣體的形態進行說明。 具體而言，以下文所示之製程條件將遮罩膜300作為蝕刻遮罩而對氧化矽膜201與氮化矽膜202之積層膜200進行電漿蝕刻。製程條件如下所述。 (第1步驟) ・冷卻器單元之設定溫度：-60℃ ・氣體：H2 /CF4 /CHF3 ・壓力：60 mTorr(8.0 Pa) ・第1高頻電力HF：2500 W、連續波 ・第2高頻電力LF：4000 W、脈衝波、頻率0.3 kHz、工作比55% (第2步驟) ・冷卻器單元之設定溫度：-60℃ ・氣體：二氟甲烷(CH2 F2 )/甲烷(CH4 )/三氟化氮(NF3 )/HBr ・壓力：60 mTorr(8.0 Pa) ・第1高頻電力HF：2500 W、連續波 ・第2高頻電力LF：5500 W、連續波 圖6係說明第2實施形態之電漿蝕刻之效果之圖，下圖表示將上圖中之區域A放大之剖面。具體而言，圖6表示於第1步驟後進行本實施形態之第2步驟之蝕刻後之積層膜200之剖面。 如圖6所示，藉由使用包含HBr之第2處理氣體作為蝕刻氣體而對積層膜200進行蝕刻，可與第1實施形態同樣地將於氧化矽膜201與氮化矽膜202之界面產生之階差去除。 如以上所說明般，於第2實施形態之電漿蝕刻方法中，於使用包含含氟氣體之第1處理氣體之電漿對積層膜200進行蝕刻後，使用包含含溴氣體之第2處理氣體之電漿對積層膜200進行蝕刻。藉此，可將於氧化矽膜201與氮化矽膜202之界面產生之階差去除。 以上，藉由上述實施形態對電漿蝕刻方法進行了說明，但本發明之電漿蝕刻方法並不限定於上述實施形態，可於本發明之範圍內進行各種變化及改良。 例如，本發明之電漿蝕刻方法不僅可應用於在積層膜形成孔之情形，亦可應用於在積層膜形成溝槽之情形。 又，例如本發明之電漿蝕刻方法不僅可應用於電容耦合型電漿(CCP：Capacitively Coupled Plasma)裝置，亦可應用於其他蝕刻處理裝置。作為其他蝕刻處理裝置，亦可為電感耦合型電漿(ICP：Inductively Coupled Plasma)、使用放射狀線槽孔天線之電漿蝕刻裝置、螺旋波激發型電漿(HWP：Helicon Wave Plasma)裝置、電子迴旋共振電漿(ECR：Electron Cyclotron Resonance Plasma)裝置等。 又，例如，由本發明之蝕刻處理裝置處理之基板不限於晶圓，例如亦可為平板顯示器(Flat Panel Display)用之大型基板、EL(Electro Luminescence，電致發光)元件或太陽電池用之基板。Hereinafter, a mode for implementing the present invention will be described with reference to the drawings. Furthermore, in this specification and drawings, for substantially the same configuration, the same symbols are used to omit repeated descriptions. [Overall Configuration of Plasma Etching Apparatus] First, a plasma etching apparatus according to an embodiment of the present invention will be described based on FIG. 1. Fig. 1 is a diagram showing an example of a longitudinal section of the plasma etching apparatus of the present embodiment. The plasma etching apparatus 1 includes, for example, a cylindrical chamber 10 containing aluminum whose surface is treated with an aluminum oxide film (anodic oxidation treatment). The chamber 10 is grounded. A mounting table 12 is provided inside the chamber 10. The mounting table 12 is made of, for example, aluminum (Al), titanium (Ti), silicon carbide (SiC), or the like, and is supported by the supporting portion 16 via an insulating holding portion 14. Thereby, the placing table 12 is installed at the bottom of the chamber 10. An exhaust pipe 26 is provided at the bottom of the chamber 10, and the exhaust pipe 26 is connected to an exhaust device 28. The exhaust device 28 includes a vacuum pump such as a turbomolecular pump or a dry pump, which reduces the processing space in the chamber 10 to a specific vacuum degree, and guides the gas in the chamber 10 to the exhaust passage 20 and the exhaust port 24, Exhaust. A baffle 22 for controlling the flow of gas is installed in the exhaust passage 20. A gate valve 30 is provided on the side wall of the chamber 10. The wafer W is carried in and out of the chamber 10 by opening and closing the gate valve 30. To the mounting table 12, a first high-frequency power source 31 for generating plasma is connected via a matching device 33, and a second high-frequency power source 32 for extracting ions in the plasma to the wafer W is connected via a matching device 34. For example, the first high-frequency power supply 31 applies to the mounting table 12 a first high-frequency power HF (high-frequency power for plasma generation) of a first frequency suitable for generating plasma in the chamber 10, for example, 100 MHz. The second high-frequency power supply 32 applies, to the mounting table 12, a second high-frequency power LF of a second frequency lower than the first frequency, such as 3.2 MHz, suitable for extracting ions in the plasma onto the wafer W on the mounting table 12 (High frequency power for bias voltage generation). For example, the second high-frequency power LF is applied in synchronization with the first high-frequency power HF. In this way, the mounting table 12 mounts the wafer W and has a function as a lower electrode. An electrostatic chuck 40 for holding the wafer W with electrostatic adsorption force is provided on the upper surface of the mounting table 12. The electrostatic chuck 40 is formed by sandwiching an electrode 40 a including a conductive film between a pair of insulating layers 40 b (or insulating sheets), and a DC voltage source 42 is connected to the electrode 40 a via a switch 43. The electrostatic chuck 40 uses the voltage from the DC voltage source 42 to attract and hold the wafer W on the electrostatic chuck using Coulomb force. The electrostatic chuck 40 is provided with a temperature sensor 77 to measure the temperature of the electrostatic chuck 40. In this way, the temperature of the wafer W on the electrostatic chuck 40 is measured. A focus ring 18 is arranged on the periphery of the electrostatic chuck 40 so as to surround the periphery of the mounting table 12. The focus ring 18 is formed of silicon or quartz, for example. The focus ring 18 functions to improve the uniformity of etching in the plane. A gas shower head 38 is provided on the top wall of the chamber 10 as a ground potential upper electrode. Thereby, the first high-frequency power HF output from the first high-frequency power supply 31 is capacitively applied between the mounting table 12 and the gas shower head 38. The gas shower head 38 includes an electrode plate 56 having a plurality of gas vent holes 56 a, and an electrode support 58 that detachably supports the electrode plate 56. The gas supply source 62 supplies processing gas into the gas shower head 38 from the gas inlet 60 a via the gas supply pipe 64. The processing gas diffuses in the gas diffusion chamber 57 and is introduced into the chamber 10 from the plurality of gas vent holes 56a. A magnet 66 extending in a ring or concentric shape is arranged around the chamber 10, and the plasma generated in the plasma generating space of the upper electrode and the lower electrode is controlled by the magnetic force. The heater 75 may be embedded in the electrostatic chuck 40. The heater 75 can also be attached to the back of the electrostatic chuck 40 instead of being buried in the electrostatic chuck 40. The current output from the AC power source 44 is supplied to the heater 75 via the feeder line. Thereby, the heater 75 heats the mounting table 12. A refrigerant pipe 70 is formed inside the mounting table 12. The refrigerant (hereinafter, also referred to as "Brine") supplied from the cooler unit 71 circulates in the refrigerant pipe 70 and the refrigerant circulation pipe 73 to cool the mounting table 12. With this configuration, the mounting table 12 is cooled by flowing salt water of a specific temperature through the refrigerant pipe 70 in the mounting table 12. In this way, the wafer W is adjusted to the required temperature. In addition, a heat transfer gas such as helium (He) is supplied between the upper surface of the electrostatic chuck 40 and the back surface of the wafer W via the heat transfer gas supply line 72. The control unit 50 includes a CPU (Central Processing Unit) 51, ROM (Read Only Memory) 52, RAM (Random Access Memory) 53, and HDD (Hard Disk Drive). Magnetic drive) 54. The CPU 51 performs plasma etching such as etching according to the program set by the recipe recorded in the recording section of the ROM52, RAM53 or HDD54. In addition, various data such as the following data sheet are recorded in the recording section. The control unit 50 controls the temperature of the heating mechanism using the heater 75 or the cooling mechanism using salt water. During plasma etching, the opening and closing of the gate valve 30 is controlled, and the wafer W is carried into the chamber 10 and placed on the electrostatic chuck 40. The gate valve 30 is closed after the wafer W is loaded. The pressure in the chamber 10 is reduced to a set value by the exhaust device 28. By applying a voltage from the DC voltage source 42 to the electrode 40 a of the electrostatic chuck 40, the wafer W is electrostatically attracted to the electrostatic chuck 40. Then, a specific gas is introduced into the chamber 10 in a shower shape from the gas shower head 38, and the first high-frequency power HF for plasma generation of a specific power is applied to the mounting table 12. The introduced gas is released and dissociated by the first high-frequency power HF, thereby generating plasma, and plasma etching such as etching is performed on the wafer W by the action of the plasma. The second high frequency power LF for generating a bias voltage may be applied to the mounting table 12. After the plasma etching is completed, the wafer W is carried out of the chamber 10. [Plasma Etching Method] Next, the etching of a laminated film of a silicon oxide film (SiO 2 ) and a silicon nitride film (SiN) using a fluorine-containing gas will be described based on FIG. 2. Fig. 2 is a diagram illustrating the cross-sectional shape of the laminated film before and after etching. Fig. 2(a) shows a schematic cross section of the laminated film before etching, and Fig. 2(b) shows a schematic cross section of the laminated film after etching. As shown in FIG. 2(a), a layered film 200 formed by alternately layering a silicon oxide film 201 and a silicon nitride film 202 is formed on the wafer W. The layered film 200 is formed with an opening 300a. Shield film 300. The wafer W is, for example, a silicon wafer. The mask film 300 is, for example, a polysilicon film, an organic film, an amorphous carbon film, or a titanium nitride film. As shown in FIG. 2(b), if the mask film 300 is used as an etching mask, and the build-up film 200 is etched by plasma generated from the first process gas containing a fluorine-containing gas, a hole is formed in the build-up film 200 200h. At this time, there is a situation in which a step difference (striated uneven structure) occurs at the interface between the silicon oxide film 201 and the silicon nitride film 202 at the sidewall 200sw of the hole 200h formed in the build-up film 200. The reason is that during etching, the rate at which the silicon oxide film 201 is etched (etching rate) is different from the rate at which the silicon nitride film 202 is etched (etching rate). If a step difference occurs at the interface between the silicon oxide film 201 and the silicon nitride film 202 in this way, when a film is formed in the hole 200h in a step after the hole 200h is formed, the formed film is easily peeled off, and the reliability is reduced. . Such a step difference between the silicon oxide film 201 and the silicon nitride film 202 is likely to occur when etching is performed in an extremely low temperature environment where the temperature of the wafer W is below -30°C. Furthermore, the first processing gas may include hydrogen-containing gas. As an example, the shape of the hole 200h formed by etching the laminated film 200 of the silicon oxide film 201 and the silicon nitride film 202 under the process conditions under the extremely low temperature environment shown below will be described. The process conditions are as follows.・Set temperature of cooler unit: -60℃ ・Gas: hydrogen (H 2 )/carbon tetrafluoride (CF 4 )/trifluoromethane (CHF 3 ) ・pressure: 60 mTorr (8.0 Pa) ・1st high frequency Power HF: 2500 W, continuous wave, second high frequency power LF: 4000 W, pulse wave, frequency 0.3 kHz, operating ratio 55% Figure 3 illustrates the step difference generated at the interface between the silicon oxide film and the silicon nitride film Figure, the bottom figure shows the cross-section of the area A in the above figure enlarged. As shown in FIG. 3, when the mask film 300 is used as an etching mask, and the build-up film 200 is etched by the plasma generated from the first process gas containing a fluorine-containing gas, it is formed on the build-up film 200 The sidewall 200sw of the hole 200h has a step difference. Therefore, in the following, the plasma etching method of the first embodiment and the second embodiment that can remove the step generated at the interface between the silicon oxide film 201 and the silicon nitride film 202 during the etching of the build-up film 200 will be described. <First Embodiment> The plasma etching method of the first embodiment will be described based on FIG. 4. 4 is a flowchart showing an example of the plasma etching method of the first embodiment. As shown in FIG. 4, in the plasma etching method of this embodiment, first, the temperature of the wafer surface is controlled to an extremely low temperature below -30°C (step S2). Then, the first processing gas containing the fluorine-containing gas is supplied into the chamber 10 (step S4). For example, supply processing gas containing H 2 /CF 4 /CHF 3 . Then, the laminated film 200 of the silicon oxide film 201 and the silicon nitride film 202 is etched using the first processing gas (step S6: first step). Specifically, the first high-frequency power HF is output (turned on) from the first high-frequency power supply 31, and the high-frequency power for plasma generation is applied to the mounting table 12. In addition, the second high-frequency power LF is output (turned on) from the second high-frequency power supply 32, and the high-frequency power for generating a bias voltage is applied to the mounting table 12. At this time, the first high-frequency power HF and the second high-frequency power LF may be continuous waves or pulse waves. The execution time (specific time) of the first step is determined according to the depth of the hole 200h formed in the laminated film 200, the output of the first high-frequency power HF, the output of the second high-frequency power LF, and the like. When a specific time has elapsed, the first high-frequency power HF and the second high-frequency power are turned off (step S8). Then, the second processing gas obtained by adding the bromine-containing gas to the first processing gas containing the fluorine-containing gas is supplied into the chamber 10 (step S10). For example, a process gas containing H 2 /CF 4 /CHF 3 /hydrogen bromide (HBr) is supplied. Then, the laminated film 200 of the silicon oxide film 201 and the silicon nitride film 202 is etched using the second process gas (step S12: second step). Specifically, the first high-frequency power HF is output (turned on) from the first high-frequency power supply 31, and the high-frequency power for plasma generation is applied to the mounting table 12. In addition, the second high-frequency power LF is output (turned on) from the second high-frequency power supply 32, and the high-frequency power for generating a bias voltage is applied to the mounting table 12. At this time, the first high-frequency power HF may be a continuous wave or a pulse wave, and the second high-frequency power LF is preferably a continuous wave. The execution time (specific time) of the second step is determined based on the output of the first high-frequency power HF, the output of the second high-frequency power LF, and the like. When a specific time has elapsed, the first high-frequency power HF and the second high-frequency power are turned off (step S14). A hole 200h is formed in the laminated film 200 through the above steps. Furthermore, in this embodiment, after the first step, the first high-frequency power HF and the second high-frequency power LF are temporarily disconnected, and then in the second step, the first high-frequency power HF and the second high-frequency power are turned off again. The frequency power LF is turned on, but it is not limited to this. For example, after the first step, the second step may be continued without disconnecting the first high-frequency power HF and the second high-frequency power LF. Specifically, the process conditions shown below use the mask film 300 as an etching mask to perform plasma etching on the laminated film 200 of the silicon oxide film 201 and the silicon nitride film 202. The process conditions are as follows. (Step 1) ・Set temperature of cooler unit: -60℃ ・Gas: H 2 /CF 4 /CHF 3・Pressure: 60 mTorr (8.0 Pa) ・First high-frequency power HF: 2500 W, continuous wave ・The second high-frequency power LF: 4000 W, pulse wave, frequency 0.3 kHz, operating ratio 55% (step 2) ・Set temperature of cooler unit: -60℃ ・Gas: H 2 /CF 4 /CHF 3 /HBr・Pressure: 60 mTorr (8.0 Pa) ・The first high-frequency power HF: 2500 W, continuous wave ・The second high-frequency power LF: 5500 W, continuous wave In this case, as a comparative example, HBr is not added in the second step Except for this, plasma etching is performed by the same procedure as in the first embodiment. The process conditions are as follows. (Step 1) ・Set temperature of cooler unit: -60℃ ・Gas: H 2 /CF 4 /CHF 3・Pressure: 60 mTorr (8.0 Pa) ・First high-frequency power HF: 2500 W, continuous wave ・The second high frequency power LF: 4000 W, pulse wave, frequency 0.3 kHz, operating ratio 55% (2nd step) ・Set temperature of cooler unit: -60℃ ・Gas: H 2 /CF 4 /CHF 3・Pressure : 60 mTorr (8.0 Pa) ・The first high-frequency power HF: 2500 W, continuous wave ・The second high-frequency power LF: 5500 W, continuous wave Figure 5 is a diagram illustrating the effect of plasma etching in the first embodiment. The figure below shows the cross section of the area A in the figure above being enlarged. Specifically, FIG. 5(a) shows the cross-section of the laminated film 200 after the second step of the present embodiment is etched after the first step, and FIG. 5(b) shows the second step of the comparative example after the first step. The cross-section of the laminated film 200 after etching in the step. As shown in FIG. 5(a), by using a second process gas containing HBr as an etching gas to etch the build-up film 200 in the second step, the silicon oxide film 201 and the silicon oxide film 201 generated in the first step can be etched. The step difference generated at the interface of the silicon nitride film 202 is removed. The reason is that by adding HBr in the second step, silicon is knocked out from the laminated film 200 and deposited in the form of silicon-containing substances on the level difference generated at the interface between the silicon oxide film 201 and the silicon nitride film 202 The concave part, and the convex part of the step difference is cut off, so that the step difference is flattened. At this time, from the viewpoint of facilitating the reduction of the convex portion of the level difference, it is preferable to apply the second high frequency power LF in the second step, and it is particularly preferable that the second high frequency power LF is greater than the first high frequency power HF . Furthermore, by adding HBr, the difference between the etching rate of the silicon oxide film 201 and the etching rate of the silicon nitride film 202 can be reduced. Therefore, in the second step, the interface between the silicon oxide film 201 and the silicon nitride film 202 is less likely to have a step difference than in the first step. In the first step, the build-up film 200 is etched without adding HBr. Therefore, the hole 200h can be formed in the laminated film 200 without reducing the selection ratio (mask selection ratio) of the mask film 300 to the laminated film 200. In contrast, as shown in FIG. 5(b), when HBr is not added as an etching gas in the second step, there is almost no level difference at the interface between the silicon oxide film 201 and the silicon nitride film 202. it has been improved. Furthermore, in this embodiment, the pressure in the chamber 10 in the second step is set to 60 mTorr (8.0 Pa), but the pressure in the chamber 10 can also be 60 mTorr (8.0 Pa) or less, for example, It can be 25 mTorr (3.3 Pa), 15 mTorr (2.0 Pa). By reducing the pressure in the chamber 10 in the second step, the diameter (the bottom CD (Critical Dimension)) of the bottom of the hole 200h formed in the laminated film 200 can be enlarged. As a result, in addition to removing the step difference generated at the interface between the silicon oxide film 201 and the silicon nitride film 202, the verticality of the sidewall 200sw of the hole 200h formed in the build-up film 200 can also be improved. As described above, in the plasma etching method of the first embodiment, after the layered film 200 is etched using the plasma containing the first process gas containing fluorine gas, the second process gas containing bromine gas is used The plasma etches the laminated film 200. Thereby, the step difference generated at the interface between the silicon oxide film 201 and the silicon nitride film 202 can be removed. <Second Embodiment> The plasma etching method of the second embodiment will be described. In the first embodiment, the form in which the second processing gas used in the second step is a processing gas obtained by adding a bromine-containing gas to the first processing gas used in the first step has been described. In contrast to this, in the second embodiment, the second processing gas used in the second step is described in the form of adding bromine-containing gas to a processing gas different from the first processing gas used in the first step . Specifically, the process conditions shown below use the mask film 300 as an etching mask to perform plasma etching on the laminated film 200 of the silicon oxide film 201 and the silicon nitride film 202. The process conditions are as follows. (Step 1) ・Set temperature of cooler unit: -60℃ ・Gas: H 2 /CF 4 /CHF 3・Pressure: 60 mTorr (8.0 Pa) ・First high-frequency power HF: 2500 W, continuous wave ・The second high-frequency power LF: 4000 W, pulse wave, frequency 0.3 kHz, operating ratio 55% (2nd step) ・Set temperature of cooler unit: -60℃ ・Gas: Difluoromethane (CH 2 F 2 )/ Methane (CH 4 )/Nitrogen Trifluoride (NF 3 )/HBr ・Pressure: 60 mTorr (8.0 Pa) ・The first high-frequency power HF: 2500 W, continuous wave ・The second high-frequency power LF: 5500 W, continuous Wave diagram 6 is a diagram illustrating the effect of plasma etching in the second embodiment, and the bottom diagram shows a cross-section of enlarged area A in the top diagram. Specifically, FIG. 6 shows a cross-section of the build-up film 200 after the second step of the present embodiment is etched after the first step. As shown in FIG. 6, by using the second process gas containing HBr as the etching gas to etch the build-up film 200, the interface between the silicon oxide film 201 and the silicon nitride film 202 can be generated in the same way as in the first embodiment. The order difference is removed. As described above, in the plasma etching method of the second embodiment, after the layered film 200 is etched using the plasma of the first process gas containing fluorine-containing gas, the second process gas containing bromine-containing gas is used The plasma etches the laminated film 200. Thereby, the step difference generated at the interface between the silicon oxide film 201 and the silicon nitride film 202 can be removed. As mentioned above, the plasma etching method has been described based on the above embodiment, but the plasma etching method of the present invention is not limited to the above embodiment, and various changes and improvements can be made within the scope of the present invention. For example, the plasma etching method of the present invention can be applied not only to the case of forming a hole in the build-up film, but also to the case of forming a trench in the build-up film. Moreover, for example, the plasma etching method of the present invention can be applied not only to capacitively coupled plasma (CCP) devices, but also to other etching processing devices. As other etching processing devices, inductively coupled plasma (ICP: Inductively Coupled Plasma), plasma etching devices using radial line slot antennas, spiral wave excitation plasma (HWP: Helicon Wave Plasma) devices, Electron Cyclotron Resonance Plasma (ECR: Electron Cyclotron Resonance Plasma) device, etc. Also, for example, the substrate processed by the etching processing apparatus of the present invention is not limited to wafers, but may also be large-scale substrates for flat panel displays, EL (Electro Luminescence) devices, or substrates for solar cells. .

1‧‧‧電漿蝕刻裝置10‧‧‧腔室12‧‧‧載置台14‧‧‧保持部16‧‧‧支持部18‧‧‧聚焦環20‧‧‧排氣通路22‧‧‧擋板24‧‧‧排氣口26‧‧‧排氣管28‧‧‧排氣裝置30‧‧‧閘閥31‧‧‧第1高頻電源32‧‧‧第2高頻電源33‧‧‧匹配器34‧‧‧匹配器38‧‧‧氣體簇射頭40‧‧‧靜電吸盤40a‧‧‧電極40b‧‧‧絕緣層42‧‧‧直流電壓源43‧‧‧開關44‧‧‧交流電源50‧‧‧控制部51‧‧‧CPU52‧‧‧ROM53‧‧‧RAM54‧‧‧HDD56‧‧‧電極板56a‧‧‧氣體通氣孔57‧‧‧氣體擴散室58‧‧‧電極支持體60a‧‧‧氣體導入口62‧‧‧氣體供給源64‧‧‧氣體供給配管66‧‧‧磁鐵70‧‧‧冷媒管71‧‧‧冷卻器單元72‧‧‧傳熱氣體供給管線73‧‧‧冷媒循環管75‧‧‧加熱器77‧‧‧溫度感測器200‧‧‧積層膜200h‧‧‧孔200sw‧‧‧側壁201‧‧‧氧化矽膜202‧‧‧氮化矽膜300‧‧‧遮罩膜300a‧‧‧開口A‧‧‧區域HF‧‧‧第1高頻電力LF‧‧‧第2高頻電力S2‧‧‧步驟S4‧‧‧步驟S6‧‧‧步驟S8‧‧‧步驟S10‧‧‧步驟S12‧‧‧步驟S14‧‧‧步驟W‧‧‧晶圓1‧‧‧Plasma etching device 10‧‧‧Chamber 12‧‧‧Mounting table 14‧‧‧Holding part 16‧‧‧Supporting part 18‧‧‧Focusing ring 20‧‧‧Exhaust passage 22‧‧‧Block Plate 24‧‧‧Exhaust port 26‧‧‧Exhaust pipe 28‧‧‧Exhaust device 30‧‧‧Gate valve 31‧‧‧The first high frequency power supply 32‧‧‧The second high frequency power supply 33‧‧‧match Matcher 38‧‧‧Gas shower head 40‧‧‧Electrostatic chuck 40a‧‧‧Electrode 40b‧‧‧Insulation layer 42‧‧‧DC voltage source 43‧‧‧Switch 44‧‧‧AC power supply 50‧‧‧Control part 51‧‧‧CPU52‧‧‧ROM53‧‧‧RAM54‧‧‧HDD56‧‧‧Electrode plate 56a‧‧‧Gas vent 57‧‧‧Gas diffusion chamber 58‧‧‧Electrode support 60a ‧‧‧Gas inlet 62‧‧‧Gas supply source 64‧‧‧Gas supply pipe 66‧‧‧Magnet 70‧‧‧Refrigerant pipe 71‧‧‧Cooler unit 72‧‧‧Heat transfer gas supply pipe 73‧‧ ‧Refrigerant circulation pipe 75‧‧‧Heater 77‧‧‧Temperature sensor 200‧‧‧Laminated film 200h‧‧‧Hole 200sw‧‧‧Sidewall 201‧‧‧Silicon oxide film 202‧‧‧Silicon nitride film 300 ‧‧‧Mask film 300a‧‧‧Aperture A‧‧‧Region HF‧‧‧The first high frequency power LF‧‧‧The second high frequency power S2‧‧‧Step S4‧‧‧Step S6‧‧‧Step S8 ‧‧‧Step S10‧‧‧Step S12‧‧‧Step S14‧‧‧Step W‧‧‧Wafer

圖1係表示本實施形態之電漿蝕刻裝置之縱截面之一例之圖。 圖2(a)、(b)係說明蝕刻前後之積層膜之剖面形狀之圖。 圖3係說明於氧化矽膜與氮化矽膜之界面產生之階差之圖。 圖4係表示第1實施形態之電漿蝕刻方法之一例之流程圖。 圖5(a)、(b)係說明第1實施形態之電漿蝕刻之效果之圖。 圖6係說明第2實施形態之電漿蝕刻之效果之圖。Fig. 1 is a diagram showing an example of a longitudinal section of the plasma etching apparatus of the present embodiment. 2(a) and (b) are diagrams illustrating the cross-sectional shape of the laminated film before and after etching. FIG. 3 is a diagram illustrating the step difference generated at the interface between the silicon oxide film and the silicon nitride film. 4 is a flowchart showing an example of the plasma etching method of the first embodiment. Fig. 5 (a) and (b) are diagrams illustrating the effect of plasma etching in the first embodiment. Fig. 6 is a diagram illustrating the effect of plasma etching in the second embodiment.

200‧‧‧積層膜 200‧‧‧Laminated film

200h‧‧‧孔 200h‧‧‧hole

200sw‧‧‧側壁 200sw‧‧‧ side wall

300‧‧‧遮罩膜 300‧‧‧Mask film

A‧‧‧區域 A‧‧‧area

Claims (9)

一種電漿蝕刻方法，其包含：第1步驟，其係使用高頻電力自包含含氟氣體之第1處理氣體生成電漿，並利用所生成之電漿對氧化矽膜與氮化矽膜之積層膜進行蝕刻；及第2步驟，其係於上述第1步驟之後，使用高頻電力自包含含溴氣體之第2處理氣體生成電漿，並利用所生成之電漿對上述積層膜進行蝕刻，其中於上述第1步驟中，上述氧化矽膜與上述氮化矽膜之界面產生階差，於上述第2步驟中，將上述階差去除。 A plasma etching method comprising: a first step of using high-frequency power to generate plasma from a first processing gas containing a fluorine-containing gas, and using the generated plasma to treat a silicon oxide film and a silicon nitride film Laminated film is etched; and the second step, which is after the first step, uses high-frequency power to generate plasma from a second process gas containing bromine-containing gas, and uses the generated plasma to etch the laminated film , Wherein in the first step, a step difference is generated at the interface between the silicon oxide film and the silicon nitride film, and the step difference is removed in the second step. 如請求項1之電漿蝕刻方法，其中上述第1步驟及上述第2步驟係於-30℃以下執行。 The plasma etching method of claim 1, wherein the first step and the second step are performed below -30°C. 如請求項1或2之電漿蝕刻方法，其中上述第2處理氣體係包含上述第1處理氣體。 The plasma etching method of claim 1 or 2, wherein the second processing gas system includes the first processing gas. 如請求項1或2之電漿蝕刻方法，其中上述第2處理氣體係包含與上述第1處理氣體不同之處理氣體。 The plasma etching method of claim 1 or 2, wherein the second processing gas system includes a processing gas different from the first processing gas. 如請求項1或2之電漿蝕刻方法，其中於上述第1步驟及上述第2步驟之至少一者中，進一步施加高於上述高頻電力之高頻電力。 The plasma etching method of claim 1 or 2, wherein in at least one of the first step and the second step, a high-frequency power higher than the high-frequency power is further applied. 如請求項1或2之電漿蝕刻方法，其中上述第1處理氣體包含含氫氣體。 The plasma etching method of claim 1 or 2, wherein the first processing gas includes a hydrogen-containing gas. 如請求項6之電漿蝕刻方法，其中上述含氟氣體係CF4，上述含氫氣體係H2。 The plasma etching method of claim 6, wherein the above-mentioned fluorine-containing gas system CF 4 and the above-mentioned hydrogen-containing gas system H 2 . 如請求項1或2之電漿蝕刻方法，其中上述含溴氣體係HBr。 The plasma etching method of claim 1 or 2, wherein the bromine-containing gas system is HBr. 一種電漿蝕刻方法，其包含：載置包含氧化矽膜與氮化矽膜之積層膜之晶圓，使用含氟電漿蝕刻上述積層膜之第1步驟，使用含溴電漿蝕刻上述積層膜之第2步驟，其中於上述第1步驟中，上述氧化矽膜與上述氮化矽膜之界面產生階差，於上述第2步驟中，將上述階差去除。 A plasma etching method comprising: placing a wafer containing a laminated film of a silicon oxide film and a silicon nitride film, etching the laminated film using a fluorine-containing plasma, and etching the laminated film using a bromine-containing plasma In the second step, in the first step, a step is generated at the interface between the silicon oxide film and the silicon nitride film, and in the second step, the step is removed.
TW105138041A 2015-12-03 2016-11-21 Plasma etching method TWI706460B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-236624 2015-12-03
JP2015236624A JP6604833B2 (en) 2015-12-03 2015-12-03 Plasma etching method

Publications (2)

Publication Number Publication Date
TW201721739A TW201721739A (en) 2017-06-16
TWI706460B true TWI706460B (en) 2020-10-01

Family

ID=58799166

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105138041A TWI706460B (en) 2015-12-03 2016-11-21 Plasma etching method

Country Status (6)

Country Link
US (2) US9966273B2 (en)
JP (1) JP6604833B2 (en)
KR (1) KR102363783B1 (en)
CN (1) CN106992121B (en)
SG (1) SG10201610044VA (en)
TW (1) TWI706460B (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6948181B2 (en) * 2017-08-01 2021-10-13 東京エレクトロン株式会社 How to etch a multilayer film
JP6945388B2 (en) * 2017-08-23 2021-10-06 東京エレクトロン株式会社 Etching method and etching processing equipment
SG11202003151VA (en) * 2017-11-02 2020-05-28 Showa Denko Kk Etching method and semiconductor manufacturing method
US10811267B2 (en) 2017-12-21 2020-10-20 Micron Technology, Inc. Methods of processing semiconductor device structures and related systems
JP7018801B2 (en) 2018-03-29 2022-02-14 東京エレクトロン株式会社 Plasma processing equipment and method of transporting the object to be processed
US10555412B2 (en) 2018-05-10 2020-02-04 Applied Materials, Inc. Method of controlling ion energy distribution using a pulse generator with a current-return output stage
CN111373511B (en) 2018-10-26 2023-12-26 株式会社日立高新技术 Plasma processing method
US11476145B2 (en) 2018-11-20 2022-10-18 Applied Materials, Inc. Automatic ESC bias compensation when using pulsed DC bias
JP7451540B2 (en) 2019-01-22 2024-03-18 アプライド マテリアルズ インコーポレイテッド Feedback loop for controlling pulsed voltage waveforms
US11508554B2 (en) 2019-01-24 2022-11-22 Applied Materials, Inc. High voltage filter assembly
KR20200100555A (en) * 2019-02-18 2020-08-26 도쿄엘렉트론가부시키가이샤 Etching method
CN113614891A (en) * 2019-03-22 2021-11-05 中央硝子株式会社 Dry etching method and method for manufacturing semiconductor device
US11087989B1 (en) 2020-06-18 2021-08-10 Applied Materials, Inc. Cryogenic atomic layer etch with noble gases
JP2022021226A (en) 2020-07-21 2022-02-02 東京エレクトロン株式会社 Plasma processing method and plasma processing device
US11848176B2 (en) 2020-07-31 2023-12-19 Applied Materials, Inc. Plasma processing using pulsed-voltage and radio-frequency power
US11901157B2 (en) 2020-11-16 2024-02-13 Applied Materials, Inc. Apparatus and methods for controlling ion energy distribution
US11798790B2 (en) 2020-11-16 2023-10-24 Applied Materials, Inc. Apparatus and methods for controlling ion energy distribution
US11495470B1 (en) 2021-04-16 2022-11-08 Applied Materials, Inc. Method of enhancing etching selectivity using a pulsed plasma
US11791138B2 (en) 2021-05-12 2023-10-17 Applied Materials, Inc. Automatic electrostatic chuck bias compensation during plasma processing
US11948780B2 (en) 2021-05-12 2024-04-02 Applied Materials, Inc. Automatic electrostatic chuck bias compensation during plasma processing
US11967483B2 (en) 2021-06-02 2024-04-23 Applied Materials, Inc. Plasma excitation with ion energy control
US11984306B2 (en) 2021-06-09 2024-05-14 Applied Materials, Inc. Plasma chamber and chamber component cleaning methods
US11810760B2 (en) 2021-06-16 2023-11-07 Applied Materials, Inc. Apparatus and method of ion current compensation
US11569066B2 (en) 2021-06-23 2023-01-31 Applied Materials, Inc. Pulsed voltage source for plasma processing applications
US11776788B2 (en) 2021-06-28 2023-10-03 Applied Materials, Inc. Pulsed voltage boost for substrate processing
US11476090B1 (en) 2021-08-24 2022-10-18 Applied Materials, Inc. Voltage pulse time-domain multiplexing
US11694876B2 (en) 2021-12-08 2023-07-04 Applied Materials, Inc. Apparatus and method for delivering a plurality of waveform signals during plasma processing
WO2023132889A1 (en) * 2022-01-04 2023-07-13 Applied Materials, Inc. Electrode tuning, depositing, and etching methods
US11972924B2 (en) 2022-06-08 2024-04-30 Applied Materials, Inc. Pulsed voltage source for plasma processing applications
WO2024073390A1 (en) * 2022-09-29 2024-04-04 Lam Research Corporation Post etch plasma treatment for reducing sidewall contaminants and roughness

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150179466A1 (en) * 2013-12-19 2015-06-25 Tokyo Electron Limited Method of manufacturing semiconductor device
CN105097498A (en) * 2014-05-14 2015-11-25 东京毅力科创株式会社 Method for etching etching-target layer

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01200624A (en) * 1988-02-05 1989-08-11 Toshiba Corp Dry etching
JPH05326499A (en) * 1992-05-19 1993-12-10 Fujitsu Ltd Manufacture of semiconductor device
US6686292B1 (en) * 1998-12-28 2004-02-03 Taiwan Semiconductor Manufacturing Company Plasma etch method for forming uniform linewidth residue free patterned composite silicon containing dielectric layer/silicon stack layer
US6287974B1 (en) * 1999-06-30 2001-09-11 Lam Research Corporation Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
JP2007081383A (en) * 2005-08-15 2007-03-29 Fujitsu Ltd Method of manufacturing fine structure
JP2012079792A (en) * 2010-09-30 2012-04-19 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device
JP5981106B2 (en) * 2011-07-12 2016-08-31 東京エレクトロン株式会社 Plasma etching method
TWI497586B (en) * 2011-10-31 2015-08-21 Hitachi High Tech Corp Plasma etching method
KR102034556B1 (en) * 2012-02-09 2019-10-21 도쿄엘렉트론가부시키가이샤 Plasma processing method
JP6211947B2 (en) * 2013-07-31 2017-10-11 東京エレクトロン株式会社 Manufacturing method of semiconductor device
JP6277004B2 (en) * 2014-01-31 2018-02-07 株式会社日立ハイテクノロジーズ Dry etching method
JP6230930B2 (en) * 2014-02-17 2017-11-15 東京エレクトロン株式会社 Manufacturing method of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150179466A1 (en) * 2013-12-19 2015-06-25 Tokyo Electron Limited Method of manufacturing semiconductor device
CN105097498A (en) * 2014-05-14 2015-11-25 东京毅力科创株式会社 Method for etching etching-target layer

Also Published As

Publication number Publication date
CN106992121B (en) 2020-10-09
US10707090B2 (en) 2020-07-07
JP6604833B2 (en) 2019-11-13
TW201721739A (en) 2017-06-16
KR20170065449A (en) 2017-06-13
CN106992121A (en) 2017-07-28
JP2017103388A (en) 2017-06-08
KR102363783B1 (en) 2022-02-15
US20180226264A1 (en) 2018-08-09
SG10201610044VA (en) 2017-07-28
US20170162399A1 (en) 2017-06-08
US9966273B2 (en) 2018-05-08

Similar Documents

Publication Publication Date Title
TWI706460B (en) Plasma etching method
TWI743072B (en) Etching method and etching device
US10381237B2 (en) Etching method
JP6498022B2 (en) Etching method
TWI710021B (en) Etching treatment method
TWI723096B (en) Etching method
JP4653603B2 (en) Plasma etching method
TWI746566B (en) Etching processing method
TW200947548A (en) Plasma etching method, plasma etching apparatus and computer-readable storage medium
TWI734713B (en) Plasma etching method
US7902078B2 (en) Processing method and plasma etching method
TW200414344A (en) Method and apparatus for etching Si
JP2022034956A (en) Etching method and plasma processing apparatus
US10651077B2 (en) Etching method
JP7195113B2 (en) Processing method and substrate processing apparatus
JP2019134107A (en) Etching method and etching device
JP2015106587A (en) Method for coating electrostatic chuck and plasma processing apparatus