TWI704704B - Magnetoresistive random access memory array and methods for forming the same - Google Patents

Abstract

An array, such as an MRAM (Magnetic Random Access Memory) array formed of a multiplicity of layered thin film devices, such as MTJ (Magnetic Tunnel Junction) devices, can be simultaneously formed in a multiplicity of horizontal widths in the 60nm range while all having top electrodes with substantially equal thicknesses and coplanar upper surfaces. This allows such a multiplicity of devices to be electrically connected by a common conductor without the possibility of electrical opens and with a resulting high yield.

Description

Magnetoresistive random access memory array and its forming method

The present invention relates to the manufacture of a magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM) device, in particular to a method for depositing and patterning a multilayer magnetic tunnel junction unit.

The manufacture of magnetoresistive random access memory (MRAM) devices is usually associated with a series of process steps. These steps include depositing many metal and dielectric layers to form a stack, and then patterning the stack to form An array containing a plurality of separated magnetoresistive elements, such as a magnetic tunneling junction (MTJ) and its upper and lower electrodes, are used for electrical connection with the elements. In order to define those magnetic tunneling interface units in each magnetoresistive random access memory device and prevent them from interacting with each other (until they need to interact), a sophisticated patterning step is usually used: including Photolithography and plasma etch, such as reactive ion etching (RIE), ion beam etching (IBE) or a combination of the foregoing. In the photolithography process, the pattern is first transferred from the mask to the light-sensitive photoresist layer, and then plasma etching is used to define the array of magnetic tunnel junction elements to form independent and non-interactive elements. The magnetic tunnel junction element. After plasma etching, the smaller-sized elements in the patterned array usually leave fewer upper electrodes, because during the etching process, the photoresist layer covering the elements is consumed at a faster rate. Since the difference in electrode thickness will cause non-planar top surface, it is a big challenge for the final setting of the top metal contacts to connect the electrodes, which may cause open circuits (that is, poor contacts). Components). If those skilled in the art want to achieve high yields on magnetic tunnel junction devices of small size (for example, less than 60 nanometers (sub 60nm)), it is obvious that new methods need to be developed. Therefore, it is worth noting that the prior art patents have disclosed some methods that can solve the above-mentioned difficulties. For example, US patent U.S. 9,070,869 (Jung et al) teaches various layer structures, and US patent U.S. 8,975,088 (Satoh et al) teaches several different mask layers. However, none of these prior arts disclose the methods disclosed in the present invention, nor do they show the results that can be achieved by applying these methods.

One of the objectives of the embodiments of the present invention is to provide a method suitable for a small-scale magnetic tunnel junction element array and a plurality of yield gain methods including such elements of different sizes by patterning the magnetic tunnel junction An additional layer is added between the hard mask of the surface element and the electrode, and the electrode is the top layer of the magnetic tunnel junction surface stack to be patterned.

Another objective of the embodiments of the present invention is to provide such a yield improvement. The method of yield improvement is mainly due to the successful elimination of the electrical open circuit related to the extremely small upper electrode damage.

Another objective of the embodiments of the present invention is to provide the above-mentioned advantages to the magnetic tunnel junction elements of various sizes and arranged adjacent to each other, and at the same time, they can be simultaneously performed on a common substrate.

In the traditional prior art manufacturing process, the pattern is first transferred from the photoresist layer to the dielectric hard mask, then transferred to the upper electrode, and then to the magnetic tunnel junction stack under the upper electrode. After the etching process of pattern transfer is completed, it can be found that the size of the upper electrode with a smaller part of the pattern will be reduced after etching. When the feature size of the pattern is reduced to 60 nanometers and below, it will cause electricity Open circuit (failure of conductivity) and great yield loss.

In order to solve these deficiencies, the method disclosed in the present invention is to insert a chemical mechanical polishing (CMP) stop layer and a sacrificial layer between the photoresist hard mask pattern and the electrode. After plasma etching, any difference in photoresist consumption will only result in different thickness (height) of the sacrificial layer pattern by chemical mechanical polishing. Based on the chemical mechanical polishing stop layer as a protection, the thickness of the electrodes on the components of all sizes can be kept consistent and equal. By selecting an appropriate slurry in the subsequent chemical mechanical polishing process, any remaining sacrificial layer patterns can be completely removed and terminated on the chemical mechanical polishing stop layer. Afterwards, the chemical mechanical polishing stop layer is removed by plasma etching to expose the upper electrode underneath. Using this method, magnetic tunnel junction units of different sizes can still maintain their upper electrodes at the same height, and make it easier to deposit the top metal contacts for subsequent connections. It can effectively avoid and eliminate any yield loss caused by electrical open circuit. The method disclosed in the present invention is very helpful for the manufacturing of magnetoresistive random access memory products smaller than 60nm and other small-sized components in the future.

A sequence of schematic diagrams of the process flow are shown in Figures 1A to 1F, which reveal the application of the method of this step flow, which aims to create two adjacent and different-sized exemplary magnetic tunnel junction elements at the same time, but two The device still has an upper electrode with approximately the same height and a coplanar top surface. Therefore, it is possible to better connect the components by using common metal contacts without additionally forming an electrical open circuit (open circuit).

First, please refer to FIG. 1A, which discloses a schematic diagram of a single stacked structure of the present invention using a first plasma etching 110 to pattern two adjacent but separated magnetic tunnel junction devices. It should be understood that, in order to simplify the description of the technical idea of the embodiment of the present invention, the two elements are only exemplary. Therefore, it is expected that the technology disclosed in the embodiment of the present invention can be applied to an array including a plurality of discrete elements. Here, we note that the magnetic tunnel junction device is one of the active devices that can be fabricated using the following methods. Only any type of active multi-layer device can be formed as an array including various width devices, and electrodes can be placed on it. A top electrode with a coplanar top surface is formed. Without forming an open circuit between the array elements, a single electrical connection layer can be advantageously formed thereon.

From bottom to top, the substrate 10 may be a common electrical contact, such as a material layer made of Ta, TaN, Ti or TiN, or the top of an additional integrated electronic structure. Then, in order from above, there are the lower electrode 20, the multilayer magnetic tunnel junction stack 30, the upper electrode 40 with a thickness of about 200-1000A, and the chemical mechanical polishing stop layer 50 with a thickness of about 20-300A. , A chemical mechanical polishing sacrificial layer 60 (sometimes also referred to as sacrificial layer) with a thickness of about 200-1000A Wherein, the chemical mechanical polishing sacrificial layer 60 can be separately provided or formed in combination with a hard mask (HM) layer (not separately shown), and the composition has a thickness of about 200-2000A. An additional hard mask (HM) layer (not separately shown in the figure) provided on the chemical mechanical polishing sacrificial layer 60 can be used to improve the subsequent plasma etching selectivity. It is worth noting that the method of adding a dielectric hard mask (HM) layer to improve the etching selectivity while etching the chemical mechanical polishing of the sacrificial layer can be thought of as a "thick hard mask". This combination improves the overall Selective. For example, plasma gas materials such as CHF ₃ , CH ₂ F ₂ or C ₄ F ₈ can be used, which can be easily etched on hard masks, but have relatively low etching on photoresist materials rate. Finally, a photoresist layer (PR) with a thickness of about 1000-3000A is formed on the hard mask (if present) or the chemical mechanical polishing sacrificial layer 60. The photoresist layer shown in the present invention has been lithographically formed to include two photoresist patterns 701 and 702 with widths d1 and d2, which will eventually form two magnetic tunnel junction elements of these sizes. The upper electrode 40 freely deposited on the magnetic tunnel junction stack 30 is, for example, a conductive layer containing a conductive material such as Ta, Ti, TaN, or TiN. The chemical mechanical polishing stop layer 50 is a SiO ₂ or SiON layer and is deposited on the upper electrode 40. The chemical mechanical polishing sacrificial layer 60 is a layer of Ta, Ti, TaN and TiN, and is deposited on the chemical mechanical polishing stop layer 50. In order to improve the subsequent plasma etching selectivity and pattern integrity, a dielectric hard mask layer, such as a SiN, SiO ₂ or SiON layer, can be selectively disposed on the chemical mechanical polishing sacrificial layer 60 (not specifically shown in the figure). Out). The photoresist patterns 701 and 702 can be formed by a photolithography process known in the art. As shown in Figure 1A, in order to better understand the technical features of the method disclosed in the embodiment of the present invention, the photoresist pattern widths d1 and d2 disclosed in Figure 1A are used, where the width d1>the width d2, as two Exemplary description. In this embodiment, the width d1 is about 60-100 nm, and the width d2 is about 10-60 nm.

An important key point in this embodiment is that one of the magnetic tunnel junction elements is larger in size (in the horizontal direction) than the other, so that the etching process will eventually leave a different thickness ( Vertical direction), which may have an adverse effect on the process yield. The first plasma etching 110 is applied to the opening between the photoresist patterns 701 and 702 to separate the stack.

Next, please refer to Figure 1B, which is a schematic diagram of the structure of Figure 1A after plasma etching (reactive ion etching, ion beam etching, or a combination of the foregoing), which has two substantially uniform widths d1 and A gap 80 is formed between the remaining parts of d2. The stack portion with the larger width d1 includes the remaining CMP sacrificial layer 601 to have a final thickness h1, and the CMP sacrificial layer 602 with a smaller size pattern has a final thickness h2, where the thickness h1 is greater than the thickness h2. The reason for the difference in the final thickness is that the smaller size photoresist layer (the photoresist pattern 702 in Figure 1A) on the smaller size chemical mechanical polishing sacrificial layer 602 will be larger during the plasma etching process. It consumes quickly, causing part of the chemical mechanical polishing sacrificial layer 602 to be etched away. It is conceivable that if the upper electrode (the upper electrode 40 in Figure 1A) is directly arranged under the photoresist layer and/or the dielectric hard mask layer not shown, then the upper electrodes 401 and 402 will replace the chemical mechanical The sacrificial layers 601 and 602 are polished to leave different thicknesses.

As shown in FIG. 1C, after plasma etching, an encapsulation layer 90 is deposited in the patterned magnetic tunnel junction stack to fill the gap 80 between them (FIG. 1B). The encapsulation layer 90 may be SiN, SC or SiCN, for example, and is formed by chemical vapor deposition (CVD). Then, as shown in Figure 1C, the first chemical mechanical polishing 120 is performed using the polishing slurry 1 listed in Figure 2, which can apply the material of the encapsulation layer 90 and the optional additional dielectric hard mask (if If used, perform high grinding rate. The first chemical mechanical polishing process 120 can completely remove the upper part of the encapsulation layer 90 and the additional hard mask part (if used), and stop at the remaining chemical mechanical polishing sacrificial layers 601 and 602.

As shown in FIG. 1C, the second chemical mechanical polishing process 130 is then performed using the polishing slurry 2 listed in FIG. 2 to completely polish the remaining chemical mechanical polishing sacrificial layers 601 and 602. Since the polishing slurry 2 has an extremely low polishing rate for the material of the chemical mechanical polishing stop layer, the polishing process stops on the chemical mechanical polishing stop layer 501 and 502.

Next, referring to Figure 1D, the present invention applies a second plasma etching 140 again to etch back the chemical mechanical polishing stop layers 501 and 502, thereby exposing the upper surfaces of the electrodes 401 and 402 located below and above. . As shown in Figure 1E, at this time, the upper surfaces exposed by the resulting upper electrodes 401 and 402 are now coplanar, and the two magnetic tunnel junction elements 301 and 302 are now electrically separated and can be completely separated. The upper electrodes 401, 402 and the lower electrodes 201, 202 are individually defined. In this case, the two components are at the same height, and any height difference caused by the first etching process shown in Figure 1B has been completely eliminated at this time.

Finally, as shown in Figure 1F, a common top metal contact 100 (such as a Ta, TaN, Ti, Al, or Cu layer) is deposited on the coplanar surfaces of the upper electrodes 401 and 402 to form the same as the two embodiments The magnetic tunnel junction elements 301 and 302 (and otherwise insulated) are electrically connected. The final width d3 of the large-size pattern and the final width d4 of the small-size pattern each have their own upper electrodes 401, 402, and have a coplanar top surface and the same upper electrode thickness h3, thereby avoiding the need for conventional metal connections on the top. Problems such as yield loss caused by the formation of electrical openings in the dot 100.

As those with ordinary knowledge in the art can understand, the above description of the embodiments of the present invention is intended to provide a public description of the technical ideas of the present invention, and is not a limitation to the embodiments of the present invention. Any method, material, structure, method for forming or providing a plurality of magnetic tunnel junction elements of small size (within the horizontal size range of about 60 nanometers) to have uniform thickness (in the vertical direction) of the upper electrode Or size is modified or adjusted to improve its yield. The spirit and scope of the embodiments of the present invention are defined by the appended claims according to the embodiments of the present invention, and should still belong to the scope of the invention of the embodiments of the present invention.

According to an embodiment, a magnetoresistive random access memory array includes a common substrate; N spatially independent multilayer elements are formed on the common substrate, wherein each multilayer element has a width d _n , where n=1... N, and the widths are different from each other; each multilayer component has the same height, and the packaging layer for filling the gap is formed between adjacent multilayer components. The packaging layer has a variable width s _jk , where j=1...N, And k=j+1; wherein each of the multilayer components further includes a bottom electrode having substantially the same thickness; an active device component is formed on the bottom electrode; an upper electrode is formed on the active device component, wherein the upper electrode has substantially the same thickness , And the top surfaces of all the upper electrodes are coplanar; and a single top metal contact is formed on the upper electrodes to form an electrical connection with each upper electrode without an open circuit.

In other embodiments, the upper electrode and the lower electrode are formed of Ta, Ti, TaN or TiN, and have a thickness of about 200-1000 Å.

In other embodiments, each active device element is a magnetic tunnel junction element.

In other embodiments, the exemplary width of each multilayer element is about 60 nanometers or less.

In other embodiments, the encapsulation layer is a SiN, SC or SiCN layer.

According to one embodiment, a method for forming a magnetoresistive random access memory array includes providing a substrate; forming a multilayer stack on the substrate adjacent to each other, including a bottom electrode, contacting the substrate; and the multilayer stack including a plurality of functions Sexual element layer; upper electrode, covering the multilayer stack and having a height; chemical mechanical polishing stop layer, covering the upper electrode; chemical mechanical polishing sacrificial layer, or optionally combined with a hard mask layer, covering the chemical mechanical polishing stop layer ; The patterned photoresist layer is used to define the width and spacing between the arrays; the patterned photoresist layer is used to pattern the multilayer stack.

In other embodiments, the patterning process includes applying a first plasma etching through the patterned photoresist layer to separate the multilayer stack into an array having adjacent but independent portions, wherein each portion has a width, and Each part forms a gap with the adjacent part pre-defined by the patterned photoresist layer. After the first plasma etching, the sacrificial layer is chemically mechanically polished or selectively combined with the hard mask layer. A final undetermined height is formed, where each part has an undetermined unique height resulting in the final undetermined height; the part removed by the first plasma etching in the multilayer stack is filled by depositing an encapsulation layer; the first polishing slurry is used with In the first chemical mechanical polishing process, in the case of using a combination of a chemical mechanical polishing layer and a hard mask layer, remove the upper part of the encapsulation layer and the hard mask layer, and stop at the chemical mechanical polishing sacrificial layer, if the hard mask layer is not used For the mask layer, remove the upper part of the encapsulation layer and stop at the chemical mechanical polishing sacrificial layer; use the second slurry and the second chemical mechanical polishing process to remove the chemical mechanical polishing sacrificial layer and stop at the chemical mechanical polishing stop layer; use The second plasma etching process removes the chemical mechanical polishing stop layer exposed by the second chemical mechanical polishing process, thereby exposing upper electrodes on each part of the patterned multilayer stack, wherein each upper electrode is The top surface of the encapsulation layer between adjacent parts is coplanar, and each upper electrode has the same height; the top metal contact is formed to cover the coplanar top surface, so that the top metal contact forms an electrical connection with each upper electrode. The electrical connection has nothing to do with the open circuit.

In other embodiments, the height of the upper electrode is between about 200-1000A.

In other embodiments, the combination of the sacrificial layer and the hard mask layer using chemical mechanical polishing makes the plasma etching containing CHF ₃ , CH ₂ F ₂ or C ₄ F _{8 used} to etch the dielectric hard mask, and the light The resist layer has a relatively low etching rate.

In other embodiments, the hard mask layer is a SiN, SiO ₂ or SiON layer.

In other embodiments, the chemical mechanical polishing sacrificial layer is a Ta, Ti, TaN or TiN layer.

In other embodiments, the chemical mechanical polishing stop layer is an SiO ₂ or SiON layer.

In other embodiments, the first slurry is a slurry of zirconia particles.

In other embodiments, the second slurry is a slurry of alumina particles.

10　 base 20, 201, 202 Lower electrode 30　Magnetic tunnel junction stack 40, 401, 402 upper electrode 50, 501, 502 Chemical mechanical polishing stop layer 60, 601, 602　 chemical mechanical polishing sacrificial layer 80　 interval 90　Package layer 100　 top metal contact 110　 first plasma etching 120　First Chemical Mechanical Polishing 130　Second chemical mechanical polishing 140　 second plasma etching 301, 302　 magnetic tunnel junction element 701, 702　 photoresist pattern d1, d2, d3, d4 　 width h1, h2, h3 　 thickness

Figure 1A, Figure 1B, Figure 1C, Figure 1D, Figure 1E, Figure 1F are a sequence of schematic diagrams of manufacturing high-yield magnetoresistive random access memory devices of various sizes. FIG. 2 discloses a list of two kinds of chemical mechanical polishing slurry that can produce different polishing rates, which can be used for different devices in the magnetoresistive random access memory device layer.

10　 base 100　 top metal contact 201, 202　 lower electrode 301, 302 Magnetic tunnel junction element 401, 402 Upper electrode d3, d4 　 width h3 Thickness

Claims (10)

A magnetoresistive random access memory array, comprising: a common substrate; N multi-layer elements that are independent in space are formed on the common substrate, wherein each of the multi-layer elements has a width d _n , where n= 1...N, and the widths are different from each other; each of the multilayer components has the same height, and an encapsulation layer for filling the gap is formed between the adjacent multilayer components, and the encapsulation layer has a Variable width s _jk , where j=1...N, and k=j+1; wherein each of the multilayer components further includes: a lower electrode having approximately the same thickness; and an active device component formed on the lower electrode; An upper electrode formed on the active device device, wherein the upper electrode has approximately the same thickness, and the top surfaces of all the upper electrodes are coplanar; and a single top metal contact is formed on the upper electrodes, And physically contact each of the upper electrodes to form an electrical connection without an open circuit, and the single top metal contact is a common contact of each of the multilayer components. The magnetoresistive random access memory array described in the first item of the patent application, wherein the upper electrode and the lower electrode are formed of Ta, Ti, TaN or TiN and have a thickness of about 200-1000A. In the magnetoresistive random access memory array described in item 1 or 2 of the scope of patent application, each of the active device elements is a magnetic tunneling interface element. A method for forming a magnetoresistive random access memory array includes: providing a substrate; forming a multilayer stack on the substrate sequentially and adjacently, including: a lower electrode contacting the substrate; an active device element including a plurality of A functional element layer; an upper electrode covering the active device element and having a height; A chemical mechanical polishing stop layer covering the upper electrode; a chemical mechanical polishing sacrificial layer, or optionally combined with a hard mask layer, covering the chemical mechanical polishing stop layer; a patterned photoresist layer for defining The width and spacing distance between the arrays are calculated; the patterned photoresist layer is used to perform a patterning process on the multilayer stack. The method for forming a magnetoresistive random access memory array as described in claim 4, wherein the patterning process includes: applying a first plasma etching through the patterned photoresist layer to stack the multilayer The objects are separated into arrays with adjacent but independent parts, wherein each part has a width, and each part forms an interval with the adjacent part predefined by the patterned photoresist layer, passing through the After a plasma etching, a final undetermined height is formed on the chemical mechanical polishing sacrificial layer, or optionally in combination with the hard mask layer, where each part has an undetermined unique height resulting in the final undetermined height. Determine the height; fill the part of the multilayer stack that is removed by the first plasma etching by depositing an encapsulation layer; use a first polishing slurry and a first chemical mechanical polishing process, and use a chemical mechanical polishing layer and In the case of a combination of hard mask layers, remove the upper part of the encapsulation layer and the hard mask layer, and stop at the chemical mechanical polishing sacrificial layer, if the hard mask layer is not used, remove the upper part of the encapsulation layer And stop at the chemical mechanical polishing sacrificial layer; use a second polishing slurry and a second chemical mechanical polishing process to remove the chemical mechanical polishing sacrificial layer and stop at the chemical mechanical polishing stop layer; use a second plasma to etch Process, removing the chemical mechanical polishing stop layer exposed through the second chemical mechanical polishing process, thereby exposing the upper electrode on each part of the patterned multilayer stack, wherein each of the upper electrodes is The top surface of the encapsulation layer between adjacent parts is coplanar, and each of the upper electrodes has the same height; A top metal contact is formed to cover the coplanar top surface, so that the top metal contact forms an electrical connection with each of the upper electrodes, and the electrical connection has nothing to do with the open circuit. The method for forming a magnetoresistive random access memory array as described in item 4 or 5 of the scope of patent application, wherein the chemical mechanical polishing sacrificial layer and the hard mask layer are combined to include CHF ₃ , CH ₂ F ₂ Or C ₄ F ₈ plasma etching can be used to etch the dielectric hard mask, and has a relatively low etching rate on the photoresist layer. According to the method for forming a magnetoresistive random access memory array described in item 4 or 5 of the scope of patent application, the chemical mechanical polishing sacrificial layer is a Ta, Ti, TaN or TiN layer. According to the method for forming a magnetoresistive random access memory array described in item 4 or 5 of the scope of patent application, the chemical mechanical polishing stop layer is an SiO ₂ or SiON layer. According to the method for forming a magnetoresistive random access memory array described in item 4 or 5 of the scope of patent application, the first polishing slurry is a slurry of zirconia particles. According to the method for forming a magnetoresistive random access memory array described in item 4 or 5 of the scope of patent application, the second polishing slurry is a polishing slurry of alumina particles.

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