TWI704665B - Back end of line passivation structure and fabricating method thereof - Google Patents

Abstract

A back end of line (BEOL) passivation structure and fabricating method thereof are provided. The passivation structure includes a semiconductor chip with a plurality of conductive lines, a first oxide layer, a spin-on glass (SOG) layer, a second oxide layer and a nitride layer. The conductive lines have a first aspect ratio more than 1.5 therebetween. The first oxide layer is conformally deposited on the surfaces of the conductive lines and the surface of the semiconductor chip. The SOG layer is disposed on the first oxide layer between each two of the conductive lines, and the SOG layer has a U-shaped cross section and a second aspect ratio of 0.3-0.8. The second oxide layer is conformally deposited on the surface of the first oxide layer and the surface of the SOG layer. The nitride layer is disposed on the second oxide layer.

Description

Protective layer structure of back-end manufacturing process and manufacturing method thereof

The present invention relates to a back-end (BEOL) manufacturing process of a semiconductor manufacturing process, and particularly relates to a back-end manufacturing process and a protective layer structure and a manufacturing method thereof.

The semiconductor process includes a front-end process and a back-end process, and the packaging process is performed after the back-end process.

Usually after the packaging process, component reliability tests such as temperature, humidity, bias (THB) test, high accelerated stress test (HAST) and other component reliability tests are carried out, mainly using high temperature, high humidity and high pressure The test conditions accelerate the penetration of water vapor through the protective layer or along the interface between the protective layer and the metal wire to the inside of the device to evaluate the IC's resistance to moisture corrosion.

However, due to the height (or thickness) of the wire structure in the later process, the wire structure has a high aspect ratio, which easily causes the protective layer deposited on the surface of the wire structure to have insufficient coverage near the bottom of the wire structure. It causes cracks in the protective layer and even metal lifting (metal lifting) to make the structure incomplete. It is particularly easy to obtain low yield results in circuit probe (CP) testing or back-end (FT) testing. In the reliability test (for example: HAST), there will be problems.

Therefore, strengthening the entire structure and solving the high aspect ratio required by the manufacturing process are currently urgent problems to be solved.

The present invention provides a protective layer structure of the back-end manufacturing process, which can prevent the protective layer from cracking or lifting of the metal wire, and maintain the integrity of the structure after undergoing the reliability test of high temperature and humidity, In turn, IC reliability is improved.

The present invention provides a method for manufacturing a protective layer structure in a back-end manufacturing process, which reduces the aspect ratio of the wire structure without increasing the mask, so as to strengthen the protective layer structure and achieve the purpose of protecting components.

The protective layer structure of the back-end process of the present invention includes a semiconductor wafer with a plurality of wire structures, a first oxide layer, a spin-on glass (SOG) layer, a second oxide layer and a nitride layer. These wire structures have an aspect ratio greater than 1.5. The first oxide layer is conformally deposited on the surface of the wire structure and the surface of the semiconductor wafer. The SOG layer is located on the first oxide layer between every two wire structures, and the SOG layer has a U-shaped cross section and a second aspect ratio of 0.3 to 0.8. The second oxide layer is conformally deposited on the surface of the first oxide layer and the surface of the SOG layer, and the nitride layer is located on the second oxide layer.

In an embodiment of the present invention, the thickness of the first oxide layer is between 2000 Å and 4000 Å.

In an embodiment of the present invention, the height of the aforementioned wire structure is greater than 2 µm.

In an embodiment of the present invention, the height difference of the U-shaped cross-section of the SOG layer is less than 700 Å.

In an embodiment of the present invention, the first oxide layer located on the top of the wire structure directly contacts the second oxide layer.

In an embodiment of the present invention, the thickness of the aforementioned nitride layer is proportional to the height of each wire structure.

In an embodiment of the present invention, the material of the aforementioned wire structure includes aluminum or aluminum alloy.

The manufacturing method of the protective layer structure of the back-end process of the present invention includes forming a plurality of wire structures on a semiconductor wafer, wherein the plurality of wire structures have a first aspect ratio between them, and the first aspect ratio is greater than 1.5. Then a first oxide layer is deposited conformally on the surface of the wire structure and the surface of the semiconductor wafer, and then spin-on glass is coated on the semiconductor wafer, and the spin-on glass is etched back until the first oxide layer on the top of the wire structure is exposed An oxide layer to form a spin-on glass (SOG) layer on the first oxide layer between every two wire structures, wherein the SOG layer has a U-shaped cross section, and the SOG layer has a second aspect ratio , Wherein the second aspect ratio is between 0.3 and 0.8. A second oxide layer is conformally deposited on the surface of the first oxide layer and the surface of the SOG layer, and then a nitride layer is formed on the second oxide layer.

In another embodiment of the present invention, the steps of depositing the second oxide layer and forming the nitride layer are continuously formed in the same machine.

In another embodiment of the present invention, the method for etching back spin-on glass includes a plasma etching process.

Based on the above, the present invention first fills SOG between the BEOL wires and removes part of the SOG by etching back, so that the original aspect ratio between the wires is reduced due to the SOG with good trench filling ability. Therefore, it is possible to avoid insufficient coverage at the bottom of the protective layer (between the wires) during the subsequent deposition of the oxide layer and the nitride layer as the protective layer, resulting in cracking of the protective layer or lifting of the metal wire. Especially after the reliability test of high temperature and humidity, the integrity of the structure itself can be maintained without affecting the reliability of the IC.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Hereinafter, a few embodiments are listed in conjunction with the drawings for detailed description, but the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. In order to facilitate understanding, the same elements in the following content will be described with the same symbols. In addition, the terms "include", "include", "have" and so on used in the text are all open terms; that is, including but not limited to. Moreover, the directional terms mentioned in the text, such as "上", "下", etc., are only used to refer to the directions of the drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present invention.

FIG. 1 is a schematic diagram of a protective layer structure of a back-end process according to a first embodiment of the present invention.

1, the protective layer structure of the back-end process of this embodiment includes a semiconductor wafer 100 having a plurality of wire structures 102, a first oxide layer 104, a spin-on glass (SOG) layer 106, a second oxide layer 108, and nitrogen The compound layer 110, where the semiconductor chip 100 refers to a chip that has completed the previous process on a semiconductor wafer, that is, the semiconductor chip 100 includes at least a semiconductor wafer, various components (such as transistors, capacitors, resistors, etc.), and interconnects (Interconnection) and so on. The wire structure 102 is the outermost wiring that connects the internal circuits of the semiconductor chip 100 to the outside. The material includes aluminum or aluminum alloy, but the present invention is not limited to this. Therefore, the line width and height h of the wire structure 102 are larger than those in the previous process, for example, the height h is greater than 2 µm, such as 8k (Å), 2 µ (m), 3 µ (m) and other processes. Therefore, the wire structures 102 have a first aspect ratio greater than 1.5, where the first aspect ratio refers to the height h of each wire structure 102 divided by the distance w between the two wire structures 102 (= h/ w). The first oxide layer 104 is conformally deposited on the surface of the wire structure 102 and the surface of the semiconductor wafer 100, wherein the thickness t of the first oxide layer 104 is, for example, between 2000 Å and 4000 Å. The SOG layer 106 is located on the first oxide layer 104 between every two wire structures 102; that is, the wire structure 102 and the semiconductor wafer 100 are separated by the first oxide layer 104 and the SOG layer 106 to prevent coating During the process of distributing SOG, the lower components are affected by moisture.

Please continue to refer to FIG. 1, because the first aspect ratio is extremely large, SOG can fill the space between the wire structures 102 reliably due to the fluidity of the SOG, and form the SOG layer 106 with a U-shaped cross-section 106a, and This SOG layer 106 has a second aspect ratio between 0.3 and 0.8, where the second aspect ratio refers to the height difference d of the U-shaped cross-section 106a divided by (the distance w between the two wire structures 102 minus The value of twice the thickness t) of the first oxide layer 104 (=d/(w-2t)), where the height difference d of the U-shaped cross section 106a of the SOG layer 106 is less than 700 Å, for example. The second oxide layer 108 is conformally deposited on the surface of the first oxide layer 104 and the surface of the SOG layer 106 such that the first oxide layer 104 on the top of the wire structure 102 directly contacts the second oxide layer 108. The nitride layer 110 is located on the second oxide layer 108 as a stress layer to relieve the stress between the conductive structure 102 and the semiconductor wafer 100. The nitride layer 108 is, for example, a silicon nitride layer, a boron nitride layer or a silicon oxynitride layer, and The thickness of the nitride layer 108 may be proportional to the height h of each wire structure 102; that is, if the height h of the wire structure 102 becomes higher, the thickness of the nitride layer 108 is preferably thicker, and so on.

In this implementation, since the second aspect ratio is significantly smaller than the first aspect ratio, when depositing the second oxide layer 108 and the nitride layer 110 as the protective layer, the situation of insufficient coverage between the wire structures 102 is avoided. And to avoid the occurrence of cracking of the protective layer or lifting of the metal wire. Furthermore, the structure of the present invention can also maintain the integrity of the structure itself after undergoing high temperature and high humidity reliability tests (such as HAST, THB, etc.) without affecting the reliability of the IC.

2A to 2E are schematic cross-sectional views of a manufacturing process of a protective layer structure in a back-end process according to a second embodiment of the present invention.

2A, a plurality of wire structures 202 are formed on the semiconductor wafer 200, and the wire structures 202 have a first aspect ratio greater than 1.5; that is, the height h of the wire structure 102 is divided by the two wire structures 102 The value of the distance w (= h/w) is greater than 1.5. The material of the above-mentioned wire structure 202 includes aluminum or aluminum alloy, and its formation method includes first forming a whole layer of metal by chemical vapor deposition (CVD), physical vapor deposition (such as sputtering, etc.), and then using The method of lithography and etching defines the wire structure 202.

Then, referring to FIG. 2B, a first oxide layer 204 is conformally deposited on the surface of the wire structure 202 and the surface of the semiconductor wafer 200, wherein the thickness t of the first oxide layer 204 is, for example, between 2000Å and 4000Å, and the method of forming Including chemical vapor deposition methods, such as plasma enhanced chemical vapor deposition (PECVD).

Afterwards, referring to FIG. 2C, spin-on-glass (SOG) 206 is coated on the semiconductor wafer 200, and the formation method thereof includes spin coating. Since the spin-on glass 206 is a liquid material, it fluctuates with the contour of the underlying structure (the wire structure 102) and fills the space between the wire structures 102.

Next, referring to FIG. 2D, the spin-on glass 206 is etched back until the first oxide layer 204 on the top of the wire structure 202 is exposed, so as to form a spin on the first oxide layer 204 between every two wire structures 202. In the SOG layer 206a, the method for etching back the spin-on glass includes a plasma etching process, and the SOG is cured by baking after the etching back. In the figure, the SOG layer 206a has a second aspect ratio between 0.3 and 0.8; that is, the height difference d of the U-shaped section 206b of the SOG layer 206a is divided by (the distance w between the two wire structures 202 is reduced by The value (=d/(w-2t)) of twice the thickness t) of the first oxide layer 204 is between 0.3 and 0.8, which is significantly smaller than the aforementioned first aspect ratio.

Then, referring to FIG. 2E, a second oxide layer 208 is conformally deposited on the surface of the first oxide layer 104 and the surface of the SOG layer 206a, and then a nitride layer 210 is formed on the second oxide layer 208. The above-mentioned nitride layer 210 includes a silicon nitride layer, a boron nitride layer or a silicon oxynitride layer, and its formation methods include chemical vapor deposition, low-pressure chemical vapor deposition (low-pressure CVD, LPCVD), and plasma enhanced chemical vapor deposition. Phase deposition, atomic layer deposition (ALD), spin coating, sputtering, etc.; the method for forming the second oxide layer 208 includes chemical vapor deposition, such as plasma enhanced chemical vapor deposition. In this embodiment, the steps of depositing the second oxide layer 208 and forming the nitride layer 210 are preferably formed continuously in the same machine, and only need to replace the process gas and adjust the deposition parameters; however, the present invention is not limited to this. In another embodiment, the formation of the second oxide layer 208 and the nitride layer 210 can be made separately on different machines.

In summary, the present invention does not require additional masks in the back-end process (BEOL), and can use the minimum steps in the existing process to make the original aspect ratio between the wires due to the SOG with good trench filling ability. Therefore, during the subsequent deposition of the protective layer, it is possible to avoid the cracking of the protective layer or the lifting of the wire caused by the insufficient coverage of the bottom of the protective layer (between the wires), and the oxidation of the upper and lower SOG layers The layer closes it to ensure that the upper and lower structural layers are not affected by SOG. Moreover, after the reliability test of high temperature and high humidity, the above structure can still maintain the integrity.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 200: semiconductor wafer 102, 202: wire structure 104, 204: first oxide layer 106, 206a: Spin-on glass layer 106a, 206b: U-shaped section 108, 208: second oxide layer 110, 210: Nitride layer 206: Spin-on glass h: height w: distance d: height difference t: thickness

FIG. 1 is a schematic cross-sectional view of a protective layer structure of a back-end process according to a first embodiment of the present invention. 2A to 2E are schematic cross-sectional views of a manufacturing process of a protective layer structure in a back-end process according to a second embodiment of the present invention.

100: semiconductor wafer

102: Wire structure

104: first oxide layer

106: Spin-on glass layer

106a: U-shaped section

108: second oxide layer

110: Nitride layer

h: height

w: distance

d: height difference

t: thickness

Claims (10)

A protective layer structure for the back-end manufacturing process, including: A semiconductor chip with a plurality of wire structures, wherein the plurality of wire structures have a first aspect ratio greater than 1.5; A first oxide layer is conformally deposited on the surface of the plurality of wire structures and the surface of the semiconductor wafer; A spin-on-glass (SOG) layer is located on the first oxide layer between every two of the wire structures, and the SOG layer has a U-shaped cross section, wherein the SOG layer has a second aspect ratio ( The height difference of the U-shaped section divided by (the distance between the two wire structures minus twice the thickness of the first oxide layer), the second aspect ratio is between 0.3 and 0.8 between; A second oxide layer is conformally deposited on the surface of the first oxide layer and the surface of the SOG layer; and The nitride layer is located on the second oxide layer. The protective layer structure of the subsequent process according to claim 1, wherein the thickness of the first oxide layer is between 2000 Å and 4000 Å. The protective layer structure of the subsequent process according to claim 1, wherein the height of the wire structure is greater than 2 µm. The protective layer structure of the subsequent process according to claim 1, wherein the height difference of the U-shaped cross section of the SOG layer is less than 700 Å. The protective layer structure of the subsequent process according to claim 1, wherein the first oxide layer located on the top of the plurality of wire structures directly contacts the second oxide layer. The protective layer structure of the subsequent process according to claim 1, wherein the thickness of the nitride layer is proportional to the height of each wire structure. The protective layer structure of the subsequent process according to claim 1, wherein the material of the plurality of wire structures includes aluminum or aluminum alloy. A manufacturing method of a protective layer structure in a back-end manufacturing process, including: Forming a plurality of wire structures on the semiconductor wafer, wherein the plurality of wire structures have a first aspect ratio between them, and the first aspect ratio is greater than 1.5; Depositing a first oxide layer conformally on the surface of the plurality of wire structures and the surface of the semiconductor wafer; Coating spin-on glass on the semiconductor wafer; The spin-on glass is etched back until the first oxide layer on the top of the plurality of wire structures is exposed, so as to form a spin on the first oxide layer between every two wire structures. A coated glass (SOG) layer, wherein the SOG layer has a U-shaped cross section, and the SOG layer has a second aspect ratio, wherein the second aspect ratio is between 0.3 and 0.8; Depositing a second oxide layer conformally on the surface of the first oxide layer and the surface of the SOG layer; and A nitride layer is formed on the second oxide layer. According to claim 8 of the manufacturing method of the protective layer structure in the subsequent process, the steps of depositing the second oxide layer and forming the nitride layer are continuously formed in the same machine. The manufacturing method of the protective layer structure of the back-end process according to claim 8, wherein the method of etching back the spin-on glass includes a plasma etching process.

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