TWI703728B - Semiconductor structures - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substarte, a gate disposed on the substrate, a source disposed in the substrate and located on one side of the gate, a drain disposed in the substrate and located on the other side of the gate, and a gate extending portion disposed on the substrate and located between the gate and the drain. The doping type of the gate is opposite to that of the gate extending portion.

Description

Semiconductor structure

The present invention relates to a semiconductor structure, in particular to a semiconductor structure capable of reducing drain-to-gate capacitance.

In many semiconductor structures, a field plate structure arranged between the gate and the drain is often used as an important element to disperse the electric field strength of the drain region (drift region) to avoid the vicinity of the drain region (drift region) Excessive concentration of the electric field causes component damage. However, when the field plate structure forms an electrical connection with its adjacent gate, the field plate structure will simultaneously contribute a considerable amount of drain-to-gate capacitance.

Generally speaking, for high-speed switching elements that are expected to achieve high-efficiency electric power conversion, it is necessary to minimize the power loss during operation to maintain high-speed conversion between elements. However, when the switch is turned on and a large current flows, if the above-mentioned drain-gate capacitance exists in the transistor adjacent to the load (phase) at this time, this transistor will be undesirable due to the coupling effect. The current flows through, causing the power loss of the switching element.

At present, there are several methods to reduce the drain-gate capacitance, such as changing the field plate structure to electrically connect the source, or increasing the thickness of the oxide layer under the field plate or gate, or under the gate The surface of the substrate is implanted with dopants of the opposite doping type to the drain region (drift region). However, the various methods described above still result in many disadvantages, such as an increase in resistance.

Therefore, the development of a semiconductor structure that can not only effectively disperse the electric field intensity of the drain region (drift region), but also reduce the drain-to-gate capacitance of the drain-to-gate capacitance is expected.

According to an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes: a substrate; a gate electrode arranged on the substrate; a source electrode arranged in the substrate and located on one side of the gate electrode; a drain electrode arranged in the substrate and located on the gate electrode The other side of the pole; and a gate extension part disposed on the substrate and located between the gate and the drain electrode, wherein the doping type of the gate electrode is opposite to the doping type of the gate extension part.

In some embodiments, the substrate is a P-type substrate or an N-type substrate. In some embodiments, when the substrate is a P-type substrate, the doping type of the gate is N-type, the doping type of the source is N-type, the doping type of the drain is N-type, and the The doping type of the gate extension is P type. In some embodiments, when the substrate is an N-type substrate, the doping type of the gate is P-type, the doping type of the source is P-type, the doping type of the drain is P-type, and The doping type of the gate extension is N-type. In some embodiments, the gate and the gate extension are polysilicon doped with P-type dopants or N-type dopants.

In some embodiments, the gate is substantially in contact with the gate extension. In some embodiments, the gate is substantially separated from the gate extension.

In some embodiments, when the gate is in substantial contact with the gate extension, the semiconductor structure of the present invention further includes a metal field plate (field plate) disposed on the substrate and located between the gate extension and the drain Between poles. In some embodiments, the semiconductor structure of the present invention further includes an oxide layer disposed on the substrate and located under the metal field plate. In some embodiments, the metal field plate is electrically connected to the gate and the gate extension. In some embodiments, the metal field plate is electrically connected to the source. In some embodiments, the ratio of the width of the gate extension to the width of the gate is 0.3-1.2. In some embodiments, the sum of the width of the gate extension and the width of the gate is a fixed value.

In some embodiments, when the gate is substantially separated from the gate extension, the gate is electrically connected to the gate extension. In some embodiments, the gate extension is electrically connected to the source.

In the present invention, two regions with opposite doping types are formed in the polysilicon gate of the MOS transistor through the implantation process (for example, the region adjacent to the drain in the gate (defined as gate extension in the present invention) is P-type doping, the area far away from the drain in the gate (defined as the gate in the present invention) is N-type doping). Due to the effect of capacitor series connection, the drain-to-gate capacitance ) Therefore, the improvement, and as the ratio of the width of the gate extension to the width of the gate gradually increases, the ratio of the drain-gate capacitance decrease becomes more obvious, and the gate extension at this time also has a field plate The function of the (field plate) can effectively disperse the electric field strength of the drain region (drift region) to avoid damage to the device under high-voltage operation. In addition, the above two regions with opposite doping types can also be made into two separate structures. On the one hand, the gate extension can have the function of a field plate, and on the other hand, the overall drain can be reduced. -The effect of gate capacitance. The cost of the present invention is low, and can be simply manufactured without changing the existing MOS process specifications. Due to the decrease of the drain ­-gate capacitance, the undesired current flow due to the coupling effect of the transistor is avoided. The special semiconductor structure design of the present invention can effectively reduce the power loss of the switching element, greatly increase the switching frequency and achieve high-efficiency electric power conversion.

Please refer to FIG. 1, according to an embodiment of the present invention, a semiconductor structure (semiconductor structure) 10 is provided. FIG. 1 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 1, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source electrode 16 is disposed in the substrate 12 and located on one side of the gate electrode 14. The drain electrode 18 is disposed in the substrate 12 on the other side of the gate electrode 14. The gate extension 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extension 20. For example, when the doping type of the gate 14 is N-type, the doping type of the gate extension 20 is P Type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extension 20 is N-type. Since the doping type of the gate electrode 14 is opposite to the doping type of the gate extension portion 20, a depletion region (not shown) is naturally formed between the gate electrode 14 and the gate extension portion 20.

In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate electrode 14 is N-type, the doping type of the source electrode 16 is N-type, and the doping type of the drain electrode 18 is N-type, and The doping type of the gate extension 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate electrode 14 is P-type, the doping type of the source electrode 16 is P-type, and the doping type of the drain electrode 18 is P-type, and The doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

In Figure 1, the gate 14 is in substantial contact with the gate extension 20. For example, the gate 14 and the gate extension 20 are in substantial lateral contact (ie, the sidewalls of the gate 14 and the gate extension 20 Substantial contact). In some embodiments, the ratio of the gate width W _G extending in the width W _E of the portion 20 and gate electrode 14 is between about 0.3 and 1.2, for example, the gate portion 20 extending in the width W _E of about 0.15 micrometers, The width W _{G of the} gate electrode 14 is about 0.5 microns (the ratio of the two is about 0.3), or the width W _{E of the} gate extension 20 is about 0.25 microns, and the width W _{G of the} gate electrode 14 is about 0.4 microns (two The ratio of the two is approximately 0.625), or, the width W _{E of the} gate extension 20 is approximately 0.35 μm, and the width W _{G of the} gate 14 is approximately 0.3 μm (the ratio between the two is approximately 1.17). In some embodiments, the gate width W _E and gate extension portion 20 of the ratio of the width W _G of the electrodes 14 may range between other suitable, it is not limited thereto. In some embodiments, the boundary B _E between the gate extension 20 and the gate 14 is preferably within the range of the drain drift region 22 (that is, the gate extension 20 is only connected to the drain drift region 22 in the substrate 12 overlapping). In some embodiments, the semiconductor structure 10, a gate extending width W _E and gate portion 20 is the sum of W _T is constant width W _G of the electrodes 14, for example, when the gates extend the width W _E section 20 When the ratio to the width W _G of the gate 14 is within the range of 0.3-1.2, the sum W _T of the width W _E of the gate extension 20 and the width W _G of the gate 14 is about 0.65 μm (for example, gate extension portion 20 of a width W _E of about 0.15 microns, a width W _G of the gate 14 is approximately 0.5 microns, or, a gate extension portion 20 width W _E of about 0.25 microns, the gate width W _G 14 The width W _{E of the} gate extension 20 is about 0.35 μm, and the width W _{G of the} gate 14 is about 0.3 μm). In some embodiments, depending on the product requirements, a gate width W _E and gate extension portion 20 of the electrode 14 the width W _G of the sum of W _T also comprise other suitable sizes, it is not limited thereto.

In FIG. 1, the semiconductor structure 10 further includes a metal field plate 24, which is disposed on the substrate 12 and located between the gate extension 20 and the drain 18. As shown in FIG. 1, the semiconductor structure 10 further includes an oxide layer 26, which is disposed on the substrate 12 and located under the metal field plate 24. In Figure 1, the metal field plate 24 and the oxide layer 26 underneath cover part of the gate extension 20, and the metal field plate 24 is electrically connected to the gate 14 and the gate extension 20 through the metal layer 28. . Since the metal field plate 24 is electrically connected to the gate extension 20, in this embodiment, the gate extension 20 can also be regarded as another part of the metal field plate. According to some embodiments, the manufacturing method of the gate electrode 14 and the gate extension portion 20 that are in substantial contact between the two is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12, and then, the patterned polysilicon layer is predetermined The region where the gate electrode 14 is formed is subjected to an N-type implantation process, and a P-type implantation process is performed on the region of the patterned polysilicon layer where the gate extension 20 is scheduled to be formed, or, the gate electrode 14 is scheduled to be formed in the patterned polysilicon layer. A P-type implantation process is performed on the area of the patterned polysilicon layer, and an N-type implantation process is performed on the region where the gate extension 20 is scheduled to be formed in the patterned polysilicon layer. At this point, the gates with opposite doping patterns and substantially contacting each other are completed. Fabrication of pole 14 and gate extension 20.

Referring to FIG. 2, according to an embodiment of the present invention, a semiconductor structure (semiconductor structure) 10 is provided. FIG. 2 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 2, the semiconductor structure 10 includes a substrate 12, a gate electrode 14, a source electrode 16, a drain electrode 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source electrode 16 is disposed in the substrate 12 and located on one side of the gate electrode 14. The drain electrode 18 is disposed in the substrate 12 on the other side of the gate electrode 14. The gate extension 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extension 20. For example, when the doping type of the gate 14 is N-type, the doping type of the gate extension 20 is P Type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extension 20 is N-type. Since the doping type of the gate electrode 14 is opposite to the doping type of the gate extension portion 20, a depletion region (not shown) is naturally formed between the gate electrode 14 and the gate extension portion 20.

In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate electrode 14 is N-type, the doping type of the source electrode 16 is N-type, and the doping type of the drain electrode 18 is N-type, and The doping type of the gate extension 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate electrode 14 is P-type, the doping type of the source electrode 16 is P-type, and the doping type of the drain electrode 18 is P-type, and The doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

In Figure 2, the gate 14 is in substantial contact with the gate extension 20. For example, the gate 14 and the gate extension 20 are in substantial lateral contact (ie, the sidewalls of the gate 14 and the gate extension 20 Substantial contact). In some embodiments, the ratio of the gate width W _G extending in the width W _E of the portion 20 and gate electrode 14 is between about 0.3 and 1.2, for example, the gate portion 20 extending in the width W _E of about 0.15 micrometers, The width W _{G of the} gate electrode 14 is about 0.5 microns (the ratio of the two is about 0.3), or the width W _{E of the} gate extension 20 is about 0.25 microns, and the width W _{G of the} gate electrode 14 is about 0.4 microns (two The ratio of the two is approximately 0.625), or, the width W _{E of the} gate extension 20 is approximately 0.35 μm, and the width W _{G of the} gate 14 is approximately 0.3 μm (the ratio between the two is approximately 1.17). In some embodiments, the gate width W _E and gate extension portion 20 of the ratio of the width W _G of the electrodes 14 may range between other suitable, it is not limited thereto. In some embodiments, the boundary B _E between the gate extension 20 and the gate 14 is preferably within the range of the drain drift region 22 (that is, the gate extension 20 is only connected to the drain drift region 22 in the substrate 12 overlapping). In some embodiments, the semiconductor structure 10, a gate extending width W _E and gate portion 20 is the sum of W _T is constant width W _G of the electrodes 14, for example, when the gates extend the width W _E section 20 When the ratio to the width W _G of the gate 14 is within the range of 0.3-1.2, the sum W _T of the width W _E of the gate extension 20 and the width W _G of the gate 14 is about 0.65 μm (for example, gate extension portion 20 of a width W _E of about 0.15 microns, a width W _G of the gate 14 is approximately 0.5 microns, or, a gate extension portion 20 width W _E of about 0.25 microns, the gate width W _G 14 The width W _{E of the} gate extension 20 is about 0.35 μm, and the width W _{G of the} gate 14 is about 0.3 μm). In some embodiments, depending on the product requirements, a gate width W _E and gate extension portion 20 of the electrode 14 the width W _G of the sum of W _T also comprise other suitable sizes, it is not limited thereto.

In FIG. 2, the semiconductor structure 10 further includes a metal field plate 24, which is disposed on the substrate 12 and is located between the gate extension 20 and the drain 18. As shown in FIG. 2, the semiconductor structure 10 further includes an oxide layer 26, which is disposed on the substrate 12 and located under the metal field plate 24. In FIG. 2, the metal field plate 24 and the oxide layer 26 below it cover part of the gate extension 20, and the metal field plate 24 is electrically connected to the source 16 through the metal layer 30. According to some embodiments, the manufacturing method of the gate electrode 14 and the gate extension portion 20 that are in substantial contact between the two is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12, and then, the patterned polysilicon layer is predetermined The region where the gate electrode 14 is formed is subjected to an N-type implantation process, and a P-type implantation process is performed on the region of the patterned polysilicon layer where the gate extension 20 is scheduled to be formed, or, the gate electrode 14 is scheduled to be formed in the patterned polysilicon layer. A P-type implantation process is performed on the area of the patterned polysilicon layer, and an N-type implantation process is performed on the region where the gate extension 20 is scheduled to be formed in the patterned polysilicon layer. At this point, the gates with opposite doping patterns and substantially contacting each other are completed. Fabrication of pole 14 and gate extension 20.

Referring to FIG. 3, according to an embodiment of the present invention, a semiconductor structure (semiconductor structure) 10 is provided. FIG. 3 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 3, the semiconductor structure 10 includes a substrate 12, a gate electrode 14, a source electrode 16, a drain electrode 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source electrode 16 is disposed in the substrate 12 and located on one side of the gate electrode 14. The drain electrode 18 is disposed in the substrate 12 on the other side of the gate electrode 14. The gate extension 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extension 20. For example, when the doping type of the gate 14 is N-type, the doping type of the gate extension 20 is P Type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extension 20 is N-type. Since the doping type of the gate electrode 14 is opposite to that of the gate extension portion 20, a depletion region (not shown) is naturally formed between the gate electrode 14 and the gate extension portion 20.

In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate electrode 14 is N-type, the doping type of the source electrode 16 is N-type, and the doping type of the drain electrode 18 is N-type, and The doping type of the gate extension 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate electrode 14 is P-type, the doping type of the source electrode 16 is P-type, and the doping type of the drain electrode 18 is P-type, and The doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

In Figure 3, the gate 14 is in substantial contact with the gate extension 20. For example, the gate 14 and the gate extension 20 are in substantial lateral contact (ie, the sidewalls of the gate 14 and the gate extension 20 Substantial contact). Ratio of the width W _G of the gate width W _E of this embodiment, the gate extension portion 20 (P-doped) In the present embodiment of the electrode 14 (N-doped) of about 0.3, At this time, the gate extension portion 20 The width W _{E is} approximately 0.15 micrometers, and the width W _{G of the} gate electrode 14 is approximately 0.5 micrometers. In some embodiments, the gate width W _E and gate extension portion 20 of the ratio of the width W _G of the electrodes 14 may range between other suitable, it is not limited thereto. In some embodiments, the boundary B _E between the gate extension 20 and the gate 14 is preferably within the range of the drain drift region 22 (that is, the gate extension 20 is only connected to the drain drift region 22 in the substrate 12 overlapping). In some embodiments, in the semiconductor structure 10, the sum W _T of the width W _E of the gate extension 20 and the width W _G of the gate 14 is a certain value. In this embodiment, when the gate extension 20 When the ratio of the width W _E of the gate electrode 14 to the width W _G of the gate electrode 14 is 0.3, the sum W _T of the width W _{E of the} gate electrode extension 20 and the width W _G of the gate electrode 14 is approximately 0.65 μm (that is, the gate extension The width W _{E of the} portion 20 is approximately 0.15 μm, and the width W _{G of the} gate electrode 14 is approximately 0.5 μm). In some embodiments, depending on the product requirements, a gate width W _E and gate extension portion 20 of the electrode 14 the width W _G of the sum of W _T also comprise other suitable sizes, it is not limited thereto. In this embodiment, the gate extension 20 can be regarded as a metal field plate. If the semiconductor structure of this embodiment is used for device operation, various operating conditions (for example, threshold voltage (Vth), linear region drain current (Idlin), saturation region drain current (Idsat), static breakdown voltage (BVoff)) and The drain-to-gate capacitance (Cgd) is shown in Table 1.

According to some embodiments, the manufacturing method of the gate electrode 14 and the gate extension portion 20 that are in substantial contact between the two is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12, and then, the patterned polysilicon layer is predetermined The region where the gate 14 is formed (approximately 0.5 micrometers wide) is subjected to an N-type implantation process, and the region (approximately 0.15 micrometers wide) in the patterned polysilicon layer where the gate extension 20 is scheduled to be formed is subjected to a P-type implantation process ( As in this embodiment), or, perform a P-type implantation process on the region (approximately 0.5 microns wide) where the gate 14 is scheduled to be formed in the patterned polysilicon layer, and the gate extension 20 is scheduled to be formed in the patterned polysilicon layer The region (approximately 0.15 micrometers wide) undergoes an N-type implantation process. So far, the gate 14 and the gate extension 20 that have opposite doping patterns and are substantially in contact with each other are completed.

Please refer to FIG. 4, according to an embodiment of the present invention, a semiconductor structure (semiconductor structure) 10 is provided. FIG. 4 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 4, the semiconductor structure 10 includes a substrate 12, a gate electrode 14, a source electrode 16, a drain electrode 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source electrode 16 is disposed in the substrate 12 and located on one side of the gate electrode 14. The drain electrode 18 is disposed in the substrate 12 on the other side of the gate electrode 14. The gate extension 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extension 20. For example, when the doping type of the gate 14 is N-type, the doping type of the gate extension 20 is P Type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extension 20 is N-type. Since the doping type of the gate electrode 14 is opposite to that of the gate extension portion 20, a depletion region (not shown) is naturally formed between the gate electrode 14 and the gate extension portion 20.

In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate electrode 14 is N-type, the doping type of the source electrode 16 is N-type, and the doping type of the drain electrode 18 is N-type, and The doping type of the gate extension 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate electrode 14 is P-type, the doping type of the source electrode 16 is P-type, and the doping type of the drain electrode 18 is P-type, and The doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

In Figure 4, the gate 14 is in substantial contact with the gate extension 20. For example, the gate 14 and the gate extension 20 are in substantial lateral contact (ie, the sidewalls of the gate 14 and the gate extension 20 Substantial contact). Ratio of the width W _G of the gate width W _E of this embodiment, the gate extension portion 20 (P-doped) In the present embodiment of the electrode 14 (N-doped) of about 0.625, at this time, the gate extension portion 20 The width W _{E is} approximately 0.25 micrometers, and the width W _{G of the} gate electrode 14 is approximately 0.4 micrometers. In some embodiments, the gate width W _E and gate extension portion 20 of the ratio of the width W _G of the electrodes 14 may range between other suitable, it is not limited thereto. In some embodiments, the boundary B _E between the gate extension 20 and the gate 14 is preferably within the range of the drain drift region 22 (that is, the gate extension 20 is only connected to the drain drift region 22 in the substrate 12 overlapping). In some embodiments, in the semiconductor structure 10, the sum W _T of the width W _E of the gate extension 20 and the width W _G of the gate 14 is a certain value. In this embodiment, when the gate extension 20 When the ratio of the width W _E of the gate electrode 14 to the width W _G of the gate electrode 14 is 0.625, the sum W _T of the width W _{E of the} gate electrode extension 20 and the width W _G of the gate electrode 14 is approximately 0.65 μm (that is, the gate electrode extension The width W _{E of the} portion 20 is approximately 0.25 μm, and the width W _{G of the} gate electrode 14 is approximately 0.4 μm). In some embodiments, depending on the product requirements, a gate width W _E and gate extension portion 20 of the electrode 14 the width W _G of the sum of W _T also comprise other suitable sizes, it is not limited thereto. In this embodiment, the gate extension 20 can be regarded as a metal field plate. If the semiconductor structure of this embodiment is used for device operation, various operating conditions (for example, threshold voltage (Vth), linear region drain current (Idlin), saturation region drain current (Idsat), static breakdown voltage (BVoff)) and The drain-to-gate capacitance (Cgd) is shown in Table 1.

According to some embodiments, the manufacturing method of the gate electrode 14 and the gate extension portion 20 that are in substantial contact between the two is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12, and then, the patterned polysilicon layer is predetermined The region where the gate 14 is formed (approximately 0.4 micrometers wide) is subjected to an N-type implantation process, and the region (approximately 0.25 micrometers wide) in the patterned polysilicon layer where the gate extension 20 is scheduled to be formed is subjected to a P-type implantation process ( As in this embodiment), or, the P-type implantation process is performed on the region (approximately 0.4 microns wide) where the gate electrode 14 is scheduled to be formed in the patterned polysilicon layer, and the gate extension 20 is scheduled to be formed in the patterned polysilicon layer The region (approximately 0.25 μm wide) undergoes an N-type implantation process. So far, the gate 14 and the gate extension 20 that have the opposite doping patterns and are substantially in contact with each other are completed.

Please refer to FIG. 5, according to an embodiment of the present invention, a semiconductor structure (semiconductor structure) 10 is provided. FIG. 5 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 5, the semiconductor structure 10 includes a substrate 12, a gate electrode 14, a source electrode 16, a drain electrode 18, a gate extending portion 20 and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source electrode 16 is disposed in the substrate 12 and located on one side of the gate electrode 14. The drain electrode 18 is disposed in the substrate 12 on the other side of the gate electrode 14. The gate extension 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extension 20. For example, when the doping type of the gate 14 is N-type, the doping type of the gate extension 20 is P Type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extension 20 is N-type. Since the doping type of the gate electrode 14 is opposite to that of the gate extension portion 20, a depletion region (not shown) is naturally formed between the gate electrode 14 and the gate extension portion 20.

In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate electrode 14 is N-type, the doping type of the source electrode 16 is N-type, and the doping type of the drain electrode 18 is N-type, and The doping type of the gate extension 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate electrode 14 is P-type, the doping type of the source electrode 16 is P-type, and the doping type of the drain electrode 18 is P-type, and The doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

In Figure 5, the gate 14 is in substantial contact with the gate extension 20, for example, the gate 14 and the gate extension 20 are in substantial lateral contact (ie, the sidewalls of the gate 14 and the gate extension 20 Substantial contact). Ratio of the width W _G of the gate width W _E of this embodiment, the gate extension portion 20 (P-doped) In the present embodiment of the electrode 14 (N-doped) is about 1.17, at this time, the gate extension portion 20 The width W _{E is} approximately 0.35 μm, and the width W _{G of the} gate electrode 14 is approximately 0.3 μm. In some embodiments, the gate width W _E and gate extension portion 20 of the ratio of the width W _G of the electrodes 14 may range between other suitable, it is not limited thereto. In some embodiments, the boundary B _E between the gate extension 20 and the gate 14 is preferably within the range of the drain drift region 22 (that is, the gate extension 20 is only connected to the drain drift region 22 in the substrate 12 overlapping). In some embodiments, in the semiconductor structure 10, the sum W _T of the width W _E of the gate extension 20 and the width W _G of the gate 14 is a certain value. In this embodiment, when the gate extension 20 When the ratio of the width W _E of the gate electrode 14 to the width W _G of the gate electrode 14 is 1.17, the sum W _T of the width W _{E of the} gate electrode extension 20 and the width W _G of the gate electrode 14 is approximately 0.65 μm (that is, the gate extension The width W _{E of the} portion 20 is approximately 0.35 μm, and the width W _{G of the} gate electrode 14 is approximately 0.3 μm). In some embodiments, depending on the product requirements, a gate width W _E and gate extension portion 20 of the electrode 14 the width W _G of the sum of W _T also comprise other suitable sizes, it is not limited thereto. In this embodiment, the gate extension 20 can be regarded as a metal field plate. If the semiconductor structure of this embodiment is used for device operation, various operating conditions (for example, threshold voltage (Vth), linear region drain current (Idlin), saturation region drain current (Idsat), static breakdown voltage (BVoff)) and The drain-to-gate capacitance (Cgd) is shown in Table 1.

According to some embodiments, the manufacturing method of the gate electrode 14 and the gate extension portion 20 that are in substantial contact between the two is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12, and then, the patterned polysilicon layer is predetermined The area where the gate 14 is formed (approximately 0.3 micrometers wide) is subjected to an N-type implantation process, and the area of the patterned polysilicon layer where the gate extension 20 is scheduled to be formed (approximately 0.35 micrometers wide) is subjected to a P-type implantation process ( (As in this embodiment), or, perform a P-type implantation process on the region (approximately 0.3 μm wide) where the gate 14 is scheduled to be formed in the patterned polysilicon layer, and the gate extension 20 is scheduled to be formed in the patterned polysilicon layer The region (approximately 0.35 micrometers wide) undergoes an N-type implantation process. So far, the gate 14 and the gate extension 20 that have opposite doping patterns and are substantially in contact with each other are completed. Table 1 No P-type doping of polysilicon The semiconductor structure shown in Figure 3 The semiconductor structure shown in Figure 4 The semiconductor structure shown in Figure 5 Width of gate extension (μm)/Width of gate (μm) X/0.5 0.15/0.5 0.25/0.4 0.35/0.3 Drain-gate capacitance (Cgd) (F/μm) (Vds=0V) 1.63e-15 8.11e-16 ( -50.2% ) 3.55e-16 ( -78.2% ) 3.10e-16 ( -81.0% ) Drain-gate capacitance (Cgd) (F/μm) (Vds=1.8V) 2.08e-16 1.82e-16 ( -12.5% ) 1.76e-16 ( -15.4% ) 1.74e-16 ( -16.3% ) The sum of the width of the gate extension and the width of the gate (μm) 0.65 0.65 0.65 0.65 Critical voltage (Vth)(V) 0.880 0.880 0.880 0.879 Linear region drain current (Idlin) (μA) 239 239 239 239 Drain current in saturation region (Idsat) (mA) 4.52 4.52 4.52 4.51 Static breakdown voltage (BVoff) (V) 33.1 33.1 33.1 33.1

It can be seen from Table 1 that under the same operating conditions, as the ratio of the width of the gate extension to the width of the gate gradually increases, the effect of the series connection of capacitors makes the drain-to-gate capacitance (drain-to -gate capacitance) is significantly reduced. For example, when Vds=0V and the ratio of the width of the gate extension to the width of the gate is 0.3, the drain-gate capacitance of the semiconductor structure of the present invention is less than P-type doped polysilicon The drain-gate capacitance of the hybrid semiconductor structure is reduced by about 50.2%. When the ratio of the width of the gate extension to the width of the gate is 0.625, the drain-gate capacitance of the semiconductor structure of the present invention is less than that of polysilicon. The drain-gate capacitance of the type-doped semiconductor structure is reduced by about 78.2%. When the ratio of the width of the gate extension to the width of the gate is 1.17, the drain-gate capacitance of the semiconductor structure of the present invention is lower than that of polysilicon The drain-gate capacitance of the P-type doped semiconductor structure is reduced by about 81%. When Vds=1.8V and the ratio of the width of the gate extension to the width of the gate is 0.3, the drain of the semiconductor structure of the present invention -The gate capacitance is about 12.5% lower than the drain-gate capacitance of the semiconductor structure without P-type doping of polysilicon. When the ratio of the width of the gate extension to the width of the gate is 0.625, the semiconductor structure of the present invention is The drain-gate capacitance is about 15.4% lower than the drain-gate capacitance of a semiconductor structure without P-type doping of polysilicon. When the ratio of the width of the gate extension to the width of the gate is 1.17, the semiconductor of the present invention The drain-gate capacitance of the structure is about 16.3% lower than that of the semiconductor structure without P-type doping of polysilicon.

Please refer to FIG. 6, according to an embodiment of the present invention, a semiconductor structure (semiconductor structure) 10 is provided. FIG. 6 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 6, the semiconductor structure 10 includes a substrate 12, a gate electrode 14, a source electrode 16, a drain electrode 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source electrode 16 is disposed in the substrate 12 and located on one side of the gate electrode 14. The drain electrode 18 is disposed in the substrate 12 on the other side of the gate electrode 14. The gate extension 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extension 20. For example, when the doping type of the gate 14 is N-type, the doping type of the gate extension 20 is P Type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extension 20 is N-type.

In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate electrode 14 is N-type, the doping type of the source electrode 16 is N-type, and the doping type of the drain electrode 18 is N-type, and The doping type of the gate extension 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate electrode 14 is P-type, the doping type of the source electrode 16 is P-type, and the doping type of the drain electrode 18 is P-type, and The doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

In Figure 6, the gate 14 and the gate extension 20 are substantially separated, for example, the gate 14 and the gate extension 20 are substantially separated laterally (ie, the sidewall of the gate 14 and the sidewall of the gate extension 20 Substantial separation, no contact).

In FIG. 6, the gate extension 20 is electrically connected to the gate 14 through the metal layer 32. In this embodiment, the gate extension 20 can be regarded as a metal field plate. According to some embodiments, the gate electrode 14 and the gate extension portion 20 that are substantially separated from each other are fabricated as follows. For example, first, a patterned polysilicon layer including two separated portions is formed on the substrate 12, and then the pattern N-type implantation process is performed on the separation part of the polysilicon layer where the gate electrode 14 is scheduled to be formed, and the P-type implantation process is performed on the separation part where the gate extension 20 is scheduled to be formed in the patterned polysilicon layer, or the patterned polysilicon layer P-type implantation process is performed on the separation part where the gate electrode 14 is scheduled to be formed in the layer, and the N-type implantation process is performed on the separation part where the gate extension part 20 is scheduled to be formed in the patterned polysilicon layer. At this point, the difference between the two is completed. Fabrication of the gate electrode 14 and the gate extension portion 20 of the doped type and substantially separated from each other.

Please refer to FIG. 7, according to an embodiment of the present invention, a semiconductor structure (semiconductor structure) 10 is provided. FIG. 7 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 7, the semiconductor structure 10 includes a substrate 12, a gate electrode 14, a source electrode 16, a drain electrode 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source electrode 16 is disposed in the substrate 12 and located on one side of the gate electrode 14. The drain electrode 18 is disposed in the substrate 12 on the other side of the gate electrode 14. The gate extension 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extension 20. For example, when the doping type of the gate 14 is N-type, the doping type of the gate extension 20 is P Type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extension 20 is N-type.

In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate electrode 14 is N-type, the doping type of the source electrode 16 is N-type, and the doping type of the drain electrode 18 is N-type, and The doping type of the gate extension 20 is P type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate electrode 14 is P-type, the doping type of the source electrode 16 is P-type, and the doping type of the drain electrode 18 is P-type, and The doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

In Figure 7, the gate 14 and the gate extension 20 are substantially separated, for example, the gate 14 and the gate extension 20 are substantially separated laterally (ie, the sidewall of the gate 14 and the sidewall of the gate extension 20 Substantial separation, no contact).

In FIG. 7, the gate extension 20 is electrically connected to the source 16 through the metal layer 34. In this embodiment, the gate extension 20 can be regarded as a metal field plate. According to some embodiments, the gate electrode 14 and the gate extension portion 20 that are substantially separated from each other are manufactured as follows. For example, first, a patterned polysilicon layer including two separated portions is formed on the substrate 12, and then the pattern N-type implantation process is performed on the separation part of the polysilicon layer where the gate electrode 14 is scheduled to be formed, and the P-type implantation process is performed on the separation part where the gate extension 20 is scheduled to be formed in the patterned polysilicon layer, or the patterned polysilicon layer P-type implantation process is performed on the separation part where the gate electrode 14 is scheduled to be formed in the layer, and the N-type implantation process is performed on the separation part where the gate extension part 20 is scheduled to be formed in the patterned polysilicon layer. At this point, the difference between the two is completed. Fabrication of the gate electrode 14 and the gate extension portion 20 of the doped type and substantially separated from each other.

In the present invention, two regions with opposite doping types are formed in the polysilicon gate of the MOS transistor through the implantation process (for example, the region adjacent to the drain in the gate (defined as gate extension in the present invention) is P-type doping, the area far away from the drain in the gate (defined as the gate in the present invention) is N-type doping). Due to the effect of capacitor series connection, the drain-to-gate capacitance ) Therefore, the improvement, and as the ratio of the width of the gate extension to the width of the gate gradually increases, the ratio of the drain-gate capacitance decrease becomes more obvious, and the gate extension at this time also has a field plate The function of the (field plate) can effectively disperse the electric field strength of the drain region (drift region) to avoid damage to the device under high-voltage operation. In addition, the above two regions with opposite doping types can also be made into two separate structures. On the one hand, the gate extension can have the function of a field plate, and on the other hand, the overall drain can be reduced. -The effect of gate capacitance. The cost of the present invention is low, and can be simply manufactured without changing the existing MOS process specifications. Due to the decrease of the drain ­-gate capacitance, the undesired current flow due to the coupling effect of the transistor is avoided. The special semiconductor structure design of the present invention can effectively reduce the power loss of the switching element, greatly increase the switching frequency and achieve high-efficiency electric power conversion.

The features of the above-mentioned embodiments are beneficial to those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and/or the same advantages of the above-mentioned embodiments. Those with ordinary knowledge in the technical field should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

10: semiconductor structure 12: substrate 14: gate 16: source 18: drain 20: gate extension 22: drain drift region 24: metal field plate 26: oxide layer 28, 30, 32, 34: metal layer B _E : The boundary of the gate extension W _E : The width of the gate extension W _G : The width of the gate W _T : The sum of the width of the gate extension and the width of the gate

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; Figure 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 5 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; and FIG. 7 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

10: Semiconductor structure

12: substrate

14: Gate

16: source

18: Dip pole

20: Gate extension

22: Drain drift zone

B _E : The boundary of the gate extension

W _E : Width of the gate extension

W _G : the width of the gate

W _T : The sum of the width of the gate extension and the width of the gate

Claims (15)

A semiconductor structure including: A substrate; A gate is arranged on the substrate; A source electrode, arranged in the substrate, located on one side of the gate electrode; A drain, disposed in the substrate, on the other side of the gate; and A gate extension is disposed on the substrate and is located between the gate and the drain, wherein the doping type of the gate is opposite to that of the gate extension. According to the semiconductor structure described in item 1 of the scope of patent application, the substrate is a P-type or N-type substrate. In the semiconductor structure described in item 2 of the scope of the patent application, when the substrate is a P-type substrate, the doping type of the gate is N-type, the doping type of the source is N-type, and the doping of the drain is The hetero type is N type, and the doping type of the gate extension is P type. In the semiconductor structure described in item 2 of the patent application, when the substrate is an N-type substrate, the doping type of the gate is P-type, the doping type of the source is P-type, and the doping of the drain is The hetero type is P type, and the doping type of the gate extension is N type. In the semiconductor structure described in claim 1, wherein the gate is substantially in contact with the gate extension. In the semiconductor structure described in claim 1, wherein the gate and the gate extension are substantially separated. The semiconductor structure described in item 5 of the scope of the patent application further includes a metal field plate disposed on the substrate and located between the gate extension and the drain. The semiconductor structure described in item 7 of the scope of patent application further includes an oxide layer disposed on the substrate and under the metal field plate. The semiconductor structure described in item 7 of the scope of patent application, wherein the metal field plate is electrically connected to the gate and the gate extension. The semiconductor structure described in item 7 of the scope of patent application, wherein the metal field plate is electrically connected to the source. In the semiconductor structure described in item 6 of the scope of patent application, the gate electrode is electrically connected to the gate electrode extension. The semiconductor structure described in item 6 of the scope of patent application, wherein the gate extension is electrically connected to the source. According to the semiconductor structure described in claim 5, the ratio of the width of the gate extension to the width of the gate is between 0.3-1.2. In the semiconductor structure described in item 13 of the scope of the patent application, the sum of the width of the gate extension and the width of the gate is a fixed value. In the semiconductor structure described in item 1 of the scope of patent application, the gate and the gate extension are made of polysilicon.

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