TWI703543B - Gate driving device - Google Patents

Abstract

A gate driving device is provided. The gate driving device includes a plurality stages of gate driving circuits. The Mth gate driving circuit includes a shift register and a plurality of gate drive signal generating circuits. The shift register is configured to generate the Mth common gate signal in a first time interval, and rapidly raise a voltage level of an anti-noise enable signal in the second time interval to perform an anti-noise operation. The gate drive signal generating circuits are configured to receive the Mth common gate signal in the first time interval, and float with the shift register according to a high voltage level of the Mth common gate signal, so as to generate a plurality of gate driving signals corresponding to the internal clock signals.

Description

Gate drive device

The present invention relates to a gate driving device, and particularly to a gate driving device with a smaller layout area and high reliability to extreme temperatures.

Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) have become the mainstream of modern display technology products. Compared with Poly-Si TFT, the display made of amorphous silicon thin film transistor (a-Si TFT) can reduce production cost, and can be fabricated on a large area glass substrate at low temperature. Good performance and can increase the production rate.

With the concept of System-on-Glass (SOG) being put forward one after another, recently many products integrate the gate driving device in the display driving circuit on the glass substrate, which is called GOA (Gate Driver on Array) Circuit. GOA has many advantages. In addition to reducing the area of the display frame to achieve a narrow frame, it can also reduce the use of gate scan driver ICs, reduce the cost of purchasing ICs, and avoid disconnection problems during glass and IC bonding, so as to improve products Yield rate.

At present, the panel design of electronic products is gradually becoming narrower, and the display area is becoming larger. For this reason, the number of transistors in the gate driving device is often reduced to save unnecessary layout area. In addition, in order to achieve good picture quality, the screen resolution must be increased. In this case, the turn-on time of each scan line is shortened. Therefore, the reliability is reduced at extreme temperatures, such as low temperature (for example, -40 degrees Celsius) and high temperature (for example, 90 degrees Celsius). It can be seen from this that how to design a gate drive device with a smaller layout area and high reliability to extreme temperatures is one of the current development focuses of the gate drive device.

The present invention provides a gate driving device with a small layout area and high reliability to extreme temperatures.

The gate drive device of the present invention includes a multi-stage gate drive circuit. The above-mentioned multi-level gate drive circuits are respectively used to generate multiple gate drive signals. In the above-mentioned multi-level gate driving circuit, the M-th gate driving circuit includes a shift register and a plurality of gate driving signal generating circuits. The shift register is configured to generate the M-th stage common gate signal in the first time interval according to the first external clock signal and the (M-2)-th stage shared gate signal, and in the second time interval according to the (M-th) stage common gate signal +2) The level shared gate signal and the second external clock signal stop generating the M-th level shared gate signal, and in the second time interval, the third external clock signal and the first external clock signal are used to prevent noise The voltage level of the signal performs the first stage raising operation and the second stage raising operation. The shift register performs an anti-noise operation by the anti-noise enable signal. The multiple gate drive signal generating circuits are respectively coupled to the shift register. The above-mentioned multiple gate drive signal generating circuits are configured to receive the M-th stage shared gate signal in the first time interval, and float with the shift register according to the high voltage level of the M-th stage shared gate signal, thereby The internal clock signal is used to correspondingly generate one of the above-mentioned gate drive signals. Among them, M is a positive integer greater than 2.

Based on the above, in the gate driving device, the M-th gate driving circuit includes a shift register and a plurality of gate driving signal generating circuits. In the first time interval, the shift register generates the M-th stage shared gate signal. The multiple gate drive signal generating circuits receive the M-th stage shared gate signal, and generate multiple gate drive signals according to the high voltage level of the M-th stage shared gate signal and the shift register floating. In addition, in the second time interval, the shift register performs a two-stage raising operation on the voltage level of the anti-noise enabling signal, so as to perform the anti-noise operation. As a result, the gate driving device of the present invention has a smaller layout area and higher reliability against extreme temperatures.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1 and FIG. 4. FIG. 1 is a circuit diagram of the M-th gate driving circuit according to the first embodiment of the present invention. FIG. 4 is a timing diagram drawn according to an embodiment of the invention. In this embodiment, the gate driving device includes a multi-stage gate driving circuit. The above-mentioned multi-level gate drive circuits are respectively used to generate multiple gate drive signals. In the above-mentioned multi-stage gate drive circuit, the M-th stage gate drive circuit 100 includes a shift register 110 and gate drive signal generating circuits 120_1 to 120_8. M is a positive integer greater than 2. The number of gate drive signal generating circuits of the present invention can be multiple, and is not limited to this embodiment.

In this embodiment, the shift register 110 receives the first external clock signal CK1, the second external clock signal CK3, the third external clock signal CK4, and the (M-2)th stage common gate signal G( M-2) and the (M+2) level share the gate signal G(M+2). The shift register 110 generates the M-th stage shared gate signal G(M-2) according to the first external clock signal CK1 and the (M-2)th stage shared gate signal G(M-2) in the first time interval T1 ). The shift register 110 will stop generating the M-th stage shared gate signal G(M+2) and the second external clock signal CK3 during the second time interval T2. M). In addition, in the second time interval T2, the shift register 110 also performs a two-stage raising of the voltage level of the anti-noise enable signal according to the third external clock signal CK4 and the first external clock signal CK1 . That is, the shift register 110 performs the first-stage raising operation and the second-stage raising operation on the voltage level of the anti-noise enable signal during the second time interval T2. The shift register 110 performs an anti-noise operation by the anti-noise enable signal. Performing the first-stage raising operation and the second-stage raising operation on the voltage level of the anti-noise enabling signal enables the anti-noise enabling signal to be quickly raised to the specified high voltage level in a low temperature environment. Therefore, the shift register 110 can perform an anti-noise operation by using an anti-noise enable signal with a sufficiently high voltage level in a low temperature environment. In this embodiment, the second time interval T2 continues after the first time interval T1. The time interval during which the third external clock signal CK4 is at the high voltage level partially overlaps the time interval during which the first external clock signal CK1 is at the high voltage level. The first external clock signal CK1 is inverted from the second external clock signal CK3.

In this embodiment, the gate drive signal generating circuits 120_1 to 120_8 are respectively coupled to the shift register 110. The gate drive signal generating circuits 120_1 to 120_8 are used for receiving the M-th common gate signal G(M) provided by the shift register 110 in the first time interval T1. The gate drive signal generating circuits 120_1~120_8 will float to the shift register 110 according to the high voltage level of the M-th shared gate signal G(M), thereby using the internal clock signals clk1~clk8 to generate gates correspondingly Drive signals GS(1)~GS(8). The duty cycle of the external clock signals CK1~CK4 is greater than the duty cycle of the internal clock signals clk1~clk8. That is, the duty cycles of the first external clock signal CK1, the second external clock signal CK3, and the third external clock signal CK4 are greater than the duty cycles of the internal clock signals clk1~clk8. In this embodiment, after the shift register 110 is floating, the gate drive signal generating circuits 120_1~120_8 receive the M-th stage common gate signal G(M) at the receiving end that is floating. Therefore, the gate drive signal generating circuits 120_1~120_8 can couple the above-mentioned receiving end through the internal capacitors (eg, parasitic capacitance) of the gate drive signal generating circuits 120_1~120_8 according to the internal clock signals clk1~clk8 to raise the receiving end. (Ie, the voltage level of the M-th shared gate signal G(M)). Therefore, the above-mentioned mechanism can compensate the electrical degradation of the gate drive signal generating circuits 120_1 to 120_8 due to high temperature. Thus, the internal clock signals clk1~clk8 are used to completely output the gate drive signals GS(1)~GS(8). In this embodiment, after the gate drive signal generating circuits 120_1 to 120_8 and the shift register 110 are floating, the gate drive signal generating circuit 120_1 uses the internal clock signal clk1 to generate the gate drive signal GS(1). The gate drive signal generating circuit 120_2 uses the internal clock signal clk2 to generate the gate drive signal GS(2), and so on.

It is worth mentioning here that, in the gate driving device, the M-th gate driving circuit 100 includes a single shift register 110 and 8 gate driving signal generating circuits 120_1 to 120_8. In the first time interval T1, the shift register 110 generates the M-th stage common gate signal G(M). The gate drive signal generating circuits 120_1~120_8 are connected to the shift register 110 according to the high voltage level of the M-th shared gate signal G(M) to generate 8 gate drive signals GS(1)~GS( 8). In this way, this embodiment can provide a gate driving device with a smaller layout area. In addition, in the first time interval T1, the gate drive signal generating circuits 120_1~120_8 use the above floating mechanism to raise the voltage level of the M-th shared gate signal G(M) to compensate for the gate drive The signal generating circuits 120_1~120_8 are electrically degraded due to high temperature. In the second time interval T2, the shift register 110 performs a two-stage raising operation on the voltage level of the anti-noise enabling signal, so as to quickly raise the voltage level of the anti-noise enabling signal. In this way, the gate driving device of this embodiment can be more reliable in extreme temperature environments.

Further explain the implementation details of the shift register. Please refer to FIG. 2 and FIG. 4. FIG. 2 is a circuit diagram of the shift register according to the first embodiment of the present invention. In this embodiment, the shift register 110 includes a charging and discharging circuit 112, an output stage circuit 114, and an anti-noise circuit 116.

In this embodiment, the charging and discharging circuit 112 provides a control signal CS. During the first sub-time interval T11 of the first time interval T1, the charging and discharging circuit 112 raises the voltage level of the control signal CS according to the (M-2)th stage shared gate signal G(M-2), thereby reducing the control signal CS The voltage level rises to the high voltage level. The output stage circuit 114 is coupled to the charge and discharge circuit 112 to receive the control signal CS. The output stage circuit 114 generates the M-th stage common gate signal G(M) according to the control signal CS and the first external clock signal CK1 in the second sub-time interval T12 of the first time interval T1. In addition, the charging and discharging circuit 112 also pulls down the voltage level of the control signal CS in the second time interval T2 according to the (M+2)th stage shared gate signal G(M+2), thereby pulling down the voltage level of the control signal CS To the low voltage level. The output stage circuit 114 also pulls down the voltage level of the M-th common gate signal G(M) in the second time interval T2 according to the second external clock signal CK3.

In this embodiment, the anti-noise circuit 116 is coupled to the charging and discharging circuit 112 and the output stage circuit 114. The anti-noise circuit 116 pulls down the voltage level of the anti-noise enable signal during the first time interval T1. The anti-noise circuit 116 raises the voltage level of the anti-noise enabling signal in two stages during the second time interval T2. In the second time interval T2, the anti-noise circuit 116 performs the first-stage raising operation according to the voltage level of the third external clock signal CK4 against the noise enable signal, and then according to the third external clock signal CK4 and the first The voltage level of the external clock signal CK1 against the noise enabling signal performs the second stage of raising operation.

In detail, the charging and discharging circuit 112 includes a pre-charging transistor M1 and a discharging transistor M2. The first terminal of the pre-charge transistor M1 is configured to receive the system high voltage VDD. The second end of the precharge transistor M1 is coupled to the output stage circuit 114 and the anti-noise circuit 116. The control terminal of the pre-charge transistor M1 is configured to receive the (M-2)th stage common gate signal G(M-2). The first terminal of the discharge transistor M2 is coupled to the second terminal of the precharge transistor M1. The second terminal of the discharge transistor M2 is configured to receive the system low voltage VSS. The control terminal of the discharge transistor M2 is configured to receive the (M+2)th stage common gate signal G(M+2). The charge and discharge circuit 112 provides a control signal CS via the second terminal of the pre-charge transistor M1.

The output stage circuit 114 includes output transistors M3 and M4 and an output stage capacitor C1. The first terminal of the output transistor M3 is configured to receive the first external clock signal CK1. The second terminal of the output transistor M3 is configured as the output terminal of the shift register 110. The control terminal of the output transistor M3 is coupled to the charging and discharging circuit 112 to receive the control signal CS. The first end of the output transistor M4 is coupled to the second end of the output transistor M3. The second terminal of the output transistor M4 is configured to receive the system low voltage VSS. The control terminal of the output transistor M4 is configured to receive the second external clock signal CK3. The output stage capacitor C1 is coupled between the second terminal of the transistor M1 and the control terminal of the transistor M1.

The anti-noise circuit 116 includes a first anti-noise enabling signal generator 1162, a second anti-noise enabling signal generator 1164, and a pull-down circuit 1166. The first anti-noise enabling signal generator 1162 includes a capacitor C2. The first terminal of the capacitor C2 is configured to receive the third external clock signal CK4. The second end of the capacitor C2 is configured to generate the anti-noise enabling signal AS. The capacitor C2 performs the first-stage raising operation according to the voltage level of the third external clock signal CK4 against the noise enable signal AS. The second anti-noise enabling signal generator 1164 is coupled to the second end of the capacitor C2. The second anti-noise enabling signal generator 1164 receives the first external clock signal CK1 and the M-th level common gate signal G(M). The second anti-noise enabling signal generator 1164 pulls down the voltage level of the anti-noise enabling signal AS according to the M-th shared gate signal G(M) in the first time interval T1, and according to the second time interval T2 The voltage level of the first external clock signal CK1 against the noise enable signal AS performs a second stage of raising operation. The pull-down circuit 1166 is coupled to the second end of the capacitor C2, the charging and discharging circuit 112, and the output stage circuit 114. The pull-down circuit 1166 receives the anti-noise enabling signal AS, and pulls down the voltage level of the control signal CS and the voltage level of the M-th common gate signal G(M) in the second time interval T2 according to the anti-noise enabling signal AS Bit.

Further, in this embodiment, the second anti-noise enabling signal generator 1164 includes a first transistor M7, a second transistor M8, a third transistor M9, and a fourth transistor M10. The first terminal of the first transistor M7 and the control terminal of the first transistor M7 are configured to receive the first external clock signal CK1. The first terminal of the second transistor M8 is configured to receive the first external clock signal CK1. The second terminal of the second transistor M8 is coupled to the second terminal of the capacitor C2. The control terminal of the second transistor M8 is coupled to the second terminal of the first transistor M7. The first end of the third transistor M9 is coupled to the second end of the first transistor M7. The second terminal of the third transistor M9 is configured to receive the system low voltage VSS. The control terminal of the third transistor M9 is configured to receive the M-th level common gate signal G(M). The first end of the fourth transistor M10 is coupled to the second end of the second transistor M8. The second terminal of the fourth transistor M10 is configured to receive the system low voltage VSS. The control terminal of the fourth transistor M10 is configured to receive the M-th level common gate signal G(M). The pull-down circuit 1166 includes a pull-down transistor M5 and a pull-down transistor M6. The first end of the pull-down transistor M5 is configured to receive the control signal CS. The second terminal of the pull-down transistor M5 is configured to receive the system low voltage VSS. The control terminal of the pull-down transistor M5 is configured to receive the anti-noise enabling signal AS. The first end of the pull-down transistor M6 is configured to receive the M-th level common gate signal G(M). The second terminal of the pull-down transistor M6 is configured to receive the system low voltage VSS. The control terminal of the pull-down transistor M6 is configured to receive the anti-noise enable signal AS.

Next, the implementation details of the gate drive signal generating circuit will be described. Please refer to FIG. 3, which is a schematic circuit diagram of the gate drive signal generating circuit according to the first embodiment of the present invention. In this embodiment, the gate drive signal generating circuit 120 can be used to implement one of the gate drive signal generating circuits 120_1 to 120_8 shown in FIG. 1. In this embodiment, the gate drive signal generating circuit 120 includes a bridge transistor MB1 and a transmission transistor MD1. The first terminal and the control terminal of the bridge transistor MB1 are jointly coupled to the shift register (the shift register 110 shown in FIG. 1 or FIG. 2) to receive the M-th stage common gate signal G(M) . The second end of the bridge transistor MB1 is configured to provide a switching signal gu1. In other words, the bridge transistor MB1 will provide the switching signal gu1 according to the M-th level common gate signal G(M). The first end of the transmission transistor MD1 is configured to receive the internal clock signal clk1. The control terminal of the transmission transistor MD1 is coupled to the bridge transistor MB1 to receive the switching signal gu1. The transmission transistor MD1 uses the internal clock signal clk1 as the gate drive signal GS(1) in the first time interval T1 and outputs the gate drive signal GS(1) via the second terminal of the transmission transistor MD1 according to the switching signal gu1. In this embodiment, the first end of the bridge transistor MB1 and the control end jointly receive the M-th level common gate signal G(M) at a high voltage level, and then flow through the first end and the first end of the bridge transistor MB1. The conduction current between the two terminals is equal to zero. When the conduction current is equal to 0, the gate drive signal generating circuit 120 will be in a floating state. That is, when the voltage value of the switching signal gu1 is equal to the difference between the voltage value of the M-th common gate signal G(M) and the threshold voltage value of the bridge transistor MB1, the bridge transistor MB1 and the shift register 110 floating. This means that the voltage level of the switching signal gu1 received by the control terminal of the transmission transistor MD1 is a high voltage level and floating. Therefore, when the transmission transistor MD1 receives the internal clock signal clk1 at the high voltage level, the switching signal gu1 will be coupled to the higher voltage level of the internal clock signal clk1 and the parasitic capacitance of the transmission transistor MD1. High voltage level. In this way, the transmission transistor MD1 can be completely turned on to transmit the internal clock signal clk1, and use the internal clock signal clk1 as the gate drive signal GS(1).

Please refer to FIG. 2, FIG. 3 and FIG. 4 at the same time. FIG. 4 is a timing diagram according to an embodiment of the present invention. In this embodiment, in the first sub-time interval T11 between the first time zone T1, the voltage level of the (M-2)th stage shared gate signal G(M-2) and the second external clock signal CK3 The voltage level of is the high voltage level. The voltage level of the first external clock signal CK1 and the voltage level of the (M+2)th stage shared gate signal G(M+2) are low voltage levels. The charging and discharging circuit 112 raises the voltage level of the control signal CS according to the (M-2)-level shared gate signal G(M-2) through the pre-charge transistor M1, thereby raising the voltage level of the control signal CS to High voltage level. The output stage circuit 114 pulls down the voltage level of the M-th shared gate signal G(M) through the output transistor M4 according to the second external clock signal CK3. Therefore, the voltage level of the M-th shared gate signal G(M) in the first sub-time interval T11 is a low voltage level. In addition, the second anti-noise enabling signal generator 1164 of the anti-noise circuit 116 provides the anti-noise enabling signal AS at a low voltage level according to the first external clock signal CK1.

In the second sub-time interval T12 between the first time zone T1, the voltage level of the (M-2)th stage shared gate signal G(M-2), and the (M+2)th stage shared gate signal G( The voltage level of M+2) and the voltage level of the second external clock signal CK3 are low voltage levels. The voltage level of the first external clock signal CK1 is a high voltage level. Therefore, the first external clock signal CK1 at the high voltage level will be transmitted to the second end of the output transistor M3 and used as the M-th common gate signal G(M). At this time, the voltage level of the control signal CS will be raised to a higher voltage level by the coupling of the high voltage level of the M-th shared gate signal G(M) and the output stage capacitor C1 to ensure the output transistor M3 can be completely turned on.

In the second sub-time interval T12, the first terminal of the bridge transistor MB1 and the control terminal jointly receive the M-th common gate signal G(M) at the high voltage level, and the gate drive signal generating circuit 120 will be floating status. Therefore, the voltage level of the switching signal gu1 is a high voltage level and is floating. Once the transmission transistor MD1 receives the internal clock signal clk1 at the high voltage level, the switching signal gu1 will be coupled and raised to a higher voltage level. The transmission transistor MD1 can be completely turned on to transmit the internal clock signal clk1, and use the internal clock signal clk1 as the gate drive signal GS(1).

In the same way, other gate drive signal generating circuits of the M-th gate drive circuit (the M-th gate drive circuit 100 as shown in FIG. 1) will also receive the M-th shared gate signal G at a high voltage level. (M) After that, it is in a floating state. When other gate drive signal generating circuits sequentially receive high-voltage internal clock signals, the corresponding transmission transistors can be completely turned on to output gate drive signals (eg, gate drive signal GS(2 )~GS(8)).

In addition, the second anti-noise enabling signal generator 1164 of the anti-noise circuit 116 provides a low-voltage level anti-noise enabling signal AS based on the M-th common gate signal G(M).

In the first sub-time interval T21 between the second time zone T2, the voltage level of the (M-2)th stage shared gate signal G(M-2) and the voltage level of the first external clock signal CK1 are low Voltage level. The voltage level of the (M+2) level common gate signal G(M+2) and the voltage level of the second external clock signal CK3 are high voltage levels. Therefore, the charging and discharging circuit 112 pulls down the voltage level of the control signal CS according to the (M+2)th stage common gate signal G(M+2) through the discharge transistor M2. In addition, the output stage circuit 114 pulls down the voltage level of the M-th common gate signal G(M) through the output transistor M4 according to the second external clock signal CK3. The voltage level of the M-th shared gate signal G(M) in the first sub-time interval T21 is a low voltage level. Therefore, after the first sub-time interval T21 between the second time zone T2 starts, the gate drive signals GS(1)-GS(8) at the high voltage level will not be provided.

In the second sub-time interval T22 between the second time zone T2, the voltage level of the first external clock signal CK1 is a low voltage level. The voltage level of the (M+2) level common gate signal G(M+2), the voltage level of the third external clock signal CK4 and the second external clock signal CK3 are high voltage levels. Compared to the first sub-time interval T21, the first end of the capacitor C2 receives the third external clock signal CK4 at a high voltage level, that is, the anti-noise enable signal AS performs the first stage of raising operation.

In the third sub-time interval T23 between the second time zone T2, the voltage level of the second external clock signal CK3 is a low voltage level. The voltage level of the first external clock signal CK1 and the voltage level of the third external clock signal CK4 are high voltage levels. When the voltage level of the first external clock signal CK1 and the voltage level of the third external clock signal CK4 are both high voltage levels, the voltage level of the second terminal of the capacitor C2 will be raised quickly, and It is the second stage of lifting operation against the noise enabling signal AS. In the third sub-time interval T23, the pull-down circuit 1166 pulls down the voltage level of the control signal CS and the voltage level of the M-th common gate signal G(M) according to the anti-noise enable signal AS to eliminate the pre-charge The noise at the second end of the transistor M1 and the noise at the output end of the output stage circuit 114.

In the fourth sub-time interval T24 between the second time zone T2, the voltage level of the third external clock signal CK4 drops to a low voltage level, but the voltage level of the first external clock signal CK1 remains high Voltage level. Therefore, the voltage level of the anti-noise enabling signal AS is also maintained at a high voltage level. At the end of the fourth sub-time interval T24, the voltage level of the first external clock signal CK1 is a low voltage level. Then the voltage level of the anti-noise enable signal AS is the low voltage level.

Please refer to FIG. 5, which is a schematic circuit diagram of an M-th gate drive circuit according to a second embodiment of the present invention. Compared with the first embodiment, the gate drive signal generating circuit of the M-th gate drive circuit 200 of this embodiment further includes a first pull-down transistor pair PTD1_1~PTD1_8 and a second pull-down transistor pair PTD2_1~PTD2_8 .

In this embodiment, the first pull-down transistor pair PTD1_1 is coupled to the second end of the bridge transistor MB1 and the control end of the transmission transistor MD1. The first pull-down transistor pair PTD1_2 is coupled to the second end of the bridge transistor MB2 and the control end of the transmission transistor MD2, and so on. In detail, the first pull-down transistor pair PTD1_1 includes pull-down transistor MP1 and pull-down transistor MQ1. The first end of the pull-down transistor MP1 and the first end of the pull-down transistor MQ1 are commonly coupled to the second end of the bridge transistor MB1 and the control end of the transmission transistor MD1. The second end of the pull-down transistor MP1 and the second end of the pull-down transistor MQ1 jointly receive the system low voltage VSS. The control terminal of the pull-down transistor MP1 is configured to receive the anti-noise enable signal AS. The control terminal of the pull-down transistor MQ1 is configured to receive the second external clock signal CK3. The first pull-down transistor pair PTD1_2 includes pull-down transistor MP2 and pull-down transistor MQ2. The first end of the pull-down transistor MP2 and the first end of the pull-down transistor MQ2 are commonly coupled to the second end of the bridge transistor MB2 and the control end of the transmission transistor MD2. The second end of the pull-down transistor MP2 and the second end of the pull-down transistor MQ2 jointly receive the system low voltage VSS. The control terminal of the pull-down transistor MP2 is configured to receive the anti-noise enable signal AS. The control terminal of the pull-down transistor MQ2 is configured to receive the second external clock signal CK3, and so on.

In this embodiment, the first pull-down transistor pair PTD1_1~PTD1_8 are configured to pull down the switching signals gu1~gu8 according to the anti-noise enable signal AS and the second external clock signal CK3 during the second time interval T2. Bits are used to eliminate noise on the second end of the bridge transistors MB1~MB8 and the control end of the transmission transistors MD1~MD8.

In this embodiment, the second pull-down transistor pair PTD2_1 is coupled to the second end of the transmission transistor MD2. The second pull-down transistor pair PTD2_2 is coupled to the second end of the transmission transistor MD2, and so on. In detail, the second pull-down transistor pair PTD2_1 includes pull-down transistor MR1 and pull-down transistor MS1. The first end of the pull-down transistor MR1 and the first end of the pull-down transistor MS1 are commonly coupled to the second end of the transmission transistor MD2. The second end of the pull-down transistor MR1 and the second end of the pull-down transistor MS1 jointly receive the system low voltage VSS. The control terminal of the pull-down transistor MR1 is configured to receive the anti-noise enabling signal AS. The control terminal of the pull-down transistor MS1 is configured to receive the second external clock signal CK3. The second pull-down transistor pair PTD2_2 includes pull-down transistor MR2 and pull-down transistor MS2. The first end of the pull-down transistor MR2 and the first end of the pull-down transistor MS2 are commonly coupled to the second end of the transmission transistor MD2. The second end of the pull-down transistor MR2 and the second end of the pull-down transistor MS2 jointly receive the system low voltage VSS. The control terminal of the pull-down transistor MR2 is configured to receive the anti-noise enable signal AS. The control terminal of the pull-down transistor MS2 is configured to receive the second external clock signal CK3, and so on.

In this embodiment, the second pull-down transistor pair PTD2_1~PTD2_8 are configured to pull down the gate drive signal GS(1)~ in the second time interval T2 according to the anti-noise enable signal AS and the second external clock signal CK3. The voltage level of GS(2) is located to eliminate the noise at the second end of the transmission transistors MD1~MD8.

In some embodiments, the gate drive signal generating circuit may only include the first pull-down transistor pair PTD1_1~PTD1_8. In some embodiments, the gate drive signal generating circuit may only include the second pull-down transistor pair PTD2_1~PTD2_8.

Please refer to FIG. 6, which is a schematic circuit diagram of a gate driving device according to an embodiment of the present invention. In this embodiment, the gate driving device 60 includes a multi-stage gate driving circuit. For ease of description, this embodiment only shows the first-stage gate drive circuit 610, the second-stage gate drive circuit 620, the third-stage gate drive circuit 630, and the fourth-stage gate in the multi-stage gate drive circuit. Drive circuit 640. In this embodiment, the first-stage gate drive circuit 610 receives external clock signals CK1, CK3, CK4, internal clock signals clk1~clk8, start signal Vst1, system high voltage VDD, system low voltage VSS, and third The stage shares the gate signal G(3), and provides the first stage shared gate signal G(1) and gate drive signals O(1)~O(8). The second-level gate drive circuit 620 receives external clock signals CK1, CK2, CK4, internal clock signals clk9~clk16, start signal Vst2, system high voltage VDD, system low voltage VSS, and fourth-level common gate signal G (4), and provide the second level common gate signal G(2) and gate drive signals O(9)~O(16). The third-level gate drive circuit 630 receives external clock signals CK1~CK3, internal clock signals clk1~clk8, system high voltage VDD, system low voltage VSS, first-level common gate signal G(1), fifth-level The gate signal G(5) is shared, and the third-level shared gate signal G(3) and gate drive signals O(17)~O(24) are provided. The fourth-level gate driving circuit 640 receives external clock signals CK2~CK4, internal clock signals clk9~clk16, system high voltage VDD, system low voltage VSS, second-level shared gate signal G(2), and sixth-level The gate signal G(6) is shared, and the fourth level shared gate signal G(4) and gate drive signals O(25)~O(32) are provided, and so on. In this embodiment, the third-stage gate driving circuit 630 and/or the fourth-stage gate driving circuit 640 can be implemented by the M-th gate driving circuit 100 of the first embodiment or the M-th gate driving circuit of the second embodiment. The pole drive circuit 200 is implemented.

In summary, in the gate driving device of the present invention, the M-th gate driving circuit includes a shift register and a plurality of gate driving signal generating circuits. In the first time interval, the shift register generates the M-th stage shared gate signal. The multiple gate drive signal generating circuits receive the M-th stage shared gate signal, and generate multiple gate drive signals according to the high voltage level of the M-th stage shared gate signal and the shift register floating. In addition, in the second time interval, the shift register performs a two-stage raising operation on the voltage level of the anti-noise enabling signal, so as to perform the anti-noise operation. As a result, the gate driving device of the present invention has a smaller layout area and higher reliability against extreme temperatures.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 200: M-level gate drive circuit 110: shift register 120_1~120_8: Gate drive signal generating circuit CK1: the first external clock signal CK2: External clock signal CK3: The second external clock signal CK4: Third external clock signal G(1): The first level shared gate signal G(2): The second level shared gate signal G(3): The third level shared gate signal G(4): 4th level shared gate signal G(5): 5th level shared gate signal G(6): 6th level shared gate signal G(M-2): (M-2) level shared gate signal G(M+2): (M+2) level shared gate signal G(M): M-level shared gate signal clk1~clk16: internal clock signal GS(1)~GS(8), O(1)~O(32): gate drive signal 112: charge and discharge circuit 114: output stage circuit 116: Anti-noise circuit CS: Control signal M1: pre-charged transistor M2: Discharge transistor M3, M4: output transistor M5, M6, MP1~MP8, MQ1~MQ8, MR1~MR8, MS1~MS8: pull-down transistor M7: The first transistor M8: second transistor M9: third transistor M10: The fourth transistor VDD: system high voltage VSS: system low voltage 1162: The first anti-noise enabling signal generator 1164: The second anti-noise enabling signal generator 1166: pull-down circuit C1: output stage capacitor C2: Capacitance AS: Anti-noise enabling signal gu1~gu8: switch signal MB1~MB8: bridge transistor MD1~MD8: transmission transistor PTD1_1~PTD1_8: the first pull-down transistor pair PTD2_1~PTD2_8: The second pull-down transistor pair 60: Gate drive device 610: The first stage gate drive circuit 620: 2nd stage gate drive circuit 630: 3rd stage gate drive circuit 640: 4th stage gate drive circuit T1: the first time interval T2: second time interval T11: The first sub-time interval of the first time interval T12: The second sub-time interval of the first time interval T21: The first sub-time interval of the second time interval T22: The second sub-time interval of the second time interval T23: The third sub-time interval of the second time interval T24: The fourth sub-time interval of the second time interval Vst1, Vst2: start signal

FIG. 1 is a schematic circuit diagram of the M-th gate driving circuit according to the first embodiment of the present invention. FIG. 2 is a schematic circuit diagram of the shift register according to the first embodiment of the present invention. 3 is a schematic circuit diagram of the gate drive signal generating circuit according to the first embodiment of the present invention. FIG. 4 is a timing diagram drawn according to an embodiment of the invention. FIG. 5 is a schematic circuit diagram of the M-th gate driving circuit according to the second embodiment of the present invention. FIG. 6 is a schematic circuit diagram of a gate driving device according to an embodiment of the invention.

100: M-level gate drive circuit

110: shift register

120_1~120_8: Gate drive signal generating circuit

CK1: the first external clock signal

CK3: The second external clock signal

CK4: Third external clock signal

clk1~clk8: internal clock signal

G(M-2): (M-2) level shared gate signal

G(M): M-level shared gate signal

G(M+2): (M+2) level shared gate signal

GS(1)~GS(8): Gate drive signal

Claims (14)

A gate driving device includes: a multi-level gate driving circuit for generating a plurality of gate driving signals, wherein the M-th gate driving circuit includes: a shift register configured to a first The time interval generates an M-th level shared gate signal according to a first external clock signal and a (M-2)-th level shared gate signal, and a second time interval according to a (M+2)-th level shared gate signal Signal and a second external clock signal stop generating the M-th shared gate signal, and a second time interval is based on a third external clock signal and the first external clock signal to an anti-noise The voltage level of the energy signal performs a first-stage raising operation and a second-stage raising operation, wherein the shift register performs an anti-noise operation by the anti-noise enable signal; and a plurality of gate drive signals A generating circuit, respectively coupled to the shift register, is configured to receive the M-th stage shared gate signal in the first time interval, and according to the high voltage level of the M-th stage shared gate signal and the The shift register is floating so as to use an internal clock signal to generate one of the gate drive signals, where M is a positive integer greater than 2. According to the gate driving device described in item 1 of the scope of patent application, the time interval during which the third external clock signal is at a high voltage level partially overlaps the time interval during which the first external clock signal is at a high voltage level. The gate driving device according to claim 1, wherein the shift register includes: a charging and discharging circuit configured to provide a control signal in a first sub-time interval of the first time interval Raise the voltage level of the control signal according to the (M-2)th level shared gate signal, and pull down the voltage level of the control signal according to the (M+2)th level shared gate signal in the second time interval ; An output stage circuit, coupled to the charging and discharging circuit, configured to receive the control signal, in a second sub-time interval of the first time interval according to the control signal and the first external clock signal to generate the first M-level common gate signal, and pull down the voltage level of the M-th common gate signal according to the second external clock signal in the second time interval; and an anti-noise circuit coupled to the charging and discharging circuit And the output stage circuit is configured to pull down the voltage level of the anti-noise enable signal during the first time interval, and the anti-noise enable signal according to the third external clock signal during the second time interval Performing the first stage raising operation on the voltage level of, and then performing the second stage raising operation on the voltage level of the anti-noise enabling signal according to the third external clock signal and the first external clock signal, Wherein, the charging and discharging circuit, the output stage circuit and the anti-noise circuit are also coupled to a system low voltage. The gate drive device described in item 3 of the scope of patent application, wherein the charging and discharging circuit includes: A pre-charge transistor, the first terminal of the pre-charge transistor is configured to receive a system high voltage, the second terminal of the pre-charge transistor is coupled to the output stage circuit and the anti-noise circuit, the pre-charge The control terminal of the transistor is configured to receive the (M-2)th level common gate signal; and a discharge transistor, the first terminal of which is coupled to the second terminal of the precharge transistor, the The second terminal of the discharge transistor is configured to receive the system low voltage, and the control terminal of the discharge transistor is configured to receive the (M+2)th stage common gate signal, wherein the charge and discharge circuit is configured to receive the pre-charge circuit The second end of the crystal provides the control signal. The gate drive device according to claim 3, wherein the output stage circuit includes: a first output transistor, the first end of the first output transistor is configured to receive the first external clock signal , The second terminal of the first output transistor is configured as the output terminal of the shift register, and the control terminal of the first output transistor is coupled to the charging and discharging circuit to receive the control signal; a second Output transistor, the first end of the second output transistor is coupled to the second end of the first output transistor, the second end of the second output transistor is configured to receive the system low voltage, the second The control terminal of the output transistor is configured to receive the second external clock signal; and an output stage capacitor is coupled to the second terminal of the first output transistor and the first Between the control terminals of the output transistor. The gate drive device according to item 3 of the patent application, wherein the anti-noise circuit includes: a first anti-noise enabling signal generator, including: a capacitor, the first end of the capacitor is configured to receive The third external clock signal, the second end of the capacitor is configured to generate the anti-noise enabling signal, and the capacitor performs the anti-noise enabling signal according to the voltage level of the third external clock signal The first stage of lifting operation; a second anti-noise enabling signal generator, coupled to the second end of the capacitor, configured to receive the first external clock signal and the M-th stage shared gate signal, The first time interval pulls down the voltage level of the anti-noise enable signal according to the M-th common gate signal, and the anti-noise enable signal according to the first external clock signal in the second time interval Perform the second-stage raising operation at the voltage level of, and a pull-down circuit, coupled to the second end of the capacitor, the charging and discharging circuit, and the output stage circuit, configured to receive the anti-noise enable signal, and in the The second time interval is based on the voltage level of the control signal being pulled down by the anti-noise enabling signal and the voltage level of the M-th level common gate signal. The gate drive device according to the sixth item of the scope of patent application, wherein the second anti-noise enabling signal generator includes: a first transistor, a first end of the first transistor, and the first transistor The control terminal of is configured to receive the first external clock signal; A second transistor, the first terminal of the second transistor is configured to receive the first external clock signal, the second terminal of the second transistor is coupled to the second terminal of the capacitor, the second transistor The control end of the crystal is coupled to the second end of the first transistor; a third transistor, the first end of the third transistor is coupled to the second end of the first transistor, the third transistor The second end of the third transistor is configured to receive the system low voltage, the control end of the third transistor is configured to receive the M-th level common gate signal; and a fourth transistor, the first end of the fourth transistor Coupled to the second terminal of the second transistor, the second terminal of the fourth transistor is configured to receive the system low voltage, and the control terminal of the fourth transistor is configured to receive the M-th stage common gate signal. The gate driving device according to claim 6, wherein the pull-down circuit includes: a first pull-down transistor, the first end of the first pull-down transistor is configured to receive the control signal, and the first pull-down transistor The second terminal of a pull-down transistor is configured to receive the system low voltage, the control terminal of the first pull-down transistor is configured to receive the anti-noise enable signal; and a second pull-down transistor, the first The first end of the two pull-down transistors is configured to receive the M-th common gate signal, the second end of the second pull-down transistor is configured to receive the system low voltage, and the control end of the second pull-down transistor is Configure to receive the anti-noise enable signal. As for the gate drive device described in claim 1, wherein each of the gate drive signal generating circuits includes: a bridge transistor, the first end and the control end of the bridge transistor are commonly coupled to the Shift register to receive the M-th stage common gate signal, the second end of the bridge transistor is configured to provide a switching signal; and a transmission transistor, the first end of the transmission transistor is configured to receive For the internal clock signal, the control terminal of the transmission transistor is coupled to the bridge transistor to receive the switching signal, wherein the transmission transistor uses the internal clock signal as a gate drive signal during the first time interval and The gate drive signal is output through the second terminal of the transmission transistor according to the switch signal. For the gate driving device described in item 9 of the scope of patent application, when the voltage value of the switching signal is equal to the difference between the voltage value of the M-th common gate signal and the threshold voltage value of the bridge transistor, the The bridge transistor is floating with the shift register. As described in claim 9 of the scope of patent application, each of the gate drive signal generating circuits further includes: a first pull-down transistor pair coupled to the second end of the bridge transistor And the control terminal of the transmission transistor is configured to pull down the voltage level of the switching signal according to the anti-noise enabling signal and the second external clock signal during the second time interval. For the gate driving device described in item 11 of the scope of patent application, each of the gate driving signal generating circuits further includes: A second pull-down transistor pair, coupled to the second end of the transmission transistor, configured to pull down the gate driver according to the anti-noise enable signal and the second external clock signal during the second time interval The voltage level of the signal. The gate drive device according to the first item of the scope of patent application, wherein the duty cycles of the first external clock signal, the second external clock signal, and the third external clock signal are greater than those of the internal clock signal cycle. The gate driving device described in claim 1, wherein the first external clock signal is inverted to the second external clock signal.

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