TWI702667B - Methods and systems for material property profiling of thin films - Google Patents

Abstract

Methods, tools and systems for full characterization of thin and ultra-thin layers employed in advanced semiconductor device structures are disclosed.

Description

Method and system for analyzing material properties of thin films

The invention relates to the field of semiconductor film measurement methods and devices. More specifically, the present invention provides methods, tools, and systems for the complete characterization of thin and ultra-thin layers used in advanced semiconductor device structures.

With the progress of the semiconductor industry, electronic devices have become more and more miniaturized and they use doped thin layers and ultra-thin layers or ultra-shallow junctions and advanced high-mobility semiconductors in both planar and non-planar structures. Materials such as Ge, Si-Ge and III-V compounds. In order to be able to develop and optimize these advanced devices, it is essential to measure the thin and ultra-thin layers in their structures (which can form the drain and source of, for example, MOSFETS (including multi-gate structures) Polar region or channel) various material properties. Thin and ultra-thin layers can be formed and doped by techniques such as epitaxial growth and ion implantation followed by rapid thermal or laser annealing, gas immersion laser doping, etc., and their thickness can be between 2nm and 50nm In range. Some techniques that have been used to characterize semiconductor layers include spread resistance analysis (SRP), scanning spread resistance microscopy (SSRM), secondary ion mass spectrometry (SIMS), and electrochemical C-V analysis (ECV). SIMS provides information about the composition of the dopant distribution through the thin layer, but it does not provide electrical properties that can be calculated based on some assumptions. SRP and SSRM provide film resistivity that varies according to depth, and assuming a mobility value, the carrier concentration needs to be calculated from this data. However, this Such technologies do not have the resolution to characterize the thinnest films used in advanced device structures. ECV gives a distribution of charge concentration through the measured layer, but it does not provide a mobility value.

U.S. Patent No. 7,078,919 discloses a wet technique for producing various depth distributions of thin semiconductor layers. In the other method, which is partially depicted in FIG. 1, a container 100 containing an electrolyte 101 is placed in contact with a top surface 102 of a semiconductor film 103 to be characterized. A seal 104 between the top surface 102 and the container 100 keeps the electrolyte 101 contained above a test area 105. The electrical contact elements 110A and 110B placed outside the sealing member 104 allow electrical measurement. A potential difference can be applied between at least one of the electrical contact elements 110A and 110B and a cathode 106 immersed in the electrolyte 101 to anodize the top portion 103A of the semiconductor film 103 at the test area 105, thereby converting the top portion 103A Into oxide. Then, a measurement can be performed on the remaining bottom portion 103B of the semiconductor film 103. The mathematical relationship can then be used to calculate the electrical properties or properties of the material initially (before oxidation) at the top portion 103A of the semiconductor film 103. It should be noted that some other in-depth analysis techniques use solution-based chemical etching methods instead of anodizing methods (see, for example, U.S. Patent No. 3,554,891, U.S. Patent No. 3,660,250, and U.S. Patent No. 4,303,482), in which multiple wet solution-based methods are used. Chemical etching, drying and measurement steps.

There is a need to improve the material properties analysis method for the ultra-thin semiconductor layer developed for the advanced node electronic device structure. As mentioned above, these ultra-thin layers may have a thickness of less than 50nm, and therefore analysis of these layers may require a resolution of less than 1nm so that a reasonable number of data points (such as 5 to 10) can be collected through a 2nm thick layer . The high surface roughness that can be left by oxidation or solution-based chemical etching processes and any non-uniform material removal by these techniques can have a negative impact on the accuracy or reliability of the collected data.

Therefore, it is necessary to be able to be accurate even when the test area is less than about 1000 microns x 1000 microns, preferably less than 100 microns x 100 microns, and even when the ultra-thin semiconductor layer can be placed on a 3-dimensional structure New methods and devices for accurately and reliably measuring the characteristics of these semiconductor layers.

100: container

101: Electrolyte

102: top surface

103: Semiconductor film

103A: Top part

103B: bottom part

103BB: remaining part

104: Seal

104A: Corner

104B: Thickness

105: test area

106: cathode

110A: Electrical contact element

110B: Electrical contact element

115: dotted line

116: cavity/groove

117: Location

118: Over-etched area

119: Underetched area

300: substrate

300A: upper surface

301: Semiconductor layer

302: Insulation or high resistance interface

303: test pattern

304: resist spacer

305: top side

306: top surface

307: Window

308: test area

309A: Contact area

309B: contact area

310: Process Room

311: Process cavity

312: Seal

312A: Area

313A: Electrical contact element / electrical contact

313B: Electrical contact element / electrical contact

313C: electrical contacts

313D: electrical contacts

314: Accessories

315A: Tip

315B: Tip

316: entrance

317: Exit

330: Sidewall

350: Cathode

500: Contacts define resist spacers

501: Contact opening

502: Electrical contact pad

600: System

601: Resist spacer formation station

602: Measuring Station

603: carrier

603A: substrate holder

604: Contact Pad Manufacturing Station

605: Test pattern forming station

1200: device

1201: Ultra-thin semiconductor layer

1202: Containment Room

1203: Process Room

1204: entrance

1204A: inlet valve

1205: Exit

1205A: Outlet valve

1206A: Flexible section

1206B: Flexible section

1207: soft seal

1210: top surface

1211: Arrow

1213: Gas supply line

1213A: Supply line valve

1214: discharge line

1214A: discharge line valve

1215: test area

1220: Gas

1221: Process gas

1230: beginning

1240: Limited processing space

1245: wall

1250: conductive coil

1251A: Terminal

1251B: Terminal

1300: top view

1301: Semiconductor film

1307: Process room seal

1315: measurement area

1316A: Electrical contact element

1316B: Electrical contact element

1316C: Electrical contact element

1316D: Electrical contact element

2200: substrate/wafer

2200A: Top surface

2201: measurement zone

2202: test pattern

2203A: Electrical contact element

2203AA: Tip

2203B: Electrical contact element

2203C: Electrical contact element

2203CC: tip

2203D: Electrical contact element

2204: semiconductor layer

2204A: Top surface

2204T: Test layer part

2205: Interface

2206: test area

2206A: Test area

2300: nozzle assembly

2300A: Nozzle assembly

2300AA: Nozzle assembly

2300B: Nozzle assembly

2301: gas nozzle

2303: etchant gas

2303W: exhaust gas

2304: discharge channel

2306: first gap

2307: Barrier Gas

2308: second gap

2310: dotted line

2311: Outer Wall

2312: Barrier

2313: Barrier gas inlet channel

2315: small arrow

2350: Nozzle assembly block

2351: Integrated gas inlet channel

2352: Integrated gas exhaust channel

2353: integrated channel

2354: integrated channel

2360: assembly

2361: assembly

2400: Tools/System

2400A: Etchant gas delivery system

2401: cladding

2402: auxiliary discharge port

2403: etchant source

2404: pressure bottle

2405: carrier gas source/carrier gas cylinder

2406: Barrier Gas Source

2407: discharge pipeline

2408: Vacuum pump

2409: pressure gauge

2500: nozzle

2501: etching gas

2502: measurement assembly

2505: Test layer part

V1: Valve

V2: Valve

V3: Valve

V4: Valve

V5: Valve

V6: Valve

V7: Valve

V8: Valve

V9: Valve

V10: Valve

MFC1: Mass flow controller

MFC2: Mass Flow Controller

MFC3: Mass flow controller

Figure 1 is a schematic diagram depicting a wet anodic oxidation technique used to obtain the electrical property distribution of a thin semiconductor film.

FIG. 2 is an exemplary semiconductor film partially chemically etched by a solution at a test area. The solution-based chemical etching process leaves various non-uniformities and is damaged by a seal.

Fig. 2A is an enlarged view of Fig. 1 near a seal.

FIG. 3 is an exemplary device that can be used to obtain a distribution of material properties of a thin semiconductor layer according to an embodiment of the present invention.

FIG. 3A is a schematic diagram of a process chamber whose start moves away from a top surface of a semiconductor layer to be characterized.

FIG. 3B is a schematic diagram of another process chamber having an internal volume larger than the internal volume shown in FIG. 3A.

3C is a schematic diagram of a process chamber with the ability to generate inductively coupled plasma to activate a process gas during an etching process.

Figure 4 is an exemplary Van Der Pauw patterned semiconductor layer with one of the electrical contacts disposed at four contact locations or regions.

Figure 5 shows a measurement zone that can be a wafer on a substrate.

FIG. 5A shows an enlarged view of the measurement zone in FIG. 5, where the measurement zone includes an exemplary test pattern.

FIG. 5B is a cross-sectional view of the exemplary test pattern of FIG. 5A.

Figure 6 is a schematic diagram of an exemplary nozzle assembly configured to follow a non-contact The method is to etch a layer portion of a semiconductor layer at a test area, so that the measurement can be performed on the layer portion as the thickness of the layer portion decreases.

Fig. 6A is a schematic diagram of another exemplary nozzle assembly without a discharge channel.

Fig. 6B is a schematic diagram of another nozzle assembly having at least one barrier gas inlet channel and at least one discharge channel.

Figure 6AA shows a nozzle assembly with integrated contact elements.

Figure 6AAA shows a bottom view of two exemplary integrated nozzle assemblies.

Figure 7 is an exemplary device or system that can be used to obtain a depth profile of the electrical properties of a thin semiconductor layer.

Figure 7A shows an alternative process gas or etchant gas delivery system.

8A and 8B show a process in which a nozzle assembly is used to etch a part of a semiconductor layer at a test area in a non-contact manner and then a measurement process is performed at the test area after the nozzle assembly is removed.

9A, 9B, 9C and 9D show a procedure for obtaining an electrical property distribution of a semiconductor film or layer according to a preferred embodiment of the present invention.

10A, 10B, 10C, and 10D show top views of the structure depicted in FIGS. 9A, 9B, 9C, and 9D, respectively, using an exemplary cross-shaped test pattern.

Figure 10CC shows a top view of an exemplary resist spacer.

FIG. 11A is a top view of a resist spacer having contact openings.

FIG. 11B shows a side view of a structure formed with the resist spacer of FIG. 11A placed on a test pattern. The enlarged view shows the deposition of an electrical contact pad through a contact opening in the resist spacer.

Figure 12 shows an integrated system including multiple process stations.

This invention was completed with government support No. 1632322 awarded by the National Science Foundation. The government has certain rights in this invention.

The present invention provides a method and device for measuring the material properties (such as electrical properties) of thin material layers and ultra-thin material layers (such as semiconductor layers) to obtain the depth distribution of material properties with a resolution better than 0.5nm through their equal thickness . The semiconductor layer(s) may be disposed on a substrate (such as a wafer). Electrical properties or properties may include properties such as sheet resistance, sheet conductance, resistance, magnetoresistance, conductance, resistivity, conductivity, mobility, and carrier concentration or active dopant concentration. Certain embodiments of the present invention provide methods and devices for obtaining a depth distribution of material properties without contacting the surface of the semiconductor layer and without leaving any residue. The present invention can also be used to determine the properties of other materials (such as the optical, electro-optical, physical (such as strain, stress) properties of any material layer) and to measure the leakage current in the rectifying junction. The technology is suitable for measuring all semiconductors (including metal oxide semiconductors used in the electronics industry (such as thin film transistors used in the manufacture of LCD displays and including at least one of indium, tin, gallium, zinc, silver, and cadmium). Amorphous oxide), conductive oxide and transparent conductive oxide) material properties.

FIG. 1 depicts an ideal situation in which the top portion 103A of the semiconductor film 103 at the test area 105 is converted into an insulating oxide with excellent uniformity, as shown by the dashed line 115. However, in reality, there may be non-uniformities associated with these processes. It should be noted that if a solution-based chemical etching process is used, the top portion 103A should have been removed and not oxidized.

Figure 2 shows some actual non-uniformities that can result from the previously reviewed process. A device similar to the device shown in FIG. 1 may have been used at the test area 105 to chemically etch the semiconductor film 103 in FIG. 2 by a solution, thereby leaving a cavity or trench 116 and a remaining part of the semiconductor film 103 103BB. As can be seen from FIG. 2, the sealing member 104 may have damaged the semiconductor film 103 at the position 117 (see FIG. 1). Considering that the thickness "t" of the semiconductor film 103 can be several nanometers (such as in an ultra-shallow junction structure that can be less than 20nm deep) and the sealing member 104 can have a range of 100,000nm to 1,500,000nm The fact that the sealing member 104 is pressed against the semiconductor film 103 can cause damage at the position 117 shown in FIG. 2, especially if the sealing member 104 is applied to the semiconductor without proper control. In the case of force on the top surface 102 of the membrane 103. The groove 116 in FIG. 2 may not be uniform (that is, it may not be rectangular). This can be attributed to the fact that the solution-based chemical etching process that operates on the semiconductor film 103 at the test area 105 cannot effectively remove the material close to the sealing member 104 as it removes the material at a location far away from the sealing member 104 material. This can be understood from FIG. 2A, which shows a close-up schematic view of FIG. 1 near the sealing member 104. As can be seen in FIG. 2A, the relatively thick sealing member 104 forms a corner 104A above the semiconductor film 103, where the corner 104A may have a small angle section facing the interface where the sealing member 104 and the semiconductor film 103 meet. Any electrolyte or solution that can be used in the chemical etching or oxidation process can hardly enter the corner 104A. Any reaction product resulting from the reaction between the semiconductor film 103 and the used solution can also be difficult to leave the corner 104A. Therefore, non-uniformities such as the under-etched area 119 of the trench 116 can be formed near the sealing member 104. There may also be an over-etched area 118 away from the sealing member 104 caused by other process non-uniformities.

The exemplary non-uniformity shown in FIG. 2 can lead to inaccuracies in the collected data about the semiconductor film 103. This is because when the electrical properties of the remaining portion 103BB of the semiconductor film 103 are measured after the solution-based chemical etching step, this measurement will include the specific gravity from the underetched area 119 of the semiconductor film 103 close to the sealing member 104, and It will not include the specific gravity of the over-etched area 118. The damage at location 117 will also introduce additional resistance to any current that can pass through the semiconductor film 103 during the electrical measurement. It should be noted that as the test area 105 becomes smaller and smaller, the error introduced into the electric quantity measurement due to the non-uniformity shown in FIG. 2 may become larger and larger. In the manufacture of advanced semiconductor devices, it may be necessary to perform material characterization in a 50- to 100-micron wide scribe lane on the product wafer. This means that the test area 105 must be miniaturized to that level, and it is due to the above The error caused by non-uniformity can be extremely large. Furthermore, during solution-based oxidation or etching processes, bubbles can be formed at the liquid/semiconductor surface interface, especially at sharp and low-angle corners. Air bubbles can reduce or completely hinder chemical reactions and cause non-uniform etching or oxidation of the semiconductor film surface. It is also impractical to reliably make the liquid/semiconductor surface free of air bubbles in a highly constrained sealed area having a size of one micron.

In addition, it is not possible to perform a coulometric measurement at a test area of a semiconductor film while keeping a wet or liquid chemical etchant or an anodizing solution in physical contact with a top surface of the semiconductor film at the test area. If the resistance of the liquid chemical etchant or anodizing solution is equal to or lower than the resistance of the semiconductor film at the test area, any electrical measurement performed on the semiconductor film at the test area will be affected by the liquid chemical etchant or anodizing solution. Limited resistance influence. The need to remove the liquid chemical etchant or anodizing solution after each etching or oxidation step may reduce the overall measurement throughput, may not allow continuous measurement, and may affect the process stability, especially the measurement of ultra-thin semiconductor films. In addition, solution-based oxidation may not be used in a continuous or uninterrupted process, in which coulometric measurement can be continuously performed when performing anodization of the semiconductor film surface. The reason is that anodizing involves applying a voltage to the semiconductor layer, which can interfere with the coulometric measurement, and it also involves applying other voltages to the semiconductor layer. Furthermore, the ultra-thin layer can be located on non-planar 3-dimensional complex structures (such as fins and nanotubes), making the process of solution oxidation or solution etching more challenging and non-uniform.

Therefore, in a first embodiment of the present invention, the gaseous etchant can chemically remove a portion of a semiconductor layer at a small test area in a highly controllable manner to form a trench without leaving any residue . In one example, the semiconductor layer to be characterized can be in the shape of a test pattern, which can be formed, prepared, or manufactured before performing the measurement to be discussed. The semiconductor layer can be placed in an enclosed chamber. A process chamber having an opening and including one or more entrances and exits can also be arranged in the containment chamber. During the process, the beginning of the process chamber and the top surface of the semiconductor layer The physical contact forms a restricted processing space, so that a test area of the semiconductor layer is exposed to the restricted processing space. Then, a gaseous etchant or process gas can be introduced into the confined processing space to expose the test area to the gaseous etchant. As the test area is chemically etched and thinned to form a trench, electrical contact to the semiconductor layer outside the process chamber can be used to measure the electrical properties of the remaining layer. This measurement can be performed continuously or in a stepwise manner until the depth of one of the trenches reaches a final value before the etching can be terminated.

In another embodiment, a gas delivery nozzle can be made close to a test area of the semiconductor layer without touching the top surface. The semiconductor layer can be in the shape of a test pattern. A gaseous etchant or process gas can be directed to the test area. As the test area is etched and thinned by a gaseous etchant to form a trench, the electrical properties of the remaining layer can be measured. This measurement can be performed continuously or in a stepwise manner.

In yet another embodiment, a resist spacer may be formed on a top surface of a test pattern manufactured, prepared or formed from a semiconductor layer to be characterized. The resist spacer may include a window that can expose one of the test areas of the test pattern, thereby strictly defining an area of the test area. A process chamber can be lowered onto the resist spacer so that an open end of the process chamber can seal a top side of the resist spacer, thereby forming a process chamber and exposing the test area to the process chamber. Then a liquid chemical etchant, a gaseous etchant or an anodizing solution can be introduced into the process chamber, and the etching or oxidation process(s) can be performed at the test area. The electrical contact to the test pattern outside the process chamber can be used to perform the electrical measurement after the etching/oxidation step or simultaneously with the gaseous etching step. The resist spacer can protect the top surface of the test pattern from damage to one of the seals of the process chamber, and the window can accurately define the test area. Alternatively, a gas delivery nozzle can be made close to the test area defined by the window of the resist spacer without touching the top side of the resist spacer. Then, a process gas or gaseous etchant can be guided to the test area by the gas delivery nozzle. Gaseous etching The electrical properties of the remaining layer can be measured when the test area is thinned by the agent. This measurement can be performed continuously, that is, etching and measurement can be performed simultaneously or in a stepwise manner, wherein each measurement can be performed after each etching step. The resist spacer can accurately define the test area and it can protect the top surface of the test pattern, thereby allowing etching only at the test area.

The various aspects of the present invention will now be described using drawings.

3 shows an exemplary device 1200 that can be used to electrically characterize an ultra-thin semiconductor layer 1201. The ultra-thin semiconductor layer 1201 can be placed on a substrate (such as a wafer) commonly used in the semiconductor industry (not shown to simplify the diagram) ) Above and supported by the substrate. In this embodiment, for illustrative purposes, the secondary containment or containment chamber 1202 may enclose the semiconductor layer 1201 and a processing chamber 1203. The process chamber 1203 may have one or more inlets 1204 and one or more outlets 1205, which can be connected through flexible sections 1206A and 1206B so that an opening 1230 (see FIG. 3A) of the process chamber 1203 can move toward or away from the semiconductor A top surface 1210 of layer 1201, as shown by arrow 1211. Alternatively, the process chamber 1203 can be fixed and the top surface 1210 can move toward or away from the process chamber 1203. There may also be a soft seal 1207 placed above the circumference of the opening 1230 of the process chamber 1203, so that when the opening 1230 of the process chamber 1203 and the top surface 1210 of the semiconductor layer 1201 are in physical contact, the soft seal 1207 seals the top surface 1210, Thus, a restricted processing space 1240 is surrounded by one or more walls 1245 of the process chamber 1203, and a test area 1215 of the semiconductor layer 1201 is exposed to the restricted processing space 1240. The one or more inlets 1204 and the one or more outlets 1205 may be equipped with an inlet valve 1204A and an outlet valve 1205A to be able to control the flow of gaseous species (such as a process gas) into and out of the process chamber 1203, respectively. The containment chamber 1202 may have its own gas supply line 1213 with a supply line valve 1213A and a discharge line 1214 with a discharge line valve 1214A to carry gas into the containment chamber 1202 and take the gas out of the containment chamber 1202, Also, a vacuum is generated in the containment chamber 1202 as needed. Alternatively, the containment chamber may include an atmospheric pressure air.

The process chamber 1203 can have various shapes. However, it is preferably a cylindrical shape with an inner diameter of less than 10 mm, preferably less than 5 mm, and most preferably less than 2 mm. Preferably, an area of the test area 1215 may be substantially smaller than a total area of the top surface 1210 of the semiconductor layer 1201. It should be noted that the area of the test area 1215 may be substantially the same as a cross-sectional area of the beginning 1230 of the process chamber 1203. As an example, the total area of the top surface 1210 of the semiconductor layer 1201 may be in the range of ² cm ² to 1000 cm ² or more, and the area of the test area 1215 may be less than 1% of the total area of the top surface 1210. The area of the test area 1215 is preferably less than about 0.2 cm ² and most preferably less than about 0.04 cm ² . A micro-sized o-shaped seal with an inner diameter of 0.1 mm will allow to define a test area 1215 having an area less than 0.0001 cm ² . The shape of the process chamber 1203 can be designed so that the area of the test area 1215 can be kept small but the limited processing space 1240 can be large to accommodate enough process gas to provide the required etching amount. Fig. 3B shows this exemplary design of this process chamber.

The exemplary device 1200 of FIG. 3 can be used to implement the process steps of the present invention in various ways. For example, in an exemplary process flow, the inlet valve 1204A and outlet valve 1205A and the supply line valve 1213A can be closed and the discharge valve 1214A can be opened. As shown in FIG. 3A, the process chamber 1203 can be raised away from the top surface 1210 of the semiconductor layer 1201, and a vacuum can be generated in the containment chamber 1202 by pumping the containment chamber 1202 downward through the exhaust line 1214. After reaching a base pressure (which can be less than about 30 millitorr), the discharge line valve 1214A can be closed and the open end 1230 of the process chamber 1203 can be lowered onto the top surface 1210, so that the seal 1207 defines the test area above the top surface 1210 1215. A power measurement can now be performed to measure the electrical properties of the semiconductor layer 1201 at the test area 1215. After the initial measurement is obtained, the gas supply line valve 1213A can be opened and a suitable gas 1220 (such as an inert gas) can be introduced into the containment chamber 1202 through the gas supply line 1213 until it can reach a value in the containment chamber 1202. The predetermined pressure level. At the same time, the inlet valve 1204A can be opened And a process gas 1221 can be introduced into the confined processing space 1240 of the process chamber 1203. The process gas 1221 can be delivered to the top surface 1210 of the semiconductor layer 1201 in the test area 1215 until a process pressure can be reached in the limited processing space 1240. The inlet valve 1204A can then be closed. Alternatively, the inlet valve 1204A can be kept open and the process gas 1221 can continue to flow into the restricted processing space 1240. In this case, it is preferable that the outlet valve 1205A is also opened to keep the process pressure in the restricted processing space 1240 substantially constant. A process vacuum pump (not shown) attached to the outlet 1205 after the outlet valve 1205A can be configured to adjust the process pressure in the restricted processing space 1240, because if a process pressure is desired to be less than atmospheric pressure, the process gas 1221 can continue to flow in Restricted processing space 1240. Although the process pressure in the confined processing space 1240 and the predetermined pressure level in the containment chamber 1202 may be different, it is preferable that they are substantially the same so that the semiconductor layer 1201 and its substrate may not be subjected to the process chamber The stress of a pressure difference between the interior of 1203 and the interior of the containment chamber 1202.

In another exemplary process flow, the inlet valve 1204A and the outlet valve 1205A can be opened, and an inert gas entering through the inlet valve 1204A and leaving through the outlet valve 1205A can be used to flush the restricted processing space 1240. During this time, a suitable gas 1220 (such as another inert gas) can flow into the containment chamber 1202 through the gas supply line valve 1213A and can be discharged through the discharge line valve 1214A, thereby establishing atmospheric pressure in the containment chamber 1202. During this process, the containment chamber 1202 may also contain ambient air. After flushing the process chamber 1203 with the inert gas that enters through the inlet valve 1204A, the electricity measurement system can now be used to measure the electrical properties of the semiconductor layer 1201 at the test area 1215. After obtaining the initial measurement, the process gas 1221 can be introduced into the restricted processing space 1240 of the process chamber 1203. The process gas 1221 can be delivered to the top surface 1210 of the semiconductor layer 1201 at the test area 1215, and the process gas 1221 can flow out through the outlet 1205. It should be noted that this can be an atmospheric pressure process, in which the process gas can be supplied by a source exceeding atmospheric pressure 1221. The test zone 1215 can be at atmospheric pressure or up to about 25 Torr higher than atmospheric pressure.

Once the process gas 1221 contacts the top surface 1210 of the semiconductor layer 1201, it can begin to chemically react with the semiconductor species and can begin to etch the top surface 1210 at the test area 1215, thereby forming volatile species and a trench. After a predetermined etching cycle, the removal of material from the test area 1215 can be terminated by the following steps: the self-made process chamber 1203 removes the process gas 1221 by pumping or by flushing with an inert gas and the volatilization due to the etching process Sexual gaseous species. Then, a power measurement system can be used to measure the electrical properties of the thinner remaining portion of the semiconductor layer under the trench at the test area 1215. The thinning and measurement steps can be repeated to obtain a depth distribution of electrical properties through the thickness of the semiconductor layer 1201 until a depth from the trench to the semiconductor layer 1201 reaches a final value. It should be noted that in order to measure the ultra-shallow junctions in the drain/source regions of advanced transistors, the final value of the trench depth can be less than 50nm, preferably less than 30nm. In addition, the most important measurement area can be the top 5nm thickness of the semiconductor layer. Therefore, it is preferable to adjust the etching rate in the process to be less than 5 nanometers/second, more preferably less than 2 nanometers/second, and most preferably less than 1 nanometer/second to collect high-resolution data.

In an alternative embodiment, when the semiconductor layer 1201 can be etched or thinned at the test area 1215 by the process gas 1221, the electricity measurement can be performed in a continuous or semi-continuous manner. It should be noted that FIG. 3 does not show a coulometric system for performing coulometric measurement after each etching step or during etching to simplify the diagram. The electricity measurement system may include electrical contact elements for establishing or making electrical contact to the top surface 1210 of the semiconductor layer 1201 for sheet resistance and Hall voltage measurement. It should be noted that the Hall voltage measurement can be performed by using a magnet that can apply a magnetic field to the test area 1215, wherein the magnetic field can be substantially perpendicular to the top surface 1210. The intensity of the applied magnetic field can be 2000 Gauss or higher. Other components of the electricity measurement system may include current sources, voltmeters, electronic switches, control circuits and computers.

The gaseous chemical etching process described above integrated with an electrical characterization method (such as a sheet resistance measurement and a Hall voltage or Hall coefficient measurement) has advantages over the use of solution-based wet oxidation and etching techniques. Many advantages. First, the technology of the present invention uses cleaning and drying methods to remove a test area or part of a semiconductor layer in a test area in a highly controllable manner. By controlling the process pressure, by controlling the concentration and properties of the process gas (also known as gaseous etchant or etchant gas) and/or by changing the temperature and etching cycle of the semiconductor layer, we can accurately control the amount of material removed And for the etching process that removes a small part of the semiconductor layer at the test area at a low rate (such as a rate less than 0.1 nanometer/second), a resolution better than 0.5 nm is achieved. The gaseous etching rate can also be controlled by providing light energy to the etched surface. For example, a laser beam directed onto the semiconductor surface can accelerate the etching in the area it hits. The gaseous etching of the present invention can also provide highly uniform material removal from the test area 1215, thereby leaving a surface with a roughness of less than about 0.1 nm. Therefore, the technology of the present invention can successfully characterize ultra-thin layers having a thickness of less than about 5 nm. Since the resistance of gaseous species can be much higher than the resistance of the etched semiconductor layer at the test area 1215 so that the resistance of the process gas existing above the test area 1215 does not affect the electrical measurement of the semiconductor layer, it can be sequentially (etched) +measurement+etching+measurement, etc.) or simultaneously (without removing process gas from the surface) etching and measurement steps. In the technology in which the electrolyte or anodized solution remains on the measurement area when the measurement is performed, there may be interference from the solution or electrolyte, as described above. If the anodizing step forms a highly insulating thick oxide layer above the semiconductor surface at the test area, the thick oxide layer can insulate or isolate the electrolyte from the measured semiconductor layer. However, in high-resolution measurement where the semiconductor layer smaller than 0.5nm needs to be converted into oxide, the formed ultra-thin oxide layer cannot electrically isolate the electrolyte above the ultra-thin oxide layer from the part of the semiconductor layer below it . For example, one formed on the SiGe layer or a Si 0.1nm to 0.2nm thick anodic oxide may not have a SiO ₂ insulating oxide of stoichiometric composition, but may have an alkylene oxide (SiO _x, where x <2), or Even hydroxide species. These sub-oxide and hydroxide species can have a resistivity value much lower than what we would expect from a stoichiometric SiO ₂ layer. Furthermore, the 0.1nm to 0.2nm thick oxide layer can electrically decompose during the measurement of the semiconductor layer and cause the electrolyte to be electrically shorted to the semiconductor, thereby causing the wrong results of the first few data points. Therefore, the use of electrically insulating process gas or etchant gas can perform continuous electrical measurement, in which etchant gas exists above the test area. In addition, gaseous etching leaves a clean surface, which is different from wet techniques that may require cleaning of the semiconductor layer and substrate after obtaining a depth profile.

Although gaseous chemical etching of the semiconductor layer has been used as an example to describe the preferred embodiment of the present invention, the present invention can also be practiced using a gaseous conversion process. In this case, a thin surface portion of the semiconductor layer can be converted into a converted layer (such as an oxide or a high-resistivity material) by a gaseous species (such as an oxidant), and electricity can be implemented as the thickness of the converted layer increases Measurement.

4 shows a top view 1300 of an exemplary semiconductor film 1301. The semiconductor film 1301 may be similar to the semiconductor layer 1201 of FIG. 3 and may be characterized using the teachings of the present invention. As can be seen from FIG. 4, the semiconductor film 1301 is in the form or shape of a material quality test pattern, such as a cross van der Pauw pattern. It should be noted that many Van der Pauw patterns can be used instead of the patterns shown in FIG. 4, including patterns in the form of bars, squares, and clover leaf (see, for example, Keithley Application Note No. 3180). The position of a process chamber seal 1307 that may be similar to the seal 1207 in FIG. 3 is shown as a dashed line in FIG. 4. The process chamber seal 1307 may define a measurement area 1315 that may be similar to the test area 1215 of FIG. 3. The measurement area 1315 is the shaded area shown in FIG. 4 and is located in an area surrounded by the process chamber seal 1307. There may be electrical contact elements 1316A, 1316B, 1316C, and 1316D made into electrical contacts at the contact area (which may be outside the measurement area 1315, such as at the end of the test pattern or at the arm of the Van der Pauw pattern). When the semiconductor material can be slowly thinned by the gaseous species of a process gas at the measurement area 1315 At this time, these electrical contact elements can be used to perform a power measurement at the test area or measurement area 1315, as described above. For example, by applying a current between the contact elements 1316A and 1316D through the semiconductor film 1301 and measuring the voltage drop between the contact elements 1316B and 1316C, it can be removed from the portion of the semiconductor film 1301 in the measurement area 1315 The thickness of the semiconductor film obtains the sheet resistance value. The portion of the semiconductor film 1301 that can be in the measurement area 1315 can be etched with an etchant gas in a stepwise manner or in a continuous manner to obtain a mobility value by the following steps: applying a magnetic field perpendicular to the surface of the semiconductor film 1301; A current between the contact elements 1316A and 1316C is passed through the semiconductor film 1301; and a Hall voltage between the contact elements 1316B and 1316D is measured.

Referring again to FIG. 3, the process gas 1221 may include a reactive gas with the ability to chemically etch the semiconductor layer 1201 to form volatile species that can be easily removed by the process chamber 1203 to leave a clean surface. These reactive gases include (but are not limited to) gases including halogens such as Cl, Br, I, and F. Examples of process gases include XeF ₂ , Cl ₂ , F ₂ , HCl vapor, HF vapor, SF ₆ , CF ₄ , BCl ₃ and Cl(F) _x , Br(F) _x , I(F) _x (for various " x”). The process gas may also include water vapor and O ₂ . Preferably, the process gas may include XeF ₂ .

The process pressure can be in the range of 10 ^-4 Torr to 760 Torr or higher. The process can be carried out at a temperature ranging from 20°C to 100°C. Depending on the thickness of the material to be removed or whether a coulometric measurement is performed after each successive etching step or during a continuous etching period, the etching period can be in the range of several seconds to several minutes. In a process using gradual material removal, the preferred etching cycle for each etching step can be in the range of 1 second to 20 seconds to remove a thickness of about 0.1 nm to 1 nm thick material.

So far, the above discussion has been based on the use of gaseous species to chemically etch the surface of a semiconductor layer at a predetermined test area. This method is the best embodiment of the present invention because chemical etching is gentle and it does not damage the semiconductor surface during the etching process. Chemical gaseous etching can also leave a uniform surface that does not negatively affect the electrical measurement of the semiconductor layer.

In another preferred embodiment of the present invention, a plasma (eg, a mild plasma) can be generated in the process chamber 1203 during an etching step to activate gaseous species and increase the etching rate of the semiconductor layer. Any of the well-known methods can be used to generate plasma, including (but not limited to) DC parallel plates, RF parallel plates, inductive coupling, and microwave plasma generation. Fig. 3C shows an exemplary process chamber 1203 similar to the process chamber of Fig. 3A, except that the process chamber 1203 of Fig. 3C can be constructed using an insulating material (such as ceramic, glass, or quartz) and includes a conductive coil 1250 surrounding its body. When a high-frequency power is applied between the two terminals 1251A and 1251B of the coil 1250, an inductive coupling plasma is generated inside.

In another preferred embodiment of the present invention, an atomic layer etching (ALE) type process can be used to thin the semiconductor layer before each measurement step (see, for example, ECS Journal of Solid-State Science and Technology, Vol. 4 , N5041-5053 (2015) Oehrlein et al. "Atomic layer etching at tipping point: an overview" and Journal of Vacuum Science Technology A, Vol. 33, p. 02082-1 (2015), Kanarik et al. "Overview of ALE in semiconductor industry”). Referring again to FIG. 3, in this case, the process gas 1221 may include a precursor (such as a gas including any one of Cl, F, O ₂ , and H ₂ ) that can be delivered to the restricted processing space 1240. The precursor can react with the top surface 1210 of the semiconductor layer 1201 at the test area 1215 to form a single layer of the absorption reaction product. After the precursor is removed from the restricted processing space 1240, auxiliary species can be introduced into the restricted processing space 1240 to remove the monolayer of the absorption reaction product, thereby causing an atomic layer portion of the semiconductor layer 1201 at the test area 1215 The removal. Then, the coulometric measurement of the remaining semiconductor layer can be performed as described above. By repeating the steps of ALE and electric quantity measurement, an extremely accurate electric parameter depth distribution can be obtained for the semiconductor layer 1201. Auxiliary species may include, but are not limited to, low energy ions, fast neutral atoms, electrons, and photons.

In another preferred embodiment of the present invention, a voltage-induced wet dissolution process can be used to achieve thinning or thinning of a material layer at a test area. It should be noted that in the solution-based chemical etching process, the surface of the material at the test area can be exposed to a chemical etchant solution to chemically etch the material. In this case, to stop etching, the chemical etchant solution needs to be removed from the surface of the material. In the case of the solution-based oxidation process described with reference to FIG. 1, the surface of the material layer at the test area can be exposed to an anodizing solution or electrolyte, and an anode voltage can be applied to a cathode placed in the oxidation electrolyte. To the material layer. This process converts the surface of the material layer at the test area into oxide without removing any material (that is, the anodizing solution does not have the ability to chemically dissolve the formed oxide). In a voltage-induced wet dissolution process of the present invention, the surface of the material layer at the test area can be exposed to a process solution, wherein the process solution can only apply a voltage to an electrode placed in the process solution The ability of the material layer to thin the material layer at the test area. Different from the solution-based oxidation process (which does not thin the material with or without voltage applied) and different from the solution-based chemical etching process (which thins the material by chemical etching without applying any voltage), The process solution of the voltage-induced wet dissolution process does not chemically dissolve or etch the material layer in the absence of a voltage, but it thins the material layer when a voltage is applied. Therefore, in order to stop the etching or thinning process, it is not necessary to remove the process solution from the surface of the material layer at the test area, only the applied voltage needs to be removed. Depending on the material layer and the process solution, the applied voltage can be an anode voltage or a cathode voltage. The process solution can be selected so that it does not chemically attack and etch the surface of the material layer in the absence of a voltage, but is configured to etch the surface of the material layer when a voltage is applied to the material layer. For example, a voltage-induced wet dissolution process can be used to controllably etch and reduce an exemplary process solution that mainly includes water (>99% by weight) and a small amount of ionic species (such as chloride, fluoride, iodide, or nitride). Thin Ge (germanium) layer. If a test area of the Ge layer is exposed to this exemplary process solution, no material is removed from the test area. However, when will When an anode voltage is applied to the Ge layer for an etching cycle, the test area of the Ge layer exposed to the process solution can be thinned. One mechanism of this thinning process can be: i) the surface of the Ge layer at the test area is oxidized by the applied voltage; then ii) the surface oxide is dissolved by the process solution. The amount of thinning can be controlled extremely accurately by counting the charge passing through the test area during the etching cycle. It should be noted that this process is more attractive than solution-based chemical etching techniques that use concentrated chemical solutions with low resistivity. The dilute solutions used in the voltage-induced wet dissolution process are safer to handle and use; and they have extremely high resistivity, and therefore can be left above the test area during any electrical measurement performed at the test area. The thickness control of the removed material layer can also be very accurate, because the charge transferred during the etching cycle can be measured and controlled very accurately.

In the method described above, a sealing member (such as an elastic O-ring) placed at the circumference of an open end of a process chamber may be in physical contact with a top surface of a semiconductor layer to be characterized. Although this is acceptable in a development environment for measuring blank wafers, in applications such as patterned wafer manufacturing, if the wafer is to be returned to the process flow, a product is touched during a process step The surface of the wafer may need to undergo strict cleaning procedures after the completion of the process steps. This increases the cost of the overall process flow and may have to discard wafers. Therefore, it is better to perform characterization without contacting the surface of the wafer with the elastic material into which particles can be introduced. The material removal technology used to thin the semiconductor layer at the test area also does not leave residues that are incompatible with subsequent process steps, which may involve sensitive high-temperature processes. If these conditions are met, a product wafer can be characterized and returned to the production process for further processing to complete the electronic devices on it. The following preferred embodiments of the present invention describe the non-contact delivery of process gas or gaseous etchant to the top surface of the semiconductor layer in a non-contact manner.

FIG. 5 shows a substrate or a wafer 2200 including a measurement zone 2201 indicated by a dashed line. The wafer 2200 may be a blank wafer with a semiconductor layer to be characterized on its top surface 2200A. Alternatively, the wafer 2200 may be a patterned wafer with partially finished devices (not shown) and the semiconductor layer to be characterized has been placed on the measurement zone 2201 that can be positioned in a scribe lane. It should be noted that the typical width of a scribe lane may be about 50 microns. An area of the measurement zone 2201 may be substantially smaller than a total area of the wafer 2200. For example, the measurement zone 2201 may be smaller than 10 mm×10 mm, preferably smaller than 5 mm×5 mm, and most preferably smaller than 3 mm×3 mm, and the total area of the wafer 2200 may be larger than 300 cm ² . Therefore, the area of the measurement zone 2201 can be less than 0.3% of the total area of the wafer 2200. For patterned wafers, the measurement zone area can be less than 0.0001 cm ² . For example, for a 300mm diameter wafer, the measurement zone area can be less than 0.00002% of the total wafer area. Although the boundary of the measurement zone 2201 is shown as a square in FIG. 5, the boundary can be any shape. The measurement zone 2201 may include a test pattern manufactured or prepared from the semiconductor layer by electrically isolating a small section of the semiconductor layer from its surrounding environment (see, for example, FIG. 4). This isolation can be achieved by etching, scribing, and laser ablation around the periphery of the test pattern. As mentioned above, there can be many different shapes and forms of test patterns (such as bars, crosses, circles, squares, etc.) that can be used. 5A shows an enlarged view of the measurement zone 2201 of FIG. 5 and an exemplary test pattern 2202 in the form of a cross. Four electrical contact elements 2203A, 2203B, 2203C, and 2203D are arranged at the ends of the four arms of the outer test pattern 2202 of a test area 2206. FIG. 5B shows a cross-sectional view of the test pattern 2202 for cutting the contacts 2203A and 2203C. In this cross-sectional view, one can see the semiconductor layer 2204 to be measured or characterized, which is placed on the wafer 2200. An interface 2205 at a bottom surface of the semiconductor layer 2204 can have electrical insulation properties, so that the semiconductor layer 2204 can be substantially electrically isolated from the wafer 2200 by a high resistivity material or by a reverse bias rectifying junction. The test area 2206 of the test pattern 2202 is also shown by dotted lines in FIGS. 5A and 5B. A portion of the semiconductor layer 2204 at the test area 2206 is marked as a test layer portion 2204T. The test area 2206 may be smaller than 3x3 mm ² , preferably smaller than 2x2 mm ² . The material removal and electric quantity measurement of the test layer portion 2204T can be performed at the test area 2206 according to the present invention, as will be described below.

Figure 6 depicts a preferred embodiment of the present invention. FIG. 6 shows a nozzle assembly 2300 including a gas nozzle 2301 and a discharge channel 2304. The nozzle assembly 2300 can be in close proximity to a top surface 2204A of the semiconductor layer 2204 (such as the semiconductor layer shown in FIG. 5B), thereby establishing a first gap 2306 between the gas nozzle 2301 and the top surface 2204A of the semiconductor layer 2204. The gas nozzle is configured to direct a process gas or a gaseous etchant or an etchant gas 2303 onto the layer portion 2204T at the test area 2206 (see also FIG. 5B). The wafer 2200 and the nozzle assembly 2300 can move relative to each other and both can be housed in a containment chamber or a cladding 2401 (see FIG. 7). The enclosure 2401 may include a barrier gas 2307, which is preferably an inert gas like nitrogen. The etchant gas 2303 can be directed or flowed toward the test area 2206 through the gas nozzle 2301 to begin chemically thinning the test layer portion 2204T therein, as shown by a dashed line 2310. The electrical contact elements 2203A, 2203B, 2203C, and 2203D (see also FIG. 5A) can be used to measure the electrical power required by one of the test layer portions 2204T when the test layer portion 2204T is thinned by etchant gas 2303 in a clean and non-contact manner. Parameters (such as resistivity or mobility). Since performing a series of measurements based on the removed thickness, a depth distribution of electrical properties can be calculated for the test layer portion 2204T, which can be a good representation of the semiconductor layer 2204. It should be noted that during the thinning process, an exhaust gas 2303W may be generated above the test layer portion 2204T. The exhaust gas 2303W may include an unreacted portion of the etchant gas 2303 and any gaseous reaction products that may be formed over the test layer portion 2204T during etching. As shown in FIG. 6, the discharge channel 2304 may be configured to collect the exhaust gas 2303W formed at the test area 2206 through the first gap 2306. The discharge channel 2304 can also collect the barrier gas 2307 that can flow through a second gap 2308 formed between an outer wall 2311 of the discharge channel 2304 and the top surface of the semiconductor layer 2204. Therefore, the exhaust gas 2303W can be prevented from entering the package In the shell 2401.

It should be noted that the electrical contact element can preferably be integrated into a body of a nozzle assembly (such as the integrated nozzle assembly 2300AA of FIG. 6AA). It should be noted that the electrical contact element can also be attached to the nozzle assembly 2300 of FIG. 6, preferably to the outer wall 2311. The integrated nozzle assembly 2300AA may include a nozzle assembly block 2350. The nozzle assembly block 2350 may include at least one integrated gas inlet channel 2351 and at least one integrated gas discharge channel 2352. There may be additional integrated channels 2353 and 2354 (not shown to simplify the drawings) on either side of the contacts 2203A and 2203C, as shown by the dashed lines. The additional integrated channels 2353 and 2354 can be used as barrier gas inlet channels for making a barrier gas toward the top surface 2204A of the semiconductor layer 2204 (as described below with reference to FIG. 6B) or the like can be combined with at least one integrated gas discharge channel 2352 interchange. This barrier gas can protect the tips 2203AA and 2203CC of the electrical contact elements 2203A and 2203C from any corrosive effects of the etchant gas 2303. The electrical contact elements 2203A and 2203C can be attached to the nozzle assembly block 2350 so that when the first gap 2306 between the nozzle assembly block 2350 and the top surface 2204A of the semiconductor layer 2204 is established, the electrical contact elements 2203A and 2203C The tips 2203AA and 2203CC (please note that other contact elements are not shown in this section) can contact the semiconductor layer 2204 or the test pattern 2202.

The integrated nozzle assembly of Figure 6AA can be manufactured in different shapes and forms. Figure 6AAA shows a bottom view of two exemplary integrated nozzle assemblies. The assembly 2360 may include a gas inlet channel 2351 and one or more (for example, four) integrated gas discharge channels 2352 made into the nozzle assembly block 2350. The optional additional integrated channel 2354 and electrical contact elements 2203A, 2203B, 2203C, and 2203D that can be used as barrier gas inlet channels are also shown. The assembly 2361 is designed to handle a more rectangular area and the gas inlet channel 2351 is a rectangle or a series of circular openings, as shown by the dotted line in the rectangle. The electrical contact element in this design is placed in the gas inlet channel Near the corner of the 2351 rectangle. It should be understood that a set of integrated gas discharge channels 2352 means that a distributed discharge channel is placed around the gas inlet channel 2351. Similarly, the gas inlet channel 2351 may also be a distributed inlet channel as shown for the assembly 2361. The distributed exhaust channel may include two or more individual channels and they may be placed around the gas inlet channel in various distances and orientations. There may be an optional additional integrated channel 2354 that can be used as a barrier gas inlet channel of the assembly 2361.

It should be noted that the present invention applies a gas etching process to a preselected (eg, small) area of a wafer in a highly controllable manner to thin the material during continuous or stepwise measurement of the material therein. Unlike applications where high etching rates (such as >10 nm/sec) are desired, the present invention uses methods that have the ability to provide extremely low etching rates (such as <1 nm/sec) in a highly controlled manner. It should be noted that the resolution of the process of the present invention (ie, the ability to obtain many data points for each thickness cell removed from the test layer portion 2204T shown in FIG. 5) depends on the low etching of the semiconductor material by the etchant gas Fine control of speed. In a preferred embodiment of the present invention, the wafer is in a cladding that is at or near atmospheric pressure (for example, up to 25 Torr higher than atmospheric pressure). In a more preferred embodiment, substantially the entire substrate or wafer stays in an enclosure with an air or surrounding air during the measurement.

The first gap 2306 in FIG. 6 may be less than 2 mm, more preferably less than 1 mm. The etchant gas 2303 may be a mixture of an etchant and an inert gas. Although the electrical contact elements 2203A and 2203C in FIG. 6 are shown as being independent of the nozzle assembly 2300, these contact elements can also be in the form of probes integrated with the nozzle assembly 2300 or attached to the nozzle assembly 2300 ( Preferably a spring-loaded probe), so that when the nozzle assembly is lowered toward the wafer surface and the discharge gap 2306 in FIG. 6 is established, the probe can be physically located at the predetermined contact area or point at the end of the arm of the test pattern 2202 The top surface 2204A of the semiconductor layer 2204 is contacted and thus electrically contacted (see also FIG. 6AA). Electric contact The elements 2203A and 2203C are placed in the discharge channel 2304, and a low-concentration exhaust gas 2303W further diluted by the barrier gas 2307 flows in the discharge channel 2304.

In another embodiment shown in FIG. 6B, a nozzle assembly 2300B may include the nozzle 2301, the discharge channel 2304 and the outer wall 2311 of FIG. 6, but these components may be surrounded by a barrier wall 2312, which may be on the outer wall A barrier gas inlet channel 2313 is formed between 2311 and barrier wall 2312. During operation, the barrier gas 2307, which is preferably an inert gas, can be forced downward toward the wafer 2200 through the barrier gas inlet channel 2313. The flow of the barrier gas 2307 into the discharge channel 2304 and into the cladding (flowing into the cladding, as shown by the small arrow 2315) effectively isolates the gas environment of the test area 2206 from the chamber environment. In this case, the chamber can include ambient air close to the atmosphere and substantially the entire substrate or wafer can be maintained in the environment, except for a small section in which the measurement and etching processes are performed. This method is attractive because it reduces the use of inert gases and it is an atmospheric process.

In another embodiment of a nozzle assembly 2300A shown in FIG. 6A, the discharge channel 2304 of FIG. 6 can be eliminated. In this configuration, the exhaust gas 2303W can be pushed out through the first gap 2306 into the enclosure 2401 which can have an auxiliary discharge port 2402 (see FIG. 7). Since the volume and concentration of the etchant gas 2303 used in this process can be very low, when the exhaust gas 2303W enters the cladding 2401, it can be substantially covered by the atmosphere in the cladding (which can be an inert gas flowing into the cladding). Gas) dilution. The exhaust gas and inert gas in the cladding can then be pushed out through the auxiliary discharge line 2402 shown in FIG. 7. This method can be used in applications where a very low flow rate (for example, less than 0.0001sccm) of the etchant gas 2303 can be used to process a very small test area (for example, 50 microns in diameter) and transport the etchant through small channels (for example, 50 microns in diameter) Gas 2303.

FIG. 7 shows a preferred embodiment of an exemplary tool or system 2400 that can be used to measure the electrical property distribution of a semiconductor layer disposed on a substrate (such as a wafer). The system 2400 may include a cladding 2401, and the nozzle assembly 2300B and wafer 2200 shown in FIG. 6B may be placed in the cladding 2401. It should be noted that any of the nozzle assemblies shown in FIGS. 6, 6A, 6B, 6AA, and 6AAA can be used in the system 2400 by making necessary minor adjustments in the design. The system 2400 may further include an etchant source 2403, a pressure bottle 2404, a carrier gas source 2405, a barrier gas source 2406 and various valves (V1, V2, V3, V4, V5, V6, V7, V8, V9, V10) and mass flow controllers (MFC1, MFC2, MFC3) used to adjust and control the flow of various gases. The operation of the system 2400 will now be described using XeF ₂ as an exemplary etchant, which is a solid having a vapor pressure of ~4 Torr at 25°C.

During operation, the enclosure 2401 may include ambient air at atmospheric pressure or ambient pressure. Valve V6 can be opened and a vacuum pump 2408 can evacuate the pressure bottle 2404 to a base pressure as monitored by a pressure gauge 2409. The base pressure can be less than about 20 millitorr, preferably less than about 10 millitorr, to eliminate air and water vapor. Then valve V6 can be closed and valve V7 can be opened to deliver a controlled amount of etchant vapor from etchant source 2403 to pressure bottle 2404. When a predetermined etchant pressure is reached in the pressure bottle 2404, the valve V7 can be closed and the valves V5 and V8 can be opened to bring a carrier gas from the carrier gas source 2405 into the pressure bottle 2404 until it reaches the pressure bottle 2404. A predetermined etchant gas pressure, the valve V5 can be closed at this time. Therefore, an etchant gas (which is a mixture of etchant and carrier gas) is prepared in the pressure bottle 2404. The pressure of the etchant gas in the pressure bottle 2404 may preferably be higher than the atmospheric pressure, so that it can become the driving force for the etchant gas to flow to the nozzle assembly 2300B, as we will examine next.

Before the partial etching of the semiconductor layer is initiated by the etchant gas, the valves V9, V10, and V1 can be opened to establish one of the self-barrier gas source 2406 through the MFC3 to the barrier gas channel 2313, to the discharge channel 2304, and the discharge line 2407 Obstruct gas flow. It is also possible to open valve V2 for a short time to flush out any ring that may exist in the gas nozzle 2301 by the carrier gas from the carrier gas cylinder 2405 Environment air. To start the partial etching of the semiconductor layer 2204 as described with respect to FIG. 6, the valves V4 and V3 can then be opened to direct the etchant gas from the pressure bottle 2404 to the gas nozzle 2301 through the MFC2. If it is desired to further dilute the etchant gas by the carrier gas to obtain a lower etching rate, the valve V2 can also be opened to introduce more carrier gas controlled by the MFC1 into the etchant gas flow. The carrier gas may include an inert gas such as nitrogen and argon.

In this example, the pressure of the etchant in the pressure bottle 2404 may be less than about 4 Torr. The etchant pressure may preferably be in the range of 0.05 Torr to 3.5 Torr, more preferably in the range of 0.1 Torr to 3 Torr. The pressure of the etchant gas in the pressure bottle 2404 may be higher than 1000 Torr, preferably higher than 2000 Torr. For example, if the etchant pressure in a pressure bottle 2404 is 0.5 Torr and the etchant gas pressure is 3000 Torr, the percentage of etchant in the process gas or etchant gas stream entering the surface of the semiconductor layer will be about 0.017%. This ratio is preferably less than 0.2%, more preferably less than 0.1%. This can be further diluted by the additional carrier gas from the carrier gas cylinder 2405 through the valve V2, resulting in an etching rate of the semiconductor layer much lower than 1 nm/sec, preferably lower than 0.2 nm/sec. It should be noted that the flow rate of the etchant gas adjusted by MFC2 is another factor that controls the etching rate on the surface of the semiconductor layer (lower flow rates generally produce lower etching rates, so it is better for the measurement of material property analysis Resolution).

It should be noted that the use of the pressure bottle 2404 in FIG. 7 provides flexibility to change the amount of etchant in the etchant gas over a wide range. It is also possible to eliminate the pressure bottle 2404 and only open the valves V8 and V10. The etchant source 2403 is pressurized by the carrier gas from the carrier gas source 2405 to set the etchant source 2403 (see the alternative etchant gas delivery system 2400A in FIG. 7A). ) One of the etchant gas pressure (measured by pressure gauge 2409). The etchant gas pressure may be higher than 1000 psi, preferably higher than 2000 psi. In this case, the partial pressure of the etchant in the etchant source 2403 will be its vapor pressure (~4 Torr at 25°C) and it will not change until all solid XeF _{2 is used} . However, the percentage of etchant in the etchant gas will decrease as the volume of XeF ₂ used (assuming the same total pressure) is replaced by the carrier gas. However, by reducing the carrier gas pressure in the etchant gas pressure in the etchant source 2403 as the solid XeF _{2 is} consumed, this percentage can be kept constant. The design in Figure 7A can be used in applications where etching is performed in the scribe lanes of a patterned wafer. As described above, in these applications, a channel with a similar cross-sectional area can be used to transport etchant gas over a region of 20 to 100 microns in size. The etchant gas flow rate required in these applications can be much lower than 0.001 sccm, and therefore the mass flow controller MFC2 in FIG. 7A may not be used. By replacing the MFC2 with a fixed hole, the flow rate of the etchant gas can be set to any desired value (such as 0.0001sccm or 0.00001sccm), as long as the carrier gas is supplemented to the etchant source 2403 to make the etchant gas pressure keep constant. In these applications, it is important to measure the electrical properties of a semiconductor layer with respect to the top <5nm region, preferably <3nm region. In this case, the etching process can be limited to the etching depth, so as not to etch deeper and damage the wafer.

In yet another embodiment, the gaseous chemical etching of the semiconductor layer and the measurement of its properties (such as electrical properties) can be continuously performed by moving in and out of the electrical contact element or nozzle assembly. For example, FIG. 8A shows a simplified nozzle 2500, which may have used an etching gas 2501 to etch or thin a test layer portion of the semiconductor layer 2204 at a test area 2206A, thereby leaving a thinned test layer portion 2505. As shown in FIG. 8B, the simplified nozzle 2500 can then be removed and a measurement assembly 2502 can be lowered toward the semiconductor layer 2204 to measure a material property of the thinned test layer portion 2505. Then, the etching and measurement steps can be repeated to obtain a distribution. The measurement assembly may include a 4-point probe or other probe system that can contact the semiconductor layer 2204 at a predetermined position for measurement. It should be noted that although the simplified nozzle 2500 shown in FIGS. 8A and 8B is similar to the nozzle shown in FIG. 6A, the preferred nozzle assembly of this embodiment can be shown in FIGS. 6, 6B, 6AA, and 6AAA. The design shown. Therefore, during the etching step shown in FIG. 8A, an etchant gas environment can be limited to the etched area, where the rest of the wafer and the measurement assembly 2502 stay in the environment. Angry.

In another embodiment, when the etching gas 2501 can be delivered to the test layer portion 2505 of the semiconductor layer 2204 through the nozzle 2500, the measurement assembly 2502 can perform measurement. In this case, there is no need to remove the nozzle 2500 for measurement. However, since the measurement assembly remains in the flow of the etching gas 2501, its components need to be selected so that it is not etched by the etching gas or otherwise negatively affected by the etching gas.

It should be noted that the system using the exemplary nozzle of the present invention may include more than one nozzle for increasing the measurement throughput and for simultaneously performing measurement at multiple locations above a wafer. It is also possible that the exemplary tool of FIG. 7 may include more than one pressure bottle 2404 and each pressure bottle may include a different amount of etchant. For example, the semiconductor layer to be characterized may include a thin oxide layer on its surface, and the thin oxide layer may require a higher concentration of etchant for etching. In this case, at the beginning of the etching process, a relatively concentrated etchant gas from a first pressure bottle can be used to remove oxides and then a relatively dilute etchant gas from a second pressure bottle can be used for etching The rest of the process. It should also be noted that an in situ measurement of the thickness of the material removed from the test area can be achieved by integrating an optical detector with a beam directed to the surface of the etched test area.

In the preferred embodiment described above, the test is at least partly defined by a seal or by the geometry of a nozzle used to direct an etchant gas onto the semiconductor material. Area. The preferred embodiment described below uses a resist spacer, wherein the resist spacer can be formed on the top surface of a material quality test pattern provided in the semiconductor layer to be characterized. The resist spacers of these inventions may include a window that can expose a test area on the top surface of the test pattern. During the process, a process chamber can be lowered onto the resist spacer, so that an opening of the process chamber can preferably seal the top side of the resist spacer, thereby forming a process chamber. Then a liquid or gaseous etchant or oxidant can be introduced into the system The etching or oxidation process can be performed at the test area in the process cavity. The electrical measurement can be performed after the etching/oxidation step or during the gaseous etching step using the contact made to the test pattern outside the process chamber. Some of the benefits of resist spacers include protecting the surface of the test pattern from damage to the seal, uniformly removing or oxidizing materials through the window, miniaturizing the test area and highly accurately defining the test area (for wet electrochemical Oxidation or etching methods are especially important). It should be noted that the resist spacer can also be used in a gaseous etching process, in which a nozzle (such as those depicted in FIG. 6, 6A, 6B, and 6AA) can be lowered to closely approach the resist spacer without touching Resist spacers. Then a gaseous etchant can be directed toward the test area. Then, when the gaseous etching step can be performed, the contact to the test pattern can be used to perform the electrical measurement. In this case, some of the benefits of resist spacers include uniform material removal, the possibility of miniaturizing the test area, and the highly accurate definition of the test area.

9A, 9B, 9C, and 9D describe a method or procedure for obtaining an electrical property distribution of a semiconductor film or layer according to a preferred embodiment of the present invention. FIG. 9A shows a semiconductor layer 301 for which an electrical distribution can be obtained. The semiconductor layer 301 may be disposed on an upper surface 300A of a substrate 300 (see FIG. 9B). There may be an insulating or high resistance interface 302 between the semiconductor layer 301 and the upper surface 300A of the substrate 300. The high-resistance interface 302 may include a rectifying junction, a buffer layer, a high-resistivity film, or an insulating film such as a silicon-on-insulator SOI structure. First, a test pattern 303 having a top surface 306 can be prepared or formed from the semiconductor layer 301. This can be used to remove the section of the semiconductor layer 301 from the test pattern 303 so as to electrically isolate the test pattern 303 from the rest of the semiconductor layer 301 (such as laser scribing, mechanical scribing, photolithography or resist Agent deposition, followed by gaseous or wet chemical etching, etc.) to achieve. Next, as shown in FIG. 9C, a resist spacer 304 may be formed over the top surface 306 of the test pattern 303. The resist spacer 304 includes a top side 305 and a top surface 306 exposing the test pattern 303 A window 307 on a test area 308. The resist spacer 304 may also expose one or more contact regions 309A and 309B above the top surface 306 of the test pattern 303. During the next step of the process, a beginning of a process chamber 310 can be placed above the test area 308 to form a process chamber 311. A sealing element 312 may be used to seal the process chamber, and the sealing element 312 may include a flexible elastic material. In the preferred embodiment shown in FIG. 9D, the process chamber 310 seals the top side 305 of the resist spacer 304 to avoid possible damage to the test pattern 303 as discussed above. One or more electrical contact elements 313A and 313B can then be applied to the top surface 306 of the test pattern 303 at the one or more contact areas 309A and 309B. In a preferred embodiment, one or more electrical contact elements 313A and 313B can be attached to the process chamber 310 by the attachment 314, so that when the process chamber 310 is close to the test area 308, the electrical contact elements 313A and 313B The tips 315A and 315B can contact the top surface 306 of the test pattern 303 at the contact areas 309A and 309B, thereby establishing electrical contact.

Referring again to FIGS. 9A to 9D, the semiconductor layer 301 may have a thickness in the range of 1 nm to 50 nm, and the thickness of the substrate 300 may be greater than 200,000 nm. The substrate 300 may preferably be a semiconductor wafer having a diameter greater than or equal to 10 cm. The test pattern 303 can be a pattern that can be used for sheet resistance and mobility measurement, such as a van der Pauw type structure shaped into a rectangle, square, circle, clover leaf, bar or cross (see, for example, Keithley Application Note No. 3180). The exemplary test pattern 303 in FIG. 9B is a cross-shaped pattern. The resist spacer 304 may include a material that resists the solution or dry gas that can be brought into or flowed into the process chamber 311. The resist spacer 304 may be deposited or fabricated using techniques such as photolithography, screen printing, roll coating, and preferably inkjet printing. The resist spacer 304 may have a thickness in the range of 100 nm to 10,000 nm, preferably in the range of 500 nm to 5,000 nm, and more preferably in the range of 1,000 nm to 5,000 nm. An area of the test area 308 may be less than about 0.2 cm ² , preferably less than about 0.1 cm ² and most preferably less than about 0.02 cm ² . The process chamber 310 may have one or more inlets 316 for bringing liquid chemicals and/or gases into or into the process chamber 311 and for bringing the used liquid chemicals and/or gaseous reaction products out or out of the process chamber 311 One or more exits 317.

10A, 10B, 10C, and 10D show top views of the exemplary structure depicted in FIGS. 9A, 9B, 9C, and 9D, respectively. The semiconductor layer 301 can be seen in FIG. 10A. In FIG. 10B, the test pattern 303 is in the form of a cross and the upper surface 300A of the substrate 300 is visible around the test pattern 303. FIG. 10C shows the resist spacer 304 disposed above the test pattern 303. As shown in FIG. 10CC, there is a window 307 in the middle of the resist spacer 304 and the window 307 exposes the test area 308 on the test pattern 303. As can be seen, the test area 308 is substantially the same as the area where the four arms of the cross-shaped test pattern 303 are connected together. FIG. 10D shows the position of the seal 312 above the resist spacer 304. The electrical contacts 313A, 313B, 313C, and 313D are placed at the ends of the four arms of the test pattern 303. As can be seen from FIG. 10D, an area 312A enclosed by the sealing member 312 is larger than the area of the test area 308, preferably substantially larger, for example, at least three times.

Referring to FIGS. 9D and 10D, an exemplary procedure for obtaining a depth distribution of an electrical property of the semiconductor layer 301 can be performed as follows.

During the first step of the measurement procedure, the electrical properties of the semiconductor layer 301 can be measured. To measure the sheet resistance, for example, a first current can be transmitted between the contacts 313A and 313D through the test area 308, and a first induced voltage can be measured between the contacts 313C and 313B. To measure the Hall coefficient, in the presence of a magnetic field substantially perpendicular to the top surface 306 (see FIG. 3B), a second current can be transmitted between the contacts 313A and 313B through the test area 308, and the A second induced voltage is measured between the contacts 313C and 313D. From these measurements, a first sheet resistance value and a first Hall coefficient value can be calculated for the semiconductor layer 301 using well-known mathematical expressions. During the second step of the measurement procedure, chemical species can be introduced into the process chamber 311 to oxidize or remove a predetermined portion of the semiconductor layer 301 at the test area 308 and then the above description can be repeated Measurement of sheet resistance and Hall coefficient. The difference between the measurement before material removal/oxidation and the measurement after material removal/oxidation at the test area 308 can then be used to calculate a data point. By repeating the measurement and material removal/oxidation steps, we can obtain the full depth distribution of the electrical properties of the semiconductor layer 301.

It should be noted that the chemical species used for oxidation can be an anodizing solution (not shown). In this case, a cathode 350 can be placed in the process chamber 311 so that the cathode 350 contacts the anodizing solution. Alternatively, a process solution may be used to perform a voltage-induced wet dissolution process as described above. In this case, the cathode 350 serves as an electrode and an anode or cathode voltage can be applied to the semiconductor layer 301. A solution-based chemical etching process can also be used by introducing a chemical etchant solution into the process chamber 311. The chemical species can also be gaseous, as described in the preferred embodiment previously described. In any case, material removal or oxidation can be achieved in a uniform manner through the window 307 in the resist spacer 304.

The invention can provide several benefits:

i) The use of resist spacers 304 can prevent damage to the test pattern 303 that can be caused by the seal 312, as discussed in relation to FIG. 2. Since the seal 312 can physically contact the top side 305 of the resist spacer 304 instead of the fragile and electroactive top surface 306 of the test pattern 303, more pressure can be safely applied for better sealing without worry The test pattern 303 is damaged. It should be noted that in applications where the test pattern 303 may not be fragile, the resist spacer need not extend all the way under the sealing member 312. With this design, the remaining benefits listed below still apply.

ii) Uniform material removal or oxidation can be achieved through the window 307 in the resist spacer 304, because the thick seal 312 is moved away from the edge or circumference of the test area 308, thereby eliminating the small angle corners caused by the presence of the seal And the non-uniformity introduced by the high wall, as described with reference to Figure 2A. It should be noted that the thickness of the resist spacer 304 can be in the range of only 100nm to 10,000nm The thickness of the sealing member 312 may be in the range of 100,000 nm to 1,500,000 nm. Therefore, one of the sidewalls 330 of the resist spacer 304 (see FIG. 9D) does not present a small acute angle and a high wall to the process chemicals like a large seal.

iii) The use of the resist spacer 304 can realize the miniaturization of the test area 308. If the seal is used to define the area of the test area 308, it will be very difficult or impossible to reduce the area to the micron level, because of the non-uniformity discussed above and the physical limitations of using relatively large seals. By defining the test area with a thin resist spacer 304, the area of the test area can be reduced to less than 0.0001 cm ² , and even to 0.00002 cm ² or less. In principle, using this method, we can directly measure through a high-mobility channel of a transistor by connecting the contact to an area outside the sealing member 312 by using a connecting wire under the resist spacer 304.

iv) For the method of using the solution in the process chamber 311, moving the seal 312 away from the test area 308 can avoid the formation of bubbles that tend to grow at sharp low-angle corners above the test area 308. It should be noted that these bubbles will reduce the etching/oxidation in the area to which they are attached and increase the etching/oxidation in other areas, which will receive higher than normal current density or chemical etching.

v) For a method using an anodic oxidation process, the cathode 350 (see FIG. 9D) can be moved downward and close to the resist spacer 304, or it can contact the top side 305 of the resist spacer 304 without being electrically short Connect to the test area 308. The anodic oxidation of the enclosed space can improve the uniformity of anodic oxidation in the test area 308.

vi) Using the resist spacer 304 can also achieve an accurate in-situ measurement of the thickness of the material removed from the test area 308. Referring again to FIG. 9D, as an example, the cathode 350 may be replaced by an optical detector that monitors an area surrounding the test area 308. The optical detector can be an interference detector that can measure a distance between the top side 305 of the resist spacer 304 and a horizontal plane of the test area 308. Without any etching, the optical detector will measure the sidewall of the resist spacer 304 A height of 330 (in other words, the thickness of the resist spacer 304), because the horizontal plane of the test area 308 coincides with the top surface 306 of the test pattern. When it is preferable to use gaseous species to etch or remove the material at the test area 308, the optical detector will sense the top side 305 of the resist spacer (which is not etched) and the level of the test area 308 (which starts) Descent). This height difference can provide the thickness of the material removed from the test area 308, which can then be used to map the accurate depth distribution of the measured electrical properties. It should be noted that when the etching and the electricity measurement can be performed in a stepwise or continuous manner, the optical detector can function continuously.

vii) FIG. 11A shows a top view of an example of a contact defining resist spacer 500 including a window 307 (similar to FIG. 10CC) and one of four contact openings 501. As can be seen from the side view in FIG. 11B, when the contact defining resist spacer 500 is disposed above the test pattern 303, it exposes a small portion of the top surface 306 of the test pattern 303 through the contact opening 501. As can be seen from the enlarged inset in FIG. 11B, the electrical contact pad 502 can be deposited through the contact opening 501 to establish electrical contact with the top surface 306 of the test pattern 303. This method can have one of the benefits of avoiding possible damage to the top surface 306 of the test pattern 303 by electrical contact elements (such as the electrical contact elements 313A and 313B shown in FIG. 9D), because in this case the electrical contact elements can only Contact the electrical contact pad 502. Furthermore, as the size of the test pattern 303 decreases, it may become more and more difficult to properly place the tips 315A and 315B (FIG. 9D) of the electrical contact elements 313A and 313B above the test pattern 303. The design of FIG. 11B can provide a larger electrical contact pad 502 that can be more easily contacted by electrical contact elements without damaging the test pattern 303 and without worrying about electrical shorts. It should be noted that the contact pad 502 of FIG. 11B can be formed by depositing a conductive material (such as injecting a conductive ink or paste) over the contact opening 501 where the contact defines the resist spacer 500.

viii) The resist spacer 304 of FIG. 10CC and the contact of FIG. 11A define the resist spacer 500 accurately and accurately define an area of the test area 308. Define a test by elastomer seal The area of one of the zones may not be accurate. Knowing the area of a test area is particularly important for the anodization process and the voltage induction dissolution process, because in order to determine the thickness of the oxidized material or the removed material, one needs to know the current density, which is determined by the The value obtained by dividing the current by the area of the test area.

FIG. 12 schematically shows an integrated system 600 for executing at least some of the procedures or process steps shown in FIG. 9B, FIG. 9C, and FIG. 9D. The integrated system 600 may include at least one resist spacer forming station 601 and one measuring station 602. A carrier 603 with a substrate holder 603A can move a substrate between stations. The substrate includes a test pattern as shown in FIGS. 9B and 10B. The carrier 603 can first transport the substrate with the test pattern to the resist spacer forming station 601, where a resist spacer (such as the resist spacer shown in FIG. 10CC and FIG. 11A) may be formed above the test pattern. ). The resist spacer formation station 601 may preferably include an inkjet print head that can deposit resist material over the test pattern in the form of a predetermined resist spacer design. The carrier 603 can then transport the substrate with the test pattern and resist spacers to the measuring station 602. The measurement station 602 may include a process chamber (such as the process chamber shown in Figure 3D) or any of the nozzle designs discussed previously. The process chamber or nozzle can be configured to provide solution or etching gas to a test area defined by a window in the resist spacer above the surface of the test pattern. The measuring station 602 may also include electrical components and systems and magnets to perform necessary measurements at the test area of the test pattern. The integrated system 600 may additionally include a contact pad manufacturing station 604. The contact pad manufacturing station 604 may include a conductor deposition device (such as a liquid or paste contact pad material delivery tool) to form the contact pad over the test pattern. This exemplary method of preparing one of the contact pads is described with respect to FIG. 11B. The contact pad material delivery tool can be an inkjet print head, a syringe, a dispenser, etc. The integrated system 600 may also include a test pattern forming station 605. The test pattern forming station 605 can receive a substrate on which a semiconductor layer is placed (such as FIGS. 9A and 10A). The substrate shown in) and it can prepare a test pattern (such as the test pattern shown in FIG. 9B and FIG. 10B) by removing unnecessary parts of the semiconductor layer from the substrate. The test pattern forming station 605 may include a semiconductor removal tool that can be used to form a test pattern. The semiconductor removal tool may include: a laser scribe; a gaseous or liquid etching tool; an oxidation tool, which can convert undesired parts of the semiconductor layer surrounding the test pattern into oxide; or a mechanical scribing tool, It removes a narrow part of the test pattern to electrically isolate it from the rest of the semiconductor layer.

In an exemplary manufacturing process, the carrier 603 may first transport a substrate with a semiconductor layer on it to the test pattern forming station 605 of the integrated system 600. After at least one test pattern is formed on the substrate, the carrier 603 can transport the substrate to the resist spacer forming station 601. After forming a resist spacer over the test pattern, the substrate can be transported to a contact pad manufacturing station 604. Then, the substrate can be transported from the contact pad manufacturing station 604 to the measurement station 602 to obtain the electrical property distribution of the semiconductor layer. Although a linear carrier 60% is depicted in Fig. 12, a rotating carousel or any other design can also be used to transfer substrates between stations.

Although given that a part of a semiconductor layer is thinned by a chemical reaction with gaseous species, the electrical properties of the semiconductor layer (such as resistivity, mobility, carrier concentration, and magnetoresistance) are measured as an example. The invention is described, but it should be understood that the semiconductor layer can be replaced by other materials (such as metals, semi-metals, or high resistivity materials) to perform measurements on these other materials. Furthermore, when the material layer is thinned at a test area by the etchant gas guided to the test area as described herein, other material properties of the material layer (such as optical or photoelectricity) can also be measured in situ according to the depth. Material properties (such as reflectivity, photoconductivity) and physical material properties (such as strain, stress)), and the remaining unetched part of the material layer at the test area is measured.

Therefore, according to the above, some examples of the present invention relate to a method for obtaining a depth distribution of a material property of a layer, the layer including a top surface and a test area, the method includes the following steps: measuring the test area The material properties of the layer; deliver a process gas to the top surface of the layer at the test area; use the process gas to chemically etch a predetermined thickness of the layer at the test area to be at the test area in the layer Forming a trench with a depth and leaving a remaining part of the layer at the test area; and measuring the material properties of the remaining part of the layer at the test area. In addition to one or more of the above examples or instead of one or more of the above examples, in some examples, the steps of conveying, chemical etching and measuring the material properties of the remaining part are repeated until the depth of the trench reaches a final value . In addition to or in place of one or more of the above examples, in some examples, the chemical etching step is performed at a predetermined etching rate of less than 5 nm/sec. In addition to or instead of one or more of the above examples, in some examples, the predetermined etching rate is less than 1 nanometer/second. In addition to or instead of one or more of the above examples, in some examples, the layer is a semiconductor layer. In addition to or instead of one or more of the above examples, in some examples, the material property of the semiconductor layer is an electrical property. In addition to or instead of one or more of the above examples, in some examples, the final value of the trench depth is less than 50 nm. In addition to or in place of one or more of the above examples, in some examples, the method further includes placing the layer in a surrounding area before the step of measuring the material properties of the layer at the test area Steps in a barrier chamber, and wherein the containment chamber is at atmospheric pressure. In addition to or instead of one or more of the above examples, in some examples, the containment chamber includes air. In addition to or instead of one or more of the above examples, in some examples, the semiconductor layer is in the shape of a test pattern, and the step of measuring the material properties of the remaining part includes the step of measuring the material properties of the remaining part in the contact area Make electrical contacts to the test pattern. In addition to or instead of one or more of the above examples, in some examples, the contact areas are located outside the test area. In addition to or instead of one or more of the above examples, in some examples, the electrical property is mobility and a magnetic field is applied to the test area during the step of measuring the material properties of the remaining part , Wherein the magnetic field is substantially perpendicular to the top surface. In addition to or instead of one or more of the above examples, in some examples, the process gas includes an etchant and wherein the etchant includes halogen. In addition to or instead of one or more of the above examples, in some examples, the etchant is XeF ₂ . In addition to or instead of one or more of the above examples, in some examples, a percentage of the etchant in the process gas is less than 0.1%. In addition to or instead of one or more of the above examples, in some examples, one of the test areas has an area less than 0.04 cm ² . In addition to or instead of one or more of the above examples, in some examples, the area of the test area is less than 0.0001 cm ² . In addition to or in place of one or more of the above examples, in some examples, the step of delivering the process gas to the top surface at the test area includes: including one or more walls and A process chamber at an open end physically contacts the top surface such that the open end seals the top surface to form a restricted processing space surrounded by the one or more walls of the process chamber, thereby exposing the test area to the restricted process Space; and the process gas is introduced into the confined processing space, thereby establishing a process pressure. In addition to or in place of one or more of the above examples, in some examples, the method further includes the limitation after the chemical etching step and before the step of measuring the material properties of the remaining part A step of removing the process gas from the processing space. In addition to or instead of one or more of the above examples, in some examples, the semiconductor layer is placed in a containment chamber and the containment chamber is at atmospheric pressure. In addition to or instead of one or more of the above examples, in some examples, the process pressure is atmospheric pressure. In addition to or in place of one or more of the above examples, in some examples, measurement of the material properties of the remaining part occurs when the chemical etching is performed. In addition to one or more of the above examples or instead of one or more of the above examples, in some examples, the process gas is delivered to the top surface of the layer at the test area, but not delivered to a different test area The top surface of the layer at the other zone. In addition to or instead of one or more of the above examples, in some examples, the layer is chemically etched at the test area but not at another area.

Some examples of the present invention relate to a method for obtaining a depth distribution of an electrical property of a semiconductor layer. The method includes: providing a test pattern from the semiconductor layer, the test pattern having a top surface, a test area, and a contact area; A process chamber comprising one or more walls and an open end physically contacts the top surface so that the open end seals the top surface, thereby forming a restricted processing space, wherein the test area is exposed to the restricted processing space; using the test pattern Measure the electrical properties of the semiconductor layer in the test area; introduce a process gas into the confined processing space to establish a process pressure; use the process gas to etch one of the semiconductor layers in the test area at an etching rate Predetermined thickness and leaving a remaining part of the semiconductor layer; and measuring the electrical properties of the remaining part of the semiconductor layer. In addition to or instead of one or more of the above examples, in some examples, the steps of introducing, etching, and measuring are repeated to obtain the depth distribution of the electrical property. In addition to one or more of the above examples or in place of one or more of the above examples, in some examples, the method further includes processing from the restriction after the etching step and before the step of measuring the electrical properties of the remaining part A step of space removal of the process gas. In addition to or instead of one or more of the above examples, in some examples, the process pressure is atmospheric pressure. In addition to or instead of one or more of the above examples, in some examples, the process gas includes halogen. In addition to or instead of one or more of the above examples, in some examples, the etching rate is less than 1 nanometer/sec.

Some examples of the present invention relate to a device for obtaining a depth distribution of a material property of a layer having a top surface and a test area. The device includes: a process chamber having one or more walls and an opening ; A mechanism for establishing a relative movement between the layer and the process chamber so that the opening of the process chamber can move toward the top surface to seal the top surface, thereby forming the process chamber surrounded by the walls A restricted processing space and exposing the test area to the restricted processing space; at least one inlet configured to bring a process gas into the restricted processing when the open end of the process chamber seals the top surface The space allows the use of the process gas to chemically etch a predetermined thickness of the layer at the test area during an etching cycle; and a measurement system configured to measure the material properties of the layer at the test area. In addition to or instead of one or more of the above examples, in some examples, the layer is a semiconductor layer. In addition to or instead of one or more of the above examples, in some examples, the material property is an electrical property. In addition to or instead of one or more of the above examples, in some examples, one of the test areas has an area less than 0.1 cm ² . In addition to or instead of one or more of the above examples, in some examples, the measurement system includes electrical contacts configured to contact the top surface outside the test area and configured A magnetic field is applied to a magnet of the test area, the magnetic field is substantially perpendicular to the top surface of the semiconductor layer. In addition to or instead of one or more of the above examples, in some examples, the device further includes at least one outlet configured to remove gaseous species from the process chamber after the etching cycle. In addition to or instead of one or more of the above examples, in some examples, the device further includes a containment chamber enclosing the layer and the process chamber.

Some examples of the present invention relate to a method for obtaining a depth distribution of a material property of a film having a top surface, the film being disposed at a measurement zone on a substrate having a total area, the method It includes the following steps: positioning a nozzle assembly within a threshold distance of the top surface without touching the top surface, the nozzle assembly including a nozzle; supplying an etchant gas to the nozzle; The etchant gas is guided to the top surface at a test area of the film; a test layer portion of the film at the test area is thinned; the material of the thinned test layer portion is measured Nature; and repeat the steps of guiding, thinning and measuring. In addition to or instead of one or more of the above examples, in some examples, the substrate and the nozzle assembly are placed in an enclosure having a closed environment at atmospheric pressure. In addition to or instead of one or more of the above examples, in some examples, the material property is an electrical property. In addition to or instead of one or more of the above examples, in some examples, the film is a semiconductor film and the measuring step includes using at least one electrical contact element to form the top surface of the film At least one electrical contact. In addition to or instead of one or more of the above examples, in some examples, the at least one electrical contact to the top surface of the film is made outside the test area. In addition to or instead of one or more of the above examples, in some examples, the at least one electrical contact element is integrated with the nozzle assembly such that the nozzle assembly is positioned on the top surface of the Steps within the threshold distance cause the at least one electrical contact element to touch the top surface, thereby making the at least one electrical contact to the top surface. In addition to or instead of one or more of the above examples, in some examples, the enclosed environment includes air. In addition to or in place of one or more of the above examples, in some examples, the method further includes the step of: blocking an inert gas through at least one barrier gas inlet channel integrated with the nozzle assembly Barrier gas to the top surface; and collecting an exhaust gas and an inert barrier gas into at least one integrated discharge channel in the nozzle assembly, wherein exhaust gas is generated during the thinning step and the at least one barrier gas The inlet channel and the at least one integrated exhaust channel are configured to isolate the test area from the enclosed environment. In addition to or instead of one or more of the above examples, in some examples, the film is a semiconductor film. In addition to or instead of one or more of the above examples, in some examples, the etchant gas includes halogen. In addition to or instead of one or more of the above examples, in some examples, supplying the etchant gas includes flowing the etchant gas from a pressure bottle to the nozzle, which One of the etchant gases in the pressure bottle has a pressure higher than atmospheric pressure. In addition to or instead of one or more of the above examples, in some examples, the pressure of the etchant gas in the pressure bottle is higher than 2000 Torr.

Some examples of the present invention relate to a method for obtaining a depth distribution of an electrical property of a semiconductor layer. The method includes the following steps: providing a test pattern of the semiconductor layer, the test pattern having a top surface and The contact area; depositing a resist spacer above the test pattern except the contact areas, the resist spacer having a top side and a window exposing a test area of the test pattern; in the Make two or more electrical contacts to the top surface of the test pattern at the contact area; use the two or more electrical contacts to measure the electrical properties of the semiconductor layer at the test area; the test area Exposure to a chemical; by using the chemical to make a top part of the semiconductor layer at the test area electrically inert; using the two or more electrical contacts to determine except for the top part of the semiconductor layer at the test area Electrical properties of the remaining part of the semiconductor layer at the test area. In addition to or instead of one or more of the above examples, in some examples, the chemical is an anodizing solution and making the top portion of the semiconductor layer at the test area electrically inert includes borrowing The top portion of the semiconductor layer at the test area is oxidized by applying an anode voltage to the test pattern relative to an anode that touches the anodizing solution. In addition to or in place of one or more of the above examples, in some examples, the chemical is a chemical etchant solution and making the top portion of the semiconductor layer at the test area electrically inert includes The top portion of the semiconductor layer at the test area is chemically etched using the chemical etchant solution. In addition to or instead of one or more of the above examples, in some examples, the chemical is a process solution and renders the top portion of the semiconductor layer at the test area electrically inert, including by Relative to touching an electrode of the process solution, a voltage is applied to the test pattern to dissolve the top portion of the semiconductor layer at the test area. In addition to one or more of the above examples Or instead of one or more of the above examples, in some examples, the voltage is an anode voltage. In addition to or instead of one or more of the above examples, in some examples, the process solution is configured to not chemically etch the semiconductor layer at the test area in the absence of voltage. In addition to or instead of one or more of the above examples, in some examples, the chemical is a process gas and making the top portion of the semiconductor layer at the test area electrically inert includes using the The process gas chemically etches the top portion of the semiconductor layer at the test area. In addition to or in place of one or more of the above examples, in some examples, the method further includes the step of arranging an opening of a process chamber above the test area to form a process chamber, wherein The beginning of the process chamber includes a seal that seals the process chamber at its periphery, wherein the contact areas are left outside the process chamber, wherein the test area is completely exposed to the process chamber, and wherein the test area is exposed The chemical includes introducing the chemical into the process chamber. In addition to or in place of one or more of the above examples, in some examples, the method further includes the step of arranging an opening of a process chamber above the test area to form a process chamber, wherein The beginning of the process chamber includes a seal that seals the process chamber at its periphery, wherein the contact areas are left outside the process chamber, wherein the test area is completely exposed to the process chamber, and wherein the test area is exposed The chemical includes introducing the chemical into the process chamber. In addition to or in place of one or more of the above examples, in some examples, the method further includes the step of arranging an opening of a process chamber above the test area to form a process chamber, wherein The beginning of the process chamber includes a seal that seals the process chamber at its periphery, wherein the contact areas are left outside the process chamber, wherein the test area is completely exposed to the process chamber, and wherein the test area is exposed The chemical includes introducing the chemical into the process chamber. In addition to or instead of one or more of the above examples, in some examples, the method further includes monitoring the top side of the resist spacer and the test area A distance between a surface of the remaining part of the semiconductor layer, thereby determining the rate of chemical etching. In addition to or instead of one or more of the above examples, in some examples, an optical detector is used to perform the monitoring.

Although the foregoing content has shown, illustrated and described various embodiments of the present invention, it will be obvious that those skilled in the art can make various modifications to the described embodiments without departing from the spirit and scope of the present invention. Replace, modify and change.

1200‧‧‧device

1201‧‧‧Ultra-thin semiconductor layer

1202‧‧‧Containment Room

1203‧‧‧Process room

1204‧‧‧Entrance

1204A‧‧‧Inlet valve

1205‧‧‧Exit

1205A‧‧‧Outlet valve

1206A‧‧‧Flexible section

1206B‧‧‧Flexible section

1207‧‧‧Soft seal

1210‧‧‧Top surface

1211‧‧‧Arrow

1213‧‧‧Gas supply pipeline

1213A‧‧‧Supply line valve

1214‧‧‧Discharge pipeline

1214A‧‧‧Discharge line valve

1215‧‧‧Test Area

1220‧‧‧Gas

1221‧‧‧Processing gas

1240‧‧‧Limited processing space

1245‧‧‧Wall

Claims (12)

A device for obtaining a depth distribution of an electrical property and a layer having a top surface and a test area, the device comprising: a nozzle assembly, which includes a nozzle; at least one contact element, and the nozzle assembly Integration; a mechanism for establishing a relative movement between the layer and the nozzle assembly so that the nozzle can be positioned within a threshold distance of the top surface; at least one inlet, which is configured to a During the etching cycle, an etchant gas is brought into the nozzle and the etchant gas is guided to the top surface of the layer at the test area to thin the layer at the test area; and a measurement system, which is Is configured to measure the electrical properties of the layer at the test area, wherein when the nozzle is positioned within the threshold distance of the top surface, the at least one contact element is configured to touch outside the test area The top surface. The device of claim 1, wherein the layer is a semiconductor layer and an area of the test area is less than 0.1 cm ² . The device of claim 1, further comprising at least one outlet configured to remove gaseous species from the test area during the etching cycle. A method for obtaining a depth distribution of an electrical property and a depth of a film having a top surface, the film being arranged at a measurement zone above a substrate having a total area, the method includes the following Steps: Position a nozzle assembly within a threshold distance of the top surface without touching the top surface. The nozzle assembly includes a nozzle; an etchant gas is supplied to the nozzle; the etching is performed through the nozzle The agent gas is guided to the top surface at a test area of the film; thins a test layer portion of the film at the test area; measures the electrical properties of the thinned test layer portion; and repeats guiding and thinning And measuring the steps; wherein the measuring step includes using at least one electrical contact element to make at least one electrical contact with the top surface of the film; and wherein the at least one electrical contact element and the nozzle assembly Integration such that the step of positioning the nozzle assembly within the threshold distance of the top surface causes the at least one electrical contact element to touch the top surface, thereby making the at least one electrical contact to the top surface. The method of claim 4, wherein the substrate and the nozzle assembly are placed in an enclosure having a closed environment at atmospheric pressure. The method of claim 4, wherein the film is a semiconductor film and the measuring step includes using at least one electrical contact element to make at least one electrical contact to the top surface of the film. The method of claim 4, wherein the at least one electrical contact to the top surface of the film is made outside the test area. The method of claim 5, wherein the enclosed environment includes air. The method of claim 8, further comprising the steps of: bringing an inert barrier gas to the top surface through at least one barrier gas inlet channel integrated with the nozzle assembly; and bringing an exhaust gas and the inert barrier The gas is collected into at least one integrated discharge channel in the nozzle assembly; wherein the exhaust gas is generated during the thinning step and the at least one barrier gas inlet channel and the at least one integrated discharge channel are configured to make The test area is isolated from the enclosed environment. The method of claim 9, wherein the etchant gas includes halogen. The method of claim 9, wherein supplying the etchant gas comprises flowing the etchant gas from a pressure bottle to the nozzle, wherein a pressure of the etchant gas in the pressure bottle is higher than atmospheric pressure. The method of claim 11, wherein the pressure of the etchant gas in the pressure bottle is higher than 2000 Torr.

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