TWI699442B - Film forming method, manufacturing method of thin film transistor, and thin film transistor - Google Patents

Abstract

The present invention is a film forming method that uses plasma P to sputter a target material T containing an oxide semiconductor material to form an oxide semiconductor layer on a substrate W, independent of the antenna used to generate plasma P The high frequency power supplied by 50 controls the target bias voltage applied to the target T to a negative voltage of -1 kV or more, and the volume fraction contained in the vacuum vessel 20 where the plasma P is generated is 5 vol% or more. , Sputtering gas 90 for oxygen below 100 vol%.

Description

Film forming method, manufacturing method of thin film transistor, and thin film transistor

The present invention relates to a method for forming a film on a substrate by sputtering a target using plasma, a method for manufacturing a thin film transistor including the method for forming the film, and a thin film transistor manufactured by the method .

As such a sputtering device, a magnetron sputtering device is known. As shown in Patent Document 1, the magnetron sputtering device is configured to form a magnetic field on the surface of the target material by a magnet provided on the back surface of the target material to generate plasma, and make ions in the plasma collide with the target material. As a result, the sputtered particles fly out from the target.

Regarding the specific film formation method, a negative bias voltage is applied to the target holder holding the target to generate plasma between the target and the substrate, and the bias voltage causes the cations in the plasma to collide with the target , Thereby accumulating the sputtered particles generated on the substrate.

However, when the cations in the plasma collide with the target material by the bias voltage used to generate the plasma, the energy of the cations will become too large. When the oxide semiconductor material is used as the target material, the metal elements and oxygen The bond is cut.

As a result, the sputtered particles from which oxygen is detached from the metal oxide are formed into a film, and the oxygen in the film is insufficient, resulting in a decrease in crystallinity.

[Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2016-180178

Therefore, the present invention was made to solve the above-mentioned problems, and its main subject is to form an oxide semiconductor layer with high crystallinity.

That is, the film forming method of the present invention is a method of forming an oxide semiconductor layer on a substrate by sputtering a target containing an oxide semiconductor material using plasma, and the method is characterized in that: The high-frequency power supplied by the plasma antenna controls the target bias voltage applied to the target so as to be a negative voltage of -1kV or more, and the plasma is supplied to the vacuum container containing the volume fraction It is a sputtering gas of 5 vol% or more and 100 vol% or less oxygen.

With this method of film formation, the target bias voltage is controlled independently of the high-frequency power supplied to the antenna, while maintaining the target bias voltage lower than the previous (for example, -1kV~-2kV), the supply includes The sputtering gas of oxygen having a volume fraction of 5 vol% or more and 100 vol% or less allows film formation while maintaining the oxidation state of the target. Thereby, the generation of sputtered particles from which oxygen is detached can be suppressed, so oxygen deficiency in the film is unlikely to occur, and an oxide semiconductor layer with high crystallinity can be formed.

Furthermore, the following effects can also be achieved.

That is, in the case of using a magnetron sputtering device, the plasma generated near the surface of the target material is coarse, and the target material surface is corroded. As a result, due to the erosion The scattering direction and energy of the sputtered particles become non-uniform, resulting in a decrease in the crystallinity of the formed oxide semiconductor layer.

In contrast, according to the present invention, an antenna is used to generate plasma for sputtering. Therefore, it is easy to uniformly generate plasma in the vacuum container, and corrosion can be suppressed. Thereby, the scattering direction and energy of sputtered particles can be made uniform, and an oxide semiconductor layer with high crystallinity can be obtained.

If the target bias voltage is too high, the oxidation state of the target cannot be maintained. On the other hand, if the target bias voltage is too low, the film formation speed will decrease. Therefore, in order to ensure the film formation speed and obtain an oxide semiconductor with high crystallinity For the layer, it is preferable to set the target bias voltage to -400V or more and -100V or less.

However, in order to cope with the increase in the size of the substrate in recent years, if the antenna is extended, the impedance of the antenna increases, thereby generating a large potential difference between the two ends of the antenna. As a result, under the influence of the large potential difference, the uniformity of the plasma such as the density distribution, potential distribution, and electron temperature distribution of the plasma deteriorates, and the distribution of sputtered particles coming out of the target material has shades, and the resulting film Thickness will become uneven.

Therefore, it is preferable that: the antenna has a flow path for the cooling liquid inside, and includes at least two tubular conductor units; the conductor units are arranged between the conductor units adjacent to each other. An insulated tubular insulating unit; and a capacitive element arranged in the flow path and electrically connected in series with the conductor units adjacent to each other; and the capacitive element includes one of the conductor units adjacent to each other A first electrode that is sexually connected; a second electrode that is electrically connected to the other of the conductor units that are adjacent to each other and is arranged opposite to the first electrode; and a charge A dielectric body that fills the space between the first electrode and the second electrode; and the coolant is used as the dielectric body.

If this kind of antenna is used, capacitive elements are electrically connected in series to adjacent conductor elements through insulating elements. Therefore, in simple terms, the combined reactance of the antenna becomes the form of self-inductive reactance minus capacitive reactance, which can reduce the antenna’s impedance. As a result, even in the case of extending the antenna, the increase in impedance can be suppressed, and high-frequency current can easily flow in the antenna, and plasma can be efficiently generated. Thereby, the density of plasma can be increased, and the film forming speed can also be increased.

In particular, according to the present invention, the space between the first electrode and the second electrode is filled with a coolant to form the dielectric body, and therefore the gap generated between the electrode and the dielectric body constituting the capacitor element can be eliminated. As a result, the uniformity of plasma can be improved, and the uniformity of film formation can be improved. In addition, by using the cooling liquid as the dielectric, it is not necessary to prepare a dielectric of a liquid different from the cooling liquid, and the first electrode and the second electrode can be cooled. Generally, the cooling liquid is adjusted to a certain temperature by a temperature adjustment mechanism. By using the cooling liquid as a dielectric, the change in the dielectric constant caused by the temperature change can be suppressed and the change in the capacitance value can be suppressed, thereby, It can also improve the uniformity of plasma. Furthermore, when water is used as the coolant, since the dielectric constant of water is about 80 (20° C.) and greater than the resin-made dielectric sheet, a capacitor element capable of withstanding high voltage can be constructed.

In addition, the arc discharge generated in the gap between the electrode and the dielectric body can be eliminated, and the damage of the capacitor element caused by the arc discharge can be eliminated. In addition, the distance between the first electrode and the second electrode, the facing area, and the capacitance value can be accurately set according to the dielectric constant of the coolant without considering the gap. Advance However, a structure for pressing the electrode and dielectric for filling the gap may not be required, and the complexity of the structure around the antenna caused by the pressing structure and the uniformity of the plasma generated thereby can be prevented. The deterioration.

Furthermore, the present invention is a method for manufacturing a thin film transistor, which is manufactured on a substrate including a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode thin film transistor, and the thin film transistor The method of manufacturing a crystal is characterized by including a semiconductor layer forming step of forming the oxide semiconductor layer on the gate insulating layer by sputtering a target using plasma, and the semiconductor layer forming step includes: In the film forming step, sputtering is performed by supplying a sputtering gas containing oxygen with a volume fraction of 2 vol% or less (including 0 vol%); and a second film forming step in which after the first film forming step, a gas containing volume is supplied Sputtering is carried out with a sputtering gas with an oxygen fraction of 5 vol% or more and 100 vol% or less; and the target applied to the target is controlled independently of the high-frequency power supplied to the antenna for generating the plasma The material bias voltage is set to a negative voltage of -1 kV or more.

In this manufacturing method, in the second film forming step, the target bias voltage is controlled independently of the high-frequency power supplied to the antenna, while keeping the target bias voltage lower than the previous (for example, -1kV~ -2kV), while supplying a sputtering gas containing oxygen with a volume fraction of 5 vol% or more and 100 vol% or less, the film can be formed while maintaining the oxidation state of the target. This suppresses the generation of sputtered particles from which oxygen detaches. Therefore, it is possible to manufacture a thin film transistor with an oxide semiconductor layer that lacks oxygen in the film and has high crystallinity and has a high gate threshold voltage. That is, in a state where the gate voltage is zero, the carriers generated in the channel layer can be reduced, and even if it is not applied The increased negative voltage is used as the gate voltage, and thin film transistors can also be manufactured in an interrupted state.

In the method of manufacturing the thin film transistor, it is preferable that in the second film forming step, a sputtering gas containing oxygen with a volume fraction of 20 vol% or more and 100 vol% or less is supplied for sputtering, and more preferably is supplied Sputtering is performed with a gas for sputtering containing oxygen with a volume fraction of 50 vol% or more and 100 vol% or less.

In the second film forming step, the volume fraction of oxygen in the supplied sputtering gas is increased, thereby further reducing oxygen deficiency at the interface of the oxide semiconductor layer, thereby providing a greater threshold voltage for the gate electrode Thin film transistors.

In addition, the present invention includes a thin film transistor obtained by the method of manufacturing the thin film transistor. Specifically, it includes a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode are sequentially arranged on a substrate, and the oxide semiconductor layer is from the substrate side It includes in this order: a first semiconductor layer including an amorphous oxide semiconductor film; and a second semiconductor layer including a crystalline oxide semiconductor film.

If it is such a thin film transistor, a crystalline second semiconductor layer is provided on the amorphous first semiconductor layer. Therefore, oxygen deficiency at the interface of the oxide semiconductor layer can be reduced, and the thin film transistor can be increased. Gate threshold voltage. That is, in a state where the gate voltage is zero, the carriers generated in the channel layer can be reduced, and even if a large negative voltage is not applied as the gate voltage, the thin film transistor can be set to a blocking state.

In the thin film transistor, the oxide semiconductor films constituting the first semiconductor layer and the second semiconductor layer both contain an oxide containing In as a main component, and the second semiconductor layer uses Cu-Kα X-ray diffraction measurement based on θ-2θ method In the setting, the half-height width of the wave peak confirmed near the diffraction angle 2θ=31° is preferably 4.5° or less, more preferably 3.0° or less, and particularly preferably 2.5° or less.

In the case where the oxide semiconductor layer contains In-Ga-Zn-O (IGZO) and other oxides containing In as the main component, the degree of crystallinity can be based on the use of Cu light source (Cu-Kα rays) of θ- In the X-Ray Diffraction (XRD) measurement of the 2θ method, the half-height width of the peak that can be confirmed in the vicinity of 2θ=31° is evaluated. Specifically, the smaller the half-height width of the peak, the higher the crystallinity of the oxide semiconductor layer can be evaluated. The smaller the half-width, the higher the crystallinity of the second semiconductor layer, and the larger the gate threshold voltage of the thin film transistor.

In the thin film transistor, the thickness of the second semiconductor layer is preferably 6 nm or less, more preferably 2 nm or less.

By reducing the film thickness of the second semiconductor layer, the resistance in the stacking direction of the oxide semiconductor layer can be further reduced. Thereby, the mobility of electrons in the stacking direction can be increased, and the drain current flowing through the thin film transistor can be further increased.

According to the present invention configured as described above, an oxide semiconductor layer with high crystallinity can be formed.

1: Thin film transistor

2: substrate

3: Gate electrode

4: Gate insulation layer

5: oxide semiconductor layer

5a: The first semiconductor layer (oxide semiconductor film)

5b: Second semiconductor layer (oxide semiconductor film)

6: Source electrode

7: Drain electrode

10: Insulation part

11: Target bias power supply

12: Insulating member

13: Insulating cover

14: Circulating flow path

15: Ring multi-face contact

16: sealing member

20: Vacuum container

20a: side wall (upper side wall)

20b, 20c: side wall

21: Gas inlet

30: Board holding part

40: Target holding part

50: Antenna

50a: Power supply end

50b: Terminal

51: Conductor unit (metal tube)

51a: External thread

51A: The first metal tube

51B: The second metal tube

51x, 52x: flow path

52: Insulation unit (insulation tube)

52a: Internal thread

52b: recess

53: Capacitive element (capacitor)

53A: Electrode (first electrode)

53B: Electrode (2nd electrode)

53x: Mainstream road

60: high frequency power supply

61: matching circuit

70: Vacuum exhaust device

80: Gas supply mechanism for sputtering

90: Sputtering gas

100: Sputtering device

141: Temperature adjustment mechanism

142: Circulation Mechanism

511: Contact

531: Flange

531h: Through hole

532: Extension

CL: Coolant

IR: high frequency current

P: Plasma

T: target

W: substrate

FIG. 1 is a diagram schematically showing the structure of the thin film transistor of this embodiment.

2(a) to 2(e) are diagrams schematically showing the manufacturing steps of the thin film transistor of the present embodiment.

Fig. 3 is a longitudinal cross-sectional view schematically showing the configuration of the sputtering apparatus of the present embodiment, perpendicular to the longitudinal direction of the antenna.

4 is a longitudinal cross-sectional view along the longitudinal direction of the antenna schematically showing the structure of the sputtering apparatus of this embodiment.

Fig. 5 is a partially enlarged cross-sectional view showing a capacitor portion in the antenna of this embodiment.

Fig. 6 is a graph showing the results of X-ray diffraction of an IGZO film formed by the sputtering apparatus of this embodiment.

FIG. 7 is a graph showing the drain current I _d -gate voltage V _g characteristics of the thin film transistor manufactured using the sputtering apparatus of this embodiment.

8 is a graph showing the relationship between the volume fraction of oxygen in the sputtering gas and the gate threshold voltage V _th in the second film formation step.

FIG. 9 is a graph showing the drain current I _d -gate voltage V _g characteristics of the thin film transistor manufactured using the sputtering apparatus of this embodiment.

FIG. 10 is a graph showing the results of X-ray diffraction of an IGZO film formed by the sputtering apparatus of this embodiment.

FIG. 11 is a graph showing the relationship between the crystallinity of the IGZO film and the gate threshold voltage V _th of the thin film transistor.

Hereinafter, the thin film transistor 1 and its manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.

<1. Thin Film Transistor>

The thin film transistor 1 of this embodiment is a so-called bottom gate type thin film transistor. Specifically, as shown in FIG. 1, it has a substrate 2, a gate electrode 3, a gate insulating layer 4, an oxide semiconductor layer 5, a source electrode 6 and a drain electrode 7, and they are arranged in order from the substrate 2 side ( form).

The substrate 2 includes a light-transmissive material, such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES). , Acrylic, polyimide and other plastics (synthetic resins) or glass.

A gate electrode 3 is provided on the surface of the substrate 2. The gate electrode 3 includes a material with high conductivity, and may include, for example, one or more metals selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, and the like. In addition, it may also contain Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and In-Ga-Zn-O (IGZO) and other metal oxide conductive films. The gate electrode 3 may also include a single-layer structure of these conductive films or a multilayer structure of two or more layers.

A gate insulating layer 4 is arranged on the gate electrode 3. The gate insulating layer 4 includes a material with high insulation, for example, it may include one or more selected from SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , Hf _2, etc. Oxide insulating film. The gate insulating layer 4 may be a single-layer structure or a laminated structure of two or more layers of these insulating films.

An oxide semiconductor layer 5 is arranged on the gate insulating layer 4. The oxide semiconductor layer 5 is formed from the substrate 2 side, and the first semiconductor layer 5a and the second semiconductor layer 5a and the second semiconductor layer are arranged in this order. The two-layer structure of the body layer 5b. The first semiconductor layer 5a and the second semiconductor layer 5b both include an oxide semiconductor layer mainly composed of an oxide containing In. For example, it is preferable to include In-Ga-Zn-O, In-Al-Mg-O, In-Al-Zn-O or In-Hf-Zn-O, etc. The first semiconductor layer 5a is a layer including an amorphous (amorphous) oxide semiconductor film, and the second semiconductor layer 5b is a layer including a crystalline oxide semiconductor film.

(The crystallinity of the second semiconductor layer 5b)

The higher the crystallinity of the second semiconductor layer 5b, the less oxygen deficiency in the interface, and the threshold voltage V _{th of the} thin film transistor 1 (drain current I _d =1 nA gate voltage V _g ) the greater. Therefore, the crystallinity of the second semiconductor layer 5b is preferably high. Regarding the height of the crystallinity of the second semiconductor layer 5b, when the second semiconductor layer 5b is an oxide semiconductor film containing In-Ga-Zn-O (IGZO), it can be used according to the use of a Cu light source (Cu-Kα In the X-ray diffraction (XRD) measurement of the θ-2θ method of radiation), evaluation is made by the size of the half-width of the peak that can be confirmed in the vicinity of 2θ=31°. Specifically, the smaller the half-height width of the peak, the higher the crystallinity of the second semiconductor layer 5b can be evaluated. From the viewpoint of increasing the gate threshold voltage V _th of the thin film transistor 1, the second semiconductor layer 5b is measured at 2θ=31° (for example, 30°~32°) in the measurement using X-ray diffraction (XRD). °) The full width at half maximum of the confirmable peak is preferably 4.5° or less, more preferably 3.0° or less, and particularly preferably 2.5° or less.

Furthermore, in the case where the first semiconductor layer 5a is an oxide semiconductor film containing In-Ga-Zn-O (IGZO), the measurement using X-ray diffraction (XRD) can be used in the 2θ =31° and no peaks appear to confirm that the first semiconductor layer 5a is an amorphous oxide semiconductor film.

(The film thickness of the second semiconductor layer 5b)

If the crystallinity of the second semiconductor layer 5b becomes higher, the resistance in the stacking direction of the second semiconductor layer 5b becomes larger and the drain current I _{d may} decrease. Therefore, the film thickness of the second semiconductor layer 5b should be as small as possible. Thereby, the resistance value in the stacking direction of the second semiconductor layer 5b can be reduced, and the decrease in the drain current I _d can be suppressed. The film thickness of the second semiconductor layer 5b is preferably smaller than the film thickness of the first semiconductor layer 5a. Specifically, the film thickness of the second semiconductor layer 5b is preferably 6 nm or less, more preferably 2 nm or less, and ideally, the thickness corresponding to one atom is most preferable.

In addition, the film thickness of the 1st semiconductor layer 5a and the 2nd semiconductor layer 5b can be measured using a step meter or an ellipsometer.

A source electrode 6 and a drain electrode 7 are arranged on the oxide semiconductor layer 5. The source electrode 6 and the drain electrode 7 each include a material having high conductivity so as to function as electrodes. Specifically, the same material as the gate electrode 3 may also be included.

A protective film for protecting the oxide semiconductor layer 5, the source electrode 6 and the drain electrode 7 may be disposed. The protective film may include, for example, a silicon oxide film (SiO ₂ ), a fluorinated silicon nitride film (SiN:F) containing fluorine in the silicon nitride film, and the like.

<2. Method of manufacturing thin film transistors>

Next, a method of manufacturing the thin film transistor 1 of the structure will be described with reference to FIGS. 2(a) to 2(e). The method of manufacturing the thin film transistor 1 of this embodiment includes a gate electrode forming step, a gate insulating layer forming step, a semiconductor layer forming step, a source/drain electrode forming step, and a heat treatment step. Hereinafter, each step will be described.

(1) Gate electrode formation steps

First, as shown in FIG. 2(a), for example, a substrate 2 containing quartz glass is prepared, and a gate electrode 3 is formed on the surface of the substrate 2. The method of forming the gate electrode 3 is not particularly limited. For example, it can be formed by a known method such as a vacuum evaporation method and a direct current (DC) sputtering method.

(2) Steps for forming gate insulating layer

Then, as shown in FIG. 2( b ), the gate insulating layer 4 is formed so as to cover the surfaces of the substrate 2 and the gate electrode 3. The method of forming the gate insulating layer 4 is not particularly limited, and it can be formed by a known method.

(3) Semiconductor layer formation steps

Then, as shown in FIGS. 2(c) and 2(d), an oxide semiconductor layer 5 as a channel layer is formed on the gate insulating layer 4. The semiconductor layer forming step includes a first film forming step of forming the first semiconductor layer 5a and a second film forming step of forming the second semiconductor layer 5b.

Furthermore, in the semiconductor layer formation step of this embodiment, a sputtering device 100 as shown in FIG. 3 can be used. The sputtering device 100 is performed by sputtering the target T using an inductively coupled plasma P Film formation. The sputtering apparatus 100 includes: a vacuum vessel 20; a substrate holding portion 30 that holds the substrate 2 in the vacuum vessel 20; a target holding portion 40 that faces the substrate 2 in the vacuum vessel 20 and holds the target material T; and The plurality of antennas 50 are arranged along the surface of the substrate 2 held by the substrate holding portion 30, and plasma P is generated. By using the sputtering apparatus 100, the high-frequency voltage supplied to the antenna 50 and the bias voltage of the target T can be set independently. Therefore, the bias voltage can be set to a low voltage to the extent that independently of the generation of plasma P, the ion in the plasma The degree to which the ion is introduced into the target and sputtered, and the negative bias voltage applied to the target T during sputtering can be set to a negative voltage of -1 kV or more (that is, an absolute value of 1 kV or less). The first film forming step and the second film forming step are performed by arranging the target T in the target holding portion 40 and arranging the substrate 2 in the substrate holding portion 30. Here, as the target material T, a conductive oxide sintered body such as InGaZnO used as a raw material of the oxide semiconductor layer 5 can be used.

(3-1) The first film forming step

First, the first semiconductor layer 5a is formed on the gate insulating layer 4. Specifically, after evacuating the vacuum container 20 of the sputtering device 100 to 3×10 ^-6 Torr or less, while introducing the sputtering gas at 50 sccm or more and 200 sccm or less, the pressure in the vacuum container 20 is adjusted to 0.5 Pa or more and 3.1Pa or less. Then, high-frequency power of 1 kW or more and 10 kW or less is supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma. A DC voltage pulse is applied to the target material to sputter the target material. Thereby, as shown in FIG. 2(c), the first semiconductor layer 5a is formed on the gate insulating layer 4. In addition, the pressure in the vacuum container 20 and the flow rate of the sputtering gas can also be appropriately changed.

Here, it is preferable to set the voltage applied to the target T to a negative voltage of -1 kV or more. Thereby, the generation of sputtered particles from which oxygen is detached can be suppressed, and the oxide semiconductor film 5a lacking oxygen in the film can be formed. From the viewpoint of forming the oxide semiconductor film 5a with less oxygen deficiency, it is more preferable to set the voltage applied to the target T to a negative voltage of -400V or more.

Here, the lower the oxygen concentration contained in the sputtering gas supplied in the first film forming step, the higher the density of the plasma generated near the surface of the target T can be. In addition, the film formation speed of the first semiconductor layer 5a can be increased. Therefore, it is preferable that the volume fraction of oxygen contained in the sputtering gas supplied in the first film forming step is 2 vol% or less, and it is more preferable that the volume fraction of argon gas contained is 99.99 vol% or more. By. It is best to supply only argon gas (that is, the volume fraction is 99.999 vol% or more) as the sputtering gas.

(Second film forming step)

After the first film forming step, the second semiconductor layer 5b is formed on the first semiconductor layer 5a. Specifically, the sputtering of the target material T is performed using the sputtering apparatus 100 in the same manner as in the first film forming step, thereby forming the second semiconductor layer 5b. Conditions such as the pressure in the vacuum vessel 20 and the flow rate of the sputtering gas in the second film forming step may be the same as the press sputtering step and the first film forming step, and may be changed as appropriate.

In the second film forming step, the voltage applied to the target T is set to a negative voltage of -1 kV or more (the absolute value is 1 kV or less), and a sputtering gas containing oxygen having a volume fraction of 5 vol% or more is supplied. Thereby, the generation of sputtered particles from which oxygen is detached can be suppressed, and the film can be formed while the oxidation state of the target material is maintained in a good state. Therefore, oxygen deficiency in the film is unlikely to occur, and a highly crystalline ( That is, the crystalline) oxide semiconductor film 5b can produce a thin film transistor 1 having a high gate threshold voltage _Vth .

From the viewpoint of forming the oxide semiconductor film 5b with higher crystallinity, it is preferable to set the voltage applied to the target T to a negative voltage of -400V or more. On the other hand, if the absolute value of the voltage is too small, the film formation speed will decrease. Therefore, it is preferable to set the voltage applied to the target T to a negative voltage of -100V or less.

In addition, from the viewpoint of forming the oxide semiconductor film 5b with higher crystallinity In other words, the sputtering gas to be supplied preferably contains 20 vol% or more of oxygen in volume fraction, and more preferably contains 50 vol% or more of oxygen. It is best to supply only oxygen (that is, the volume fraction is 99.999 vol% or more) as the sputtering gas.

From the viewpoint of manufacturing the thin film transistor 1 that reduces the resistance in the stacking direction of the second semiconductor layer 5b and suppresses the decrease in the drain current I _d , in the second film forming step, it is preferable to form a thin film transistor 1 having a thickness smaller than that of the first semiconductor layer. The film thickness of the layer 5a is a film thickness of the second semiconductor layer 5b. It is preferable to form the second semiconductor layer 5b having a film thickness of 6 nm or less, and it is more preferable to form the second semiconductor layer 5b having a film thickness of 2 nm or less. Ideally, it is most preferable to form the second semiconductor layer 5b having a thickness corresponding to one atom. 2 Semiconductor layer 5b. In the second film forming step, the film thickness of the second semiconductor layer 5b can be adjusted by changing any of the film forming time, the amount of high-frequency power of the antenna, and the DC voltage of the target, for example.

(4) Source/drain electrode formation steps

Then, as shown in FIG. 2(e), a source electrode 6 and a drain electrode 7 are formed on the oxide semiconductor layer 5. The source electrode 6 and the drain electrode 7 can be formed, for example, by using a known method such as radio frequency (RF) magnetron sputtering.

(5) Heat treatment steps

Finally, the heat treatment may also be performed in an atmosphere under atmospheric pressure containing oxygen. The temperature in the furnace in the heat treatment is not particularly limited, and is, for example, 150°C or higher and 300°C or lower. In addition, the heat treatment time is not particularly limited, and is, for example, 1 hour or more and 3 hours or less. Furthermore, in this embodiment, the heat treatment step is not an essential step, and the heat treatment step may be omitted.

As described above, the thin film transistor 1 of this embodiment can be obtained.

<3. Sputtering device>

The sputtering apparatus 100 of this embodiment uses an inductively coupled plasma P to sputter a target material T to form a film on a substrate W. Here, the substrate W is, for example, a substrate for a flat panel display (FPD) such as a liquid crystal display or an organic electroluminescence (Electroluminescence, EL) display, a flexible substrate for a flexible display, and the like.

Specifically, as shown in FIGS. 3 and 4, the sputtering apparatus 100 includes: a vacuum vessel 20 for performing vacuum exhaust and introducing gas; a substrate holding portion 30 for holding the substrate W in the vacuum vessel 20; and target holding The part 40 holds the target material T in the vacuum container 20; the multiple antennas 50 are arranged in the vacuum container 20 and are linear; and the high-frequency power supply 60 is applied to the multiple antennas 50 to be used in the vacuum container 20 The high frequency of inductively coupled plasma P is generated. Furthermore, the high frequency power supply 60 applies high frequency to the plurality of antennas 50, whereby the high frequency current IR flows through the plurality of antennas 50, and an induced electric field is generated in the vacuum container 20 to generate inductive coupling type plasma P.

The vacuum container 20 is, for example, a metal container, and the inside thereof is evacuated by a vacuum exhaust device 70. In this example, the vacuum container 20 is electrically grounded.

For example, the sputtering gas 90 is introduced into the vacuum container 20 via the sputtering gas supply mechanism 80 having a flow rate regulator (not shown) and the like and the gas introduction port 21. Specifically, the sputtering gas supply mechanism 80 is a supply mechanism that supplies a mixed gas of an inert gas such as argon (Ar) and oxygen, or only oxygen as a sputtering gas.

The substrate holding portion 30 is, for example, a plate-shaped substrate in the vacuum container 20 The plate W is held as a holder in a horizontal state. In this example, the holder is electrically grounded. Furthermore, a heater (not shown) that heats the substrate W may be installed in the holder.

The target holding section 40 faces the substrate W held by the substrate holding section 30 and holds the target T. The target material T of this embodiment has a rectangular flat plate shape in plan view, and is, for example, an oxide semiconductor material such as InGaZnO. The target holding portion 40 is provided on a side wall 20 a (for example, an upper side wall) forming the vacuum container 20. In addition, an insulating portion 10 having a vacuum sealing function is provided between the target holding portion 40 and the upper side wall 20 a of the vacuum container 20. In this example, the target bias power supply 11 that applies the target bias voltage to the target T is connected to the target T via the target holding portion 40. The target bias power supply 11 is a DC power supply, a DC pulse power supply, an AC power supply, or a combination of these power supplies.

The target bias voltage is a voltage at which ions (Ar ⁺ ) in the plasma P are introduced into the target T and sputtered. The target bias voltage of the present embodiment is a negative voltage of -1 kV or more, more preferably -400V or more and -100V or less. The reason is: if the target bias voltage is lower than -400V, the energy of the ions that collide with the target is too large to cut off the bond between the target metal element and oxygen. On the other hand, if the target bias voltage is higher than -100V , Then the film formation speed is reduced.

In this embodiment, a plurality of target holding parts 40 are provided. The plurality of target holding parts 40 are arranged on the surface side of the substrate W in the vacuum container 20 in parallel along the surface of the substrate W (for example, substantially parallel to the back surface of the substrate W) on the same plane. The plurality of target holding parts 40 are arranged at equal intervals so that their longitudinal directions are parallel to each other. Thereby, as shown in FIG. 3, the multiple targets T arranged in the vacuum vessel 20 It is arranged substantially parallel to the surface of the substrate W and arranged at equal intervals so that the longitudinal directions are parallel to each other. In addition, each target holding part 40 has the same structure.

The plurality of antennas 50 are arranged in parallel on the same plane on the surface side of the substrate W in the vacuum container 20 along the surface of the substrate W (for example, substantially parallel to the surface of the substrate W). The plurality of antennas 50 are arranged at equal intervals so that their longitudinal directions are parallel to each other. In addition, the antennas 50 are linear and have the same structure when viewed in plan, and their length is several tens of cm or more.

As shown in FIG. 3, the antenna 50 of this embodiment is arrange|positioned on both sides of the target material T held by each target holding part 40, respectively. That is, the configuration is such that the antenna 50 and the target material T are alternately arranged, and one target material T is sandwiched by two antennas 50. Here, the longitudinal direction of each antenna 50 and the longitudinal direction of the target material T held by each target holding section 40 are the same direction.

In addition, the material of each antenna 50 is, for example, copper, aluminum, these alloys, stainless steel, etc., but it is not limited thereto. Furthermore, the antenna 50 may be hollow, and a coolant such as cooling water may flow therein to cool the antenna 50.

Furthermore, as shown in FIG. 4, the vicinity of both ends of the antenna 50 penetrates the opposing side walls 20b and 20c of the vacuum container 20, respectively. Insulating members 12 are respectively provided in the portions where both ends of the antenna 50 penetrate to the outside of the vacuum container 20. Both ends of the antenna 50 penetrate the insulating members 12, and the penetration portions thereof are vacuum sealed by, for example, gaskets. Between each insulating member 12 and the vacuum container 20, it is also vacuum sealed by a gasket, for example. Furthermore, the material of the insulating member 12 is, for example, ceramics such as alumina; quartz; or polyphenylene sulfide (PPS) or polyether ether ketone. (Polyetheretherketone, PEEK) and other engineering plastics.

Furthermore, in each antenna 50, the part located in the vacuum container 20 is covered with the straight tube-shaped insulating cover 13 made of an insulator. The two ends of the insulating cover 13 and the vacuum container 20 may not be sealed. The reason is that even if the sputtering gas 90 enters the space in the insulating cover 13, since the space is small and the moving distance of electrons is short, the plasma P is usually not generated in the space. Furthermore, the material of the insulating cover 13 is, for example, quartz, alumina, fluororesin, silicon nitride, silicon carbide, silicon, etc., but it is not limited to these.

The high frequency power supply 60 is connected to the power feeding end 50a as one end of the antenna 50 via the matching circuit 61, and the end 50b as the other end is directly grounded. In addition, it may be configured such that an impedance adjustment circuit such as a variable capacitor or a variable reactor is provided at the power feeding end portion 50a or the terminal portion 50b to adjust the impedance of each antenna 50. By adjusting the impedance of each antenna 50 as described above, the density distribution of the plasma P in the longitudinal direction of the antenna 50 can be made uniform, and the film thickness in the longitudinal direction of the antenna 50 can be made uniform.

With this configuration, the high-frequency current IR can flow from the high-frequency power source 60 to the antenna 50 via the matching circuit 61. The frequency of the high frequency is usually 13.56 MHz, for example, but it is not limited to this.

Then, the antenna 50 of the present embodiment has a hollow structure inside which has a flow path through which the cooling liquid CL flows. Specifically, as shown in FIG. 5, the antenna 50 includes: at least two tubular metal conductor units 51 (hereinafter referred to as "metal pipes 51"); and are provided between adjacent metal pipes 51. A tubular insulating unit 52 (hereinafter, referred to as an "insulating pipe 52") insulated from the metal pipes 51; and a capacitor 53 as a capacitive element electrically connected in series with the metal pipes 51 adjacent to each other.

In this embodiment, the number of metal tubes 51 is two, and the number of insulating tubes 52 and capacitors 53 is one each. In the following description, one metal pipe 51 is also referred to as "first metal pipe 51A", and the other metal pipe is referred to as "second metal pipe 51B". Furthermore, the antenna 50 may also have a configuration with three or more metal tubes 51. In this case, the number of insulating tubes 52 and capacitors 53 is one less than the number of metal tubes 51.

Furthermore, the cooling liquid CL circulates through the antenna 50 through the circulation flow path 14 provided outside the vacuum container 20, and a heat exchanger or the like is provided in the circulation flow path 14 to adjust the cooling liquid CL to a constant temperature. A circulation mechanism 142 such as a temperature adjustment mechanism 141 and a pump for circulating the cooling liquid CL in the circulation flow path 14. As the coolant CL, from the viewpoint of electrical insulation, water with high electrical resistance is preferable, for example, pure water or water close to it is preferable. In addition, for example, a liquid coolant other than water such as a fluorine-based inert liquid may also be used.

The metal pipe 51 is a straight pipe in which a linear flow path 51x through which the cooling liquid CL flows is formed. In addition, a male screw portion 51 a is formed on the outer peripheral portion of at least one end portion in the longitudinal direction of the metal pipe 51. Regarding the metal pipe 51 of this embodiment, the end on which the male threaded portion 51a is formed and other members are formed by other parts and joined to these members, but it may be formed by a single member. In addition, in order to realize commonality with the components of the structure connecting the plurality of metal pipes 51, it is desirable to form male screw portions 51a in advance on both ends of the metal pipe 51 in the longitudinal direction to maintain compatibility. The material of the metal pipe 51 is, for example, copper, aluminum, these alloys, and stainless steel.

The insulating tube 52 is a straight tube in which a linear flow path 52x through which the cooling liquid CL flows is formed. And, on the side of both ends of the insulating tube 52 in the axial direction The peripheral wall is formed with an internal thread portion 52 a screwed and connected to the external thread portion 51 a of the metal pipe 51. In addition, on the side peripheral walls of the both ends of the insulating tube 52 in the axial direction and on the central side in the axial direction than the female threaded portion 52a, recesses 52b for fitting the electrodes 53A and 53B of the capacitor 53 are formed over the entire circumferential direction. . The insulating tube 52 of this embodiment is formed of a single member, but it is not limited to this. Furthermore, the material of the insulating tube 52 is, for example, alumina, fluororesin, polyethylene (PE), engineering plastics (for example, polyphenylene sulfide (PPS), polyether ether ketone (PEEK), etc.).

The capacitor 53 is provided inside the insulating tube 52, and specifically, is provided in the flow path 52x of the insulating tube 52 through which the cooling liquid CL flows.

Specifically, the capacitor 53 includes a first electrode 53A electrically connected to one of the metal tubes 51 adjacent to each other (the first metal tube 51A) and the other metal tube 51 (second metal tube 51B) that is adjacent to each other. ) The second electrode 53B which is electrically connected and arranged opposite to the first electrode 53A, and is configured such that the cooling liquid CL fills the space between the first electrode 53A and the second electrode 53B. That is, the cooling liquid CL flowing in the space between the first electrode 53A and the second electrode 53B becomes a dielectric body constituting the capacitor 53.

The electrodes 53A and 53B each have a substantially rotating body shape, and a main flow path 53x is formed in the center along the center axis. Specifically, each of the electrodes 53A and 53B has a flange portion 531 that is in electrical contact with an end portion of the metal tube 51 on the insulating tube 52 side, and an extension portion 532 extending from the flange portion 531 to the insulating tube 52 side. Regarding the electrodes 53A and 53B of this embodiment, the flange portion 531 and the extension portion 532 may be formed by a single member, or may be formed by other parts and joined. electrode The materials of 53A and electrode 53B are, for example, aluminum, copper, these alloys, and the like.

The flange portion 531 is in contact with the end portion of the metal pipe 51 on the insulating pipe 52 side over the entire circumferential direction. Specifically, the axial end surface of the flange portion 531 is in contact with the tip surface of the cylindrical contact portion 511 formed at the end of the metal pipe 51 over the entire circumferential direction, and passes through the contact portion 511 provided on the metal pipe 51. The ring-shaped multi-face contact 15 on the outer periphery of the metal tube 51 is in electrical contact with the end surface of the metal pipe 51. Furthermore, the flange portion 531 may also be in electrical contact with the metal tube 51 through any of these.

In addition, a plurality of through holes 531h are formed in the flange portion 531 in the thickness direction. By providing the through hole 531h in the flange portion 531, the flow path resistance of the coolant CL caused by the flange portion 531 can be reduced, and the stagnation of the coolant CL in the insulating tube 52 and the accumulation of air bubbles in the insulating tube can be prevented. Within 52.

The extension portion 532 has a cylindrical shape, and a main flow passage 53x is formed in the extension portion 532. The extension 532 of the first electrode 53A and the extension 532 of the second electrode 53B are arranged coaxially with each other. That is, it is provided in a state where the extension 532 of the second electrode 53B is inserted into the extension 532 of the first electrode 53A. Thereby, a cylindrical space along the flow path direction is formed between the extension 532 of the first electrode 53A and the extension 532 of the second electrode 53B.

The electrodes 53A and 53B configured as described above are fitted in the recesses 52 b formed on the side peripheral wall of the insulating tube 52. Specifically, the first electrode 53A is fitted into a recess 52 b formed on one end side of the insulating tube 52 in the axial direction, and the second electrode 53B is fitted into a recess 52 b formed on the other end side of the insulating tube 52 in the axial direction. By fitting the electrodes 53A and 53B in the recesses 52h as described above, the first electrode 53A The extension 532 and the extension 532 of the second electrode 53B are arranged coaxially with each other. In addition, the extension 532 of the second electrode 53B relative to the extension 532 of the first electrode 53A is defined by contacting the end surfaces of the flange portions 531 of the electrodes 53A and 53B with the surfaces of the recesses 52b facing the outside in the axial direction. Insert size.

In addition, the electrodes 53A and 53B are fitted into the recesses 52b of the insulating tube 52, and the male screw portion 51a of the metal pipe 51 is screwed with the female screw portion 52a of the insulating pipe 52, thereby contacting the metal pipe 51 The front end surface of the portion 511 is in contact with the flange portion 531 of the electrode 53A and the electrode 53B, so that each electrode 53A and the electrode 53B are sandwiched and fixed between the insulating tube 52 and the metal tube 51. As described above, the antenna 50 of this embodiment has a structure in which the metal tube 51, the insulating tube 52, the first electrode 53A, and the second electrode 53B are coaxially arranged. Furthermore, the connection part of the metal pipe 51 and the insulating pipe 52 has a sealing structure with respect to the vacuum and the cooling liquid CL. The sealing structure of the present embodiment is realized by a sealing member 16 such as a gasket provided at the base end of the male screw portion 51a. Furthermore, a tapered pipe thread structure can also be used.

As described above, the sealing between the metal tube 51 and the insulating tube 52 and the electrical contact between the metal tube 51 and the respective electrodes 53A and 53B can be performed together with the fixing of the external threaded portion 51a and the internal threaded portion 52a, so the assembly work changes It's very simple.

In this configuration, after the cooling liquid CL flows out of the first metal pipe 51A, the cooling liquid CL flows to the second electrode 53B side through the main flow path 53x and the through hole 531h of the first electrode 53A. The coolant CL that has flowed to the second electrode 53B side passes through the main flow path 53x and the through hole 531h of the second electrode 53B and flows to the second metal pipe 51B. At this time, the extension 532 of the first electrode 53A and the extension 532 of the second electrode 53B The cylindrical space between is filled with the cooling liquid CL, and this cooling liquid CL becomes a dielectric material, and the capacitor 53 is comprised.

<Effects of this embodiment>

According to the film forming method of this embodiment, the sputtering gas containing oxygen with a volume fraction of 5 vol% or more and 100 vol% or less is supplied while keeping the magnitude of the target bias voltage lower than before. The film formation is performed while maintaining the oxidation state of the target material. Thereby, the generation of sputtered particles from which oxygen is detached can be suppressed, so oxygen deficiency in the film is unlikely to occur, and an oxide semiconductor layer with high crystallinity can be formed. Furthermore, since the oxide semiconductor layer with high crystallinity can be formed, heating of the substrate W during film formation is not required, and the film can be formed as an inexpensive low-melting film.

In addition, since the antenna is used to generate the plasma for sputtering, it is easy to uniformly generate the plasma in the vacuum container, and corrosion can be suppressed. Thereby, the scattering direction and energy of sputtered particles can be made uniform, and an oxide semiconductor layer with high crystallinity can be obtained.

Furthermore, since it is easy to uniformly generate plasma in the vacuum container, compared with a magnetron sputtering device, the target material T can be consumed in the same manner, and the use efficiency of the target material T can be improved. In addition, in the present embodiment, it is a configuration that does not have a DC magnetic field near the surface of the target material, and it is easy to apply to magnetic materials.

Furthermore, the capacitor 53 is electrically connected in series to the metal pipes 51 adjacent to each other through the insulating pipe 52. Therefore, in simple terms, the combined reactance of the antenna 50 becomes the form of the self-inductive reactance minus the capacitive reactance, which can reduce the antenna 50 impedance. As a result, even when the antenna 50 is extended, the increase in its impedance can be suppressed, and the high-frequency electrical The current easily flows in the antenna 50, and the plasma P can be generated efficiently. Thereby, the density of the plasma P can be increased, and the film formation speed can also be increased.

In particular, according to the present embodiment, the space between the first electrode 53A and the second electrode 53B is filled with the coolant CL to form a dielectric body, so it can be eliminated between the electrode 53A, the electrode 53B and the dielectric body constituting the capacitor 53 The resulting gap. As a result, the uniformity of plasma P can be improved, and the uniformity of film formation can be improved. In addition, by using the cooling liquid CL as the dielectric body, it is not necessary to prepare a dielectric body of a liquid different from the cooling liquid CL, and the first electrode 53A and the second electrode 53B can be cooled. The coolant CL is adjusted to a constant temperature by the temperature adjustment mechanism. By using the coolant CL as a dielectric, the change in the dielectric constant caused by the temperature change can be suppressed and the change in the capacitance value can be suppressed, thereby, The uniformity of plasma P can also be improved. Furthermore, when water is used as the cooling liquid CL, since the dielectric constant of water is about 80 (20° C.) and greater than the resin-made dielectric sheet, the capacitor 53 that can withstand high voltage can be constructed.

In addition, the arc discharge that can be generated in the gap between the electrode 53A, the electrode 53B and the dielectric body can be eliminated, and the damage of the capacitor 53 caused by the arc discharge can be eliminated. In addition, the distance between the first electrode 53A and the second electrode 53B, the facing area, and the capacitance value can be accurately set based on the dielectric constant of the coolant CL without considering the gap. Furthermore, there is no need to press the electrode 53A, the electrode 53B, and the dielectric body for filling the gap, and it is possible to prevent the complexity of the structure around the antenna caused by the pressing structure and the electricity generated thereby. The uniformity of pulp P deteriorates.

<Other Modified Embodiments>

In addition, this invention is not limited to the said embodiment.

For example, in the above-mentioned embodiment, InGaZnO is used as the target T, but for example, an oxide semiconductor material such as InSnO or InWZnO may be used as the target T.

Furthermore, the target material T of a nitride semiconductor material or a boride semiconductor material can also be used. As a film forming method in this case, the following film forming method can be cited: using plasma to sputter a target containing a semiconductor material to form a semiconductor layer on a substrate, and in the method, independent of the pair used to produce the The high-frequency power supplied by the plasma antenna controls the target bias voltage applied to the target so as to be a negative voltage of -1kV or more, and the plasma is supplied to the vacuum container containing the volume fraction Sputtering gas for nitrogen or boron gas at 5 vol% or more and 100 vol% or less.

In the above-mentioned embodiment, the antenna has a linear shape, but it may also have a curved or bent shape. In this case, the metal tube may have a bent or bent shape, and the insulating tube may have a bent or bent shape.

In the electrode of the above-mentioned embodiment, the extension part is cylindrical, and may be another angular cylindrical shape, or may be a flat plate or a curved or bent plate shape.

In the above-mentioned embodiment, the structure has a plurality of target holding parts, but it may be a structure having one target holding part. In this case, it is also desirable to have a configuration with a plurality of antennas, or a configuration with one antenna.

In addition, the present invention is not limited to the above-mentioned embodiment, and of course various modifications can be made without departing from the spirit thereof.

[Example]

Hereinafter, the present invention will be further described in detail with examples. Original hair It is clear that it is not limited by the following embodiments, and can be modified and implemented within a scope suitable for the above and below-mentioned gist, and these are all included in the technical scope of the present invention.

<Example 1: Evaluation of the relationship between the volume fraction of oxygen and crystallinity>

In the sputtering apparatus 100 of this embodiment, the relationship between the volume fraction of oxygen contained in the sputtering gas 90 and the crystallinity of the formed IGZO film was evaluated. Furthermore, the substrate used was a glass substrate, and the target T used was IGZO1114.

After evacuating the vacuum container 20 to 4.0×10 ^-4 Pa or less, a sputtering gas 90 of 100 sccm was introduced at a supply pressure of 0.9 Pa. After that, 7 kW of high-frequency power is supplied to the plurality of antennas 50 to generate/maintain inductively coupled plasma P. Then, a direct-current voltage pulse (-200V, 75 kHz, 95.7% duty) was applied to the target T to sputter the target T to form an IGZO film with a film thickness of 150 nm.

Cu-Kα is used for the IGZO film when the volume fraction of oxygen contained in the sputtering gas 90 is set to 0 vol%, 5 vol%, 20 vol%, 50 vol%, and 100 vol% based on the film forming conditions. The rays are subjected to X-ray diffraction (XRD), and the results are shown in FIG. 6.

The diffraction peak appearing in the spectrum shown in FIG. 6 is derived from In in the IGZO film. The FWHM (Full Width at Half Maximum, FWHM) of the diffraction peak is related to the crystallinity of the crystal structure of the semiconductor layer. When the crystallinity is poor, the FWHM becomes wider, and when the crystallinity is good, the half-width The height and width become narrower.

In view of the foregoing, it can be understood that the higher the volume fraction of oxygen contained in the sputtering gas 90, the higher the crystallinity of the IGZO film. Specifically, in order to obtain For the IGZO film with high crystallinity, the volume fraction of oxygen contained in the sputtering gas 90 is preferably 5 vol% or more, more preferably 50 vol% or more.

<Example 2: Evaluation of the relationship between the volume fraction of oxygen and the gate threshold voltage V _th >

Next, the relationship between the volume fraction of oxygen contained in the sputtering gas and the gate threshold voltage V _th of the thin film transistor was evaluated. Specifically, based on the manufacturing method, three thin-film transistor samples with a bottom gate structure using a low-resistance silicon substrate as a gate electrode were produced. A gate insulating layer containing SiO ₂ is set on the gate electrode of a low-resistance silicon substrate, an oxide semiconductor layer containing an IGZO film (IGZO1114) is set on the gate insulating layer, and a source electrode is set on the oxide semiconductor layer And the drain electrode (Mo: 80nm, Pt: 20nm).

For any sample, the sputtering device 100 was used, the pressure in the vacuum vessel was reduced to 0.9 Pa or less, the high frequency power of 7 kW was supplied to multiple antennas, and the DC pulse voltage of -400 V was applied to the target. The target is sputtered to form an oxide semiconductor layer. Specifically, first, only argon gas (99.999 vol% or more in volume fraction) is supplied as a sputtering gas, and sputtering is performed at room temperature to form the first semiconductor layer 5a (film thickness: 45 nm). Then, a mixed gas of oxygen and argon is supplied as a sputtering gas, and sputtering is performed at room temperature to form the second semiconductor layer 5b (film thickness: 5 nm). Here, regarding the three samples, the volume fraction of oxygen contained in the sputtering gas was set to 5 vol%, 20 vol%, and 50 vol% to form the second semiconductor layer 5b. In addition, the manufacturing conditions not specifically described are equivalent to the conditions described in the manufacturing method. In addition, no heat treatment was performed on any samples.

The drain current-gate voltage characteristics (I _d -V _g characteristics) were measured for the three manufactured samples, and the results are shown in FIG. 7. In addition, the gate threshold voltage V _th (gate voltage V _g under drain current I _d =1 nA) in each sample is shown in FIG. 8. As shown in FIGS. 7 and 8, it can be confirmed that the higher the volume fraction of oxygen in the sputtering gas when the second semiconductor layer 5b is formed, the greater the gate threshold voltage V _{th of the} thin film transistor 1 becomes . It is thought that the reason is that the higher the volume fraction of oxygen in the sputtering gas, the more the film can be formed while maintaining the oxidation state of the target material, and therefore the crystallinity of the second semiconductor layer 5b formed becomes higher. And can reduce the oxygen deficiency in the interface.

<Example 3: Evaluation of the relationship between the film thickness of the second semiconductor layer and the drain current I _d >

Next, the relationship between the film thickness of the second semiconductor layer 5b and the drain current I _d in a thin film transistor having two IGZO films as oxide semiconductor layers was evaluated. Specifically, two thin-film transistor samples with different film thicknesses (5 nm, 1.5 nm) of the second semiconductor layer 5b were produced using the same outline as in the second embodiment. Regarding any sample, the volume fraction of oxygen contained in the sputtering gas was set to 50 vol% to produce the second semiconductor layer 5b. The drain current-gate voltage characteristics (I _d -V _g characteristics) were measured for each of the prepared samples. The results are shown in Fig. 9.

According to FIG. 9, it was confirmed that the smaller the film thickness of the second semiconductor layer 5b, the higher the drain current I _{d can} be made. The reason for this is considered to be that the smaller the film thickness of the second semiconductor layer 5b, the smaller the resistance value in the stacking direction of the oxide semiconductor layer, thereby increasing the mobility of electrons.

<Example 4: Evaluation of the relationship between the crystallinity of the second semiconductor layer and the gate threshold voltage V _th >

Next, the relationship between the crystallinity of the second semiconductor layer 5b and the gate threshold voltage _Vth in the thin film transistor having two IGZO films as the oxide semiconductor layer was evaluated. Specifically, for the second semiconductor layer 5b of the three samples of the thin film transistor produced in the above-mentioned Example 2, X-rays manufactured by Bruker AXS using a Cu light source (Cu-Kα rays) were used. Diffraction device (model: D8 DISCOVER) for X-ray diffraction (XRD). The results are shown in Fig. 10. Calculate the half-height width (FWHM) of the diffraction peaks (derived from the diffraction peaks of In in the IGZO film) appearing in the spectra shown in FIG. 10, and compare the calculated half-height widths with those in Example 2. The relationship between the measured gate threshold voltage V _th of each sample was evaluated. The results are shown in Fig. 11.

According to FIG. 10, it was confirmed that the higher the volume fraction of oxygen in the sputtering gas, the higher the crystallinity of the second semiconductor layer 5b. Also, according to FIG. 11, it was confirmed that the higher the crystallinity of the second semiconductor layer 5b (that is, the smaller the half-height width of the diffraction peak), the higher the gate threshold voltage V _{th of the} thin film transistor becomes. Specifically, it can be seen that the half-height width of the peak that can be confirmed in the vicinity of 2θ=31° is preferably 4.5° or less, more preferably 3.0° or less, and particularly preferably 2.5° or less. It is considered that the reason is that the higher the crystallinity of the second semiconductor layer 5b, the less oxygen deficiency in the interface can be made.

This application claims priority based on Japanese Patent Application No. 2018-052230 whose application date is March 20, 2018, and Japanese Patent Application No. 2018-052230 is accompanied by It is incorporated into this manual by reference.

[Industrial availability]

According to the film forming method of one embodiment of the present invention, an oxide semiconductor layer with high crystallinity can be formed.

Claims (12)

A film forming method is a film forming method of forming an oxide semiconductor layer on a substrate by sputtering a target material containing an oxide semiconductor material using plasma, and The target bias voltage applied to the target is controlled independently of the high-frequency power supplied to the antenna for generating the plasma to be a negative voltage of -1 kV or more, and A sputtering gas containing oxygen with a volume fraction of 5% by volume or more and 100% by volume or less is supplied into the vacuum container where the plasma is generated. The film forming method described in the first item of the scope of patent application, wherein the target bias voltage is set to -400 V or more and -100 V or less. The film forming method described in item 1 or item 2 of the scope of the patent application, wherein the antenna has a flow path for cooling liquid inside, and includes: at least two tube-shaped conductor units; A tubular insulating unit that insulates the adjacent conductor units between the conductor units; and a capacitive element disposed in the flow path and electrically connected in series with the adjacent conductor units; and The capacitive element includes a first electrode electrically connected to one of the conductor units adjacent to each other; electrically connected to the other of the conductor units adjacent to each other, and arranged opposite to the first electrode A second electrode; and a dielectric that fills the space between the first electrode and the second electrode; and The cooling liquid is used as the dielectric body. A method for manufacturing a thin film transistor, which is manufactured on a substrate and includes a thin film transistor including a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode, and The manufacturing method of the thin film transistor includes a semiconductor layer forming step of forming the oxide semiconductor layer on the gate insulating layer by sputtering a target using plasma, The step of forming the semiconductor layer includes: In the first film formation step, sputtering is performed by supplying a sputtering gas containing oxygen with a volume fraction of 2% by volume or less (including 0% by volume); and In the second film forming step, after the first film forming step, sputtering is performed by supplying a sputtering gas containing oxygen with a volume fraction of 5 vol% or more and 100 vol% or less; and The target bias voltage applied to the target is controlled to be a negative voltage of -1 kV or more independently of the high-frequency power supplied to the antenna for generating the plasma. The method for manufacturing a thin-film transistor according to claim 4, wherein in the second film forming step, a sputtering gas containing oxygen with a volume fraction of 20% by volume or more and 100% by volume or less is supplied To sputter. The method for manufacturing a thin-film transistor according to claim 4, wherein in the second film forming step, a sputtering gas containing oxygen with a volume fraction of 50% by volume or more and 100% by volume or less is supplied To sputter. A thin film transistor, which is sequentially arranged with a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode on a substrate, and The oxide semiconductor layer includes in order from the substrate side: A first semiconductor layer including an amorphous oxide semiconductor film; and The second semiconductor layer including a crystalline oxide semiconductor film. The thin-film transistor according to claim 7, wherein the oxide semiconductor films constituting the first semiconductor layer and the second semiconductor layer both contain an oxide containing In as a main component, and In the X-ray diffraction measurement of the second semiconductor layer by the θ-2θ method using Cu-Kα rays, the half-width of the peak confirmed at a diffraction angle of 2θ=31° is 4.5° or less. The thin film transistor according to the eighth item of the scope of patent application, wherein the second semiconductor layer is in the X-ray diffraction measurement by the θ-2θ method using Cu-Kα rays at a diffraction angle of 2θ=31° The full width at half maximum of the confirmed peak is 3.0° or less. The thin film transistor according to the eighth item of the scope of patent application, wherein the second semiconductor layer is in the X-ray diffraction measurement by the θ-2θ method using Cu-Kα rays at a diffraction angle of 2θ=31° The full width at half maximum of the confirmed wave peak is 2.5° or less. The thin film transistor according to any one of items 7 to 10 of the scope of patent application, wherein the film thickness of the second semiconductor layer is 6 nm or less. The thin film transistor according to any one of items 7 to 10 of the scope of patent application, wherein the film thickness of the second semiconductor layer is 2 nm or less.

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