TWI699143B - Printed circuit board and method of fabricating the same - Google Patents

Abstract

A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

Description

Printed circuit board and method of manufacturing printed circuit board [Cross reference to related applications]

This application claims the priority of Korean Patent Application No. 10-2015-0100404 (filed on July 15, 2015) based on 35 U.S.C.119 and 35 U.S.C.365, which is hereby incorporated by reference in its entirety.

The present invention relates to a printed circuit board, and more specifically, to a printed circuit board including a circuit pattern having a curved surface and a surface treatment layer formed by electrolytic plating in a part of its lateral side; and manufacturing The printed circuit board method.

A printed circuit board (PCB) formed by using a conductive material such as copper (Cu) to print circuit line patterns on an electrically insulating substrate means a board just before mounting electronic components thereon. That is, PCB means a circuit board for determining the mounting position of electronic components, and circuit patterns are printed on a flat panel and fixed to the surface of the flat panel to connect the electronic components to each other, so that various types of electronic devices are densely mounted on the flat panel.

Generally speaking, for the surface treatment of the circuit pattern formed on the PCB, organic solderability preservative (OSP) has been used, and electrolytic nickel/gold, electrolytic nickel/gold-cobalt alloy, or no Electrode nickel/palladium/gold.

In this situation, various surface treatment solutions can be used according to the purpose of use. For example, surface treatment solutions for soldering, wire bonding, and connectors can be used.

Fig. 1 is a cross-sectional view showing a PCB according to the prior art.

1(a) and 1(b), the PCB includes an insulating layer 10, an electroplating seed layer 20, a circuit pattern 30, a protective layer 40, a first surface treatment layer 50 and a second surface treatment layer 60.

Figures 1(a) and 1(b) show the insulating layer 10, the electroplating seed layer 20, the circuit pattern 30, the first surface treatment layer 50 and the second surface treatment layer 60 with the same structure, only according to the used The shape has a different structure outside the protective layer 40.

In other words, the protective layer 40 shown in FIG. 1(a) covers the entire exposed surface of the insulating layer 10 and at least a part of the top surface of the circuit pattern 30, and has a shape protruding upward from the surface of the second surface treatment layer 60.

The protective layer 40 shown in Fig. 1(b) only serves as a dam. Therefore, the protective layer 40 exposes at least a part of the surface of the insulating layer 10 when the protective layer 40 is not in contact with the circuit pattern 30.

Meanwhile, the above PCB according to the prior art includes two of the following for surface treatment of the circuit pattern 30: a first surface treatment layer 50 including nickel (Ni), and a second surface treatment layer 60 including gold (Au).

In this situation, the first surface treatment layer 50 and the second surface treatment layer 60 are usually formed by electroless electroplating because the seed layer used for electroplating does not exist separately.

In addition, in order to form the first surface treatment layer 50 and the second surface treatment layer 60 through electrolytic plating, a plating seed layer must be separately formed.

However, design limitations may exist due to the fact that an additional seed layer is formed to perform electrolytic plating, although the surface treatment of the PCB is usually performed through electroless plating.

In addition, for the diffusion of the circuit pattern 30 including Cu, the surface treatment of the PCB essentially requires the formation of the first surface treatment layer 50 including a metal such as Ni.

Embodiments of the present invention provide a printed circuit board with a surface treatment layer of a circuit pattern formed by electroplating using an electroplating seed layer used when forming a circuit pattern; and a method of manufacturing a printed circuit board.

An embodiment of the present invention provides a printed circuit board including a circuit pattern having a curved surface in at least a part of its lateral side; and a method of manufacturing a printed circuit board.

An embodiment of the present invention provides a printed circuit board comprising a surface treatment layer formed on a circuit pattern and having a lower surface than the bottom surface of the circuit pattern The width is narrow and wider than the width of the top surface of the circuit pattern; and a method of manufacturing a printed circuit board.

The technical objectives of the embodiment may not be limited to the above objectives, and those familiar with the art will apparent other technical objectives of the embodiment from the following description.

According to an embodiment, a printed circuit board is provided, which includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface with a width wider than a width of a top surface of the circuit pattern.

In addition, in the circuit pattern, at least one of the upper right lateral side and the upper left lateral side of the circuit pattern has a predetermined curvature.

In addition, the width of the top surface of the circuit pattern is narrower than a width of a bottom surface of the circuit pattern, and the bottom surface of the circuit pattern includes a first area vertically overlapping the top surface of the circuit pattern , And a second area except the first area.

In addition, the surface treatment layer includes a gold (Au) surface treatment layer, the gold (Au) surface treatment layer includes a metal material, the metal material includes gold (Au), and a bottom of the gold (Au) surface treatment layer The surface is in direct contact with the top surface of the circuit pattern.

The bottom surface of the surface treatment layer has a width narrower than a width of a bottom surface of the circuit pattern.

In addition, the surface treatment layer includes a contact area contacting the top surface of the circuit pattern and a non-contact area not contacting the top surface of the circuit pattern, and the second area of the circuit pattern includes a contact area not contacting the top surface of the circuit pattern. A third area vertically overlapping the non-contact area of the surface treatment layer and a fourth area vertically overlapping the non-contact area of the surface treatment layer, and the third area has a width wider than that of the fourth area One width.

In addition, the width of the third area satisfies a range of 1.5 to 4.0 for the width of the fourth area.

In addition, it additionally includes an electroplating seed layer inserted between the insulating layer and the circuit pattern, and the electroplating seed layer serves as a seed layer for the circuit pattern and the surface treatment layer.

In addition, at least one of a left lateral side and a right lateral side of the circuit pattern includes a first portion substantially perpendicular to a bottom surface of the circuit pattern, and extends from the first member and has a predetermined curvature A second part of a curved surface.

In addition, a left side area or a right side area of the surface treatment layer respectively protrudes outward from an upper left lateral side or an upper right lateral side of the circuit pattern.

In addition, it additionally includes a protective layer formed on the insulating layer to cover at least a part of the surface of the insulating layer.

Meanwhile, according to the embodiment, a method of manufacturing a printed circuit board is provided. The method includes: preparing an insulating layer with an electroplating seed layer formed on a top surface of the insulating layer; and forming a circuit pattern on the insulating layer by performing electroplating on the electroplating seed layer serving as a seed layer Forming a mask with an opening on the electroplating seed layer to expose at least a portion of a top surface of the circuit pattern; by performing electroplating on the electroplating seed layer serving as the seed layer to perform electroplating in the circuit pattern A surface treatment layer is formed thereon so that the surface treatment layer fills at least a part of the opening; the mask is removed from the electroplating seed layer; and the electroplating seed layer is removed from the insulating layer.

The mask includes a dry film.

In addition, the opening of the mask has a width narrower than a width of the top surface of the circuit pattern, and the at least part of the top surface of the circuit pattern is covered by the mask.

In addition, the circuit pattern that exists before the electroplating seed layer is removed includes a first top surface in contact with a bottom surface of the surface treatment layer and a second surface not in contact with the bottom surface of the surface treatment layer The top surface, and a part of the second top surface of the circuit pattern is removed together with the electroplating seed layer when the electroplating seed layer is removed.

In addition, the circuit pattern that exists after the electroplating seed layer is removed includes a top surface having a width narrower than a width of the bottom surface of the surface treatment layer.

In addition, the circuit pattern existing after the electroplating seed layer is removed has a lateral side extending from the second top surface and having a predetermined curvature.

In addition, the surface treatment layer includes a gold (Au) surface treatment layer including a metal material, the metal material includes gold (Au), and the bottom surface of the gold (Au) surface treatment layer is in direct contact with the top surface of the circuit pattern.

In addition, the bottom surface of the surface treatment layer has a width narrower than the width of the bottom surface of the circuit pattern.

In addition, it further includes a step of forming a protective layer on the insulating layer to cover at least a part of the surface of the insulating layer.

According to an embodiment of the present invention, the surface treatment layer is formed by using a removable film type material and an electroplating seed layer used in the circuit pattern, so that electrolytic surface treatment can be selectively used without restrictions on the design And electrodeless surface treatment.

According to the embodiment of the present invention, the surface treatment layer including Au is formed using the electroplating seed layer used when forming the circuit pattern, so that the conventional Ni surface treatment layer serving as the seed layer for the Au surface treatment layer can be omitted. Therefore, the thickness of the product can be reduced, and the product cost can be reduced due to the omission of the Ni surface treatment layer.

In addition, according to the embodiments of the present invention, the conventional nickel (Ni) surface treatment layer can be omitted, and the surface treatment layer including gold (Au) can be directly formed on the circuit pattern, thereby increasing the electrical conductivity and reducing the resistance. Therefore, the RF characteristics can be improved.

In addition, according to an embodiment of the present invention, the surface treatment layer formed on the circuit pattern has an eaves structure protruding outward from the lateral side of the upper portion of the circuit pattern, so that the mounting area of the components mounted on the circuit pattern can be increased. Therefore, the reliability of customers can be improved.

The details of one or more embodiments are set forth in the accompanying drawings and descriptions below. Other features will be obvious from the description content and drawings and from the scope of patent application.

10‧‧‧Insulation layer

20‧‧‧Plating seed layer

30‧‧‧Circuit pattern

40‧‧‧Protection layer

50‧‧‧First surface treatment layer

60‧‧‧Second surface treatment layer

100‧‧‧Printed Circuit Board

110‧‧‧Insulation layer

120‧‧‧Plating seed layer

125‧‧‧First Mask

130‧‧‧Circuit pattern

131‧‧‧First part

132‧‧‧Second part

135‧‧‧Second mask

140‧‧‧Surface treatment layer

200‧‧‧Printed Circuit Board

210‧‧‧Insulation layer

220‧‧‧Plating seed layer

225‧‧‧Mask

230‧‧‧Circuit pattern

240‧‧‧Surface treatment layer

300‧‧‧Printed Circuit Board

310‧‧‧Insulation layer

320‧‧‧Plating seed layer

330‧‧‧Circuit pattern

340‧‧‧Surface treatment layer

400‧‧‧Printed Circuit Board

410‧‧‧Insulation layer

420‧‧‧Plating seed layer

430‧‧‧Circuit pattern

440‧‧‧Surface treatment layer

450‧‧‧Protection layer

500‧‧‧Printed Circuit Board

510‧‧‧Insulation layer

520‧‧‧Plating seed layer

530‧‧‧Circuit pattern

540‧‧‧Surface treatment layer

550‧‧‧Protection layer

a‧‧‧Open

b‧‧‧Open

B‧‧‧Open

W1‧‧‧First width

W2‧‧‧Second width

W3‧‧‧Third width

W4‧‧‧Fourth width

W5‧‧‧Fifth width

W6‧‧‧Sixth width

FIG. 1 is a cross-sectional view showing a printed circuit board according to the related art.

2 is a cross-sectional view showing the structure of the printed circuit board according to the first embodiment of the invention.

FIG. 3 is a cross-sectional view showing the circuit pattern of FIG. 2 in detail.

4 to 11 are cross-sectional views showing the method of manufacturing the printed circuit board of FIG. 2 in a manufacturing sequence.

12 is a cross-sectional view showing the structure of a printed circuit board according to a second embodiment of the invention.

13 to 15 are cross-sectional views showing a method of manufacturing the printed circuit board of FIG. 12.

16 is a cross-sectional view showing the structure of a printed circuit board according to a third embodiment of the invention.

Fig. 17 is a sectional view showing the structure of a printed circuit board according to a fourth embodiment of the invention.

18 is a cross-sectional view showing the structure of a printed circuit board according to a fifth embodiment of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily replicate the embodiments. However, the embodiment may have various modifications, and the present invention Not limited to this.

In the following description, when a predetermined component "includes" a predetermined element, the predetermined component does not exclude other elements, but may further include other components, unless otherwise indicated.

For convenience or clarity, the thickness and size of each layer shown in the drawings can be exaggerated, omitted or schematically drawn. In addition, the size of the component does not fully reflect the actual size. Throughout the drawings, the same reference numbers are assigned to the same elements.

In the description of the embodiments, it should be understood that when a layer, film, region or plate is referred to as "on another layer, another film, another region, or another plate", it can be "directly" on another layer, One or more intervening layers may also be present on the film, zone, board, or. Meanwhile, it should be understood that when a layer, film, region, or plate is referred to as being "directly on another layer, another film, another region, or another plate," there is no intervening layer.

The present invention provides a printed circuit board. In the printed circuit board, a surface treatment layer can be formed by using a removable film-type material and an additional seed layer instead of the conventional Ni surface treatment layer, and the seed layer can be removed. At this time, a part of the top surface of the circuit pattern and the seed layer are removed together.

2 is a cross-sectional view showing the structure of the printed circuit board according to the first embodiment of the invention. FIG. 3 is a cross-sectional view showing the circuit pattern of FIG. 2 in detail.

2 and 3, the printed circuit board 100 includes an insulating layer 110, an electroplating seed layer 120, a circuit pattern 130, and a surface treatment layer 140.

The insulating layer 110 may mean a support substrate of the printed circuit board 100 having a single circuit pattern, and means an insulating layer area having one circuit pattern 130 in a printed circuit board having a plurality of laminated structures.

When the insulating layer 110 means one insulating layer constituting a plurality of laminated structures, a plurality of circuit patterns may be continuously formed on the top surface and the bottom surface of the insulating layer 110.

The insulating layer 110 may constitute an insulating board, and may include a thermally cured or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite substrate, or a glass fiber impregnated substrate. If the insulating layer 110 includes a polymer resin, the insulating layer may include an insulating epoxy resin, or may include a polyimide-based resin.

The insulating layer 110 has a circuit pattern 130 formed thereon.

Preferably, the electroplating seed layer 120 to be used when forming the circuit pattern 130 It is formed between the insulating layer 110 and the circuit pattern 130.

The top surface and the bottom surface of the electroplating seed layer 120 may have equal widths.

Next, the circuit pattern 130 is formed on the electroplating seed layer 120.

Unlike the electroplating seed layer 120, the circuit pattern 130 may be formed in a shape whose top surface and bottom surface have mutually different widths. In this situation, the width of the bottom surface of the circuit pattern 130 may be equal to the width of the top or bottom surface of the electroplating seed layer 120, and the width of the top surface of the circuit pattern 130 may be narrower than the width of the bottom surface of the circuit pattern 130.

The electroplating seed layer 120 and the circuit pattern 130 may be formed of a metal including copper (Cu) and having electrical conductivity.

The circuit pattern 130 may undergo an additive process, an elimination process, a modified semi-additive process (MSAP), or a semi-additive process (SAP) which is a typical process for manufacturing printed circuit boards. Formed, and its details will be omitted.

Although the figures show that a single circuit pattern 130 is formed on the insulating layer 110, a plurality of circuit patterns 130 may be formed on at least one of the top surface and the bottom surface of the insulating layer 110 while being spaced apart from each other.

Hereinafter, the circuit pattern 130 will be described in more detail with reference to FIG. 3. The circuit pattern 130 includes: a first part 131 formed on the electroplating seed layer 120 to have a bottom surface in contact with the top surface of the electroplating seed layer 120; and a second part 132 formed on the first part 131 to At least a part of the top surface is in contact with the bottom surface of the surface treatment layer 140.

Although the circuit pattern 130 includes the first part 131 and the second part 132, the first part 131 and the second part 132 are provided only for the purpose of explaining the shape of the circuit pattern 130. In fact, the first component 131 and the second component 132 are integrated with each other as a component.

The bottom surface of the first part 131 of the circuit pattern 130 is in direct contact with the top surface of the electroplating seed layer 120.

In this situation, the first part 131 of the circuit pattern 130 may have a shape in which the top surface and the bottom surface of the first part 131 have equal widths.

In addition, the second part 132 of the circuit pattern 130 has mutually different widths at the bottom surface and the top surface thereof.

In other words, in the second part 132 of the circuit pattern 130, the width of the top surface Narrower than the width of the bottom surface. Therefore, the lateral sides of the second member 132 are formed with a predetermined longitudinal curvature.

In this situation, the second part 132 of the circuit pattern 130 may include a first lateral side having a first curvature and a second lateral side having a second curvature. In addition, the first curvature of the first lateral side may be substantially equal to the second curvature of the second lateral side.

Therefore, the circuit pattern 130 has a left lateral side and a right lateral side. Each of the left lateral side and the right lateral side includes a first portion substantially perpendicular to the main surface, and a second portion extending from the first portion and including a curved surface having a predetermined curvature.

The surface treatment layer 140 is formed on the circuit pattern 130 for surface treatment of the circuit pattern 130.

The surface treatment layer 140 may be formed of a metal including gold (Au) or an alloy including Au.

When the surface treatment layer 140 is formed of an alloy including Au, the surface treatment layer 140 may be formed of an Au alloy including cobalt (Co). In this situation, the surface treatment layer 140 is formed by electrolytic plating.

Preferably, the surface treatment layer 140 is formed by performing electroplating on the electroplating seed layer 120, which is the same as the electroplating seed layer used when forming the circuit pattern 130.

The surface treatment layer 140 is formed on the circuit pattern 130. Therefore, the bottom surface of the surface treatment layer 140 directly contacts the top surface of the circuit pattern 130.

In this situation, the surface treatment layer 140 includes a bottom surface having a width wider than that of the top surface of the circuit pattern 130.

Therefore, the bottom surface of the surface treatment layer 140 includes a first bottom surface that directly contacts the top surface of the circuit pattern 130 and a second bottom surface that does not contact the top surface of the circuit pattern 130.

In this situation, the first bottom surface of the surface treatment layer 140 may be the central area of the bottom surface of the surface treatment layer 140, and the second bottom surface of the surface treatment layer 140 may be the left and right areas of the surface treatment layer 140.

In addition, the surface treatment layer 140 may have a shape in which the width of the top surface is equal to the width of the bottom surface.

Meanwhile, the top surface and the bottom surface of the surface treatment layer 140 may have a width narrower than the width of the bottom surface of the circuit pattern 130.

Therefore, as shown in FIG. 2, the surface treatment layer 140 has an eaves structure protruding outward from the upper lateral side of the circuit pattern 130.

As described above, according to the present invention, the surface treatment layer 140 including Au is formed using the electroplating seed layer 120 used in forming the circuit pattern 130, and the nickel serving as the seed layer of the gold (Au) surface treatment layer can be removed. (Ni) Surface treatment layer.

In addition, as described above, according to the present invention, the conventional nickel (Ni) surface treatment layer is omitted, and the surface treatment layer 140 including gold (Au) is directly formed on the circuit pattern 130, thereby increasing the conductivity and reducing the resistance. . Therefore, the RF characteristics can be improved.

In addition, as described above, according to the present invention, the surface treatment layer 140 formed on the circuit pattern 130 has an eave structure protruding outward from the upper lateral side of the circuit pattern 130, so that the mounting area of the component mounted on the circuit pattern Can be increased. Therefore, the reliability of customers can be improved.

Hereinafter, the relationship between the circuit pattern 130 and the surface treatment layer 140 will be described in more detail.

Referring to FIG. 2, the circuit pattern 130 has a top surface and a bottom surface, and the top surface and the bottom surface have different widths from each other. In this situation, the bottom surface of the circuit pattern 130 has a first width W1, and the top surface of the circuit pattern 130 has a second width W2 that is narrower than the first width W1.

Therefore, the bottom surface of the circuit pattern 130 includes a second area that vertically overlaps the top surface of the circuit pattern 130 and a first area that does not overlap the top surface of the circuit pattern 130.

In addition, the surface treatment layer 140 is formed on the circuit pattern 130, and the top surface and the bottom surface of the surface treatment layer 140 may have the same third width W3.

In this situation, the third width W3 is narrower than the first width W1 and wider than the second width W2.

Therefore, the bottom surface of the surface treatment layer 140 includes a contact area contacting the top surface of the circuit pattern 130 and a non-contact area protruding from the top surface of the circuit pattern 130 beyond the contact area and not contacting the top surface of the circuit pattern 130 .

In this case, the bottom surface of the circuit pattern 130 may have a width wider than the width of the top surface of the circuit pattern 130 by the fourth width W4.

That is, the first area of the circuit pattern 130 may have a fourth width W4.

In this situation, the first area of the circuit pattern 130 partially overlaps the non-contact area of the surface treatment layer 140.

In other words, the first area of the circuit pattern 130 includes the third area, which does not vertically overlap the non-contact area of the surface treatment layer 140 and has a fifth width W5; and the fourth area, which is in contact with the non-contact area of the surface treatment layer 140 They overlap vertically and have a sixth width W6.

In this situation, preferably, the fifth width W5 of the third area is wider than the sixth width W6 of the fourth area.

More preferably, the ratio of the fifth width W5 to the sixth width W6 is in the range of 1.5 to 4.0.

In other words, when the ratio of the fifth width W5 to the sixth width W6 is less than 1.5, the non-contact area of the surface treatment layer 140 has a wider area. In this situation, the non-contact area of the surface treatment layer 140 protruding outward from the top surface of the circuit pattern 130 has an unstable structure, so that the non-contact area may collapse, thereby causing an electrical short circuit.

In addition, when the ratio of the fifth width W5 to the sixth width W6 is greater than 4.0, the non-contact area of the surface treatment layer 140 has a narrower width. In this situation, since the entire width of the surface treatment layer 140 is narrowed, the installation area can be narrowed.

Therefore, according to the present invention, when the surface treatment layer 140 having the eaves structure is formed as described above, the ratio of the fifth width W5 to the sixth width W6 satisfies the range of 1.5 to 4.0. In this situation, the fifth width W5 is wider than the sixth width W6, so that the fifth width W5 has a value ranging from 1.5 to 4 times the value of the sixth width W6.

Hereinafter, the method of manufacturing the printed circuit board shown in FIG. 2 will be described in detail with reference to FIGS. 4 to 11.

4 to 11 are cross-sectional views showing the method of manufacturing the printed circuit board of FIG. 2 in a manufacturing sequence.

Referring to FIG. 4, after the insulating layer 110 is prepared, a plating seed layer 120 is formed on the prepared insulating layer 110.

The electroplating seed layer 120 may be formed by performing electroless electroplating on the insulating layer 110 using a metal including Cu.

The insulating layer 110 may include a thermally cured or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite substrate, or a glass fiber impregnated substrate. If the insulating layer 110 includes a polymer resin, the insulating layer 110 may include an insulating epoxy resin, or may include a polyimide-based resin.

The electroplating seed layer 120 may be formed by performing a typical copper clad laminate (CCL) on the surface of the insulating layer 110 instead of electroless plating.

In this situation, when the electroplating seed layer 120 is formed via electroless electroplating, surface roughness is applied to the top surface of the insulating layer 110, so that electroless electroplating can be performed smoothly.

The electroless plating scheme can be executed in the following sequence: degreasing process, soft etching process, pre-catalyst process, catalyst treatment process, accelerator process, electroless plating process, and anti-oxidation process. In addition, the electroplating seed layer 120 may be formed by sputtering metal particles using plasma.

In this situation, before the electroplating seed layer 120 is formed through the electroplating process, a decontamination process of removing stains from the surface of the insulating layer 110 may be additionally performed. The decontamination process is performed to enhance the electroplating ability for forming the electroplating seed layer 120 by applying surface roughness to the surface of the insulating layer 11.

Thereafter, referring to FIG. 5, a first mask 125 is formed on the electroplating seed layer 120. In this case, the first mask 125 may include a dry film.

In this situation, the first mask 125 has an opening a to expose at least a part of the top surface of the electroplating seed layer 120.

In this situation, the top surface of the electroplating seed layer 120 exposed by the opening a of the first mask 125 corresponds to the area of the circuit pattern 130.

In other words, the first mask 125 having the opening a to expose the area of the circuit pattern 130 on the top surface of the electroplating seed layer 120 is formed on the electroplating seed layer 120.

In this case, the first mask 125 may be formed to cover the entire top surface of the electroplating seed layer 120. Therefore, the opening a can be formed by removing a part of the area of the electroplating seed layer 120 for forming the circuit pattern 130.

Next, referring to FIG. 6, the circuit pattern 130 is formed on the electroplating seed layer 120 so that the circuit pattern 130 fills at least a part of the opening a of the first mask 125.

The circuit pattern 130 may be formed while filling at least a part of the opening a of the first mask 125 by the following operation: electroplating is performed on the electroplating seed layer 120 serving as a seed layer using an alloy of a conductive material, preferably including Cu.

Next, referring to FIG. 7, the first mask 125 is removed from the electroplating seed layer 120.

In this situation, after the first mask 125 has been removed, the remaining part of the first mask 125 may remain on the surface of the electroplating seed layer 120. Therefore, an additional process of removing the remaining part of the first mask 125 may be performed.

Next, referring to FIG. 8, the second mask 135 is formed on the electroplating seed layer 120.

In this situation, preferably, the second mask 135 may include a dry film with strong heat resistance and easily removable properties.

The second mask 135 includes an opening b to expose the top surface of the circuit pattern 130.

In this situation, the opening b of the second mask 135 is formed with a width narrower than the width of the top surface of the circuit pattern 130.

Therefore, at least a part of the top surface of the circuit pattern 130 is covered by the second mask 135. Preferably, the central area of the top surface of the circuit pattern 130 is exposed to the outside through the opening b of the second mask 135, and the edge area of the top surface of the circuit pattern 130 is covered by the second mask 135.

Next, referring to FIG. 9, the surface treatment layer 140 is formed on the circuit pattern 130 by using both of the electroplating seed layer 120 and the circuit pattern 130 as seed layers.

In this situation, the surface treatment layer 140 is formed with a width equal to the width of the opening b of the second mask 135.

The surface treatment layer 140 may be formed of a metal including only gold Au or an alloy including Au.

When the surface treatment layer 140 is formed of an alloy including Au, the surface treatment layer 140 may be formed of an Au alloy including Cobalt. In this case, the surface treatment layer 140 may be formed by electroless plating.

Preferably, the surface treatment layer 140 is formed by performing electroplating with respect to the electroplating seed layer 120, which is the same as the electroplating seed layer used when forming the circuit pattern 130. In other words, since the electroplating seed layer 120 is connected to the circuit pattern 130, the short circuit occurs in the electroplating Between the seed layer 120 and the circuit pattern 130, the surface treatment layer 140 is formed by electroplating.

The surface treatment layer 140 is formed on the circuit pattern 130 such that the bottom surface of the surface treatment layer 140 directly contacts the top surface of the circuit pattern 130.

In this case, the surface treatment layer 140 existing before the electroplating seed layer 120 is removed includes a top surface and a bottom surface, the top surface and the bottom surface having a width narrower than the width of the top surface of the circuit pattern 130.

Therefore, the top surface of the circuit pattern 130 includes parts that are in contact with the surface treatment layer 140 and parts that are not in contact with the surface treatment layer 140.

Next, referring to FIG. 10, the second mask 135 formed on the electroplating seed layer 120 is removed.

In this situation, if the second mask 135 is removed similar to the process of removing the first mask 125, an additional process can be performed to remove the remaining second mask 135 on the electroplating seed layer 120 The remaining part.

Thereafter, referring to FIG. 11, a process of removing a part of the electroplating seed layer 120 is performed. The part of the electroplating seed layer is formed on the insulating layer 110 and does not have the circuit pattern 130.

In other words, after the second mask 135 has been removed, a process of removing the portion of the electroplating seed layer 120 formed on the insulating layer 110 is performed. In this situation, when the process of removing the electroplating seed layer 120 is performed, the part of the electroplating seed layer 120 formed under the circuit pattern 130 is not removed due to the circuit pattern 130, but only selectively The portion of the plating seed layer 120 that does not have the circuit pattern 130 is removed.

In this situation, the edge area of the top surface of the circuit pattern 130 does not have the surface treatment layer 140. Therefore, when the process of removing the portion of the electroplating seed layer 120 formed on the insulating layer 110 without the circuit pattern 130 is performed, the edge area of the top surface of the circuit pattern 130 that is not covered by the surface treatment layer 140 is also removed .

In this situation, only a portion of the top surface of the circuit pattern 130 that is not covered by the surface treatment layer 140 is removed.

Therefore, the upper lateral side of the circuit pattern 130 having a predetermined curvature different from the predetermined curvature of the lower portion of the circuit pattern 130 is removed.

Therefore, the bottom surface of the surface treatment layer 140 may be larger than the top of the circuit pattern 130. The width of the surface is wide.

In addition, due to the above process of removing the electroplating seed layer 120, the bottom surface of the surface treatment layer 140 includes the first bottom surface that directly contacts the top surface of the circuit pattern 130, and the bottom surface that does not contact the top surface of the circuit pattern 130. The second bottom surface.

In this situation, the first bottom surface of the surface treatment layer 140 may be the central area of the bottom surface of the surface treatment layer 140, and the second bottom surface of the surface treatment layer 140 may be the left and right areas of the surface treatment layer 140.

Meanwhile, the top surface and the bottom surface of the surface treatment layer 140 may have a width narrower than the width of the bottom surface of the circuit pattern 130.

In other words, as the edge area of the upper portion of the circuit pattern 130 is removed in the process of removing the electroplating seed layer 120, the circuit pattern 130 can be divided into the first part 131 and the second part 132 as described above.

The bottom surface of the first part 131 of the circuit pattern 130 is in direct contact with the top surface of the electroplating seed layer 120.

In this situation, the first part 131 of the circuit pattern 130 has a shape in which the top surface and the bottom surface of the first part 131 have equal widths.

In addition, the second part 132 of the circuit pattern 130 has a shape in which the top surface and the bottom surface have mutually different widths.

In other words, in the second part 132 of the circuit pattern 130, the width of the top surface is narrower than the width of the bottom surface. Therefore, the lateral sides of the second member 132 are formed with a predetermined longitudinal curvature.

In this situation, the second part 132 of the circuit pattern 130 may include a first lateral side having a first curvature and a second lateral side having a second curvature. In addition, the first curvature of the first lateral side may be substantially equal to the second curvature of the second lateral side.

Therefore, the circuit pattern 130 has a left lateral side and a right lateral side, and each of the left lateral side and the right lateral side includes a first portion substantially perpendicular to the main surface, and extends from the first portion and includes a curve having a predetermined curvature. The second part of the surface.

Therefore, as shown in FIG. 2, the surface treatment layer 140 has an eaves structure protruding outward from the upper lateral side of the circuit pattern 130.

As described above, according to the present invention, the surface treatment layer 140 comprising Au is By using the electroplating seed layer 120 used in forming the circuit pattern 130, the nickel (Ni) surface treatment layer serving as the seed layer for the gold (Au) surface treatment layer can be omitted.

In addition, as described above, according to the present invention, the conventional nickel (Ni) surface treatment layer is omitted, and the surface treatment layer 140 including gold (Au) is directly formed on the circuit pattern 130, thereby increasing the conductivity and reducing the resistance. . Therefore, the RF characteristics can be improved.

In addition, as described above, according to the present invention, the surface treatment layer 140 formed on the circuit pattern 130 has an eave structure protruding outward from the upper lateral side of the circuit pattern 130, so that the mounting area of the component mounted on the circuit pattern Can be increased. Therefore, the reliability of customers can be improved.

12 is a cross-sectional view showing the structure of a printed circuit board according to a second embodiment of the invention.

12, the printed circuit board 200 includes an insulating layer 210, a plating seed layer 220, a circuit pattern 230, and a surface treatment layer 240.

The insulating layer 210 can mean a supporting substrate of the printed circuit board 100 with a single circuit pattern, and means an insulating layer area with one circuit pattern 230 in a printed circuit board with a plurality of laminated structures.

The insulating layer 210 may constitute an insulating board, and may include a thermally cured or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite substrate or a glass fiber impregnated substrate. If the insulating layer 210 includes a polymer resin, the insulating layer 210 may include an insulating epoxy resin, or may include a polyimide-based resin.

The circuit pattern 230 is formed on the insulating layer 210.

Preferably, the electroplating seed layer 220 for forming the circuit pattern 230 is formed between the insulating layer 210 and the circuit pattern 230.

The top surface and the bottom surface of the electroplating seed layer 220 may have equal widths.

In addition, the circuit pattern 230 is formed on the electroplating seed layer 220.

Unlike the electroplating seed layer 220, the circuit pattern 230 may have a shape whose top surface and bottom surface have mutually different widths. In this case, the width of the bottom surface of the circuit pattern 230 may be equal to the width of the top surface or the bottom surface of the electroplating seed layer 220. The width of the top surface of the circuit pattern 230 may be narrower than the width of the bottom surface of the circuit pattern 230.

The electroplating seed layer 220 and the circuit pattern 230 are formed of a metal including Cu and having electrical conductivity.

The circuit pattern 230 can be formed through an additive process, an erasure process, a modified semi-additive process (MSAP), or a semi-additive process (SAP) which is a typical process for manufacturing printed circuit boards, and the details will be omitted.

Although the figures show that a single circuit pattern 230 is formed on the insulating layer 210, a plurality of circuit patterns 230 may be formed on at least one of the top surface and the bottom surface of the insulating layer 210 while being spaced apart from each other by a predetermined distance.

In this case, the circuit pattern 230 may have a shape similar to that of the circuit pattern 130 according to the first embodiment. Although the two lateral sides of the circuit pattern 130 according to the first embodiment have predetermined curvatures, the circuit pattern 230 according to the second embodiment only has a predetermined curvature at the upper right lateral side thereof.

In other words, the left lateral side of the circuit pattern 230 is substantially perpendicular to the bottom surface of the circuit pattern 230, and the right lateral side of the circuit pattern 230 has a portion substantially perpendicular to the bottom surface of the circuit pattern 230 and extends from the vertical portion and has a predetermined curvature The curved surface part.

The surface treatment layer 240 is formed on the circuit pattern 230 to perform surface treatment of the circuit pattern 230.

The surface treatment layer 240 may be formed of a metal including only gold Au or an alloy including Au.

When the surface treatment layer 240 is formed of an alloy including Au, the surface treatment layer 240 may be formed of an Au alloy including Cobalt. In this situation, the surface treatment layer 240 is formed by electroless plating.

Preferably, the surface treatment layer 240 is formed by performing electroplating with respect to the electroplating seed layer 220, which is the same as the electroplating seed layer used when forming the circuit pattern 230.

The surface treatment layer 240 is formed on the circuit pattern 230 such that the bottom surface of the surface treatment layer 240 directly contacts the top surface of the circuit pattern 230.

In this situation, the surface treatment layer 240 includes a bottom surface having a width wider than that of the top surface of the circuit pattern 230.

Therefore, the bottom surface of the surface treatment layer 240 includes a first bottom surface that directly contacts the top surface of the circuit pattern 230 and a second bottom surface that does not contact the top surface of the circuit pattern 230.

In this situation, the first bottom surface of the surface treatment layer 240 may include the central area and the left area of the bottom surface of the surface treatment layer 240, and the second bottom surface of the surface treatment layer 240 may include the right area of the surface treatment layer 240.

In addition, the surface treatment layer 240 may have a shape whose top surface and bottom surface have equal widths.

Meanwhile, both the top surface and the bottom surface of the surface treatment layer 240 may have a width narrower than the width of the bottom surface of the circuit pattern 230.

Therefore, unlike the surface treatment layer of the first embodiment, the surface treatment layer 240 according to the second embodiment has an eaves structure protruding outward from only the upper lateral side of the circuit pattern 230.

As described above, according to the present invention, the surface treatment layer 240 including Au is formed using the electroplating seed layer 220 used when forming the circuit pattern 230, so that the seed layer serving as the gold (Au) surface treatment layer can be omitted The nickel (Ni) surface treatment layer.

In addition, as described above, according to the present invention, the conventional nickel (Ni) surface treatment layer is omitted, and the surface treatment layer 140 including gold (Au) is directly formed on the circuit pattern 130, thereby increasing electrical conductivity and reducing resistance. Therefore, the RF characteristics can be improved.

In addition, as described above, according to the present invention, the surface treatment layer 240 formed on the circuit pattern 230 has an eaves structure protruding outward from the upper right lateral side of the circuit pattern 230, so that the components mounted on the circuit pattern 230 can be installed The area can be increased. Therefore, the reliability of customers can be improved.

Hereinafter, a method of manufacturing the printed circuit board shown in FIG. 12 will be described with reference to FIGS. 13 to 15.

13 to 15 are cross-sectional views showing the method of manufacturing the printed circuit board shown in FIG. 12 in a manufacturing sequence.

First, referring to FIG. 13, after preparing the insulating layer 210, an electroplating seed layer 220 is formed on the prepared insulating layer 210.

The electroplating seed layer 220 can be used for the insulating layer 210 by using a metal including Cu. Perform electroless plating to form.

The insulating layer 210 may include a thermally cured or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite substrate, or a glass fiber impregnated substrate. If the insulating layer 210 includes a polymer resin, the insulating layer 210 may include an insulating epoxy resin, or may include a polyimide-based resin.

Next, the circuit pattern 230 is formed by performing electroplating on the electroplating seed layer 220 serving as a seed layer using an alloy of a conductive material preferably including Cu.

Thereafter, the mask 225 is formed on the electroplating seed layer 220.

In this situation, preferably, the mask 225 may include a dry film with strong heat resistance and easily removable properties.

The mask 225 includes an opening B to expose the top surface of the circuit pattern 230.

The width of the opening B of the mask 225 is narrower than the width of the top surface of the circuit pattern 230.

Therefore, at least a part of the top surface of the circuit pattern 230 is covered by the mask 225. Preferably, the center area and the left area of the top surface of the circuit pattern 230 are exposed to the outside by the opening B of the mask 225, and the right edge area of the top surface of the circuit pattern 230 is covered by the mask 225.

Next, referring to FIG. 14, the surface treatment layer 240 is formed on the circuit pattern 230 by using the electroplating seed layer 220 and the circuit pattern 230 as the seed layer.

Under this condition, the surface treatment layer 240 has a width equal to the width of the opening B of the mask 225.

The surface treatment layer 240 may be formed of a metal including only gold Au or an alloy including Au.

When the surface treatment layer 240 is formed of an alloy including Au, the surface treatment layer 240 may be formed of an Au alloy including Cobalt. In this situation, the surface treatment layer 240 is formed by electroless plating.

Preferably, the surface treatment layer 240 is formed by performing electroplating with respect to the electroplating seed layer 220, which is the same as the electroplating seed layer used when forming the circuit pattern 230. In other words, since the electroplating seed layer 220 is connected to the circuit pattern 230 so that a short circuit occurs between the electroplating seed layer 220 and the circuit pattern 230, the surface treatment layer 240 is formed by electroplating.

The surface treatment layer 240 is formed on the circuit pattern 230 such that the bottom surface of the surface treatment layer 240 directly contacts the top surface of the circuit pattern 230.

In this situation, the surface treatment layer 240 existing before the electroplating seed layer 220 is removed includes a top surface and a bottom surface having a width narrower than that of the top surface of the circuit pattern 230.

Therefore, the top surface of the circuit pattern 230 includes a portion contacting the surface treatment layer 240 and a portion not contacting the surface treatment layer 240.

Thereafter, referring to FIG. 15, the mask 225 is removed from the electroplating seed layer 220.

Then, a process of removing a part of the electroplating seed layer 220, which is formed on the insulating layer 210 and does not have the circuit pattern 230, is performed.

In other words, after the mask 225 has been removed, a process of removing the portion of the electroplating seed layer 220 formed on the insulating layer 210 without the circuit pattern 230 is performed. In this situation, when the process of removing the portion of the electroplating seed layer 220 formed on the insulating layer 210 without the circuit pattern 230 is performed, the portion of the electroplating seed layer 220 is not removed due to the circuit pattern 230. It is formed at a part below the circuit pattern 230, but only the part of the plating seed layer 220 that does not have the circuit pattern 230 is selectively removed.

In this situation, the right edge area of the top surface of the circuit pattern 230 does not have the surface treatment layer 240. Therefore, when the process of removing the electroplating seed layer 220 is performed, the right edge area of the top surface of the circuit pattern 230 that is not covered by the surface treatment layer 240 is also removed.

In this situation, only the upper portion of the circuit pattern 230 that is not covered by the surface treatment layer 240 is removed.

Therefore, the upper right portion of the circuit pattern 230 that is not covered by the surface treatment layer 240 has a lateral side with a predetermined curvature, which is different from the curvature of the lower portion of the circuit pattern 230.

Therefore, the bottom surface of the surface treatment layer 240 has a width wider than the width of the top surface of the circuit pattern 230.

Due to the process of removing the electroplating seed layer 220, the bottom surface of the surface treatment layer 240 includes a first bottom surface that directly contacts the top surface of the circuit pattern 230, and a second bottom surface that does not contact the top surface of the circuit pattern 230. surface.

In this case, the first bottom surface of the surface treatment layer 240 may include surface treatment The central area and the left area of the bottom surface of the layer 240, and the second bottom surface of the surface treatment layer 240 may include the right area of the surface treatment layer 240.

Meanwhile, the top surface and the bottom surface of the surface treatment layer 240 may have a width narrower than the width of the bottom surface of the circuit pattern 230.

In addition, the upper right lateral side of the circuit pattern 230 is formed with a predetermined longitudinal curvature.

Therefore, as shown in FIG. 12, the surface treatment layer 240 has an eaves structure protruding outward from the upper right lateral side of the circuit pattern 230.

As described above, according to the present invention, the surface treatment layer 240 including Au is formed using the electroplating seed layer 220 used when forming the circuit pattern 230, so that the seed layer serving as the gold (Au) surface treatment layer can be omitted The nickel (Ni) surface treatment layer.

In addition, as described above, according to the present invention, the conventional nickel (Ni) surface treatment layer is omitted, and the surface treatment layer 140 including gold (Au) is directly formed on the circuit pattern 130, thereby increasing electrical conductivity and reducing resistance. Therefore, the RF characteristics can be improved.

In addition, as described above, according to the present invention, the surface treatment layer 240 formed on the circuit pattern 230 has an eaves structure protruding outward from the upper right lateral side of the circuit pattern 230, so that the mounting area of the component mounted on the circuit pattern Can be increased. Therefore, the reliability of customers can be improved.

16 is a cross-sectional view showing the structure of a printed circuit board according to a third embodiment of the invention.

16, the printed circuit board 300 includes an insulating layer 310, a plating seed layer 320, a circuit pattern 330, and a surface treatment layer 340.

In this case, since the insulating layer 310 and the electroplating seed layer 320 are the same as those of the first embodiment and the second embodiment, their details will be omitted.

In addition, the circuit pattern 230 according to the second embodiment includes an upper right lateral side having a predetermined curvature.

However, the circuit pattern 330 according to the third embodiment of the present invention has an upper left lateral side having a predetermined curvature; and the right lateral side is formed to be substantially perpendicular to the bottom surface.

FIG. 17 is a diagram showing a printed circuit board 400 according to a fourth embodiment of the present invention Sectional view.

17, the printed circuit board 400 includes an insulating layer 410, a plating seed layer 420, a circuit pattern 430, a surface treatment layer 440, and a protective layer 450.

In this situation, since the insulating layer 410, the electroplating seed layer 420, the circuit pattern 430, and the surface treatment layer 440 are the same as those of the printed circuit board according to the first embodiment of the present invention shown in FIG. 2, therefore The details will be omitted.

The printed circuit board 400 according to the fourth embodiment further includes a protective layer 450 formed on the insulating layer 410 to cover the surface of the insulating layer 410, the lateral side of the electroplating seed layer 420, the lateral side of the circuit pattern 430, and the surface treatment layer Part of the top surface of 440.

The protective layer 450 protrudes from the top surface of the surface treatment layer 440 to a predetermined height.

The protective layer 450 may include a solder resist to protect the surface of the insulating layer 410, and at least a part of the top surface of the surface treatment layer 240 of the circuit pattern formed on the insulating layer 410.

The protective layer 450 according to the fourth embodiment covers the entire exposed surface of the insulating layer 410.

Fig. 18 is a cross-sectional view showing a printed circuit board according to a fifth embodiment.

18, the printed circuit board 500 includes an insulating layer 510, a plating seed layer 520, a circuit pattern 530, a surface treatment layer 540, and a protective layer 550.

Since the insulating layer 510, the electroplating seed layer 520, the circuit pattern 530, and the surface treatment layer 540 are the same as those of the printed circuit board according to the first embodiment of the present invention shown in FIG. 2, the details thereof will be omitted.

The printed circuit board 500 according to the fifth embodiment further includes a protective layer 550 formed on the insulating layer 510 to cover a part of the surface of the insulating layer 510.

The protective layer 550 is formed on the insulating layer 510 and is separated from the circuit pattern 530 by a predetermined distance.

The protective layer 550 may include a solder resist to protect the surface of the insulating layer 510 and expose the top surface of the surface treatment layer 540 of the circuit pattern formed on the insulating layer 510 and a part of the surface of the insulating layer 510.

According to the embodiment of the present invention, the surface treatment layer is formed by using a removable film-type material and an electroplating seed layer used in the circuit pattern, so that it can be designed without restrictions on the design. Select electrolytic surface treatment and electrodeless surface treatment.

According to the embodiment of the present invention, the surface treatment layer including Au is formed using the electroplating seed layer used when forming the circuit pattern, so that the Ni surface serving as the seed layer for the Au surface treatment layer according to the prior art can be omitted Processing layer. Therefore, the thickness of the product can be reduced, and the product cost can be reduced due to the omission of the Ni surface treatment layer.

In addition, according to the present invention, the conventional nickel (Ni) surface treatment layer is omitted, and the surface treatment layer 140 including gold (Au) is directly formed on the circuit pattern 130, thereby increasing the conductivity and reducing the resistance. Therefore, the RF characteristics can be improved.

In addition, according to the embodiment of the present invention, the surface treatment layer formed on the circuit pattern has an eaves structure protruding outward from the lateral side of the upper portion of the circuit pattern, so that the mounting area of the components mounted on the circuit pattern can be increased. Therefore, the reliability of customers can be improved.

Any reference to "one embodiment (one embodiment, an embodiment)", "example embodiment", etc. in this specification means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The appearances of these phrases in various places in this specification do not necessarily all refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in conjunction with any embodiment, it is considered that the implementation of this feature, structure, or characteristic in combination with other embodiments is within the authority of those skilled in the art.

Although the embodiments have been described with reference to several illustrative embodiments of the embodiments, it should be understood that many other modifications and embodiments that fall within the spirit and scope of the principles of the present invention can be devised by those skilled in the art. More specifically, there may be various changes and modifications of the component parts and/or configurations of the subject combination configuration within the scope of the present invention, the drawings and the appended patents. In addition to changes and modifications of components and/or configurations, alternative uses will also be obvious to those familiar with the technology.

100‧‧‧Printed Circuit Board

110‧‧‧Insulation layer

120‧‧‧Plating seed layer

130‧‧‧Circuit pattern

140‧‧‧Surface treatment layer

W1‧‧‧First width

W2‧‧‧Second width

W3‧‧‧Third width

W4‧‧‧Fourth width

W5‧‧‧Fifth width

W6‧‧‧Sixth width

Claims (10)

A printed circuit board, comprising: an insulating layer; an electroplating seed layer on the insulating layer; a circuit pattern on the electroplating seed layer; and a surface treatment layer on the circuit pattern, wherein the surface treatment layer includes A bottom surface, the bottom surface has a width wider than a width of a top surface of the circuit pattern, wherein the bottom surface of the surface treatment layer includes: a first portion contacting the top surface of the circuit pattern, and a second Partly separated from the insulating layer and the circuit pattern by a predetermined distance, wherein the width of the top surface of the circuit pattern is narrower than a width of the bottom surface of the circuit pattern, wherein the bottom surface of the circuit pattern includes a The first area vertically overlaps the top surface of the circuit pattern and a second area other than the first area, wherein the second area of the circuit pattern includes a third area that does not vertically overlap the second area of the surface treatment layer Part and a fourth area vertically overlap the second part of the surface treatment layer, wherein the width of a bottom surface of the circuit pattern is equal to the width of the top surface of the electroplating seed layer. For example, the printed circuit board of item 1 of the patent application, wherein, in the circuit pattern, at least one of an upper right lateral side and an upper left lateral side of the circuit pattern has a predetermined curvature, wherein a surface of the predetermined curvature No contact with the surface treatment layer. For example, the printed circuit board of item 1 of the scope of patent application, wherein the third area has a width wider than that of the fourth area. For example, the printed circuit board of item 1 of the scope of patent application, wherein the surface treatment layer includes a gold (Au) surface treatment layer including a metal material, and the metal material includes gold (Au). For example, the printed circuit board of item 3 of the scope of patent application, wherein the width of the third area meets a range of 1.5 to 4.0 for the width of the fourth area. For example, the printed circuit board of item 4 of the scope of patent application, wherein the circuit pattern is formed of metal including copper (Cu). For example, the printed circuit board of item 1 of the scope of patent application, wherein the bottom surface of the surface treatment layer has There is a width narrower than a width of a bottom surface of the circuit pattern. For example, the printed circuit board of item 1 of the scope of patent application, wherein the electroplating seed layer serves as a seed layer for the circuit pattern and the surface treatment layer. For example, the printed circuit board of item 1 of the scope of patent application, wherein at least one of a left lateral side and a right lateral side of the circuit pattern includes a first part having a plane, and extending from the first part and having a predetermined One of the curvatures is a second part of the curved surface. For example, the printed circuit board of item 1 of the scope of patent application, wherein a left side area or a right side area of the surface treatment layer respectively protrudes outward from an upper left lateral side or an upper right lateral side of the circuit pattern.

Images