TWI698016B - Semiconductor structures - Google Patents

Abstract

A semiconductor structure includes a semiconductor substrate, a buried layer, a pair of first wells, a second well, a body doped region, and a first heavily doped region. The semiconductor substrate has a first conductivity type. The buried layer having a second conductivity type is disposed on the semiconductor substrate. The pair of first wells having the second conductivity type are disposed on the buried layer. The second well having the first conductivity type is disposed on the buried layer and between the pair of first wells. The body doped region having the first conductivity type is disposed in the second well. The first heavily doped region having the first conductivity type is disposed in the body doped region. In a top view, the first heavily doped region and the pair of first wells extend along a first direction, and the first heavily doped region extends beyond opposite edges of the pair of first wells.

Description

Semiconductor structure

The present invention relates to semiconductor structures, particularly to bidirectional semiconductor structures.

A battery disconnect switch (also known as a bidirectional power switch) is a bidirectional switch that can be used to control whether to allow current to flow between the battery and the load or between the battery and the charger. The traditional power Metal-Oxide-Semiconductor Field-Effect Transistor (power MOSFET) can be used to form battery-separated switches. However, in a single power metal-oxide semiconductor field-effect transistor ( The single PN junction between the source and the drain included in the power MOSFET cannot block the bidirectional current.

Nowadays, the ability to control bidirectional current between two or more power supplies is almost a necessary function for all battery separated switches. The use of disconnected power MOSFETs requires two Two devices are connected back to back, wherein the two devices have a common source region or drain region. The total resistance of the aforementioned battery-separated switch is twice the resistance of a single power metal oxide semiconductor field effect transistor, and it is prone to problems such as excessive current density, leakage current, and uneven conduction.

Some embodiments of the present invention provide a semiconductor structure including: a semiconductor substrate, a buried layer, a pair of first well regions, a second well region, a body doped region, and a first heavily doped region. The semiconductor substrate has the first conductivity type. The buried layer is located on the semiconductor substrate and has a second conductivity type different from the first conductivity type. The pair of first well regions are located on the buried layer and have the second conductivity type. The second well region is located on the buried layer and between the pair of first well regions, and has a first conductivity type and a first doping concentration. The body doped region is located in the second well region, which has the first conductivity type and the second doping concentration. The first heavily doped region is located in the body doped region, and has a first conductivity type and a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than This first doping concentration. In the top view, the first heavily doped region and the pair of first well regions extend along the first direction, and the first heavily doped region extends along the first direction beyond two of the pair of first well regions Opposite edges.

Some embodiments of the present invention provide a semiconductor structure including: a semiconductor substrate, a buried layer, a pair of first well regions, a pair of second well regions, a pair of bulk doped regions, a pair of first heavily doped regions, And the third well area. The semiconductor substrate has the first conductivity type. The buried layer is located on the semiconductor substrate and has a second conductivity type different from the first conductivity type. The pair of first well regions are located on the buried layer and have the second conductivity type. The pair of second well regions are located on the buried layer and are respectively located between the pair of first well regions, and have the first conductivity type and the first doping concentration. The pair of bulk doped regions are respectively located in the pair of second well regions, which have the first conductivity type and the second doping concentration. The pair of first heavily doped regions are respectively located in the pair of body doped regions, which have the first conductivity type and the second Three doping concentrations, where the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration. The third well area is located on the buried layer and between the pair of second well areas, and has the second conductivity type. In the top view, the pair of first heavily doped regions and the pair of first well regions extend along the first direction, and the pair of first heavily doped regions extend beyond the pair of first well regions along the first direction The two opposite edges.

100, 500, 600, 700, 1000, 1200, 1300, 1400: semiconductor structure

101, 701: the first well area

102, 702: second well area

103, 703: body doped area

104, 704: the first heavily doped region

105, 705: third well area

106, 707: fourth well area

107, 708: Fifth Well Area

108, 710: Active area

200, 800: semiconductor substrate

201, 801: Buried layer

202, 802: first conductivity type area

203, 803: source region/drain region

204, 706: second heavily doped region

205, 805: gate dielectric layer

206, 806: gate electrode layer

207, 807: insulating layer

208, 808: metal layer

209, 809: isolation structure

220, 820: gate structure

221, 821: Gate spacer

210, 211, 212, 810, 811, 812: heavily doped regions

413, 913: epitaxial layer

604, 1104, 1204: additional first heavily doped region

709: The Sixth Well

804: third heavily doped region

G1, G2: gate electrode

S/D: source/drain electrode

E1, E2: Electrode

L1: first length

L2: second length

D1: first distance

D2: second distance

W1: width

W2: first drift distance

W3: second drift distance

H1, H2: depth

A1-A1, A2-A2, A3-A3, B1-B1, B2-B2, C-C: Section

The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale and are only used for illustration. In fact, the size of the element may be arbitrarily enlarged or reduced to clearly show the characteristics of the embodiment of the present invention.

Figure 1 is a partial top view of an exemplary semiconductor structure according to some embodiments of the present invention.

FIG. 2 is a schematic cross-sectional view of the A1-A1 line segment corresponding to the semiconductor structure shown in FIG. 1, according to some embodiments of the present invention.

FIG. 3 is a schematic cross-sectional view of the line segment A2-A2 corresponding to the semiconductor structure shown in FIG. 1, according to some embodiments of the present invention.

FIG. 4 is a schematic cross-sectional view of the line A3-A3 corresponding to the semiconductor structure shown in FIG. 1 according to another embodiment of the present invention.

FIG. 5 is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention.

FIG. 6 is a partial top view of an exemplary semiconductor structure according to still other embodiments of the present invention.

FIG. 7 is a partial top view of an exemplary semiconductor structure according to some embodiments of the present invention.

FIG. 8 is a schematic cross-sectional view of the line segment B1-B1 corresponding to the semiconductor structure shown in FIG. 7, according to some embodiments of the present invention.

FIG. 9 is a schematic cross-sectional view of the line segment B2-B2 corresponding to the semiconductor structure shown in FIG. 7 according to another embodiment of the present invention.

FIG. 10 is a partial top view of an exemplary semiconductor structure according to some embodiments of the present invention.

FIG. 11 is a schematic cross-sectional view of the C-C line segment corresponding to the semiconductor structure shown in FIG. 10 according to some embodiments of the present invention.

FIG. 12 is a partial top view showing an exemplary semiconductor structure according to other embodiments of the present invention.

FIG. 13 is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention.

FIG. 14 is a partial top view of an exemplary semiconductor structure according to still other embodiments of the present invention.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not used to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or it may An embodiment that includes additional elements formed between the first and second elements so that they do not directly contact. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, and is not used to express the relationship between the different embodiments discussed.

In addition, terms that are relative to space may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spaces are relatively used In order to facilitate the description of the relationship between one element or feature(s) and another element(s) or feature in the illustration, the relative terms in space include the different orientations of the device in use or operation, and the The orientation described. When the device is turned to different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

Here, the terms "about", "approximately" and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, if there is no specific description of "about", "approximately" or "approximately", "about", "approximately" and "approximately" can still be implied. The meaning of "probably".

Although the components in some of the described embodiments are described in a specific order, these descriptions can also be performed in other logical orders. Other components can be added to the semiconductor structure in the embodiment of the present invention. In different embodiments, some components may be replaced or omitted.

An embodiment of the present invention provides a semiconductor structure, which includes a novel floating body dual gate (Floating Body Dual Gate, FBDG) metal oxide semiconductor Body field effect transistor (MOSFET). According to some embodiments of the present invention, a semiconductor structure including a floating body double-gate metal oxide semiconductor field effect transistor (FBDG MOSFET) can be applied to a lithium ion battery disconnect switch (Lithium Ion Battery Disconnect Switch) or other similar batteries For the separate switch, it should be noted that the application of the embodiment of the present invention is not limited to this. The semiconductor structure provided by the embodiment of the present invention includes a doped region located between a plurality of well regions and extending along a specific direction. The configuration of this doped region can improve the conduction uniformity of the transistor, improve the leakage current between the well regions, and reduce the resistance and the area of the active region.

First, please refer to Figure 1 and also refer to Figures 2-4. FIG. 1 is a partial top view of an exemplary semiconductor structure 100 according to some embodiments of the present invention, and FIG. 2 is a schematic cross-sectional view along the line A1-A1 shown in FIG. 1. FIG. 3 is a schematic cross-sectional view along the line A2-A2 depicted in FIG. 1, and FIG. 4 is a schematic cross-sectional view along the line A3-A3 depicted in FIG. 1. It should be understood that, in order to briefly describe the embodiments of the present invention, not all the elements of the semiconductor structure 100 are shown in FIGS. 1-4.

As shown in FIG. 1, according to some embodiments of the present invention, a partial top view of an exemplary semiconductor structure 100 is shown. According to some embodiments of the present invention, the semiconductor structure 100 includes a pair of first well regions 101, a second well region 102 between the pair of first well regions 101, and a bulk doped region ( The body doped region) 103 and the first heavily doped region 104, wherein the end shape of the first heavily doped region 104 in the top view is an I-type.

In the top view, according to some embodiments of the present invention, the first heavily doped region 104 and the pair of first well regions 101 both extend along the first direction, and the first heavily doped region 104 extends beyond the two opposite edges of the pair of first well regions 101 along the first direction. In some embodiments, the second well region 102 has a first length L1 extending along the first direction, and the pair of first well regions 101 has a second length L2 extending along the first direction, wherein the first length L1 is less than Or equal to the second length L2. In some embodiments, for example, the potential difference between the pair of first well regions 101 is greater than 0 volts, when the first length L1 is less than the second length L2 and the width W1 is less than 2 microns (micrometer, um), a surface current leakage path can be generated (surface leakage path) affects circuit operation.

In the above view, according to some embodiments of the present invention, the distance of the first heavily doped region 104 beyond the first edge of the second well region 102 along the first direction is the first distance D1, and the pair of first well regions 101 are along The distance beyond the first edge of the second well region 102 in the first direction is the second distance D2, where the first distance D1 must be greater than or equal to the second distance D2. For example, the first distance D1 may range from about 1 micrometer (um) to about 1) micrometer (um), for example, 3 micrometers (um), and the second distance D2 may range from about 1 micrometer (um) to about 1 micrometer (um). The range of about 10 micrometers (um), for example, can be 2 micrometers (um), where the difference between the first distance D1 and the second distance D2 (ie D1-D2) can range from about 0 micrometers (um) to about 10 micrometers (um). The range of) may be 1 micron (um), for example. In some embodiments, when the difference between the first distance D1 and the second distance D2 is greater than 0 micrometers (um), the effect of suppressing the surface current can be produced. In other embodiments, when the difference between the first distance D1 and the second distance D2 is less than 0 micrometer (um), the leakage path of the surface current may be generated and the circuit operation may be affected.

According to some embodiments of the present invention, the semiconductor structure 100 includes a body doped region 103 and a first heavily doped region 104 located between a pair of first well regions 101 and extending along a first direction, using the body doped region 103 The protection structure formed by the configuration of the first heavily doped region 104 can reduce or avoid the leakage current between the pair of first well regions 101. in In some embodiments, when the distance between the pair of first well regions 101 (for example, the width W1 in Figure 1) is less than 2 micrometers (um), the body doped region 103 and the first heavily doped region 104 can be used The configuration to avoid leakage current. It should be understood that, in order to briefly describe the embodiment of the present invention and highlight its technical features, not all the elements of the semiconductor structure 100 are shown in Figure 1. The elements in the cross-sectional views shown in Figures 2 and 4 are also Not all are shown in Figure 1.

As shown in Figure 1, according to some embodiments of the present invention, in the semiconductor structure 100, the pair of first well regions 101 is surrounded by the third well region 105, the third well region 105 is surrounded by the fourth well region 106, and the second The fourth well area 106 is surrounded by the fifth well area 107. In some embodiments, the pair of first well region 101 and fourth well region 106 has the second conductivity type, and the second well region 102, third well region 105, and fifth well region 107 have the opposite conductivity type to the second well region. The first conductivity type. In some embodiments, the first conductivity type is, for example, p-type, and the second conductivity type is, for example, n-type, but the invention is not limited thereto.

As shown in FIG. 2 and in conjunction with the top view shown in FIG. 1, according to some embodiments of the present invention, the semiconductor structure 100 mainly includes a semiconductor substrate 200 having a first conductivity type, and a second conductive type located on the semiconductor substrate 200. A buried layer 201 of conductivity type, a pair of first well regions 101 located on the buried layer 201, a second well region 102 located on the buried layer 201 and between the pair of first well regions 101, and a second well region 102 located on the buried layer 201. The body doped region 103 in the well region 102 and the first heavily doped region 104 in the body doped region 103. In some embodiments, the pair of first well regions 101 have the same second conductivity type as the buried layer 201, and the second well region 102, the body doped region 103, and the first heavily doped region 104 have the same conductivity as the semiconductor The substrate 200 has the same first conductivity type. In some embodiments, the first conductivity type is, for example, p-type, and the second conductivity type opposite to the first conductivity type is n-type. In some embodiments, the second well region 102 has a first doping concentration, the body doping region 103 has a second doping concentration, and the first heavily doped region 104 has a third doping concentration, where the third doping concentration is The concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration.

As shown in FIG. 2, in some embodiments, the semiconductor substrate 200 may be a silicon substrate, but the embodiment of the present invention is not limited to this. For example, the semiconductor substrate 200 may also be an elemental semiconductor (elemental semiconductor), including: germanium (germanium); a compound semiconductor (compound semiconductor), including: gallium nitride (GaN), silicon carbide (silicon carbide), Gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductor, including : Silicon Germanium Alloy (SiGe), Phosphorus Gallium Arsenide (GaAsP), Aluminum Indium Arsenide (AlInAs), Aluminum Gallium Arsenide (AlGaAs), Indium Gallium Arsenide (GaInAs), Gallium Indium Phosphorus (GaInP), and/ Or Phosphorus Indium Gallium Arsenide (GaInAsP), or a combination of the above materials. In some embodiments, the semiconductor substrate may include a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In some embodiments, the semiconductor substrate 200 has a first conductivity type, such as p-type, and its dopants such as boron, aluminum, gallium, indium, boron trifluoride ions (BF ₃ ⁺ ), or a combination of the above, doped The impurity concentration is in the range of about 10 ¹⁵ /cm ³ to about 10 ¹⁶ /cm ³ .

As shown in FIG. 2, according to some embodiments of the present invention, the semiconductor structure 100 includes a buried layer 201 on the semiconductor substrate 200. In some embodiments, the buried layer 201 has the second conductivity type, for example, n-type, and its dopant is nitrogen, arsenic, phosphorus, antimony ions, or a combination of the foregoing, and the doping concentration is about 10 ¹⁷ /cm ³ to about 10 ¹⁸ /cm ³ range. In some embodiments, the thickness of the buried layer 201 may be about 6 micrometers (um). In some embodiments, the buried layer 201 may be formed by an ion implantation process.

As shown in FIG. 2, according to some embodiments of the present invention, the semiconductor structure 100 includes a pair of first well regions 101 located on the buried layer 201. In some embodiments, the pair of first well regions 101 have the second conductivity type, for example, n-type, and the dopant is nitrogen, phosphorus, arsenic, antimony ion, or a combination of the foregoing, and the doping concentration is about 10 ^{The range of 15} /cm ³ to about 10 ¹⁶ /cm ³ . In some embodiments, the pair of first well regions 101 may be formed by an ion implantation process or a diffusion process. In some embodiments, the first conductivity type region 202 is included between the first well region 101 and the buried layer 201. The first conductivity type region 202 may have the same doping method and concentration as the semiconductor substrate 200, so it is not here. Repeat it again. In other embodiments, the first well region 101 may directly contact the buried layer 201.

As shown in FIG. 2, according to some embodiments of the present invention, the semiconductor structure 100 includes a second well region 102 located on the buried layer 201 and between the pair of first well regions 101. In some embodiments, the second well region 102 has the first conductivity type, such as p-type, with dopants such as boron, aluminum, gallium, indium, boron trifluoride ion (BF ₃ ⁺ ), or a combination thereof , The doping concentration ranges from about 10 ¹⁵ /cm ³ to about 10 ¹⁶ /cm ³ . In some embodiments, the second well region 102 may be formed by an ion implantation process or a diffusion process. In the top view, for example as shown in Figure 1, in some embodiments, the width W1 of the second well region 102 along the second direction does not exceed 2 microns (um), for example, it can be 2 microns (um) or 1 Micron (um).

As shown in Figure 2, according to some embodiments of the present invention, the semiconductor structure 100 includes a pair of third well regions 105 on the buried layer 201, which are arranged outside the pair of first well regions 101 and surround them (such as Shown in Figure 1). In some embodiments, the pair of third well regions 105 have the first conductivity type and can have the same doping method and concentration as the second well region 102, so it will not be repeated here. In some embodiments, a heavily doped region 210 having the same conductivity type as the third well region 105 can be formed close to the upper surface of the semiconductor substrate 200. This heavily doped region 210 can be formed by an interconnect structure (not shown) (Shown) is electrically connected to the electrode (not shown).

In FIG. 2, according to some embodiments of the present invention, an isolation structure 209 is formed between the first well region 101 and the third well region 105, and the isolation structure 209 is formed close to the upper surface of the semiconductor substrate 200. In some embodiments, the isolation structure 209 may be made of silicon oxide, and is a local oxidation of silicon (LOCOS) isolation structure 209 formed by a thermal oxidation method. In other embodiments, the isolation structure 209 may be a shallow trench isolation (STI) structure formed by etching and deposition processes.

As shown in FIG. 2, according to some embodiments of the present invention, the semiconductor structure 100 includes a body doped region 103 located in the second well region 102. In some embodiments, the bulk doped region 103 has the first conductivity type, for example, it may be p-type, with dopants such as boron, aluminum, gallium, indium, boron trifluoride ion (BF ₃ ⁺ ), or a combination thereof , The doping concentration is in the range of about 10 ¹⁷ /cm ³ to about 10 ¹⁸ /cm ³ . In some embodiments, the depth H1 of the bulk doped region 103 ranges from about 0.5 micrometer (um) to about 1 micrometer (um), for example, it may be 0.6 micrometer (um). In some embodiments, the bulk doped region 103 may be formed by an ion implantation process or a diffusion process.

As shown in FIG. 2, according to some embodiments of the present invention, the semiconductor structure 100 includes a first heavily doped region 104 in the body doped region 103. In some embodiments, the first heavily doped region 104 has the first conductivity type, such as p-type, and its dopants such as boron, gallium, aluminum, indium, boron trifluoride ion (BF ₃ ⁺ ), or the above For the combination, the doping concentration is in the range of about 10 ¹⁸ /cm ³ to about 10 ¹⁹ /cm ³ . In some embodiments, the depth H2 of the first heavily doped region 104 is less than about 0.5 micrometer (um), for example, it may be 0.2 micrometer (um). In some embodiments, the first heavily doped region 104 may be formed by an ion implantation process or a diffusion process.

Next, referring to FIG. 2 and FIG. 3, the configuration of the bulk doped region 103 and the first heavily doped region 104 will be clearly described. As shown in FIG. 3, which is a schematic cross-sectional view along the line A2-A2 depicted in FIG. 1, according to some embodiments of the present invention, the semiconductor structure 100 includes a semiconductor substrate 200, The buried layer 201, the second well region 102, the body doped region 103, and the first heavily doped region 104. It can be seen from this that, in some embodiments, although only the portion of the first heavily doped region 104 that extends beyond the second well region 102 along the first direction is depicted in Figure 1, the portion of the first heavily doped region 104 that exceeds the second well region 102 The part includes both the first heavily doped region 104 and the body doped region 103 under the first heavily doped region 104. The configuration of the bulk doped region 103 and the first heavily doped region 104 provided by the embodiment of the present invention can be used as a protection structure when the distance between the first well region 101 is small (for example, less than 2 micrometers (um)). Effectively improve the leakage current between well areas.

As shown in FIG. 2, according to some embodiments of the present invention, the semiconductor structure 100 further includes source/drain regions 203 respectively located in the pair of first well regions 101, wherein the source/drain regions 203 are formed close to On the upper surface of the semiconductor substrate 200. In some embodiments, the source/drain regions 203 have the second conductivity type, such as n-type. source The electrode region/drain region 203 can be electrically connected to the source/drain electrode S/D through an interconnect structure (not shown).

In some embodiments, the distance between the source region (drain region) 203 and the interface between the pair of first well regions 101 and the second well region 102 is a first drift distance W2, and the drain region (source region) 203 is a distance The interface between the pair of first well regions 101 and the second well region 102 is a second drift distance W3, wherein the first drift distance W2 and the second drift distance W3 do not exceed 2 microns. In some embodiments, the first drift distance W2 and the second drift distance W3 are the same, so the pair of first well regions 101 may be symmetrical to the first heavily doped region 104. In other embodiments, the first drift distance W2 and the second drift distance W3 are different, so the pair of first well regions 101 is asymmetric to the first heavily doped region 104. In this case, the pair of first well regions 101 have different drift distances (that is, the pair of first well regions 101 respectively have different areas), so the pair of first well regions 101 can withstand voltages of different magnitudes. For example, the voltage that one of the first well regions 101 with a smaller drift distance can withstand is also less than the voltage that the other first well region 101 with a larger drift distance can withstand. In some embodiments of the present invention, according to the application potential, the respective drift distances of the pair of first well regions 101 can be adjusted to reduce the area size of the active region (such as the active region 108) of the semiconductor structure 100.

As shown in Figure 2, according to some embodiments of the present invention, the semiconductor structure 100 further includes a pair of second heavily doped regions 204 located in the second well region 102, wherein the first heavily doped region 104 is located in the pair of second Between heavily doped regions 204. In some embodiments, the pair of second heavily doped regions 204 has the second conductivity type, for example, n-type, and its dopant is, for example, nitrogen, phosphorus, arsenic, antimony ions, or a combination of the foregoing. In some embodiments, the pair of second heavily doped regions 204 may be formed by an ion implantation process or a diffusion process. In some implementation In an example, the first heavily doped region 104 and the second heavily doped region 204 are connected via a surface conductor, the first heavily doped region 104 and the second heavily doped region 204 can be floating, and the conduction current flows therethrough. The surface conductor circulates without passing through an additional interconnection structure, thereby achieving the effect of reducing winding resistance and improving conduction uniformity. In other embodiments, the first heavily doped region 104 and the second heavily doped region 204 may be electrically connected to electrodes (not shown) through interconnect structures (not shown).

As shown in Figure 2, according to some embodiments of the present invention, the semiconductor structure 100 further includes a pair of gate structures 220 on the pair of first well regions 101 and the second well region 102, which partially cover the pair of second well regions. Heavy doped region 204. In some embodiments, the pair of gate structures 220 may respectively include a gate dielectric layer 205, a gate electrode layer 206 on the gate dielectric layer 205, an insulating layer 207, a metal layer 208, and a gate spacer 221. The gate spacers 221 are located on opposite sides of the stacked gate dielectric layer 205 and the gate electrode layer 206. The insulating layer 207 partially covers the first well region 101 and extends to cover the gate spacer 221 and the gate electrode layer 206 Part of the top surface, and the metal layer 208 covers the insulating layer 207 on a part of the top surface of the gate electrode layer 206 and extends to the insulating layer 207 on a part of the top surface of the first well region 101. In some embodiments, the gate electrode layer 206 and the metal layer 208 can be electrically connected to the gate electrodes G1 and G2 through the interconnect structure. In some embodiments, the metal layer 208 electrically connected to the gate electrode layer 206 extends to the insulating layer 207 on a part of the top surface of the first well region 101, which can produce the effect of a lateral field plate. .

In some embodiments, the material of the gate dielectric layer 205 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, combinations of the foregoing, or other suitable dielectric materials. material. In some embodiments, the gate dielectric layer 205 It may be formed by thermal oxidation (thermal oxidation), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

The material of the gate electrode layer 206 may include metal silicide, amorphous silicon, polysilicon, one or more metals, metal nitrides, conductive metal oxides, combinations of the foregoing, or other suitable conductive materials. The conductive material layer can be formed by chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or other suitable deposition methods.

The insulating layer 207 can be made of silicon nitride, silicon oxynitride, silicon carbide, silicon oxide, silicon carbide nitride, other suitable materials, or a combination thereof. In some embodiments, the insulating layer 207 may be formed by a deposition process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (high density plasma CVD, HDPCVD), and other suitable Method or a combination of the foregoing.

The metal layer 208 can be formed by a deposition process, and its material includes conductive materials, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride (TiN), tantalum nitride (TaN), nickel silicide ( Nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), aluminized Titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), metal oxide, metal alloy, other suitable conductive materials, or a combination of the foregoing.

Then, please refer to Figure 1 and Figure 4 for the combination. FIG. 4 is a schematic cross-sectional view of the line A3-A3 corresponding to the semiconductor structure shown in FIG. 1 according to another embodiment of the present invention. According to other embodiments of the present invention, the semiconductor structure 100 includes a pair of fourth well regions 106 on the buried layer 201, which are arranged outside and surround the pair of third well regions 105 (as shown in Figure 1) . In some embodiments, the pair of fourth well regions 106 have the second conductivity type and can have the same doping method and concentration as the first well region 101, so it will not be repeated here. In some embodiments, a heavily doped region 211 having the same conductivity type as the fourth well region 106 can be formed close to the upper surface of the semiconductor substrate 200, and the heavily doped region 211 can be formed by an interconnect structure (not shown) ) Is electrically connected to the electrode E1.

According to other embodiments of the present invention, the semiconductor structure 100 includes a pair of fifth well regions 107 on the epitaxial layer 413, which are arranged outside and surround the pair of fourth well regions 106 (as shown in FIG. 1) . In some embodiments, the epitaxial layer 413 may be an epitaxial layer of the first conductivity type. In some embodiments, the pair of fifth well regions 107 have the first conductivity type and can have the same doping mode and concentration as the second well region 102 and the third well region 105, so it will not be repeated here. In some embodiments, a heavily doped region 212 having the same conductivity type as the fifth well region 107 can be formed close to the upper surface of the semiconductor substrate 200, and the heavily doped region 212 can be formed by an interconnect structure (not shown) ) Is electrically connected to electrode E2.

In Figure 4, according to some embodiments of the present invention, an isolation structure 209 is formed between the third well region 105, the fourth well region 106, and the fifth well region 107, and the isolation structure 209 is formed close to the semiconductor substrate 200 Above the surface. The material and forming method of the isolation structure 209 shown here are substantially the same as the material and forming method of the isolation structure 209 shown in FIG. 2, so it will not be repeated here.

FIG. 5 is a partial top view of an exemplary semiconductor structure according to other embodiments of the present invention. The semiconductor structure 500 depicted in FIG. 5 is substantially the same as the semiconductor structure 100 depicted in FIG. 1. The only difference is that the end shape of the first heavily doped region 104 depicted in FIG. 5 is T-shaped, and The end shape of the first heavily doped region 104 shown in FIG. 1 is an I-type. FIG. 6 is a partial top view of an exemplary semiconductor structure according to still other embodiments of the present invention. The semiconductor structure 600 depicted in FIG. 6 is substantially the same as the semiconductor structure 100 depicted in FIG. 1, except that the semiconductor structure 600 in FIG. 6 further includes at least a pair of additional first heavily doped regions 604 Located around the pair of first well areas 101. For example, the additional first heavily doped region 604 can also surround the pair of first well regions 101 (not shown) along the boundary of the active region 108. The pair of additional first heavily doped regions 604 may be connected or not connected to the first heavily doped regions 104 respectively. In some embodiments, when the pair of additional first heavily doped regions 604 is connected to the first heavily doped region 104, although Figure 6 only shows the pair of additional first heavily doped regions around the first well region 101 The doped region 604, but the pair of additional first heavily doped regions 604 may also include doped regions such as the body doped region 103. In some embodiments, the additional first heavily doped region 604 and the first heavily doped region 104 may be connected by, for example, contacts or metal (not shown). According to some embodiments of the present invention, the exemplary semiconductor structures 100, 500, and 600 shown in FIGS. 1 and 5-6 respectively include the first heavily doped region 104 and/or the additional first The shape of the heavily doped region 604 can be determined according to the circuit layout, process conditions, and design rules. Furthermore, the shape of the first heavily doped region 104 is not limited to the shape disclosed in the embodiment of the present invention.

As shown in FIGS. 1-6, the semiconductor structure 100, 500, 600 provided by the embodiment of the present invention includes a plurality of first well regions 101 and along the first well region. The bulk doped region 103 and the first heavily doped region 104 extending in one direction. Utilizing this configuration of the doped region and the well region can improve the conduction uniformity of the semiconductor structure, improve the leakage current between the well regions, and reduce the resistance and the wiring area of the active region (such as the active region 108).

Please refer to Fig. 7 in conjunction with Figs. 8-9, which depicts another aspect of the semiconductor structure 700 of the present invention. According to some embodiments of the present invention, the active regions 710 of the semiconductor structure 700 disclosed in FIG. 7 can be understood as connecting a pair of active regions 108 of the semiconductor structure 100 disclosed in FIG. 2 back to back (the connection method is, for example, " Drain-source"-"source-drain", or "source-drain"-"drain-source") structure formed. It is worth noting that for the clarity of the embodiment, the active region 710 of the semiconductor structure 700 shown in FIG. 7 only includes a pair of active regions 108 of the semiconductor structure 100 shown in FIG. 2, but the present invention The embodiment is not limited to this. In other words, the active region 710 of the semiconductor structure 700 may also include two or more pairs of active regions 108 of the semiconductor structure 100.

FIG. 7 is a partial top view of an exemplary semiconductor structure 700 according to some embodiments of the present invention. FIG. 8 is a schematic cross-sectional view taken along the line B1-B1 shown in FIG. 7. Figure 9 is a schematic cross-sectional view taken along the line B2-B2 drawn in Figure 7. It should be understood that, in order to briefly describe the embodiments of the present invention, not all the elements of the semiconductor structure 700 are shown in FIGS. 7-9, and not all the elements in the cross-sectional views shown in FIGS. 8 and 9 are shown. Shown in Figure 7.

As shown in FIG. 7, a partial top view of an exemplary semiconductor structure 700 according to some embodiments of the present invention. According to some embodiments of the present invention, the semiconductor structure 700 includes a pair of first well regions 701, a pair of second well regions 702 between the pair of first well regions 701, and a pair of second well regions 702 respectively located within the pair of second well regions 702. The body doped region 703 and the pair of first A heavily doped region 704, a third well region 705 between the pair of second well regions 702, and a second heavily doped region 706 in the third well region 705, wherein the pair of first heavily doped regions 704 The end shape is I type.

In the top view, according to some embodiments of the present invention, the pair of first heavily doped regions 704 and the pair of first well regions 701 all extend along the first direction, and the pair of first heavily doped regions 704 extends along the first direction. One direction extends beyond the two opposite edges of the pair of first well regions 701. In some embodiments, the pair of second well regions 702 have a first length L1 extending along the first direction, and the pair of first well regions 701 have a second length L2 extending along the first direction, wherein the first The length L1 is less than the second length L2. In the above view, according to some embodiments of the present invention, the distance between the pair of first heavily doped regions 704 and the first edge of the pair of second well regions 702 along the first direction is the first distance D1, and the pair of The distance of a well area 701 beyond the first edge of the pair of second well areas 702 along the first direction is a second distance D2, wherein the first distance D1 is greater than the second distance D2. It is worth noting that the numerical relationship of the first length L1, the second length L2, the first distance D1, and the second distance D2 here is substantially the same as the numerical relationship described in the first figure, so it will not be repeated here.

According to some embodiments of the present invention, the semiconductor structure 700 includes a body doped region 703 and a first heavily doped region 704 located between a pair of first well regions 701 and extending along a specific direction. The body doped region 703 and The protection structure formed by the configuration of the first heavily doped region 704 can reduce or avoid the leakage current between the pair of first well regions 701. In some embodiments, when the distance between the pair of first well regions 701 (for example, the width W1 in Figure 7) is less than 2 micrometers (um), the above-mentioned body doped region 703 and the first heavily doped region can be used 704 configuration to avoid leakage current. It should be understood that, in order to concisely describe the embodiments of the present invention and highlight its technical features, not all elements of the semiconductor structure 700 are Shown in Figure 7.

As shown in Figure 7, according to some embodiments of the present invention, in the semiconductor structure 700, the pair of first well regions 701 is surrounded by a fourth well region 707, the fourth well region 707 is surrounded by a fifth well region 708, and the second The Wujing area 708 is surrounded by the sixth well area 709. In some embodiments, the pair of first well area 701, third well area 705, and fifth well area 708 have the second conductivity type, and the second well area 702, fourth well area 707, and sixth well area 709 It has a first conductivity type opposite to the second conductivity type. In some embodiments, the first conductivity type is, for example, p-type, and the second conductivity type is, for example, n-type, but the invention is not limited thereto.

As shown in FIG. 8 and in conjunction with the top view shown in FIG. 7, according to some embodiments of the present invention, the semiconductor structure 700 mainly includes a semiconductor substrate 800 having a first conductivity type, and a second semiconductor substrate 800 on the semiconductor substrate 800. A buried layer 801 of conductivity type, a pair of first well regions 701 located on the buried layer 801, a pair of second well regions 702 located on the buried layer 801 and located between the pair of first well regions 701, respectively A pair of body doped regions 703 in the pair of second well regions 702, a pair of first heavily doped regions 704 in the pair of body doped regions 703, and a pair of bulk doped regions 704 on the buried layer 801 The third well area 705 between the second well area 702. In some embodiments, the pair of first well regions 701 and the third well region 705 have the same second conductivity type as the buried layer 801, and the pair of second well regions 702, the pair of bulk doped regions 703, and The pair of first heavily doped regions 704 has the same first conductivity type as the semiconductor substrate 800. In some embodiments, the first conductivity type is, for example, p-type, and the second conductivity type opposite to the first conductivity type is n-type. In some embodiments, the pair of second well regions 702 has a first doping concentration, the pair of body doped regions 703 has a second doping concentration, and the pair of first heavily doped regions 704 has a third doping concentration. Degree, wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration.

As shown in FIG. 8, in some embodiments, the semiconductor substrate 800 may be a silicon substrate, but the embodiment of the present invention is not limited to this. For example, the material, conductivity type, and doping concentration of the semiconductor substrate 800 are substantially the same as those of the semiconductor substrate 200 shown in FIG. 2, so the details are not described here.

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 includes a buried layer 801 on the semiconductor substrate 800. In some embodiments, the material, thickness, conductivity type, and doping concentration of the buried layer 801 are substantially the same as those of the buried layer 201 shown in FIG. 2, so it will not be repeated here.

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 includes a pair of first well regions 701 located on the buried layer 801. In some embodiments, the material, conductivity type, and doping concentration of the pair of first well regions 701 are substantially the same as those of the first well region 101 shown in FIG. 2, so it will not be repeated here. In some embodiments, the pair of first well regions 701 can directly contact the buried layer 801. In other embodiments, the first conductivity type region 802 is included between the pair of first well regions 701 and the buried layer 801. The first conductivity type region 802 may have the same doping method and concentration as the semiconductor substrate 800, so I won't repeat it here.

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 includes a pair of second well regions 702 on the buried layer 801 and between the pair of first well regions 701. In some embodiments, the material, conductivity type, and doping concentration of the pair of second well regions 702 are substantially the same as those of the second well region 102 shown in FIG. 2, so it will not be repeated here. In the top view, such as that shown in Figure 7, in some embodiments, The width W1 of the pair of second well regions 702 along the second direction does not exceed 2 micrometers (um), for example, can be 2 micrometers (um) or 1 micrometer (um).

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 includes a pair of fourth well regions 707 on the buried layer 801, which are arranged outside the pair of first well regions 701 and surround them (such as As shown in Figure 7). In some embodiments, the pair of fourth well regions 707 have the first conductivity type and may have the same doping method and concentration as the pair of second well regions 702, so it will not be repeated here. In some embodiments, a heavily doped region 810 having the same conductivity type as the fourth well region 707 can be formed close to the upper surface of the semiconductor substrate 800, and the heavily doped region 810 can be formed by an interconnect structure (not shown) Electrically connected with electrodes (not shown).

In FIG. 8, according to some embodiments of the present invention, an isolation structure 809 is formed between the first well region 701 and the fourth well region 707, and the isolation structure 809 is formed near the upper surface of the semiconductor substrate 800. In some embodiments, the isolation structure 809 may be made of silicon oxide, and is a local oxidation of silicon (LOCOS) isolation structure 809 formed by a thermal oxidation method. In other embodiments, the isolation structure 809 may be a shallow trench isolation (STI) structure formed by etching and deposition processes.

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 includes a pair of bulk doped regions 703, which are respectively located in the pair of second well regions 702. In some embodiments, the material, conductivity type, and doping concentration of the pair of body-doped regions 703 are substantially the same as those of the body-doped regions 103 shown in FIG. 2, so they will not be repeated here. In some embodiments, the depth H1 of the pair of bulk doped regions 703 ranges from about 0.5 micrometer (um) to about 1 micrometer (um). In some embodiments, the pair of bulk doped regions 703 can be formed by an ion implantation process or a diffusion process.

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 includes a pair of first heavily doped regions 704, which are respectively located in the pair of body doped regions 703. In some embodiments, the material, conductivity type, and doping concentration of the pair of first heavily doped regions 704 are substantially the same as those of the first heavily doped region 104 shown in FIG. Repeat. In some embodiments, the depth H2 of the pair of first heavily doped regions 704 is less than about 0.5 micrometer (um), for example, can be 0.2 micrometer (um). In some embodiments, the pair of first heavily doped regions 704 can be formed by an ion implantation process or a diffusion process.

In order to more clearly describe the configuration of the pair of bulk doped regions 703 and the pair of first heavily doped regions 704, reference may be made to FIGS. 7 and 3 together. In Figure 7, according to some embodiments of the present invention, although Figure 7 only shows the part of a pair of first heavily doped regions 704 extending beyond a pair of second well regions 702 along the first direction, The part beyond the pair of second well regions 702 includes both the first heavily doped region 704 and the bulk doped region 703 below the first heavily doped region 704 (that is, as shown in Figure 3, so it is not here Repeat). The configuration of the bulk doped region 703 and the first heavily doped region 704 provided by the embodiment of the present invention can be used as a protection structure when the distance between the first well region 701 is small (for example, less than 2 micrometers (um)). Effectively improve the leakage current between well areas.

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 includes a third well region 705 on the buried layer 801, wherein the third well region 705 is located between the pair of second well regions 702. In some embodiments, the third well region 705 has the second conductivity type and can have the same doping method and concentration as the pair of first well regions 701, so it will not be repeated here. In some embodiments, the second heavily doped region 706 having the same conductivity type as the third well region 705 can be formed close to the upper surface of the semiconductor substrate 800. In some embodiments, the second heavily doped region 706 can be formed by an interconnection structure (not shown) It is electrically connected to the source/drain electrode S/D.

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 further includes source/drain regions 803 respectively located in the pair of first well regions 701, wherein the source/drain regions 803 are formed close to On the upper surface of the semiconductor substrate 800. In some embodiments, the source/drain region 803 has the second conductivity type, for example, n-type. The source/drain region 803 can be electrically connected to the source/drain electrode S/D through an interconnect structure (not shown).

In some embodiments, the source region (drain region) 803 is a first drift distance W2 from the interface between the pair of first well regions 701 and the second well region 702, and the second heavily doped region 706 is a third distance away. The interface between the well region 705 and the second well region 702 is a second drift distance W3, wherein both the first drift distance W2 and the second drift distance W3 do not exceed 2 microns. In some embodiments, the first drift distance W2 and the second drift distance W3 are different, so the pair of first well regions 701 and the third well region 705 have different drift distances (that is, the pair of first well regions 701 and The third well area 705 has different areas), so the pair of first well area 701 and the third well area 705 can withstand voltages of different magnitudes, for example, one of the first well areas 701 with a smaller drift distance can The withstand voltage is also smaller than the voltage with which the third well region 705 can withstand a larger drift distance. In some embodiments of the present invention, according to the application potential, the drift distance between the pair of first well regions 701 and the third well region 705 can be adjusted to reduce the active region of the semiconductor structure 700 (for example, the active region 710). )area size.

As shown in FIG. 8, according to some embodiments of the present invention, the pair of second well regions 702 included in the semiconductor structure 700 further includes a pair of third heavily doped regions 804, wherein the pair of first heavily doped regions 704 One of them is located in the pair of third heavily doped regions Between 804. In some embodiments, the pair of third heavily doped regions 804 has the second conductivity type, such as n-type, and its dopant is, for example, nitrogen, phosphorus, arsenic, antimony ions, or a combination of the foregoing. In some embodiments, the pair of third heavily doped regions 804 may be formed by an ion implantation process or a diffusion process. In some embodiments, the first heavily doped region 704 and the third heavily doped region 804 can be floating, and the conduction current flows through the surface conductors without passing through additional interconnection structures, thereby achieving The effect of reducing winding resistance and improving conduction uniformity. In other embodiments, the first heavily doped region 704 and the third heavily doped region 804 may be electrically connected to electrodes (not shown) through interconnect structures (not shown).

As shown in FIG. 8, according to some embodiments of the present invention, the semiconductor structure 700 further includes a plurality of pairs located above the first well region 701 and the second well region 702 and above the second well region 702 and the third well region 705 The gate structure 820 partially covers the pair of third heavily doped regions 804. In some embodiments, the multiple pairs of gate structures 820 may respectively include a gate dielectric layer 805, a gate electrode layer 806 on the gate dielectric layer 805, an insulating layer 807, a metal layer 808, and a gate spacer物821. The gate spacers 821 are located on opposite sides of the stacked gate dielectric layer 805 and the gate electrode layer 806. The insulating layer 807 partially covers the first well region 701 and extends to cover the gate spacer 821 and the gate electrode layer 806 Part of the top surface, and the metal layer 808 covers the insulating layer 807 on a part of the top surface of the gate electrode layer 806 and extends to the insulating layer 807 on a part of the top surface of the first well region 701. In some embodiments, the gate electrode layer 806 and the metal layer 808 can be electrically connected to the gate electrodes G1 and G2 through the interconnect structure. In some embodiments, the metal layer 808 electrically connected to the gate electrode layer 806 extends to the insulating layer 807 on a part of the top surface of the first well region 701, which can produce the effect of a lateral field plate. . In some embodiments, the material and forming method of the gate structure 820 are substantially the same as those shown in FIG. 2 The material and forming method of the gate structure 220 are not repeated here.

Then, please refer to Figure 7 and Figure 9 for the combination. FIG. 9 is a schematic cross-sectional view corresponding to the semiconductor structure shown in FIG. 7 according to other embodiments of the present invention. According to other embodiments of the present invention, the semiconductor structure 700 includes a pair of fifth well regions 708 on the buried layer 801, which are arranged outside and surround the pair of fourth well regions 707 (as shown in FIG. 7) . In some embodiments, the pair of fifth well regions 708 have the second conductivity type and can have the same doping method and concentration as the first well region 701 and the third well region 705, so it will not be repeated here. In some embodiments, a heavily doped region 811 having the same conductivity type as the fifth well region 708 can be formed close to the upper surface of the semiconductor substrate 800, and the heavily doped region 811 can be formed by an interconnect structure (not shown) ) Is electrically connected to the electrode E1 (not shown).

According to other embodiments of the present invention, the semiconductor structure 700 includes a pair of sixth well regions 709 on the epitaxial layer 913, which are arranged outside and surround the pair of fifth well regions 708 (as shown in FIG. 7) . In some embodiments, the epitaxial layer 913 may be an epitaxial layer of the first conductivity type. In some embodiments, the pair of sixth well regions 709 have the first conductivity type and can have the same doping mode and concentration as the second well region 702 and the fourth well region 707, so it will not be repeated here. In some embodiments, a heavily doped region 812 having the same conductivity type as the sixth well region 709 can be formed close to the upper surface of the semiconductor substrate 800, and the heavily doped region 812 can be formed by an interconnect structure (not shown) ) Is electrically connected to electrode E2 (not shown).

In Figure 9, according to some embodiments of the present invention, an isolation structure 809 is formed between the fourth well region 707, the fifth well region 708, and the sixth well region 709, and the isolation structure 809 is formed near the semiconductor substrate 800. Upper surface. The gap shown here The material and forming method of the isolation structure 809 are substantially the same as the material and forming method of the isolation structure 809 shown in FIG. 8, so it will not be repeated here.

FIG. 10 is a partial top view of an exemplary semiconductor structure 1000 according to some embodiments of the present invention, and FIG. 11 is a schematic cross-sectional view taken along the line C-C shown in FIG. 10. It should be understood that, in order to briefly describe the embodiment of the present invention, not all the elements of the semiconductor structure 1000 are shown in FIGS. 10-11, and not all the elements in the cross-sectional view shown in FIG. 11 are shown in Figure 10.

According to some embodiments of the present invention, the difference between the semiconductor structure 1000 shown in FIG. 10 and the semiconductor structure 700 shown in FIG. 7 is that the semiconductor structure 1000 further includes a pair of additional second well regions 702 disposed in a pair of The outer side of the first well region 701, and a pair of bulk doped regions 703 and a pair of first heavily doped regions 704 respectively located in the pair of second well regions 702.

As shown in FIG. 11, in conjunction with the top view shown in FIG. 10, according to some embodiments of the present invention, the cross-section of the semiconductor structure 1000 shown in FIG. 11 and the cross-section of the semiconductor structure 700 shown in FIG. 8 The difference is that the semiconductor structure 1000 further includes a pair of additional second well regions 702 respectively disposed between a pair of first well regions 701 and a pair of fourth well regions 707 and located on the buried layer 801, and includes A pair of body doped regions 703 in the pair of second well regions 702 and a pair of first heavily doped regions 704 and a third heavily doped region 804 in the pair of body doped regions 703 respectively. In some embodiments, the material, conductivity type, and doping concentration of the pair of additional second well regions 702, body doped regions 703, first heavily doped regions 704, and third heavily doped regions 804 and The structure shown in Figure 8 is basically the same, so it will not be repeated here.

Figure 12 is a drawing showing an example according to other embodiments of the present invention Partial top view of a sexual semiconductor structure. The semiconductor structure 1200 depicted in FIG. 12 is substantially the same as the semiconductor structure 700 depicted in FIG. 7, except that the end shape of the first heavily doped region 704 depicted in FIG. 12 is T-shaped, and The end shape of the first heavily doped region 704 shown in FIG. 7 is an I-type. The semiconductor structures 1300 and 1400 depicted in FIGS. 13-14 are substantially the same as the semiconductor structure 700 depicted in FIG. 7. The only difference is that the semiconductor structures 1300 and 1400 in FIGS. 13-14 further include at least a pair of additional The first heavily doped regions 1104 and 1204 are located around the pair of first well regions 701. As shown in FIG. 13, in some embodiments, the additional first heavily doped region 1104 and the first heavily doped region 704 may be connected by, for example, contacts or metal (not shown). As shown in FIG. 14, the pair of additional first heavily doped regions 1204 may be connected or not connected to the first heavily doped region 704, respectively. In some embodiments, when the pair of additional first heavily doped regions 1104 and 1204 are respectively connected to the first heavily doped region 704, although Figures 13-14 only show the pair of extra first heavily doped regions 701 Additional first heavily doped regions 1104 and 1204, but the pair of additional first heavily doped regions 1104 and 1204 may also include doped regions such as body doped regions 703. According to some embodiments of the present invention, the exemplary semiconductor structures 700, 1200, 1300, and 1400 shown in FIGS. 7 and 12-14 include the first heavily doped region 704 and/or the additional The shape of the first heavily doped region 1104, 1204 can be determined according to the circuit layout, process conditions, and design rules. Furthermore, the shape of the first heavily doped region 704 is not limited to the shape disclosed in the embodiment of the present invention .

As shown in FIGS. 7-14, the semiconductor structure 700, 1000, 1200, 1300, 1400 provided by the embodiment of the present invention includes a pair of bodies located between a plurality of first well regions 701 and extending along a first direction. The doped region 703 and a pair of first heavily doped regions 704, the configuration of this doped region and the well region can improve the conductivity of the semiconductor structure Conduct uniformity, improve leakage current between well regions, and reduce resistance and wiring area of active regions (such as active region 710).

The embodiment of the semiconductor structure provided by the present invention can be understood as a bi-conducting semiconductor structure including one or multiple floating body double gate metal oxide semiconductor field effect transistors (FBDG MOSFETs) connected back to back. The semiconductor structure provided by the embodiment of the present invention can be applied to a battery separated switch (for example, a lithium ion battery separated switch). In some embodiments, the number of back-to-back floating body double-gate metal oxide semiconductor field effect transistors (FBDG MOSFETs) included in the semiconductor structure depends on the driving capability required by the battery-type split switch. According to an embodiment of the present invention, the semiconductor structure includes a pair of bulk doped regions and a pair of first heavily doped regions between a plurality of first well regions and extending along a specific direction, such doped regions and well regions The configuration can effectively improve the conduction uniformity of the semiconductor structure, improve the leakage current between the well regions, and reduce the resistance and the wiring area of the active region.

The foregoing summarizes several embodiments so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can, without departing from the spirit and scope of the present invention, Make all kinds of changes, substitutions and replacements.

100: semiconductor structure

101: The first well area

102: The second well area

103: body doped region

104: The first heavily doped region

105: Third Well Area

106: The fourth well area

107: Fifth Well Area

108: active area

D1: first distance

D2: second distance

L1: first length

L2: second length

W1: width

A1-A1, A2-A2, A3-A3: Section

Claims (24)

A semiconductor structure includes: a semiconductor substrate having a first conductivity type; a buried layer located on the semiconductor substrate and having a second conductivity type different from the first conductivity type; a pair of first well regions, Located on the buried layer and having the second conductivity type; a second well region located on the buried layer and between the pair of first well regions, and having the first conductivity type and a first doping Concentration; One body doped region, located in the second well region, which has the first conductivity type and a second doping concentration; a first heavily doped region, located in the body doped region, which has the first A conductivity type and a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, the second doping concentration is greater than the first doping concentration; and in the top view, the first doping concentration The doped region and the pair of first well regions extend along a first direction, and the first heavily doped region extends beyond the two opposite edges of the pair of first well regions along the first direction. The semiconductor structure described in claim 1, wherein in the top view, the second well region has a first length extending along the first direction, and the pair of first well regions has a first length along the first A second length extends in one direction, wherein the first length is smaller than the second length. The semiconductor structure described in item 1 of the scope of the patent application, in which the above In the view, the first heavily doped region extends beyond a first edge of the second well region by a first distance along the first direction, and the pair of first well regions extend beyond the second well along the first direction The first edge of the zone has a second distance, wherein the first distance is greater than the second distance. According to the semiconductor structure described in claim 1, wherein the depth of the first heavily doped region is less than about 0.5 μm, and the depth of the bulk doped region is in the range of about 0.5 μm to about 1 μm. According to the semiconductor structure described in claim 1, wherein the width of the second well region along a second direction does not exceed 2 microns. The semiconductor structure described in claim 1 further includes a source region/drain region having the second conductivity type, wherein the source region/drain region are respectively located in the pair of first well regions. The semiconductor structure according to claim 6, wherein the source region is a first drift distance from the interface between the pair of first well regions and the second well region, and the drain region is away from the pair of first well regions. The interface between the well region and the second well region has a second drift distance, wherein both the first drift distance and the second drift distance do not exceed 2 microns. The semiconductor structure described in claim 7, wherein the first drift distance is different from the second drift distance, and the pair of first well regions are asymmetrical to the first heavily doped region. According to the semiconductor structure described in claim 1, wherein the pair of first well regions are symmetrical to the first heavily doped region. As the semiconductor structure described in item 1 of the scope of patent application, the first The second well region further includes a pair of second heavily doped regions having the second conductivity type, wherein the first heavily doped region is located between the pair of second heavily doped regions. The semiconductor structure described in item 10 of the scope of patent application further includes a pair of gate structures located on the pair of first well regions and the second well region, wherein the pair of gate structures partially cover the pair of second well regions. Doped area. The semiconductor structure described in claim 1 further includes a pair of third well regions located on the buried layer and having the first conductivity type, wherein the pair of first well regions are located in the pair of third well regions between. According to the semiconductor structure described in claim 1, wherein in the top view, the end shape of the first heavily doped region is an I-type or a T-type. According to the semiconductor structure described in claim 1, wherein in the top view, at least a pair of additional first heavily doped regions are located around the pair of first well regions. A semiconductor structure includes: a semiconductor substrate having a first conductivity type; a buried layer located on the semiconductor substrate and having a second conductivity type different from the first conductivity type; a pair of first well regions, Is located on the buried layer and has the second conductivity type; a pair of second well regions are located on the buried layer and are respectively located between the pair of first well regions, and have the first conductivity type and a first Doping concentration; a pair of body doping regions, respectively located in the pair of second well regions, which have the first conductivity type and a second doping concentration; A pair of first heavily doped regions, respectively located in the pair of body doped regions, has the first conductivity type and a third doping concentration, wherein the third doping concentration is greater than the second doping concentration, the The second doping concentration is greater than the first doping concentration; a third well region is located on the buried layer and between the pair of second well regions and has the second conductivity type; and in the top view, The pair of first heavily doped regions and the pair of first well regions extend along a first direction, and the pair of first heavily doped regions extends along the first direction beyond the two of the pair of first well regions. edge. The semiconductor structure according to claim 15, wherein in the top view, the pair of second well regions have a first length extending along the first direction, and the pair of first well regions have a length along the The first direction extends a second length, wherein the first length is smaller than the second length. The semiconductor structure according to claim 15, wherein in the top view, the pair of first heavily doped regions extends along the first direction from a first edge of the pair of second well regions by a first distance, And the pair of first well regions extend beyond the first edge of the pair of second well regions along the first direction by a second distance, wherein the first distance is greater than the second distance. The semiconductor structure according to claim 15, wherein the depth of the pair of first heavily doped regions is less than about 0.5 micrometers, the depth of the pair of bulk doped regions is in the range of about 0.5 micrometers to about 1 micrometer, and the The width of the second well area along a second direction does not exceed 2 microns. The semiconductor structure described in claim 15 further includes a second heavily doped region located in the third well region and having the second conductivity type. The semiconductor structure described in item 19 of the patent application further includes a source region/drain region having the second conductivity type, wherein the source region/drain region are respectively located in the pair of first well regions. The semiconductor structure according to claim 20, wherein the source region/drain region is a first drift distance from the interface between the pair of first well regions and the second well region, and the second heavily doped The distance between the miscellaneous area and the interface between the second well area and the third well area is a second drift distance, wherein neither the first drift distance nor the second drift distance exceeds 2 microns. According to the semiconductor structure described in claim 15, wherein the pair of second well regions further respectively include a pair of third heavily doped regions having the second conductivity type, wherein one of the pair of first heavily doped regions One is located between the pair of third heavily doped regions. The semiconductor structure described in item 22 of the scope of the patent application further includes a plurality of pairs of gate structures located on the pair of first well regions and the pair of second well regions and the pair of second well regions and the third well region Above, the plurality of pairs of gate structures partially cover the pair of third heavily doped regions. The semiconductor structure according to claim 15, wherein in the top view, at least a pair of additional first heavily doped regions is located around the pair of first well regions and connected to the pair of first heavily doped regions.

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