TWI695582B - Signal processing circuit - Google Patents

Abstract

The invention lies in suppressing the influence of the offset voltage of the amplifier and improving the response speed. The charge amplifier (101) provided in the signal processing circuit (100) of the present invention has parallel connected first and second systems (SYSa, SYSb). The first system (SYSa) has: a first amplifier (AMP1a), which is provided in The first holding capacitor (Cos1a) of the output path, the first switch (SW1a) provided in the short-circuit path, the second switch (SW2a) provided in the feedback path, and one end are connected to connect the first amplifier (AMP1a) and the reference voltage source (Vref1) The connected path and the other end is connected to the third switch (SW3a) of the path connecting the first holding capacitor (Cos1a) and the gain amplifier (102). The first state in which the first switch (SW1a) and the third switch (SW3a) are closed and the second switch (SW2a) is open, and the second state in which the switches of the switches are reversed can be obtained. The second system (SYSb) is also the same.

Description

Signal processing circuit

The invention relates to a signal processing circuit.

Sensor signals output from sensors such as self-pressure inductance sensors or thermal inductance sensors are weak and unstable analog signals. Therefore, before converting the sensor signal into a digital signal, sometimes signal processing such as amplification of the sensor signal or removal of noise components is necessary. In order to perform such signal processing, a signal processing circuit called an analog front end is connected to the sensor.

For example, Patent Document 1 discloses an imaging device including: a sensor array having a plurality of photoelectric conversion elements; an operational amplifier connected to each photoelectric conversion element; and a TFT switching element provided on the photoelectric conversion element and Between operational amplifiers; charge storage integration capacitors, which are provided in the feedback path of the operational amplifier; and reset switches, which are connected in parallel to the above integration capacitors and reset the integration capacitors. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Unexamined Patent Publication No. 2007-312361

[Problems to be solved by the invention]

When the signal processing circuit uses the amplifier to process the sensor signal, for example, even if the input level of the sensor signal is the same and the gain of each amplifier is the same, sometimes the offset voltage of each amplifier is different. As a result, the output level of each amplifier is different. In particular, in the case of processing by a multi-stage amplifier, the difference in signal level due to the difference in the offset voltage in the amplifier in the front stage is amplified in the rear stage, so it is required to reduce the difference due to the difference in the offset voltage in the front stage The difference of the signal level generated.

As a method of eliminating the fluctuation of the signal level caused by the offset voltage of the amplifier, for example, a chopper stabilization technique is known. However, if a chopper switch is provided at the foremost stage connected to the sensor, rebound noise will be generated in the sensor. As another method, a method of eliminating the offset voltage by providing a holding capacitor that holds the offset voltage in the output path is known. However, if a switch is provided in the input path from the sensor to the foremost stage to switch the offset holding mode in which the offset voltage is stored in the holding capacitor and the signal output mode of the output signal, the charge generated by the charge feedthrough of the switch Flow into the sensor. Therefore, there is a problem that the standby time until the influence of the charge flowing into the sensor is sufficiently attenuated, and the response speed becomes slow.

The present invention has been completed in view of this situation, and its object is to provide a signal processing circuit that can suppress the influence of the offset voltage of the amplifier and improve the response speed. [Technical means to solve the problem]

A signal processing circuit of one aspect of the present invention includes: a charge amplifier that converts each of a pair of first and second charge signals output from a sensor into first and second voltage signals; and a gain amplifier, which Amplifies the third and fourth voltage signals corresponding to the first and second voltage signals; and a filter that makes the high-frequency components contained in the fifth and sixth voltage signals corresponding to the third and fourth voltage signals Attenuation; and the charge amplifier has the first and second systems connected in parallel, the first system has: a first amplifier, which converts the input first charge signal into a first voltage signal; a first holding capacitor, which is set in the first The output path of the amplifier; the first switch, which is provided in the short-circuit path connecting the output terminal of the first amplifier to the input terminal and short-circuiting the first amplifier; the second switch, which is provided in the feedback path of the first amplifier and connected in parallel The first switch; and the third switch, one end of which is connected to the path connecting the reference voltage source of the first amplifier and the first amplifier, and the other end is connected to the path of connecting the first holding capacitor to the gain amplifier; the second system has: The second amplifier converts the input second charge signal into a second voltage signal; the second holding capacitor is provided in the output path of the second amplifier; the fourth switch is provided in the output terminal of the second amplifier and A short-circuit path where the input terminal is connected and short-circuits the second amplifier; the fifth switch, which is provided in the feedback path of the second amplifier and is connected in parallel to the fourth switch; and the sixth switch, which is connected at one end to the second amplifier and the second The path where the reference voltage source of the amplifier is connected, and the other end is connected to the path connecting the second holding capacitor to the gain amplifier; the first, third, fourth and sixth switches are closed and the second and fifth switches are open State 1 and the second state where the first, third, fourth, and sixth switches are open and the second and fifth switches are closed. [Effect of invention]

According to the present invention, a signal processing circuit can be provided, which can suppress the influence of the offset voltage of the amplifier and improve the response speed.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description of the following drawings, the same or similar constituent elements are denoted by the same or similar symbols. The drawing is an illustration, and the size or shape of each part is schematic, and should not be limited to this embodiment to explain the technical scope of the present invention.

<First Embodiment> First, referring to FIGS. 1 and 2, the circuit configuration of the signal processing circuit 100 according to the first embodiment of the present invention will be described. FIG. 1 is a diagram schematically showing the circuit configuration of the signal processing circuit of the first embodiment. FIG. 2 is a diagram schematically showing the circuit configuration of the charge amplifier of the first embodiment.

(Signal processing circuit 100) The signal processing circuit 100 is a signal processing circuit that amplifies the first sensor signal SIGa and the second sensor signal SIGb output from the sensor SEN. For example, the sensor SEN is a piezoelectric sensor or a thermal sensor, and the first sensor signal SIGa and the second sensor signal SIGb are paired differential signals. As shown in FIG. 1, the signal processing circuit 100 is a multi-stage amplifier circuit including a charge amplifier 101, a gain amplifier 102, and a filter 103 connected in series.

(Charge amplifier 101) The charge amplifier 101 converts each of the first sensor signal SIGa and the second sensor signal SIGb from a charge value to a voltage value. Specifically, the charge amplifier 101 converts the first charge amplifier input signal SIGIN1a corresponding to the first sensor signal SIGa into the first charge amplifier output signal SIGOUT1a to eliminate the offset contained in the first charge amplifier output signal SIGOUT1a Voltage Vos1a. In addition, the charge amplifier 101 converts the second charge amplifier input signal SIGIN1b corresponding to the second sensor signal SIGb into the second charge amplifier output signal SIGOUT1b to eliminate the offset voltage Vos1b included in the second charge amplifier output signal SIGOUT1b . In this embodiment, the first charge amplifier input signal SIGIN1a is equivalent to the first sensor signal SIGa, and the second charge amplifier input signal SIGIN1b is equivalent to the second sensor signal SIGb. The first sensor signal SIGa and the second sensor signal SIGb are equivalent to the first charge signal and the second charge signal. The first charge amplifier output signal SIGOUT1a and the second charge amplifier output signal SIGOUT1b are respectively equivalent to the first piezoelectric signal and the second voltage signal. The charge amplifier 101 has a first system SYSa and a second system SYSb connected in parallel. The first system SYSa processes the first sensor signal SIGa, and the second system SYSb processes the second sensor signal SIGb.

The first system SYSa includes an amplifier AMP1a, a feedback circuit FB1a, a storage capacitor Cos1a, and switches SW1a, SW2a, and SW3a. The second system SYSb includes an amplifier AMP1b, a feedback circuit FB1b, a storage capacitor Cos1b, and switches SW1b, SW2b, and SW3b. The amplifiers AMP1a and AMP1b respectively correspond to the first amplifier and the second amplifier, the feedback circuits FB1a and FB1b respectively correspond to the first feedback circuit and the second feedback circuit, and the holding capacitors Cos1a and Cos1b respectively correspond to the first holding capacitor and the second holding capacitor . The switches SW1a, SW2a, SW3a correspond to the first switch, the second switch, and the third switch, respectively, and the switches SW1b, SW2b, SW3b correspond to the fourth switch, the fifth switch, and the sixth switch, respectively.

A sensor SEN and a reference voltage source Vref1 are connected to the input terminals of the amplifiers AMP1a and AMP1b. The amplifier AMP1a converts the first charge amplifier input signal SIGIN1a into the first charge amplifier output signal SIGOUT1a. The amplifier AMP1b converts the second charge amplifier input signal SIGIN1b to the second charge amplifier output signal SIGOUT1b. From the viewpoint of reducing the difference in offset voltage, the MOS (Metal-Oxide Semiconductor, Metal Oxide Semiconductor) transistors provided at the input terminals of each of the amplifiers AMP1a and AMP1b are arranged in a common centroid. Also, from the viewpoint of noise reduction, the area of the gate electrode of the MOS transistor provided to the input terminal of each of the amplifiers AMP1a and AMP1b is larger than the MOS transistor provided to the input terminal of the amplifier AMP2 of the gain amplifier 102 described later The area of the gate electrode.

One end of the feedback circuit FB1a is connected to the input terminal of the first charge amplifier input signal SIGIN1a input in the amplifier AMP1a, and the other end of the feedback circuit FB1a is connected to the output terminal of the amplifier AMP1a. One end of the feedback circuit FB1b is connected to the input terminal of the second charge amplifier input signal SIGIN1b input in the amplifier AMP1b, and the other end of the feedback circuit FB1b is connected to the output terminal of the amplifier AMP1b.

One end of the holding capacitor Cos1a is connected to the output terminal of the amplifier AMP1a, and the other end of the holding capacitor Cos1a is connected to the reference voltage source Vref1. One end of the holding capacitor Cos1b is connected to the output terminal of the amplifier AMP1b, and the other end of the holding capacitor Cos1b is connected to the reference voltage source Vref1. Specifically, the other end of the holding capacitor Cos1a is connected to a path connecting the reference voltage source Vref1 and the amplifier AMP1a. The other end of the holding capacitor Cos1b is connected to a path connecting the reference voltage source Vref1 and the amplifier AMP1b. The holding capacitor Cos1a is provided in the output path of the amplifier AMP1a, and the holding capacitor Cos1b is provided in the output path of the amplifier AMP1b.

The switch SW1a is provided in a short-circuit path that short-circuits the amplifier AMP1a and connects the input terminal and the output terminal of the amplifier AMP1a. The switch SW1b is provided in a short-circuit path that short-circuits the amplifier AMP1a and connects the input terminal and the output terminal of the amplifier AMP1b. Specifically, one end of the switch SW1a is connected to a path connecting the sensor SEN and the amplifier AMP1a, and the other end of the switch SW1a is connected to a path connecting the amplifier AMP1a and the holding capacitor Cos1a. The short-circuit path of the amplifier AMP1a connects the input terminal and the output terminal of the amplifier AMP1a without passing through the feedback circuit FB1a. One end of the switch SW1b is connected to a path connecting the sensor SEN and the amplifier AMP1b, and the other end of the switch SW1b is connected to a path connecting the amplifier AMP1b and the holding capacitor Cos1b. The short-circuit path of the amplifier AMP1b connects the input terminal and the output terminal of the amplifier AMP1b without passing through the feedback circuit FB1b.

The switch SW2a is provided in a feedback path from the output terminal of the amplifier AMP1a to the input terminal. The feedback path connecting the output terminal and the input terminal of the amplifier AMP1a is provided with a feedback circuit FB1a and a switch SW2a connected in series. The switch SW2b is provided in the feedback path from the output terminal of the amplifier AMP1b to the input terminal. The feedback path connecting the output terminal and the input terminal of the amplifier AMP1b is provided with a feedback circuit FB1b and a switch SW2b connected in series. The short circuit path of the amplifier AMP1a is connected in parallel with the feedback path, and the short circuit path of the amplifier AMP1b is connected in parallel with the feedback path. Specifically, one end of the switch SW2a is connected to the feedback circuit FB1a, and the other end of the switch SW2a is connected to the output terminal of the amplifier AMP1a. One end of the switch SW2b is connected to the feedback circuit FB1b, and the other end of the switch SW2b is connected to the output terminal of the amplifier AMP1b. The switch SW2a is connected in parallel to the switch SW1a, and the switch SW2b is connected in parallel to the switch SW1b.

The switch SW3a is provided in a path connecting the holding capacitor Cos1a and the reference voltage source Vref1. The switch SW3b is provided in a path connecting the holding capacitor Cos1b and the reference voltage source Vref1. Specifically, one end of the switch SW3a is connected to a path connecting the amplifier AMP1a and the reference voltage source Vref1, and the other end of the switch SW3a is connected to a path connecting the holding capacitor Cos1a and the gain amplifier 102. One end of the switch SW3b is connected to a path connecting the amplifier AMP1b and the reference voltage source Vref1, and the other end of the switch SW3b is connected to a path connecting the holding capacitor Cos1b and the gain amplifier 102.

(Amplifiers AMP1a, AMP1b) As shown in FIG. 2, the amplifier AMP1a has an input section IS1a, an output section OS1a, OS2a, phase compensation capacitors Cpc1a, Cpc2a, and a common mode feedback circuit CMFB1a. The amplifier AMP1b has an input section IS1b, output sections OS1b, OS2b, phase compensation capacitors Cpc1b, Cpc2b, and a common mode feedback circuit CMFB1b.

The input section IS1a processes the first charge amplifier input signal SIGIN1a, and the output sections OS1a and OS2a process the signal output from the input section IS1a. The input section IS1a has two output paths, one output path is provided with an output section OS1a, and the other output path is provided with an output section OS2a. The output terminals of the output sections OS1a and OS2a are connected to the common mode feedback circuit CMFB1a. The output terminal of the output section OS1a is further connected to the holding capacitor Cos1a and the switches SW1a and SW2a.

A phase compensation capacitor Cpc1a for preventing oscillation is provided in the feedback path of the output section OS1a, and a phase compensation capacitor Cpc2a for preventing oscillation is provided in the feedback path of the output section OS1b. Specifically, one end of the phase compensation capacitor Cpc1a is connected to the path connecting the output section OS1a and the common mode feedback circuit CMFB1a, and the other end of the phase compensation capacitor Cpc1a is connected to the input section IS1a. One end of the phase compensation capacitor Cpc2a is connected to the path connecting the output section OS2a and the common mode feedback circuit CMFB1a, and the other end of the phase compensation capacitor Cpc2a is connected to the input section IS1a.

The common mode feedback circuit CMFB1a detects the output common voltage of the input section IS1a, and performs feedback control of the input section IS1a in such a manner that the output common voltage becomes fixed. The input terminal of the common mode feedback circuit CMFB1a is connected to the output terminals of the output sections OS1a and OS2a, and the output terminal of the common mode feedback circuit CMFB1a is connected to the internal node of the input section IS1a.

The amplifiers AMP1a and AMP1b have the same configuration. Therefore, detailed descriptions of the input section IS1b, the output sections OS1b, OS2b, the phase compensation capacitors Cpc1b, Cpc2b, and the common mode feedback circuit CMFB1b are omitted.

(Feedback circuit FB1a, FB1b) The feedback circuit FB1a is an RC resonance circuit with a feedback resistor Rfb1a and a feedback capacitor Cfb1a connected in parallel, and improves the characteristics of the amplifier AMP1a. The feedback circuit FB1b is an RC resonant circuit with a feedback resistor Rfb1b and a feedback capacitor Cfb1b connected in parallel to improve the characteristics of the amplifier AMP1b.

The resonance frequency generated by the RC resonance circuit of the feedback circuit FB1a is a frequency determined by the time constant of a resistor and a capacitor connected in parallel, and is set to f _fb . The cut-off frequency of the first sensor signal SIGa is determined by the time constant of the resistance and capacitance of the series connection in the sensor SEN, and is set to f _in . f _in is the inherent value of the sensor, so by changing the resistance and capacitance of the feedback circuit FB1a, the magnitude relationship of the two frequencies is determined, and the signal frequency band of the charge amplifier is defined. For example, the element value of each of the feedback resistor Rfb1a and the feedback capacitor Cfb1a connected in parallel is set to a larger value so that f _fb <f _in . In this case, f _fb functions as the lower band limit of the charge amplifier, and f _in functions as the upper band limit of the charge amplifier. That is, f _fb functions as the cut-off frequency of the high-pass filter, and f _in functions as the cut-off frequency of the low-pass filter.

The feedback circuit FB1b has the same configuration and function as the feedback circuit FB1a. Therefore, the detailed description of the feedback circuit FB1b is omitted.

(Operation of charge amplifier 101) Next, the operation of the charge amplifier 101 will be described while referring to FIGS. 3 and 4. FIG. 3 is a diagram showing the operation in the offset holding mode of the charge amplifier of the first embodiment. 4 is a diagram showing the operation in the signal output mode of the charge amplifier of the first embodiment.

The charge amplifier 101 operates in the offset hold mode before the operation in the signal output mode that outputs the first charge amplifier output signal SIGOUT1a and the second charge amplifier output signal SIGOUT1b. As shown in FIG. 3, in the offset holding mode, the switches SW1a, SW1b, SW3a, SW3b are closed, and the switches SW2a, SW2b are opened. In other words, a closed circuit including the amplifier AMP1a and the storage capacitor Cos1a and a closed circuit including the amplifier AMP1b and the storage capacitor Cos1b are formed. Therefore, the offset voltage Vos1a of the amplifier AMP1a is applied to the storage capacitor Cos1a, and the offset voltage Vos1b of the amplifier AMP1b is applied to the storage capacitor Cos1b.

In the offset holding mode, the charge amplifier 101 completely accumulates charge in each of the holding capacitors Cos1a and Cos1b to maintain the offset voltages Vos1a and Vos1b, and then switches to the signal output mode. As shown in FIG. 4, in the signal output mode, the switches SW1a, SW1b, SW3a, SW3b are turned on, and the switches SW2a, SW2b are turned off. In other words, a closed circuit including the amplifier AMP1a and the feedback circuit Fb1a and a closed circuit including the amplifier AMP1b and the feedback circuit FB1b are formed. The first charge amplifier output signal SIGOUT1a processed by the amplifier AMP1a is fed back to the amplifier AMP1a through the feedback circuit Fb1a, and is output to the gain amplifier 102 through the holding capacitor Cos1a. The second charge amplifier output signal SIGOUT1b processed by the amplifier AMP1b is fed back to the amplifier AMP1b via the feedback circuit Fb1b, and is output to the gain amplifier 102 via the holding capacitor Cos1b. At this time, the offset voltage Vos1a included in the first charge amplifier output signal SIGOUT1a is eliminated in the holding capacitor Cos1a. The offset voltage Vos1b included in the second charge amplifier output signal SIGOUT1b is eliminated in the holding capacitor Cos1b.

In addition, charges caused by charge feedthrough are generated when the switch is opened. When the charge amplifier 101 is connected to a sensor SEN having a weak signal signal such as a piezoresistor or a thermal sensor, if the charge due to the charge feedthrough does not discharge and flows into the sensor SEN, in the signal output mode, causes the sensor SEN to generate rebound noise. In addition, if there is a switch between the output terminal of the sensor SEN and the input terminal of the charge amplifier 101, the sensor is required at the time point when the switch is switched from short-circuit to open, that is, immediately after changing to the offset holding mode The standby time until the output terminal of SEN returns to normal charge amount, the response speed decreases. However, in this embodiment, without the switch, when the self-offset hold mode is switched to the signal output mode, the charge generated by the charge feedthrough generated in the switches SW1a and SW1b is discharged through the switches SW2a and SW2b. Therefore, rebound noise can be reduced. When the self-signal output mode is switched to the offset hold mode, the charge generated by the charge feedthrough generated in the switches SW2a, SW2b is discharged through the switches SW1a, SW1b. Therefore, the operating mode is switched without waiting for the influence caused by the charge feedthrough to subside, and there is no decrease in response speed.

The first charge amplifier output signal SIGOUT1a eliminates the offset voltage Vos1a via the holding capacitor Cos1a, and then outputs to the gain amplifier 102 via the inter-segment resistor Rin2a connected in series to the holding capacitor Cos1a. Similarly, the second charge amplifier output signal SIGOUT1b eliminates the offset voltage Vos1b through the holding capacitor Cos1b, and then outputs to the gain amplifier 102 through the inter-segment resistor Rin2b connected in series to the holding capacitor Cos1b.

(Gain amplifier 102) Next, the configuration and operation of the gain amplifier 102 will be described while referring to FIG. 5. 5 is a diagram showing the operation of the gain amplifier according to the first embodiment.

The gain amplifier 102 amplifies the first gain amplifier input signal SIGIN2a and the second gain amplifier input signal SIGIN2b corresponding to each of the first charge amplifier output signal SIGOUT1a and the second charge amplifier output signal SIGOUT1b. The gain amplifier 102 amplifies the first gain amplifier input signal SIGIN2a to output the first gain amplifier output signal SIGOUT2a, and amplifies the second gain amplifier input signal SIGIN2b to output the second gain amplifier output signal SIGOUT2b. The input signals SIGIN2a and SIGIN2b of the first and second gain amplifiers are equivalent to the third voltage signal and the fourth voltage signal. The gain amplifier 102 is an amplifier using chopper stabilization technology, and includes an amplifier AMP2, chopper switches SWCP1, SWCP2, and feedback resistors Rfb2a, Rfb2b. The gain amplifier 102 has two input systems S1a, S1b, two processing systems S2a, S2b, and two output systems S3a, S3b. The first gain amplifier input signal SIGIN2a is input to the input system S1a, and the second gain amplifier input signal SIGIN2b is input to the input system S1b. The output signal of the output system S3a is defined as the first gain amplifier output signal SIGOUT2a, and the output signal of the output system S3b is defined as the second gain amplifier output signal SIGOUT2b.

The reference voltage source Vref2 is connected to the amplifier AMP2. The reference voltage source Vref2 may also be the same as the reference voltage source Vref1. The input side of the amplifier AMP2 is defined as the processing systems S2a, S2b. The amplifier AMP2 has an offset voltage Vos2, for example, the voltage of the processing system S2a is higher than the processing system S2b by the offset voltage Vos2.

The chopper switch SWCP1 is provided on a path connecting the charge amplifier 101 and the amplifier AMP2. Two input systems S1a, S1b are connected to one end of the chopper switch SWCP1, and two processing systems S2a, S2b are connected to the other end of the chopper switch SWCP1. The chopper switch SWCP2 is provided on a path connecting the amplifier AMP2 and the filter 103. Two output terminals of the amplifier AMP2 corresponding to the two processing systems S2a, S2b are connected to one end of the chopper switch SWCP2, and two output systems S3a, S3b are connected to the other end of the chopper switch SWCP2. The chopper switch SWCP1 corresponds to the first chopper switch, and the chopper switch SWCP2 corresponds to the second chopper switch.

One end of the feedback resistor Rfb2a is connected to the input system S1a, and the other end of the feedback resistor Rfb2a is connected to the output system S3a. One end of the feedback resistor Rfb2b is connected to the input system S1b, and the other end of the feedback resistor Rfb2b is connected to the output system S3b.

(Gain G2) Next, the gain G2 of the amplifier AMP2 will be described using the element value of each element provided on the input system S1a side. In addition, the component value of each component provided on the input system S1b side is the same as the component value of each component provided on the input system S1a side, and therefore the description is omitted.

The element values of the holding capacitor Cos1a, the inter-segment resistance Rin2a, and the feedback resistance Rfb2a are represented by Cos1a, Rin2a, and Rfb2a as the symbols of each, and the frequency of the first sensor signal SIGa is set to f, when When s=2πf, the following formula holds. G2=Rfb2a/{Rin2a+1/(s×Cos1a)} Therefore, when Rin2a<<1/(s×Cos1a), it can be approximated as G2≒s×Cos1a×Rfb2a. In addition, when Rin2a >> 1/(s×Cos1a), it can be approximated as G2≒Rfb2a/Rin2a. In this embodiment, Rin2a is sufficiently smaller than 1/(s×Cos1a), so the gain 2 of the amplifier AMP2 does not depend on the size of the inter-segment resistor Rin2a, but can be determined by the product of the holding capacitor Cos1a and the feedback resistor Rfb2a.

(Operation of gain amplifier 102) The chopper switch SWCP1 can intermittently replace the first gain amplifier input signal SIGIN2a and the second gain amplifier input signal SIGIN2b input to the amplifier AMP2. The chopper switch SWCP2 again replaces the signal output from the amplifier AMP2. The chopper switches SWCP1 and SWCP2 select the path of the input and output signals of the amplifier AMP2 based on the clock input to each. The frequency of the clock is higher than the upper limit of the frequency band of the first gain amplifier input signal SIGIN2a and the second gain amplifier input signal SIGIN2b.

In the example shown in FIG. 5, when Clock=H, the chopper switch SWCP1 connects the input system S1a and the processing system S2a, and connects the input system S1b and the processing system S2b. Moreover, the chopper switch SWCP2 connects the processing system S2a and the output system S3a, and connects the processing system S2b and the output system S3b. When Clock=L, the chopper switch SWCP1 connects the input system S1a and the processing system S2b, and connects the input system S1b and the processing system S2a. Moreover, the chopper switch SWCP2 connects the processing system S2a and the output system S3b, and connects the processing system S2b and the output system S3a. In other words, when Clock=H, the offset voltage Vos2 is applied to the output system S3a, and when Clock=L, the offset voltage Vos2 is applied to the output system S3b. Therefore, if the time average of the differential voltage of the output system S3a and the output system S3b is obtained, the offset voltage Vos2 is eliminated.

The first gain amplifier output signal SIGOUT2a amplified in the gain amplifier 102 shown in FIG. 1 is input to the filter 103 through a resistor Rin3a provided in a path connecting the gain amplifier 102 and the filter 103. Similarly, the second gain amplifier output signal SIGOUT2b amplified by the gain amplifier 102 is input to the filter 103 through the inter-segment resistor Rin3b.

(Filter 103) The filter 103 shown in FIG. 1 makes the high included in the first filter input signal SIGIN3a and the second filter input signal SIGIN3b corresponding to each of the first gain amplifier output signal SIGOUT2a and the second gain amplifier output signal SIGOUT2b Frequency components are attenuated. The filter 103 attenuates high-frequency components contained in the first filter input signal SIGIN3a to output the first filter output signal SIGOUT3a, and attenuates high-frequency components contained in the second filter input signal SIGIN3b to output the second filter Output signal SIGOUT3b. The first filter input signal SIGIN3a and the second filter input signal SIGIN3b are signals corresponding to the first gain amplifier output signal SIGOUT2a and the second gain amplifier output signal SIGOUT2b, and the first gain amplifier output signal SIGOUT2a and the second gain amplifier output signal SIGOUT2b is a signal corresponding to the first gain amplifier input signal SIGIN2a and the second gain amplifier input signal SIGIN2b corresponding to the third input signal and the fourth input signal. Therefore, the first filter input signal SIGIN3a and the second filter input signal SIGIN3b are equivalent to the fifth voltage signal and the sixth voltage signal. The attenuated high-frequency component is, for example, the peak noise of the clock frequency generated by the stabilization of the chopper of the gain amplifier 102. The filter 103 is an active low-pass filter including an amplifier AMP3, feedback resistors Rfb3a, Rfb3b, and feedback capacitors Cfb3a, Cfb3b. The filter 103 has two processing systems.

The reference voltage source Vref3 is connected to the amplifier AMP3. The reference voltage source Vref3 may be the same as the reference voltage source Vref1 and the reference voltage source Vref2. The amplifier AMP3 is installed in two processing systems, and amplifies the first filter input signal SIGIN3a and the second filter input signal SIGIN3b flowing through each of the two processing systems.

The feedback resistor Rfb3a is provided in the feedback path on the SIGIN3a side of the first filter input signal in the amplifier AMP3. The feedback resistor Rfb3b is provided in the feedback path of the second filter input signal SIGIN3b side of the amplifier AMP3.

The feedback capacitor Cfb3a is connected in parallel to the feedback resistor Rfb3a in the feedback path on the side of the first filter input signal SIGIN3a in the amplifier AMP3. The feedback capacitor Cfb3b is connected in parallel to the feedback resistor Rfb3b in the feedback path on the side of the second filter input signal SIGIN3b in the amplifier AMP3.

(Component value) Next, an example of the component value of each component included in the signal processing circuit 100 will be listed. The feedback resistors Rfb1a and Rfb1b of the charge amplifier 101 are 6.8×10 ⁶ Ω, the feedback capacitors Cfb1a and Cfb1b of the charge amplifier 101 are 390×10 ^-12 F, and the holding capacitors Cos1a and Cos1b of the charge amplifier 101 are 100×10 ^{− 12} F. At this time, the cutoff frequency of the charge amplifier 101 becomes 1/(2π×6.8×10 ⁶ ×390×10 ^-12 )=60 Hz. The gain G1 of the charge amplifier 101 can be approximated as G1≒1/(1+s×Cfb1 when the feedback capacitors Cfb1a and Cfb1b are set to Cfb1 and the input resistance of the input path to the charge amplifier 101, which is not shown, is set to Rin1 ×Rin1) (s=2πf).

The inter-segment resistances Rin2a and Rin2b of the charge amplifier 101 and the gain amplifier 102 are 100 Ω, respectively. The feedback resistors Rfb2a and Rfb2b of the gain amplifier 102 are 1×10 ⁶ Ω, respectively. As described above, the gain G2 of the gain amplifier 102 can be approximated as G2≒s×Cos1a×Rfb2a (s=2πf).

The inter-segment resistances Rin3a and Rin3b of the gain amplifier 102 and the filter 103 are 12×10 ³ Ω, respectively. The feedback resistances Rfb3a and Rfb3b of the filter 103 are 47×10 ³ Ω, respectively, and the feedback capacitances Cfb3a and Cfb3b of the filter 103 are 100×10 ^-12 F, respectively. At this time, the cutoff frequency of the filter 103 becomes 1/(2π×47×10 ³ ×100×10 ^-12 )=34×10 ³ Hz. The gain G3 of the transmission band of the filter 103 becomes G3=47×10 ³ /12×10 ³ =3.9.

As described above, in the present embodiment, the first system SYSa and the second system SYSb of the charge amplifier 101 respectively have the amplifiers AMP1a, AMP1b that convert the first sensor signal SIGa and the second sensor signal SIGb, and are provided in the amplifier The holding capacitors Cos1a and Cos1b of the output paths of AMP1a and AMP1b. In addition, the first system SYSa and the second system SYSb have switches SW1a and SW1b provided in the short-circuit path, switches SW2a and SW2b provided in the feedback path, and switches SW3a and SW3b that control the application of voltage to the holding capacitors Cos1a and Cos1b, respectively . In this way, by holding the offset voltages Vos1a, Vos1b of the amplifiers AMP1a, AMP1b of the holding capacitors Cos1a, Cos1b, the offset voltages Vos1a, Vos1b can be eliminated from the outputs of the amplifiers AMP1a, AMP1b. The amplifiers AMP1a and AMP1b input the first sensor signal SIGa and the second sensor signal SIGb without switching, so they do not wait for the effects of charge feedthrough to subside in the switching between the offset hold mode and the signal output mode And switch the action mode. Therefore, in the charge amplifier 101, it is possible to suppress a decrease in the response speed due to the prolonged shift holding mode.

The MOS transistors provided at the input terminals of each of the amplifiers AMP1a and AMP1b are arranged with a common centroid. Therefore, the difference between the offset voltage Vos1a of the amplifier AMP1a and the offset voltage Vos1b of the amplifier AMP1b can be reduced.

The area of the gate electrode of the MOS transistor provided in the input terminal of each of the amplifiers AMP1a and AMP1b is larger than the area of the gate electrode of the MOS transistor provided in the input terminal of the amplifier AMP2. In the multi-stage amplifier circuit, by strengthening the noise countermeasures in the initial stage, the effect of noise reduction can be obtained.

Before and after the amplifier AMP2 of the gain amplifier 102, chopper switches SWCP1 and SWCP2 are respectively provided. Therefore, by stabilizing the chopper, the offset voltage Vos2 of the amplifier AMP2 can be eliminated.

In addition, the chopper switches SWCP1 and SWCP2 may be omitted. In this configuration, the offset voltages Vos1a and Vos1b of the charge amplifier 101 at the forefront of the multi-segment amplifier, which causes a large deviation in the output signal, can be eliminated.

Hereinafter, the circuit configuration of the signal processing circuit according to another embodiment of the present invention will be described. In addition, in the following embodiments, descriptions that are common to the above-described first embodiment will be omitted, and only differences will be described. Symbols are attached to the same constituent elements, and detailed explanations are omitted. The same effects produced by the same composition are not mentioned in order.

<Second Embodiment> Next, the circuit configuration of the charge amplifier 201 included in the signal processing circuit of the second embodiment will be described with reference to FIG. 6. FIG. 6 is a diagram schematically showing the circuit configuration of the charge amplifier of the second embodiment.

The charge amplifier 201 of the second embodiment differs from the charge amplifier 101 of the first embodiment in that detection and feedback control of the output common voltage of the input sections ISIa and ISIb are performed by a common common mode feedback circuit CMFB1. Specifically, the input terminal of the common mode feedback circuit CMFB1 is connected to the output terminal of each of the output section OS1a of the first amplifier AMP1a and the output section OS1b of the second amplifier AMP1b. The output terminal of the common mode feedback circuit CMFB1 is connected to the internal node of each of the input section IS1a of the first amplifier AMP1a and the input section IS1b of the first amplifier AMP1a. In addition, the input section IS1a corresponds to the first input section, the input section IS1b corresponds to the second input section, the output section OS1a corresponds to the first output section, and the output section OS1b corresponds to the second output section. The phase compensation capacitor Cpc1a corresponds to the first phase compensation capacitor, and the phase compensation capacitor Cpc1a corresponds to the second phase compensation capacitor.

According to this embodiment, the number of parts can be reduced. Therefore, power consumption can be reduced, and the wafer area can be reduced.

<Third Embodiment> Next, the circuit configuration of the signal processing circuit 300 of the third embodiment will be described with reference to FIG. 7. 7 is a diagram schematically showing the circuit configuration of the signal processing circuit of the third embodiment. The signal processing circuit 300 of the third embodiment includes a charge amplifier 301, a gain amplifier 302, and a filter 303 as in the first embodiment. The configuration of the gain amplifier 302 and the filter 303 is the same as the first embodiment.

The third embodiment differs from the first embodiment in omitting the storage capacitor and the switch of the charge amplifier 301. Specifically, the first system SYSa includes an amplifier AMP1a and a feedback circuit FB1a, and the second system SYSb includes an amplifier AMP1b and a feedback circuit FB1b. In the amplifiers AMP1a and AMP1b, the first sensor signal SIGa and the second sensor signal SIGb output from the sensor SEN are not input through the switch, and the first charge amplifier output signal that converts the charge value into the voltage value SIGOUT1a and the second charge amplifier output signal SIGOUT1b are output to the gain amplifier 302 without a switch. One end and the other end of the feedback circuit FB1a are respectively connected to the input terminal and the output terminal of the amplifier AMP1a without a switch, and one end and the other end of the feedback circuit FB1b are respectively connected to the input terminal and the output terminal of the amplifier AMP1b without a switch.

According to this embodiment, the charge caused by the charge feedthrough in the charge amplifier 301 is not generated. Therefore, the generation of rebound noise can be suppressed. The offset voltage of the charge amplifier 301 is not eliminated, but the offset voltage of the gain amplifier 302 can be eliminated.

<Summary> In the following, some or all of the embodiments of the present invention are appended. In addition, the present invention is not limited to the following configurations.

According to one aspect of the present invention, there is provided a signal processing circuit including: a charge amplifier that converts a pair of first and second charge signals output from a sensor into first and second voltage signals; A gain amplifier that amplifies the third and fourth voltage signals corresponding to the first and second voltage signals; and a filter that includes the fifth and sixth voltage signals corresponding to the third and fourth voltage signals The high frequency component of the attenuation; and the charge amplifier has the first and second systems connected in parallel, the first system has: a first amplifier that converts the input first charge signal into a first voltage signal; the first holding capacitor, which It is provided in the output path of the first amplifier; the first switch is provided in a short-circuit path connecting the output terminal of the first amplifier to the input terminal and short-circuiting the first amplifier; the second switch is provided in the feedback path of the first amplifier And connected in parallel to the first switch; and the third switch, one end of which is connected to the path connecting the reference voltage source of the first amplifier and the first amplifier, and the other end is connected to the path of connecting the first holding capacitor and the gain amplifier; 2 The system has: a second amplifier that converts the input second charge signal into a second voltage signal; a second holding capacitor, which is connected to the output path of the second amplifier; and a fourth switch, which is provided to connect the second amplifier The output terminal is connected to the input terminal and short-circuit path that short-circuits the second amplifier; the fifth switch, which is provided in the feedback path of the second amplifier and is connected in parallel to the fourth switch; and the sixth switch, one end of which is connected to the second The path connecting the reference voltage source of the amplifier and the second amplifier, the other end is connected to the path connecting the second holding capacitor and the gain amplifier; the first, third, fourth and sixth switches can be closed and the second and fifth The first state where the switch is open, and the second state where the first, third, fourth, and sixth switches are open and the second and fifth switches are closed. According to this, by holding the offset voltages of the first and second amplifiers by each of the first and second holding capacitors, the offset voltage can be eliminated from the output of each of the first and second amplifiers. The first and second sensor signals are input to the first and second amplifiers without the switch, and the charges caused by the charge feedthrough of the first, second, fourth, and fifth switches do not flow due to discharge To the sensor. Therefore, in the switching between the offset holding mode and the signal output mode, the operation mode is switched without being affected by the charge feedthrough. Therefore, in the charge amplifier, it is possible to suppress a decrease in the response speed due to the prolonged shift holding mode.

As an aspect, the MOS transistors included in the input terminals of each of the first and second amplifiers are arranged with a common centroid. Accordingly, the difference between the offset voltage of the first amplifier and the offset voltage of the second amplifier can be reduced.

As one aspect, the area of the gate electrode of the MOS transistor provided to the input terminal of each of the first and second amplifiers is larger than the area of the gate electrode of the MOS transistor provided to the input terminal of the gain amplifier. In the multi-stage amplifier circuit, by strengthening the noise countermeasures in the initial stage, the effect of noise reduction can be obtained.

As an example, the first amplifier has a first input section, a first output section, and a first phase compensation capacitor provided in the feedback path of the first output section, and the second amplifier has a second input section, a second output section, And the second phase compensation capacitor provided in the feedback path of the second output stage, the charge amplifier further has a common mode feedback circuit, which is connected to the output terminal of each of the first and second output stages with the input terminal, and the first and second The internal node of the second input section is connected to the output terminal. Accordingly, the number of parts can be reduced. Therefore, power consumption can be reduced, and the wafer area can be reduced.

As one aspect, the first state is obtained in an offset holding mode in which each of the first and second holding capacitors holds the offset voltage of the first and second amplifiers, and the second state is after the offset holding mode It is obtained in the signal output mode where the charge amplifier outputs the first and second voltage signals.

As one aspect, the first system further has a first feedback circuit provided in the feedback path of the first amplifier, the second system further has a second feedback circuit provided in the feedback path of the second amplifier, and the first and second feedback circuits They have feedback resistors and feedback capacitors connected in parallel.

As one aspect, the cut-off frequency set by the first feedback circuit is less than the lower band limit of the first voltage signal, and the cut-off frequency set by the second feedback circuit is less than the lower band limit of the second voltage signal.

As one aspect, the gain amplifier further includes: a third amplifier that amplifies the third and fourth voltage signals; a first chopper switch that intermittently replaces the third and fourth voltage signals input to the third amplifier ; And the second chopper switch, which again replaces the third and fourth voltage signals output from the third amplifier. According to this, the offset voltage of the amplifier of the gain amplifier can be eliminated by the stabilization of the chopper.

As an aspect, the first and second charge signals are the differential signals of the pair output from the pressure sensor or the thermal sensor.

As described above, according to one aspect of the present invention, a signal processing circuit can be provided, which can suppress the influence of the offset voltage and respond faster.

In addition, the embodiments described above are for the ease of understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed/improved without departing from the gist thereof, and the present invention also includes equivalents thereof. That is, as long as the characteristics of the present invention are provided, those having ordinary knowledge in the technical field who appropriately apply design changes to each embodiment are also included in the scope of the present invention. For example, the elements included in each embodiment and their arrangement, materials, conditions, shapes, dimensions, etc. should not be limited to the exemplified ones and can be changed as appropriate. In addition, each element included in each embodiment can be combined within a technically possible range, and those who combine these are also included in the scope of the present invention as long as the features of the present invention are included.

100: signal processing circuit SEN: Sensor SIGa: No. 1 sensor signal SIGb: the second sensor signal SIGIN1a: Input signal of the first charge amplifier SIGIN1b: Input signal of the second charge amplifier SIGOUT1a: output signal of the first charge amplifier SIGOUT1b: output signal of the second charge amplifier SIGIN2a: Input signal of the first gain amplifier SIGIN2b: Input signal of the second gain amplifier SIGOUT2a: Output signal of the first gain amplifier SIGOUT2b: output signal of the second gain amplifier SIGIN3a: input signal of the first filter SIGIN3b: input signal of the second filter SIGOUT3a: the first filter output signal SIGOUT3b: output signal of the second filter 101: Charge amplifier 102: gain amplifier 103: filter SYSa: The first system SYSb: the second system AMP1a: amplifier (first amplifier) AMP1b: amplifier (second amplifier) AMP2, AMP3: amplifier FB1a: Feedback circuit (first feedback circuit) FB1b: Feedback circuit (second feedback circuit) Cos1a: holding capacitor (first holding capacitor) Cos1b: holding capacitor (second holding capacitor) Cfb3a, Cfb3b: feedback capacitance Rfb2a, Rfb2b, Rfb3a, Rfb3b: feedback resistance Rin2a, Rin2b, Rin3a, Rin3b: resistance between segments SW1a: switch (first switch) SW2a: switch (second switch) SW3a: switch (third switch) SW1b: switch (4th switch) SW2b: Switch (5th switch) SW3b: Switch (6th switch) Vref1: reference voltage source Vref2: reference voltage source Vref3: reference voltage source

FIG. 1 is a diagram schematically showing the circuit configuration of the signal processing circuit of the first embodiment. FIG. 2 is a diagram schematically showing the circuit configuration of the charge amplifier of the first embodiment. FIG. 3 is a diagram showing the operation in the offset holding mode of the charge amplifier of the first embodiment. 4 is a diagram showing the operation in the signal output mode of the charge amplifier of the first embodiment. 5 is a diagram showing the operation of the gain amplifier according to the first embodiment. FIG. 6 is a diagram schematically showing the circuit configuration of the charge amplifier of the second embodiment. 7 is a diagram schematically showing the circuit configuration of the signal processing circuit of the third embodiment.

100: signal processing circuit 101: Charge amplifier 102: gain amplifier 103: filter AMP1a: amplifier (first amplifier) AMP1b: amplifier (second amplifier) AMP2, AMP3: amplifier Cos1a: holding capacitor (first holding capacitor) Cos1b: holding capacitor (second holding capacitor) Cfb3a, Cfb3b: feedback capacitance FB1a: Feedback circuit (first feedback circuit) FB1b: Feedback circuit (second feedback circuit) Rfb2a, Rfb2b, Rfb3a, Rfb3b: feedback resistance Rin2a, Rin2b, Rin3a, Rin3b: resistance between segments SEN: Sensor SIGa: No. 1 sensor signal SIGb: the second sensor signal SIGIN1a: Input signal of the first charge amplifier SIGIN1b: Input signal of the second charge amplifier SIGOUT1a: output signal of the first charge amplifier SIGOUT1b: output signal of the second charge amplifier SIGIN2a: Input signal of the first gain amplifier SIGIN2b: Input signal of the second gain amplifier SIGOUT2a: Output signal of the first gain amplifier SIGOUT2b: output signal of the second gain amplifier SIGIN3a: input signal of the first filter SIGIN3b: input signal of the second filter SIGOUT3a: the first filter output signal SIGOUT3b: output signal of the second filter SW1a: switch (first switch) SW2a: switch (second switch) SW3a: switch (third switch) SW1b: switch (4th switch) SW2b: Switch (5th switch) SW3b: Switch (6th switch) SWCP1, SWCP2: chopper switch SYSa: The first system SYSb: the second system Vref1: reference voltage source Vref2: reference voltage source Vref3: reference voltage source

Claims (9)

A signal processing circuit includes: a charge amplifier that converts each of a pair of first and second charge signals output from a sensor into first and second voltage signals; and a gain amplifier, which The third and fourth voltage signals corresponding to the second voltage signal are amplified, and the output terminals are connected in parallel to the feedback resistance and the inter-segment resistance; and the filter is to make the fifth and sixth voltages corresponding to the above third and fourth voltage signals The high frequency components contained in the signal are attenuated; the charge amplifier has first and second systems connected in parallel, and the first system has: a first amplifier that converts the input first charge signal into the first voltage signal A first holding capacitor, which is provided in the output path of the first amplifier; a first switch, which is provided in a short-circuit path that connects the output terminal of the first amplifier to the input terminal and short-circuits the first amplifier; the second switch , Which is provided in the feedback path of the first amplifier and connected in parallel to the first switch, the feedback path is an RC resonance circuit; and a third switch, one end of which is connected to a reference voltage connecting the first amplifier and the first amplifier The source connection path, the other end is connected to the path connecting the first holding capacitor and the gain amplifier; the second system has: a second amplifier that converts the input second charge signal into the second voltage signal; The second holding capacitor is connected to the output path of the second amplifier; the fourth switch is provided on a short-circuit path connecting the output terminal of the second amplifier to the input terminal and short-circuiting the second amplifier; the fifth switch, It is provided in the feedback path of the second amplifier and connected in parallel to the fourth switch, The feedback path is an RC resonance circuit; and a sixth switch, one end of which is connected to a path connecting the reference voltage source of the second amplifier and the second amplifier, and the other end is connected to connect the second holding capacitor to the gain amplifier Path; the first state where the first, third, fourth, and sixth switches are closed and the second and fifth switches are open, and the first, third, fourth, and sixth switches are open and the above The second state where the second and fifth switches are closed. The signal processing circuit according to claim 1, wherein the MOS transistors provided for the input terminals of each of the first and second amplifiers are arranged with a common centroid. The signal processing circuit according to claim 1 or 2, wherein the area of the gate electrode of the MOS transistor provided in the input terminal of each of the first and second amplifiers is larger than that provided in the input terminal of the gain amplifier The area of the gate electrode of the MOS transistor. The signal processing circuit according to claim 1 or 2, wherein the first amplifier has a first input stage, a first output stage, and a first phase compensation capacitor provided in the feedback path of the first output stage, the first 2 The amplifier has a second input section, a second output section, and a second phase compensation capacitor provided in the feedback path of the second output section, the charge amplifier further has a common mode feedback circuit, which is output on the first and second outputs Input terminals are connected to the output terminals of each segment, and output terminals are connected to the internal nodes of the first and second input segments. The signal processing circuit according to claim 1 or 2, wherein the first state is an offset holding mode in which each of the first and second holding capacitors holds the offset voltage of the first and second amplifiers The second state is obtained after the offset holding mode, and the first and second 2 Obtained in the signal output mode of the voltage signal. The signal processing circuit according to claim 1 or 2, wherein the first system further has a first feedback circuit provided in the feedback path of the first amplifier, and the second system further has feedback provided in the second amplifier In the second feedback circuit of the path, the first and second feedback circuits have feedback resistors and feedback capacitors connected in parallel, respectively. The signal processing circuit according to claim 6, wherein the cut-off frequency set by the first feedback circuit is less than the lower limit of the frequency band of the first voltage signal, and the cut-off frequency set by the second feedback circuit is less than the second voltage The lower limit of the frequency band of the signal. The signal processing circuit according to claim 1 or 2, wherein the gain amplifier further includes: a third amplifier that amplifies the third and fourth voltage signals; and a first chopper switch that intermittently replaces the input The third and fourth voltage signals to the third amplifier; and the second chopper switch, which replaces the third and fourth voltage signals output from the third amplifier again. The signal processing circuit according to claim 1 or 2, wherein the first and second charge signals are paired differential signals acquired from a voltage sensor or a thermal sensor.

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