TWI691031B - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
TWI691031B
TWI691031B TW105100334A TW105100334A TWI691031B TW I691031 B TWI691031 B TW I691031B TW 105100334 A TW105100334 A TW 105100334A TW 105100334 A TW105100334 A TW 105100334A TW I691031 B TWI691031 B TW I691031B
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Taiwan
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semiconductor
semiconductor package
layer
shielding layer
isolation layer
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TW105100334A
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Chinese (zh)
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TW201637156A (en
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白五賢
鞠健
高泳哲
金雲培
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南韓商三星電子股份有限公司
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Publication of TW201637156A publication Critical patent/TW201637156A/en
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Publication of TWI691031B publication Critical patent/TWI691031B/en

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Abstract

A semiconductor package includes a semiconductor chip mounted on a substrate, an insulating layer covering at least a portion of the semiconductor chip and including a thixotropic material or a hot melt material, and a shielding layer covering at least a portion of the semiconductor chip and the insulating layer. A method of manufacturing the semiconductor package includes forming an insulating layer and a shielding layer having a high aspect ratio by using a three-dimensional printer.

Description

半導體封裝及其製造方法Semiconductor package and its manufacturing method [相關申請案] [Related application]

本申請案主張於2015年1月9日在韓國智慧財產局提出申請的韓國專利申請案第10-2015-0003469號、及於2015年6月22日在韓國智慧財產局提出申請的韓國專利申請案第10-2015-0088717號的權利，所述韓國專利申請案的內容全文併入本案供參考。 This application claims Korean Patent Application No. 10-2015-0003469 filed with the Korean Intellectual Property Office on January 9, 2015, and Korean Patent Application filed with the Korean Intellectual Property Office on June 22, 2015 Case No. 10-2015-0088717, the contents of the Korean patent application are incorporated in this case for reference.

本發明是有關於一種半導體封裝及其製造方法，且更具體而言，是有關於一種包括用於保護半導體封裝中的半導體晶片不受外部因素影響並屏蔽電磁波的電磁波屏蔽構件(electromagnetic waves shielding member)的半導體封裝、及其製造方法。 The present invention relates to a semiconductor package and a manufacturing method thereof, and more specifically, to an electromagnetic wave shielding member (electromagnetic waves shielding member) for protecting a semiconductor chip in a semiconductor package from external factors and shielding electromagnetic waves )'S semiconductor package and its manufacturing method.

隨著電子產品市場的擴大，對具有更多功能性及更小的可攜式裝置的需求已迅速增加，且因此技術已使得電子產品中的 電子組件變得微型化及重量減輕。就此而言，不僅各種電子組件的大小減小，且若干分立的半導體晶片亦可置於一個半導體封裝中。具體而言，能夠處理高頻率訊號的半導體封裝不僅應被微型化，且亦應包括用於減輕電磁干擾或電磁敏感度(eletromagnetic susceptibility)的各種電磁波屏蔽結構。 With the expansion of the electronic product market, the demand for portable devices with more functionality and smaller has rapidly increased, and thus technology has made the Electronic components have become miniaturized and reduced in weight. In this regard, not only is the size of various electronic components reduced, but several discrete semiconductor chips can also be placed in one semiconductor package. Specifically, a semiconductor package capable of handling high-frequency signals should not only be miniaturized, but also include various electromagnetic wave shielding structures for mitigating electromagnetic interference or electromagnetic susceptibility.

本發明提供一種半導體封裝，所述半導體封裝包括電磁波屏蔽結構，所述電磁波屏蔽結構使所述半導體封裝能夠微型化及重量減輕，且亦對於電磁干擾具有極佳屏蔽特性。 The present invention provides a semiconductor package including an electromagnetic wave shielding structure that enables the semiconductor package to be miniaturized and weight-reduced, and also has excellent shielding characteristics against electromagnetic interference.

其他態樣將在以下說明中予以部分闡述，且這些態樣將藉由所述說明而部分地變得顯而易見，抑或可藉由實踐所提供的示例性實施例而得知。 Other aspects will be partially explained in the following description, and these aspects will become partially apparent from the description, or may be known by practicing the exemplary embodiments provided.

根據示例性實施例的態樣，一種半導體封裝包括：半導體晶片，裝設於基板上；以及屏蔽層，覆蓋所述半導體晶片的至少一部分；其中所述屏蔽層的側表面部分的厚度小於所述屏蔽層的所述側表面部分的高度。 According to an aspect of an exemplary embodiment, a semiconductor package includes: a semiconductor wafer mounted on a substrate; and a shielding layer covering at least a portion of the semiconductor wafer; wherein a thickness of a side surface portion of the shielding layer is smaller than the The height of the side surface portion of the shield layer.

所述半導體封裝可包括多晶片封裝(multi-chip package，MCP)。 The semiconductor package may include a multi-chip package (MCP).

所述屏蔽層的所述側表面部分的所述厚度可小於所述屏蔽層的側表面部分的高度的五分之一。 The thickness of the side surface portion of the shielding layer may be less than one fifth of the height of the side surface portion of the shielding layer.

所述屏蔽層的上表面與所述屏蔽層的側表面形成實質上 90°的角度。 The upper surface of the shielding layer and the side surface of the shielding layer form substantially 90° angle.

所述屏蔽層可包括邊緣，所述屏蔽層的上表面與所述屏蔽層的側表面在所述邊緣上彼此接觸，所述邊緣具有預定曲率半徑(radius of curvature)，且所述預定曲率半徑可小於所述屏蔽層的所述上表面的厚度與所述屏蔽層的所述側表面的厚度之和。 The shielding layer may include an edge on which an upper surface of the shielding layer and a side surface of the shielding layer are in contact with each other, the edge has a predetermined radius of curvature, and the predetermined radius of curvature It may be smaller than the sum of the thickness of the upper surface of the shield layer and the thickness of the side surface of the shield layer.

所述半導體封裝可更包括位於所述半導體晶片與所述屏蔽層之間的隔離層，所述隔離層包含觸變材料(thixotropic material)或熱熔材料(hot melt material)。 The semiconductor package may further include an isolation layer between the semiconductor wafer and the shielding layer, the isolation layer including a thixotropic material or a hot melt material.

所述觸變材料可包括以下中的至少一者：複合精細氧化矽(composite fine silica)、膨土(bentonite)、表面經處理的碳酸鈣的細粒、氫化蓖麻油(hydrogenated castor oil)、金屬皂(metal soap)、硬脂酸鋁、聚醯胺蠟(polyamide wax)、氧化聚乙烯(oxidized polyethylene)、及亞麻籽聚合油(linseed polymerized oil)。 The thixotropic material may include at least one of: composite fine silica, bentonite, fine particles of surface-treated calcium carbonate, hydrogenated castor oil, metal Soap (metal soap), aluminum stearate, polyamide wax, oxidized polyethylene, and linseed polymerized oil.

所述熱熔材料可包括以下中的至少一者：聚氨酯、聚脲、聚氯乙烯、聚苯乙烯、丙烯腈-丁二烯-苯乙烯(acrylonitrile butadiene styrene，ABS)、聚醯胺、丙烯酸、及聚對苯二甲酸丁二酯(polybutylene terephthalate，PBTP)。 The hot-melt material may include at least one of the following: polyurethane, polyurea, polyvinyl chloride, polystyrene, acrylonitrile butadiene styrene (ABS), polyamide, acrylic, And polybutylene terephthalate (PBTP).

所述觸變材料或所述熱熔材料可藉由紫外光固化(ultraviolet curing)或熱固化(heat curing)而固化。 The thixotropic material or the hot-melt material may be cured by ultraviolet curing or heat curing.

所述屏蔽層可為金屬材料。 The shielding layer may be a metal material.

所述屏蔽層及所述隔離層中的至少一者可藉由三維印刷(three-dimensional printing)形成。 At least one of the shielding layer and the isolation layer may be formed by three-dimensional printing.

所述半導體封裝可包括在行動電話中使用的應用程式處理器(application processor，AP)。 The semiconductor package may include an application processor (AP) used in a mobile phone.

根據另一示例性實施例的態樣，一種半導體封裝包括：半導體晶片，裝設於基板上；隔離層，覆蓋所述半導體晶片的至少一部分，且其中所述隔離層可為觸變材料或熱熔材料；以及屏蔽層，覆蓋所述半導體晶片及所述隔離層。 According to an aspect of another exemplary embodiment, a semiconductor package includes: a semiconductor wafer mounted on a substrate; an isolation layer covering at least a portion of the semiconductor wafer, and wherein the isolation layer may be a thixotropic material or heat Molten material; and a shielding layer covering the semiconductor wafer and the isolation layer.

所述觸變材料可包括以下中的至少一者：複合精細氧化矽、膨土、表面經處理的碳酸鈣的細粒、氫化蓖麻油、金屬皂、硬脂酸鋁、聚醯胺蠟、氧化聚乙烯、及亞麻籽聚合油。 The thixotropic material may include at least one of the following: composite fine silica, bentonite, fine particles of surface-treated calcium carbonate, hydrogenated castor oil, metal soap, aluminum stearate, polyamide wax, oxidation Polyethylene, and linseed polymer oil.

所述熱熔材料可包括以下中的至少一者：聚氨酯、聚脲、聚氯乙烯、聚苯乙烯、丙烯腈-丁二烯-苯乙烯、聚醯胺、丙烯酸、及聚對苯二甲酸丁二酯。 The hot melt material may include at least one of the following: polyurethane, polyurea, polyvinyl chloride, polystyrene, acrylonitrile-butadiene-styrene, polyamide, acrylic acid, and polybutylene terephthalate Diester.

所述觸變材料或所述熱熔材料可藉由紫外光固化或熱固化而固化。 The thixotropic material or the hot melt material can be cured by ultraviolet light curing or thermal curing.

所述屏蔽層可包含金屬材料。 The shielding layer may include a metal material.

所述隔離層的厚度與所述屏蔽層的厚度之和可小於所述隔離層的高度。 The sum of the thickness of the isolation layer and the thickness of the shielding layer may be smaller than the height of the isolation layer.

所述隔離層的厚度與所述屏蔽層的厚度之和可小於所述隔離層的高度的五分之一。 The sum of the thickness of the isolation layer and the thickness of the shielding layer may be less than one fifth of the height of the isolation layer.

所述半導體封裝可包括以下中的至少一者：應用程式處理器、顯示驅動器積體電路(display driver integrated circuit)、計時控制器(timing controller)及電源模組積體電路(power module integrated circuit)。 The semiconductor package may include at least one of the following: an application processor, a display driver integrated circuit, a timing controller, and a power module integrated circuit integrated circuit).

所述隔離層及所述屏蔽層中的至少一者可藉由三維印刷形成。 At least one of the isolation layer and the shielding layer may be formed by three-dimensional printing.

所述隔離層及所述屏蔽層中的至少一者可藉由材料供應裝置形成，所述材料供應裝置包括開口，所述開口具有與所述隔離層及所述屏蔽層中對應的一者的側表面形狀相同的形狀。 At least one of the isolation layer and the shielding layer may be formed by a material supply device including an opening having one corresponding to the isolation layer and the shielding layer The shape of the side surface is the same shape.

所述隔離層覆蓋所述半導體晶片的至少一部分。 The isolation layer covers at least a part of the semiconductor wafer.

所述半導體晶片可包括第一半導體晶片及第二半導體晶片，所述第一半導體晶片與所述第二半導體晶片可在所述基板上對齊，且所述隔離層可夾置於所述第一半導體晶片與所述第二半導體晶片之間。 The semiconductor wafer may include a first semiconductor wafer and a second semiconductor wafer, the first semiconductor wafer and the second semiconductor wafer may be aligned on the substrate, and the isolation layer may be sandwiched between the first Between the semiconductor wafer and the second semiconductor wafer.

根據另一示例性實施例的態樣，一種半導體封裝包括：封裝基板，經由連接端子而連接至印刷電路板(printed circuit board，PCB)；多個半導體晶片，以多層結構堆疊於所述封裝基板上；隔離層，覆蓋所述多個半導體晶片的至少一部分、且包括觸變材料或熱熔材料；以及屏蔽層，覆蓋所述隔離層及所述多個半導體晶片的至少一部分，其中所述屏蔽層的側表面部分的厚度小於所述屏蔽層的側表面部分的高度。 According to an aspect of another exemplary embodiment, a semiconductor package includes: a package substrate connected to a printed circuit board (PCB) via a connection terminal; a plurality of semiconductor wafers stacked on the package substrate in a multilayer structure Upper; an isolation layer covering at least a portion of the plurality of semiconductor wafers and including a thixotropic material or a hot-melt material; and a shielding layer covering the isolation layer and at least a portion of the plurality of semiconductor wafers, wherein the shielding The thickness of the side surface portion of the layer is less than the height of the side surface portion of the shield layer.

所述多個半導體晶片中的每一者可包括貫通電極(through-electrode)，且所述多個半導體晶片中的每一者經由所述貫通電極而連接至所述多個半導體晶片中的至少另一者。 Each of the plurality of semiconductor wafers may include a through-electrode, and each of the plurality of semiconductor wafers is connected to at least one of the plurality of semiconductor wafers via the through-electrode The other.

所述半導體封裝可更包括導線，所述導線將所述多個半 導體晶片連接至所述封裝基板，其中所述導線用以在所述多個半導體晶片與所述封裝基板之間傳輸電訊號。 The semiconductor package may further include a wire, the wire The conductor chip is connected to the packaging substrate, wherein the wire is used to transmit electrical signals between the plurality of semiconductor chips and the packaging substrate.

所述屏蔽層的所述側表面部分的所述厚度可小於所述屏蔽層的所述高度的五分之一。 The thickness of the side surface portion of the shielding layer may be less than one fifth of the height of the shielding layer.

所述觸變材料可包括以下中的至少一者：複合精細氧化矽、膨土、表面經處理的碳酸鈣的細粒、氫化蓖麻油、金屬皂、硬脂酸鋁、聚醯胺蠟、氧化聚乙烯、及亞麻籽聚合油。 The thixotropic material may include at least one of the following: composite fine silica, bentonite, fine particles of surface-treated calcium carbonate, hydrogenated castor oil, metal soap, aluminum stearate, polyamide wax, oxidation Polyethylene, and linseed polymer oil.

所述熱熔材料可包括以下中的至少一者：聚氨酯、聚脲、聚氯乙烯、聚苯乙烯、丙烯腈-丁二烯-苯乙烯、聚醯胺、丙烯酸、及聚對苯二甲酸丁二酯。 The hot melt material may include at least one of the following: polyurethane, polyurea, polyvinyl chloride, polystyrene, acrylonitrile-butadiene-styrene, polyamide, acrylic acid, and polybutylene terephthalate Diester.

所述隔離層及所述屏蔽層中的至少一者是藉由材料供應裝置形成，所述材料供應裝置包括開口，所述開口具有與所述隔離層及所述屏蔽層中對應的一者的側表面形狀相同的形狀。 At least one of the isolation layer and the shielding layer is formed by a material supply device including an opening having one corresponding to the isolation layer and the shielding layer The shape of the side surface is the same shape.

根據另一示例性實施例的態樣，一種半導體封裝包括：印刷電路板；第一半導體封裝，形成於所述印刷電路板上，且包括經由第一連接端子而連接至所述印刷電路板的第一封裝基板、及裝設於所述第一封裝基板上的第一半導體晶片；第二半導體封裝，形成於所述第一封裝基板上，且包括經由第二連接端子而連接至所述第一封裝基板的第二封裝基板、及以多層結構堆疊於所述第二封裝基板上的多個第二半導體晶片；隔離層，覆蓋所述第一半導體封裝的側表面及所述第二半導體封裝的側表面的至少一部分，且包括觸變材料或熱熔材料；以及屏蔽層，覆蓋所述第一半導體封裝 的所述側表面以及所述第二半導體封裝的上表面及所述側表面的至少一部分，其中所述屏蔽層的側表面部分的厚度小於所述屏蔽層的高度。 According to an aspect of another exemplary embodiment, a semiconductor package includes: a printed circuit board; a first semiconductor package formed on the printed circuit board and including a device connected to the printed circuit board via a first connection terminal A first package substrate, and a first semiconductor chip mounted on the first package substrate; a second semiconductor package is formed on the first package substrate, and includes connecting to the first package via a second connection terminal A second package substrate of a package substrate, and a plurality of second semiconductor chips stacked on the second package substrate in a multilayer structure; an isolation layer covering the side surface of the first semiconductor package and the second semiconductor package At least a part of the side surface of and including a thixotropic material or a hot-melt material; and a shielding layer covering the first semiconductor package And at least a portion of the upper surface and the side surface of the second semiconductor package, wherein the thickness of the side surface portion of the shielding layer is less than the height of the shielding layer.

所述半導體封裝可更包括導線，所述導線將所述多個第二半導體晶片連接至所述第二封裝基板，其中所述導線用以在所述多個第二半導體晶片與所述第二封裝基板之間傳輸電訊號。 The semiconductor package may further include a wire connecting the plurality of second semiconductor chips to the second packaging substrate, wherein the wire is used to connect the plurality of second semiconductor chips and the second Transmission of electrical signals between package substrates.

根據另一示例性實施例的態樣，一種製造半導體封裝的方法包括：將半導體晶片裝設於基板上；形成覆蓋所述半導體晶片的至少一部分的隔離層，所述隔離層包含觸變材料或熱熔材料；以及形成屏蔽層，所述屏蔽層覆蓋所述隔離層及所述半導體晶片的至少一部分。 According to an aspect of another exemplary embodiment, a method of manufacturing a semiconductor package includes: mounting a semiconductor wafer on a substrate; forming an isolation layer covering at least a portion of the semiconductor wafer, the isolation layer containing a thixotropic material or Hot-melt material; and forming a shielding layer that covers the isolation layer and at least a portion of the semiconductor wafer.

所述觸變材料可包括以下中的至少一者：複合精細氧化矽、膨土、表面經處理的碳酸鈣的細粒、氫化蓖麻油、金屬皂、硬脂酸鋁、聚醯胺蠟、氧化聚乙烯、及亞麻籽聚合油。 The thixotropic material may include at least one of the following: composite fine silica, bentonite, fine particles of surface-treated calcium carbonate, hydrogenated castor oil, metal soap, aluminum stearate, polyamide wax, oxidation Polyethylene, and linseed polymer oil.

所述熱熔材料可包括以下中的至少一者：聚氨酯、聚脲、聚氯乙烯、聚苯乙烯、丙烯腈-丁二烯-苯乙烯、聚醯胺、丙烯酸、及聚對苯二甲酸丁二酯。 The hot melt material may include at least one of the following: polyurethane, polyurea, polyvinyl chloride, polystyrene, acrylonitrile-butadiene-styrene, polyamide, acrylic acid, and polybutylene terephthalate Diester.

可藉由紫外光固化或熱固化來固化所述觸變材料或所述熱熔材料。 The thixotropic material or the hot melt material may be cured by ultraviolet light curing or thermal curing.

所述屏蔽層可包含金屬材料。 The shielding layer may include a metal material.

所述隔離層的厚度與所述屏蔽層的厚度之和可小於所述隔離層的高度。 The sum of the thickness of the isolation layer and the thickness of the shielding layer may be smaller than the height of the isolation layer.

所述隔離層的厚度與所述屏蔽層的厚度之和可小於所述隔離層的高度的五分之一。 The sum of the thickness of the isolation layer and the thickness of the shielding layer may be less than one fifth of the height of the isolation layer.

所述隔離層或所述屏蔽層中的至少一者可藉由材料供應裝置形成，所述材料供應裝置包括開口，所述開口具有與所述隔離層及所述屏蔽層中對應的一者的側表面形狀相同的形狀。 At least one of the isolation layer or the shielding layer may be formed by a material supply device including an opening having one corresponding to the isolation layer and the shielding layer The shape of the side surface is the same shape.

所述屏蔽層及所述隔離層中的至少一者可藉由三維印刷形成。 At least one of the shielding layer and the isolation layer may be formed by three-dimensional printing.

根據另一示例性實施例的態樣，一種行動電話包括：通訊模組，用以自伺服器接收應用程式的安裝資料；記憶體模組，用以儲存所述應用程式的所述所接收的安裝資料；以及應用程式處理器，用以基於所述應用程式的所述安裝資料而將所述應用程式安裝於所述行動電話上、並執行所述行動電話上的所述所安裝的應用程式，其中所述應用程式處理器及所述記憶體模組中的至少一者包括半導體封裝及屏蔽層，所述半導體封裝包括裝設於基板上的半導體晶片，所述屏蔽層覆蓋所述半導體晶片，其中所述屏蔽層的側表面部分的厚度小於所述屏蔽層的所述側表面部分的高度。 According to an aspect of another exemplary embodiment, a mobile phone includes: a communication module to receive installation data of an application from a server; and a memory module to store the received data of the application Installation data; and an application processor for installing the application on the mobile phone based on the installation data of the application and executing the installed application on the mobile phone , Wherein at least one of the application processor and the memory module includes a semiconductor package and a shielding layer, the semiconductor package includes a semiconductor chip mounted on a substrate, the shielding layer covers the semiconductor chip , Wherein the thickness of the side surface portion of the shielding layer is less than the height of the side surface portion of the shielding layer.

所述屏蔽層的所述側表面部分的所述厚度可小於所述屏蔽層的所述側表面部分的所述高度的五分之一。 The thickness of the side surface portion of the shield layer may be less than one fifth of the height of the side surface portion of the shield layer.

所述行動電話可更包括位於所述半導體晶片與所述屏蔽層之間的隔離層，所述隔離層包含觸變材料或熱熔材料。 The mobile phone may further include an isolation layer between the semiconductor wafer and the shielding layer, the isolation layer including a thixotropic material or a hot-melt material.

根據另一示例性實施例的態樣，一種三維列印機包括：晶片運輸單元(chip transportation unit)，用以在第一方向上運輸基 板及裝設於所述基板上的半導體晶片；分配頭單元(dispensing head unit)，用以藉由經由分配製程(dispensing process)將屏蔽材料及絕緣材料分別注射至所述半導體晶片的上表面及側表面上而形成屏蔽層及隔離層；以及頭運輸單元(head transportation unit)，用以在所述第一方向、與所述第一方向垂直的第二方向、及與所述第一方向及所述第二方向中的每一者垂直的第三方向上運輸所述分配頭單元。所述屏蔽材料及所述絕緣材料中的每一者包括觸變材料或熱熔材料，且所述屏蔽層的側表面部分的厚度與所述隔離層的側表面部分的厚度之和小於所述屏蔽層的所述側表面部分的高度。 According to an aspect of another exemplary embodiment, a three-dimensional printing machine includes: a chip transportation unit (chip transportation unit) for transporting a substrate in a first direction A board and a semiconductor chip mounted on the substrate; a dispensing head unit (dispensing head unit) for injecting a shielding material and an insulating material to the upper surface of the semiconductor wafer by a dispensing process (dispensing process) Forming a shielding layer and an isolation layer on the side surface; and a head transportation unit (head transportation unit) for the first direction, the second direction perpendicular to the first direction, and the first direction and A vertical third party in each of the second directions transports the dispensing head unit upward. Each of the shielding material and the insulating material includes a thixotropic material or a hot-melt material, and the sum of the thickness of the side surface portion of the shielding layer and the thickness of the side surface portion of the isolation layer is smaller than the The height of the side surface portion of the shield layer.

所述分配頭單元可包括：第一注射幫浦，用以容納具有觸變特性或熱熔特性的所述屏蔽材料；以及第一噴嘴，用以藉由將所述屏蔽材料注射至所述半導體晶片的所述上表面上、並以所述屏蔽材料對所述半導體晶片的所述上表面進行塗佈來形成所述屏蔽層。 The dispensing head unit may include: a first injection pump for accommodating the shielding material having thixotropic or hot-melt characteristics; and a first nozzle for injecting the shielding material into the semiconductor The upper surface of the wafer is coated with the shielding material to form the shielding layer.

所述分配頭單元可包括：第二注射幫浦，用以容納具有觸變特性或熱熔特性的所述絕緣材料；以及第二噴嘴，用以藉由將所述絕緣材料注射至所述半導體晶片的所述側表面上來形成所述隔離層。 The dispensing head unit may include: a second injection pump for accommodating the insulating material having thixotropic or hot-melt characteristics; and a second nozzle for injecting the insulating material to the semiconductor The isolation layer is formed on the side surface of the wafer.

所述三維列印機可更包括光源，所述光源用以藉由熱固化或紫外光固化來對所述屏蔽材料及所述絕緣材料進行固化。 The three-dimensional printing machine may further include a light source for curing the shielding material and the insulating material by thermal curing or ultraviolet curing.

100、100a、100b、100c、100d、100e、100f、100g、100h:半導體封裝 100, 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h: semiconductor package

110、110b、110d、110e、110f、110g、110h、112d:隔離層 110, 110b, 110d, 110e, 110f, 110g, 110h, 112d: isolation layer

112e、112f、112g:塑模單元 112e, 112f, 112g: Molding unit

114h:底填充構件 114h: Underfill member

120、120a、120b、120c、120d、120e、120f、120g、120h:屏蔽層 120, 120a, 120b, 120c, 120d, 120e, 120f, 120g, 120h: shielding layer

120edge:邊緣 120edge: edge

120edge’:邊緣 120edge’: Edge

120r:曲率半徑 120r: radius of curvature

120t:厚度 120t: thickness

130、130a、130d、130g、130h、131b、131c、131d、131e、131f、132b、132c、132d、132e、132f、133e、133f、135g、136g:半導體晶片 130, 130a, 130d, 130g, 130h, 131b, 131c, 131d, 131e, 131f, 132b, 132c, 132d, 132e, 132f, 133e, 133f, 135g, 136g: semiconductor wafer

131g:第一半導體封裝 131g: the first semiconductor package

132g:第二半導體封裝 132g: Second semiconductor package

140、140a、140b、140c、140e、140f、140h:封裝基板 140, 140a, 140b, 140c, 140e, 140f, 140h: package substrate

140d:基板 140d: substrate

140g:第一封裝基板 140g: the first package substrate

142g:第二封裝基板 142g: second package substrate

150、150a、150b、150d、150e、150f、150h、151、151a、151b、151c、151d、151e、151f、151g、151h、152b、152c、152d、152e、152g、152h、153g、154e、154f、154g、154h:接觸焊墊 150, 150a, 150b, 150d, 150e, 150f, 150h, 151, 151a, 151b, 151c, 151d, 151e, 151f, 151g, 151h, 152b, 152c, 152d, 152e, 152g, 152h, 153g, 154e, 154f, 154g, 154h: contact pad

150g:接地單元 150g: grounding unit

153e:貫通電極 153e: through electrode

160e、160f、160g、160h:印刷電路板 160e, 160f, 160g, 160h: printed circuit board

171e、171f、171g:第一層間隔離層 171e, 171f, 171g: the first interlayer isolation layer

172e、172f、172g:第二層間隔離層 172e, 172f, 172g: second layer isolation layer

173e、173f:第三層間隔離層 173e, 173f: third interlayer isolation layer

181f、181g、182f、182g:導線 181f, 181g, 182f, 182g: wire

200、200a、200b:半導體晶片 200, 200a, 200b: semiconductor wafer

210:隔離層 210: isolation layer

210’:絕緣材料 210’: insulating material

210a、210b、212a、212b:觸變材料 210a, 210b, 212a, 212b: thixotropic materials

220:屏蔽層 220: shielding layer

230、240:連接焊墊 230, 240: connection pad

300:三維列印機 300: 3D printer

300A:分配頭單元 300A: distribution head unit

310:幫浦結構 310: Pump structure

312:幫浦結構 312: Pump structure

322:注射單元 322: Injection unit

324:管 324: Tube

326:螺鑽幫浦 326: Screw drill pump

328:旋轉環 328: Rotating ring

330、330’、330a、330b、332:噴嘴 330, 330’, 330a, 330b, 332: nozzle

334:塗佈分配器 334: coating dispenser

336:開口 336: opening

340:光源 340: Light source

350:框架單元 350: frame unit

360:頭運輸單元 360: head transport unit

370:晶片運輸單元 370: Wafer transport unit

380:量測單元 380: Measuring unit

1000:半導體封裝 1000: semiconductor package

1100:半導體封裝 1100: Semiconductor packaging

1110:微處理單元 1110: Microprocessing unit

1120:記憶體模組 1120: Memory module

1130:介面 1130: Interface

1140:圖形處理單元 1140: Graphics processing unit

1150:功能區塊 1150: Functional block

1160:匯流排 1160: busbar

1200:電子系統 1200: Electronic system

1210:微處理單元/圖形處理單元 1210: Microprocessing unit/graphics processing unit

1220:記憶體裝置 1220: Memory device

1230:輸入/輸出裝置 1230: Input/output device

1240:顯示裝置 1240: display device

1250:匯流排 1250: bus

1300:行動電話 1300: Mobile phone

1310:半導體封裝 1310: Semiconductor packaging

A15:部分 A15: Part

a:距離 a: distance

a”:厚度 a”: thickness

a'''、a'''':厚度之和 a''', a'''': sum of thickness

b、b’、b”、b'''、b'''':高度 b, b’, b", b''', b'''': height

X、Y、Z:方向 X, Y, Z: direction

Figure 105100334-A0305-02-0044-1
:第一曲線
Figure 105100334-A0305-02-0044-1
: First curve

Figure 105100334-A0305-02-0044-2
:第二曲線
Figure 105100334-A0305-02-0044-2
: Second curve

△time:時移 △time: time shift

藉由結合附圖閱讀示例性實施例的以下說明，這些及/或其他態樣將變得顯而易見且更易於理解，在附圖中：圖1是根據示例性實施例的半導體封裝的剖視圖。 These and/or other aspects will become apparent and easier to understand by reading the following description of the exemplary embodiment in conjunction with the drawings. In the drawings: FIG. 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖2A及圖2B是用於闡述包含於根據示例性實施例的半導體封裝中的觸變材料的狀態的圖。 2A and 2B are diagrams for explaining the state of the thixotropic material included in the semiconductor package according to the exemplary embodiment.

圖3是根據示例性實施例的半導體封裝的剖視圖。 FIG. 3 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖4是根據示例性實施例的半導體封裝的剖視圖。 4 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖5是根據示例性實施例的半導體封裝的剖視圖。 5 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖6是根據示例性實施例的半導體封裝的剖視圖。 6 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖7是根據示例性實施例的半導體封裝的剖視圖。 7 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖8是根據示例性實施例的半導體封裝的剖視圖。 8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖9是根據示例性實施例的半導體封裝的剖視圖。 9 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖10是根據示例性實施例的半導體封裝的剖視圖。 FIG. 10 is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

圖11A至圖11E是用於闡述根據示例性實施例的一種製造半導體封裝的製程的圖。 11A to 11E are diagrams for explaining a manufacturing process of a semiconductor package according to an exemplary embodiment.

圖12是根據示例性實施例的用於製造半導體封裝的三維(three-dimensional，3D)列印機的立體圖。 FIG. 12 is a perspective view of a three-dimensional (3D) printer for manufacturing a semiconductor package according to an exemplary embodiment.

圖13是用於闡述根據示例性實施例的用於製造半導體封裝的三維列印機的概念圖。 FIG. 13 is a conceptual diagram for explaining a three-dimensional printer for manufacturing a semiconductor package according to an exemplary embodiment.

圖14是用於闡述根據示例性實施例的一種用於製造半導體封裝的三維列印機的運作方法的圖。 FIG. 14 is a diagram for explaining an operation method of a three-dimensional printer for manufacturing a semiconductor package according to an exemplary embodiment.

圖15A及圖15B是用於闡述根據示例性實施例的一種製造半導體封裝的方法的圖。 15A and 15B are diagrams for explaining a method of manufacturing a semiconductor package according to an exemplary embodiment.

圖16A及圖16B是用於闡述根據示例性實施例的一種製造半導體封裝的方法的圖。 16A and 16B are diagrams for explaining a method of manufacturing a semiconductor package according to an exemplary embodiment.

圖17是根據示例性實施例的半導體封裝的結構的示意圖。 17 is a schematic diagram of the structure of a semiconductor package according to an exemplary embodiment.

圖18是根據示例性實施例的包括半導體封裝的電子系統的圖。 FIG. 18 is a diagram of an electronic system including a semiconductor package according to an exemplary embodiment.

圖19是根據示例性實施例的其中應用有半導體封裝的電子裝置的示意性立體圖。 FIG. 19 is a schematic perspective view of an electronic device in which a semiconductor package is applied according to an exemplary embodiment.

現在將參照其中示出各種實施例的元件的附圖更充分地闡述本發明的各種實施例。本發明可實施為諸多不同形式、而不應被視為僅限於本文所說明的示例性實施例。更確切而言，提供這些實施例是為了使此揭露內容將透徹及完整，且將向此項技術中具有通常知識者充分傳達本發明的範圍。通篇中相同的參考編號指代相同的元件。在圖式中，為清晰起見，可誇大層及區的厚度以及組件的大小。亦應理解，示出每一細節的詳細圖式可能是不可行的。因此，當示出元件時，應理解其可為近似形式或聚合形式。舉例而言，若示出接觸焊墊，則所述接觸焊墊可代表大量單獨的接觸焊墊。 Various embodiments of the invention will now be explained more fully with reference to the drawings in which the elements of various embodiments are shown. The invention can be implemented in many different forms and should not be considered as limited to the exemplary embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those of ordinary skill in the art. The same reference numbers refer to the same elements throughout. In the drawings, the thickness of layers and regions and the size of components can be exaggerated for clarity. It should also be understood that a detailed drawing showing every detail may not be feasible. Therefore, when an element is shown, it should be understood that it may be in an approximate form or an aggregate form. For example, if a contact pad is shown, the contact pad may represent a large number of individual contact pads.

應理解，當稱一元件(例如層、區或基板)位於另一元件「上(on)」、「連接至(connected to)」或「耦合至(coupled to)」 另一元件時，所述元件可直接位於所述另一元件上、連接至或耦合至所述另一元件，抑或可存在中間元件。相比之下，當稱一元件「直接(directly)」位於另一元件或層「上(on)」、「直接連接至(directly connected to)」或「直接耦合至(directly coupled to)」另一元件或層時，則不存在中間元件或層。其他用於闡述元件或層之間關係的用詞應以相同的方式加以解釋(例如，「位於...之間(between)」相對於「直接位於...之間(directly between)」、「臨近(adjacent)」相對於「直接臨近(directly adjacent)」等)。 It should be understood that when an element (such as a layer, region, or substrate) is said to be "on", "connected to", or "coupled to" another element In the case of another element, the element may be directly on, connected to, or coupled to the other element, or an intermediate element may be present. In contrast, when a component is said to be "directly" on another component or layer "on", "directly connected to" or "directly coupled to" another For an element or layer, there are no intermediate elements or layers. Other terms used to explain the relationship between components or layers should be interpreted in the same way (for example, "between" versus "directly between", "Adjacent" is relative to "directly adjacent" etc.).

應理解，儘管可能使用用語「第一(first)」、「第二(second)」、「第三(third)」等來闡述各種元件、組件、區、層、及/或區段，然而這些元件、組件、區、層、及/或區段不應受限於這些用語。這些用語僅用於區分各個元件、組件、區、層或區段。因此，下文所述的第一元件、組件、區、層或區段可被稱為第二元件、組件、區、層或區段而不背離示例性實施例的教示內容。 It should be understood that although the terms "first", "second", "third", etc. may be used to describe various elements, components, regions, layers, and/or sections, these Elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish individual elements, components, regions, layers or sections. Therefore, the first element, component, region, layer or section described below may be referred to as the second element, component, region, layer or section without departing from the teachings of the exemplary embodiments.

除非上下文中清楚地另外指明，否則本文所用的單數形式「一」及「所述」旨在亦包括複數形式。更應理解，本文中使用用語「包括(comprises及/或comprising)」是表明所陳述的特徵、整數、步驟、操作、構件、組件及/或其群組的存在，但不排除一或多個其他特徵、整數、步驟、操作、構件、組件及/或其群組的存在或添加。本文所用的用語「及/或」包括相關所列項中一或多者的任意及所有組合。例如「...中的至少一者」等表達在位於一系列元件之前時，是修飾整個系列元件而非修飾所述系列的各別元 件。 Unless the context clearly indicates otherwise, the singular forms "a" and "said" as used herein are intended to include the plural forms as well. It should be further understood that the term "comprises and/or comprising" is used herein to indicate the existence of the stated features, integers, steps, operations, components, components, and/or groups thereof, but does not exclude one or more The presence or addition of other features, integers, steps, operations, components, components, and/or groups thereof. The term "and/or" as used herein includes any and all combinations of one or more of the relevant listed items. Expressions such as "at least one of" before a series of elements modify the entire series of elements rather than the individual elements of the series Pieces.

除非在本發明中另有定義，否則本文中所使用的所有用語(包括技術及科學用語)的意義皆與示例性實施例所屬技術域中具有通常知識者所通常理解的意義相同。 Unless otherwise defined in the present invention, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those with ordinary knowledge in the technical field to which the exemplary embodiments belong.

在下文中，將詳細闡述本發明的示例性實施例。 Hereinafter, exemplary embodiments of the present invention will be explained in detail.

圖1是根據示例性實施例的半導體封裝100的剖視圖。參照圖1，半導體封裝100經由接觸焊墊150及接觸焊墊151而結合至封裝基板140的上表面。接觸焊墊150可形成為使半導體晶片130接地，且接觸焊墊151可形成為使半導體晶片130接地或傳輸訊號。接觸焊墊亦可稱為連接端子。 FIG. 1 is a cross-sectional view of a semiconductor package 100 according to an exemplary embodiment. Referring to FIG. 1, the semiconductor package 100 is bonded to the upper surface of the package substrate 140 via the contact pad 150 and the contact pad 151. The contact pad 150 may be formed to ground the semiconductor wafer 130, and the contact pad 151 may be formed to ground the semiconductor wafer 130 or transmit signals. Contact pads can also be called connection terminals.

在半導體封裝100中，半導體晶片130及隔離層110可安置於封裝基板140上，且隔離層110可安置成鄰近屏蔽層120的內側表面及接觸焊墊150的內側表面。因此，屏蔽層120可覆蓋半導體晶片130及隔離層110。屏蔽層120亦可連接至接觸焊墊150，且隔離層110可形成為將半導體晶片130與接觸焊墊150彼此分隔開。 In the semiconductor package 100, the semiconductor wafer 130 and the isolation layer 110 may be disposed on the packaging substrate 140, and the isolation layer 110 may be disposed adjacent to the inner surface of the shield layer 120 and the inner surface of the contact pad 150. Therefore, the shielding layer 120 can cover the semiconductor wafer 130 and the isolation layer 110. The shielding layer 120 may also be connected to the contact pad 150, and the isolation layer 110 may be formed to separate the semiconductor wafer 130 and the contact pad 150 from each other.

本發明中所使用的「覆蓋(cover)」未必表示僅位於某物上方。覆蓋物體XYZ的物體ABC一般可表示物體ABC鄰近物體XYZ的表面，而無論ABC是否與物體XYZ間隔開距離。因此，當ABC位於XYZ下方、靠近XYZ、位於XYZ上方及ABC圍繞XYZ之任意組合時，可稱ABC覆蓋XYZ。 The "cover" used in the present invention does not necessarily mean that it is just above something. The object ABC covering the object XYZ can generally represent the surface of the object ABC adjacent to the object XYZ, regardless of whether ABC is spaced apart from the object XYZ. Therefore, when ABC is below XYZ, close to XYZ, above XYZ, and any combination of ABC around XYZ, ABC can be said to cover XYZ.

半導體封裝100可具有例如矽貫通孔(through silicon via， TSV)結構、多晶片封裝(MCP)結構或堆疊式封裝(package on package，PoP)結構。此外，半導體封裝100可包含於應用程式處理器、顯示驅動器積體電路(integrated circuit，IC)、計時控制器或電源模組積體電路中。此外，半導體封裝100可包含於智慧型電話、顯示設備或可穿戴裝置中。 The semiconductor package 100 may have, for example, through silicon via (through silicon via, TSV) structure, multi-chip package (MCP) structure or package on package (PoP) structure. In addition, the semiconductor package 100 may be included in an application processor, an integrated circuit of a display driver (IC), a timing controller, or an integrated circuit of a power module. In addition, the semiconductor package 100 may be included in a smart phone, a display device, or a wearable device.

若半導體封裝100裝設於包括封裝基板140的電子裝置(例如，手機)中，則由半導體封裝100中的電子組件所產生的電磁波可能造成對裝設於所述電子裝置中的其他電子組件的電磁干擾(electro-magnetic interference，EMI)。因此，在具有半導體封裝100的電子裝置中可能發生錯誤，且產品的可靠性可能劣化。 If the semiconductor package 100 is installed in an electronic device (for example, a mobile phone) including the packaging substrate 140, the electromagnetic waves generated by the electronic components in the semiconductor package 100 may cause damage to other electronic components installed in the electronic device Electromagnetic interference (electro-magnetic interference, EMI). Therefore, an error may occur in the electronic device having the semiconductor package 100, and the reliability of the product may be deteriorated.

在半導體封裝100為可具有高速運作的若干組件的情形中，因雜散電磁波(stray electromagnetic wave)而造成的此種錯誤問題已變得愈發嚴峻。因此，屏蔽層120可減少在半導體封裝100的運作期間所發射的電磁波的量，亦可減少由其他半導體封裝所發射的電磁波對半導體晶片130的干擾。 In the case where the semiconductor package 100 is a number of components capable of high-speed operation, such error problems caused by stray electromagnetic waves have become more severe. Therefore, the shielding layer 120 can reduce the amount of electromagnetic waves emitted during the operation of the semiconductor package 100, and can also reduce the interference of the electromagnetic waves emitted by other semiconductor packages on the semiconductor chip 130.

然而，隔離層110或屏蔽層120的厚度可能在半導體封裝中造成低效程度的積體化。半導體封裝的高度對其面積的比率稱為長寬比(aspect ratio)。參照圖1，半導體封裝100的長寬比可藉由將其高度(‘b’-相對於封裝基板140的高度)除以隔離層110的側表面部分的厚度與屏蔽層120的側表面部分的厚度之和(距離‘a’)而獲得。所述長寬比(r)可由以下方程式表示。 However, the thickness of the isolation layer 110 or the shielding layer 120 may cause inefficient integration in the semiconductor package. The ratio of the height of a semiconductor package to its area is called the aspect ratio. Referring to FIG. 1, the aspect ratio of the semiconductor package 100 can be obtained by dividing its height ('b'-height relative to the package substrate 140) by the thickness of the side surface portion of the isolation layer 110 and the side surface portion of the shield layer 120 The sum of the thickness (distance'a') is obtained. The aspect ratio (r) can be expressed by the following equation.

長寬比(r)=b/a [方程式1] 因此，低長寬比可為對半導體晶片的垂直空間利用效率低下及/或對封裝基板140上的水平空間利用效率過於低下的標誌。 Aspect ratio (r) = b/a [Equation 1] Therefore, the low aspect ratio may be a sign that the vertical space utilization efficiency of the semiconductor wafer is low and/or the horizontal space utilization efficiency on the package substrate 140 is too low.

因此，可力求使用各種實施方式來增大半導體封裝100的長寬比，以使得可減小半導體封裝100在封裝基板140上所佔的相對面積，藉此增大積體化程度。 Therefore, various embodiments can be used to increase the aspect ratio of the semiconductor package 100 so that the relative area occupied by the semiconductor package 100 on the package substrate 140 can be reduced, thereby increasing the degree of integration.

屏蔽層120可在半導體晶片130上形成為例如矩形形狀。屏蔽層120的上表面可相對於屏蔽層120的側表面而形成為90°或實質上90°。然而，屏蔽層120的形狀並非僅限於此。 The shield layer 120 may be formed on the semiconductor wafer 130 into, for example, a rectangular shape. The upper surface of the shield layer 120 may be formed at 90° or substantially 90° with respect to the side surface of the shield layer 120. However, the shape of the shielding layer 120 is not limited to this.

根據示例性實施例，半導體封裝100的長寬比可等於或大於1，而5或更大的更高長寬比可為所期望的。為此，隔離層110可藉由使用觸變材料或熱熔材料而形成。觸變材料或熱熔材料可以流體形式注射並接著藉由紫外(ultraviolet，UV)光或熱而固化(或硬化)。隔離層110中的觸變材料或熱熔材料可包括用於幫助屏蔽電磁干擾的金屬材料。 According to an exemplary embodiment, the aspect ratio of the semiconductor package 100 may be equal to or greater than 1, and a higher aspect ratio of 5 or greater may be desired. For this, the isolation layer 110 may be formed by using a thixotropic material or a hot-melt material. The thixotropic material or hot melt material may be injected in a fluid form and then cured (or hardened) by ultraviolet (UV) light or heat. The thixotropic material or the hot-melt material in the isolation layer 110 may include a metal material to help shield electromagnetic interference.

本發明的各種實施例可使用三維(3D)印刷來形成隔離層110及/或屏蔽層120。因此，可減少與製造裝備相關的高費用及製造製程所耗費的時間。此外，根據示例性實施例，隔離層110或屏蔽層120可藉由材料供應裝置而形成，所述材料供應裝置包括開口，所述開口具有與隔離層110或屏蔽層120的側表面的形狀相同的形狀。 Various embodiments of the present invention may use three-dimensional (3D) printing to form the isolation layer 110 and/or the shielding layer 120. Therefore, the high cost associated with manufacturing equipment and the time consumed by the manufacturing process can be reduced. Furthermore, according to an exemplary embodiment, the isolation layer 110 or the shield layer 120 may be formed by a material supply device including an opening having the same shape as the side surface of the isolation layer 110 or the shield layer 120 shape.

圖2A及圖2B是用於闡述包含於根據示例性實施例的半導體封裝中的觸變材料的圖。 2A and 2B are diagrams for explaining thixotropic materials included in a semiconductor package according to an exemplary embodiment.

參照圖2A，所述觸變材料能夠因剪切應力(shear stress)而在凝膠狀態(gel state)與溶膠狀態(sol state)之間發生相變。舉例而言，若剪切應力被施加至處於凝膠狀態的觸變材料，則所述觸變材料變至溶膠狀態。舉例而言，儘管觸變材料保持於溶膠狀態，然而若一段時間內不施加剪切應力至所述觸變材料，則所述觸變材料重新變至凝膠狀態。 Referring to FIG. 2A, the thixotropic material can undergo a phase change between a gel state and a sol state due to shear stress. For example, if a shear stress is applied to the thixotropic material in the gel state, the thixotropic material changes to the sol state. For example, although the thixotropic material remains in the sol state, if no shear stress is applied to the thixotropic material for a period of time, the thixotropic material changes to the gel state again.

參照圖2B，若剪切應力被施加至觸變材料，則所述觸變材料的黏度(viscosity)變低，使得觸變材料變至可輕易改變的狀態，而若使觸變材料在時移(time lapse)期間處於其中剪切應力被消除的狀態中，則所述觸變材料會重新變至具有高黏度並恢復至其初始形狀。亦即，若剪切應力被施加至觸變材料，則所述觸變材料的網狀結構(net structure)被破壞，以使得觸變材料具有低黏度，而若剪切應力被消除，則所述觸變材料會恢復至其網狀結構以具有高黏度。 Referring to FIG. 2B, if a shear stress is applied to the thixotropic material, the viscosity of the thixotropic material becomes lower, so that the thixotropic material becomes easily changeable, and if the thixotropic material is shifted in time (time lapse) is in a state where the shear stress is eliminated, then the thixotropic material will change back to have a high viscosity and return to its original shape. That is, if shear stress is applied to the thixotropic material, the net structure of the thixotropic material is destroyed, so that the thixotropic material has a low viscosity, and if the shear stress is eliminated, the The thixotropic material will return to its network structure to have a high viscosity.

舉例而言，參照第一曲線

Figure 105100334-A0305-02-0018-3
，當剪切應力被施加至處於溶膠狀態的觸變材料時，黏度的變化小。參照第二曲線
Figure 105100334-A0305-02-0018-4
，當剪切應力被施加至處於凝膠狀態的觸變材料時，黏度的變化大。此外，根據時移△time，觸變材料可自第一曲線
Figure 105100334-A0305-02-0018-5
所示的狀態變至第二曲線
Figure 105100334-A0305-02-0018-6
所示的狀態。亦即，觸變材料的黏度可根據時移△time及剪切應力的強度而變化。 For example, refer to the first curve
Figure 105100334-A0305-02-0018-3
When the shear stress is applied to the thixotropic material in the sol state, the change in viscosity is small. Refer to the second curve
Figure 105100334-A0305-02-0018-4
When the shear stress is applied to the thixotropic material in the gel state, the viscosity changes greatly. In addition, according to the time shift △time, the thixotropic material can
Figure 105100334-A0305-02-0018-5
The state shown changes to the second curve
Figure 105100334-A0305-02-0018-6
The state shown. That is, the viscosity of the thixotropic material can be changed according to the time shift Δtime and the strength of the shear stress.

所述觸變材料可藉由對高黏度材料添加觸變添加劑(thixotropic additive)來實現。舉例而言，觸變材料可藉由添加 圖1的說明中所提及的材料(例如，複合精細氧化矽、膨土、表面經處理的碳酸鈣的細粒、氫化蓖麻油、金屬皂、硬脂酸鋁、聚醯胺蠟、氧化聚乙烯及亞麻籽聚合油)來達成。 The thixotropic material can be realized by adding a thixotropic additive to the high viscosity material. For example, thixotropic materials can be added by The materials mentioned in the description of FIG. 1 (for example, composite fine silica, bentonite, fine particles of surface-treated calcium carbonate, hydrogenated castor oil, metal soap, aluminum stearate, polyamide wax, oxidized poly Ethylene and linseed polymer oil).

隔離層是藉由使用被施加剪切應力的具有低黏度的材料而形成，且所述隔離層可藉由紫外光固化或熱固化而固化。 The isolation layer is formed by using a material having a low viscosity to which shear stress is applied, and the isolation layer can be cured by ultraviolet curing or thermal curing.

圖3是根據示例性實施例的半導體封裝100a的剖視圖。參照圖3，半導體封裝100a可經由接觸焊墊150a及151a而裝設於封裝基板140a的上表面上。半導體封裝100a可包括覆蓋半導體晶片130a的屏蔽層120a。半導體封裝100a可相似於圖1所示的半導體封裝100。半導體封裝100a的長寬比示為：r=b’/a’。應注意，不存在如圖1所示的隔離層，因此若高度b’相同於高度b，則所述長寬比可大於圖1所示的半導體封裝的長寬比。 FIG. 3 is a cross-sectional view of a semiconductor package 100a according to an exemplary embodiment. Referring to FIG. 3, the semiconductor package 100a may be mounted on the upper surface of the package substrate 140a via contact pads 150a and 151a. The semiconductor package 100a may include a shielding layer 120a covering the semiconductor wafer 130a. The semiconductor package 100a may be similar to the semiconductor package 100 shown in FIG. The aspect ratio of the semiconductor package 100a is shown as: r=b'/a'. It should be noted that there is no isolation layer as shown in FIG. 1, so if the height b'is the same as the height b, the aspect ratio may be greater than the aspect ratio of the semiconductor package shown in FIG.

根據示例性實施例，半導體封裝100a的長寬比可等於或大於1，且在各種實施例中，半導體封裝100a的長寬比可等於或大於5。因此，組件的微型化可為可能的，且由此使用這些組件的各種產品可被製成得更小。 According to an exemplary embodiment, the aspect ratio of the semiconductor package 100a may be equal to or greater than 1, and in various embodiments, the aspect ratio of the semiconductor package 100a may be equal to or greater than 5. Therefore, miniaturization of components may be possible, and thus various products using these components may be made smaller.

圖4是根據示例性實施例的半導體封裝100b的剖視圖。參照圖4，半導體封裝100b可實現為堆疊式封裝結構。 FIG. 4 is a cross-sectional view of a semiconductor package 100b according to an exemplary embodiment. Referring to FIG. 4, the semiconductor package 100b may be implemented as a stacked package structure.

在半導體封裝100b中，半導體晶片131b及半導體晶片132b以及隔離層110b可安置於封裝基板140b上，且隔離層110b可安置成鄰近屏蔽層120b的內側表面及接觸焊墊150b的內側表面。因此，屏蔽層120b可覆蓋半導體晶片131b及半導體晶片132b 以及隔離層110b。封裝基板140b與半導體晶片132b可經由接觸焊墊151b而連接至彼此。半導體晶片131b與半導體晶片132b可經由接觸焊墊152b而連接至彼此。 In the semiconductor package 100b, the semiconductor wafer 131b and the semiconductor wafer 132b and the isolation layer 110b may be disposed on the package substrate 140b, and the isolation layer 110b may be disposed adjacent to the inner surface of the shield layer 120b and the inner surface of the contact pad 150b. Therefore, the shielding layer 120b can cover the semiconductor wafer 131b and the semiconductor wafer 132b 和保护层110b。 The isolation layer 110b. The package substrate 140b and the semiconductor wafer 132b may be connected to each other via the contact pad 151b. The semiconductor wafer 131b and the semiconductor wafer 132b may be connected to each other via the contact pad 152b.

根據示例性實施例，半導體晶片131b及半導體晶片132b可為可用於行動電話中的應用程式處理器、中央處理單元(central processing unit，CPU)、控制器或應用專用積體電路(application specific integrated circuit，ASIC)。 According to an exemplary embodiment, the semiconductor chip 131b and the semiconductor chip 132b may be an application processor, a central processing unit (CPU), a controller, or an application specific integrated circuit that can be used in a mobile phone , ASIC).

接觸焊墊151b及接觸焊墊152b中的每一者可用於在半導體晶片131b與半導體晶片132b之間傳輸訊號。作為另一選擇，接觸焊墊151b及接觸焊墊152b中的任意者可分別用於使半導體晶片131b及半導體晶片132b接地。 Each of the contact pad 151b and the contact pad 152b may be used to transmit signals between the semiconductor wafer 131b and the semiconductor wafer 132b. Alternatively, any one of the contact pad 151b and the contact pad 152b may be used to ground the semiconductor wafer 131b and the semiconductor wafer 132b, respectively.

具有堆疊式封裝結構的半導體封裝100b的隔離層110b及屏蔽層120b可藉由三維印刷來實現，且因此可在晶片層次上進行電磁干擾屏蔽。因此，可達成半導體封裝100b的高長寬比，所述高長寬比可有助於半導體封裝100b的高度積體化。 The isolation layer 110b and the shielding layer 120b of the semiconductor package 100b with a stacked packaging structure can be realized by three-dimensional printing, and therefore electromagnetic interference shielding can be performed at the wafer level. Therefore, a high aspect ratio of the semiconductor package 100b can be achieved, and the high aspect ratio can contribute to the high integration of the semiconductor package 100b.

與圖1所示的隔離層110相同，隔離層110b可藉由使用觸變材料或熱熔材料而形成。所述觸變材料或所述熱熔材料可處於流體狀態以使其可經由分配器而輕易地注射，且接著可對所述觸變材料或所述熱熔材料進行紫外光固化或熱固化而使其硬化。此外，隔離層110b可為金屬材料。隔離層110b可由金屬材料形成，以增大電磁干擾降低效應(EMI reduction effect)。 Like the isolation layer 110 shown in FIG. 1, the isolation layer 110b can be formed by using a thixotropic material or a hot-melt material. The thixotropic material or the hot-melt material can be in a fluid state so that it can be easily injected through a dispenser, and then the thixotropic material or the hot-melt material can be cured by ultraviolet light or heat Harden it. In addition, the isolation layer 110b may be a metal material. The isolation layer 110b may be formed of a metal material to increase the electromagnetic interference reduction effect (EMI reduction effect).

圖5是根據示例性實施例的半導體封裝100c的剖視圖。 參照圖5，半導體封裝100c可實現為堆疊式封裝結構。 FIG. 5 is a cross-sectional view of a semiconductor package 100c according to an exemplary embodiment. Referring to FIG. 5, the semiconductor package 100c may be implemented as a stacked package structure.

在半導體封裝100c中，半導體晶片131c及半導體晶片132c可安置於封裝基板140c上。封裝基板140c與半導體晶片132c可經由接觸焊墊151c而連接至彼此。半導體晶片131c與半導體晶片132c可經由接觸焊墊152c而連接至彼此。此外，屏蔽層120c可覆蓋半導體晶片131c及132c。 In the semiconductor package 100c, the semiconductor wafer 131c and the semiconductor wafer 132c may be disposed on the packaging substrate 140c. The package substrate 140c and the semiconductor wafer 132c may be connected to each other via the contact pad 151c. The semiconductor wafer 131c and the semiconductor wafer 132c may be connected to each other via the contact pad 152c. In addition, the shielding layer 120c may cover the semiconductor wafers 131c and 132c.

接觸焊墊151c及152c中的每一者可用於在半導體晶片131c與半導體晶片132c之間傳輸訊號。作為另一種選擇，接觸焊墊151c及152c中的任意一者亦可分別用於使半導體晶片131c及132c接地。 Each of the contact pads 151c and 152c may be used to transmit signals between the semiconductor wafer 131c and the semiconductor wafer 132c. Alternatively, any one of the contact pads 151c and 152c can also be used to ground the semiconductor wafers 131c and 132c, respectively.

具有堆疊式封裝結構的半導體封裝100c的屏蔽層120c可藉由三維印刷來達成，以使得可達成半導體封裝100c的高長寬比。因此，可在晶片層次上進行電磁干擾屏蔽。所述高長寬比可有助於高度積體化。 The shielding layer 120c of the semiconductor package 100c having a stacked packaging structure can be achieved by three-dimensional printing, so that a high aspect ratio of the semiconductor package 100c can be achieved. Therefore, electromagnetic interference shielding can be performed at the wafer level. The high aspect ratio can contribute to high integration.

圖6是根據示例性實施例的半導體封裝100d的剖視圖。參照圖6，半導體封裝100d可實現為包括半導體晶片131d及132d的多晶片封裝結構。 6 is a cross-sectional view of a semiconductor package 100d according to an exemplary embodiment. Referring to FIG. 6, the semiconductor package 100d may be implemented as a multi-chip package structure including semiconductor chips 131d and 132d.

半導體封裝100d可包括安置於基板140d上的半導體晶片131d及半導體晶片132d。基板140d可基於以下中的任意一者而形成：例如，矽基板、陶瓷基板、印刷電路板(PCB)、有機基板及夾置基板(interposer substrate)。半導體晶片131d及半導體晶片132d可為同一類型的半導體晶片，或者可為不同類型的半導 體晶片。舉例而言，半導體晶片131d及132d中的每一者可為以下中的任意一者：可用於例如行動電話中的應用程式處理器、中央處理單元、控制器及應用專用積體電路。半導體晶片131d及半導體晶片132d可位於基板140d上且可分別經由接觸焊墊151d及接觸焊墊152d而連接至基板140d。此外，屏蔽層120d可覆蓋半導體晶片131d及半導體晶片132d。 The semiconductor package 100d may include a semiconductor wafer 131d and a semiconductor wafer 132d disposed on the substrate 140d. The substrate 140d may be formed based on any one of the following: for example, a silicon substrate, a ceramic substrate, a printed circuit board (PCB), an organic substrate, and an interposer substrate. The semiconductor wafer 131d and the semiconductor wafer 132d may be the same type of semiconductor wafer, or may be different types of semiconductors Body wafer. For example, each of the semiconductor chips 131d and 132d may be any one of the following: may be used in, for example, an application processor, a central processing unit, a controller, and an application-specific integrated circuit in a mobile phone. The semiconductor wafer 131d and the semiconductor wafer 132d may be located on the substrate 140d and may be connected to the substrate 140d via the contact pad 151d and the contact pad 152d, respectively. In addition, the shielding layer 120d may cover the semiconductor wafer 131d and the semiconductor wafer 132d.

接觸焊墊151d及152d可用於分別將電訊號傳輸至半導體晶片131d及半導體晶片132d。接觸焊墊150d可用於使半導體晶片131d及半導體晶片132d接地。 The contact pads 151d and 152d can be used to transmit electrical signals to the semiconductor wafer 131d and the semiconductor wafer 132d, respectively. The contact pad 150d can be used to ground the semiconductor wafer 131d and the semiconductor wafer 132d.

隔離層110d可安置於基板140d上且可被安置成鄰近屏蔽層120d的內側表面及接觸焊墊150d的內側表面。隔離層112d可安置於基板140d上並位於半導體晶片131d與半導體晶片132d之間。隔離層110d及112d可藉由使用觸變材料或熱熔材料而形成，且可對所述觸變材料或所述熱熔材料進行紫外光固化或熱固化。 The isolation layer 110d may be disposed on the substrate 140d and may be disposed adjacent to the inner surface of the shield layer 120d and the inner surface of the contact pad 150d. The isolation layer 112d may be disposed on the substrate 140d and between the semiconductor wafer 131d and the semiconductor wafer 132d. The isolation layers 110d and 112d may be formed by using a thixotropic material or a hot-melt material, and the thixotropic material or the hot-melt material may be cured by ultraviolet light or heat.

根據示例性實施例，半導體封裝100d的長寬比可等於或大於1，且在各種實施例中，半導體封裝100d的長寬比可等於或大於5。半導體封裝100d的屏蔽層120d可藉由三維印刷來達成，以達成半導體封裝100d的高長寬比。因此，可在晶片層次上進行電磁干擾屏蔽。所述高長寬比可有助於高度積體化。 According to exemplary embodiments, the aspect ratio of the semiconductor package 100d may be equal to or greater than 1, and in various embodiments, the aspect ratio of the semiconductor package 100d may be equal to or greater than 5. The shielding layer 120d of the semiconductor package 100d can be achieved by three-dimensional printing to achieve a high aspect ratio of the semiconductor package 100d. Therefore, electromagnetic interference shielding can be performed at the wafer level. The high aspect ratio can contribute to high integration.

圖7是根據示例性實施例的半導體封裝100e的剖視圖。參照圖7，半導體封裝100e可實現為包括以多層結構堆疊的多個 半導體晶片131e、132e及133e的多晶片封裝結構。 FIG. 7 is a cross-sectional view of a semiconductor package 100e according to an exemplary embodiment. Referring to FIG. 7, the semiconductor package 100e may be implemented to include a plurality of stacked in a multi-layer structure Multi-chip package structure of semiconductor chips 131e, 132e and 133e.

半導體封裝100e可包括隔離層110e、屏蔽層120e、多個半導體晶片131e、132e及133e、封裝基板140e、接觸焊墊151e及印刷電路板160e。所述多個半導體晶片131e、132e及133e可堆疊於封裝基板140e上，且封裝基板140e可經由接觸焊墊151e而連接至印刷電路板160e。因此，半導體封裝100e可形成為多層結構。所述多個半導體晶片可包括半導體晶片131e、半導體晶片132e及半導體晶片133e。然而，堆疊中的半導體晶片的數目未必僅限於三個，而是可為適合設計或實施目的的任意數目。 The semiconductor package 100e may include an isolation layer 110e, a shielding layer 120e, a plurality of semiconductor chips 131e, 132e, and 133e, a package substrate 140e, a contact pad 151e, and a printed circuit board 160e. The plurality of semiconductor chips 131e, 132e, and 133e may be stacked on the packaging substrate 140e, and the packaging substrate 140e may be connected to the printed circuit board 160e via the contact pad 151e. Therefore, the semiconductor package 100e may be formed in a multilayer structure. The plurality of semiconductor wafers may include a semiconductor wafer 131e, a semiconductor wafer 132e, and a semiconductor wafer 133e. However, the number of semiconductor wafers in the stack is not necessarily limited to three, but may be any number suitable for design or implementation purposes.

根據示例性實施例，半導體晶片131e、132e及133e可為同一類型的半導體晶片。舉例而言，半導體晶片131e、132e及133e可為用於行動電話中的應用程式處理器。半導體晶片131e、132e及133e中的每一者可包括用於彼此交換電訊號的貫通電極153e。 According to exemplary embodiments, the semiconductor wafers 131e, 132e, and 133e may be the same type of semiconductor wafers. For example, the semiconductor chips 131e, 132e, and 133e may be application processors used in mobile phones. Each of the semiconductor chips 131e, 132e, and 133e may include a through electrode 153e for exchanging electrical signals with each other.

第一層間隔離層171e可夾置於封裝基板140e與半導體晶片131e之間。第二層間隔離層172e可夾置於半導體晶片131e與半導體晶片132e之間，且第三層間隔離層173e可夾置於半導體晶片132e與半導體晶片133e之間。接觸焊墊152e可安置於封裝基板140e與半導體晶片131e、132e及133e之間，以電性連接封裝基板140e與半導體晶片131e、132e及133e。 The first interlayer isolation layer 171e may be sandwiched between the packaging substrate 140e and the semiconductor wafer 131e. The second interlayer isolation layer 172e may be interposed between the semiconductor wafer 131e and the semiconductor wafer 132e, and the third interlayer isolation layer 173e may be interposed between the semiconductor wafer 132e and the semiconductor wafer 133e. The contact pad 152e may be disposed between the packaging substrate 140e and the semiconductor wafers 131e, 132e, and 133e to electrically connect the packaging substrate 140e and the semiconductor wafers 131e, 132e, and 133e.

接觸焊墊150e可用於使半導體晶片131e、132e及133e接地。接觸焊墊151e可用於電性連接印刷電路板160e與封裝基板140e。接觸焊墊151e可例如藉由球柵陣列(ball grid array， BGA)方法(例如，焊料球(solder ball))而形成。接觸焊墊154e可形成於印刷電路板160e與接觸焊墊151e之間，且可用於在印刷電路板160e與封裝基板140e之間進行電性連接。 The contact pad 150e may be used to ground the semiconductor wafers 131e, 132e, and 133e. The contact pad 151e can be used to electrically connect the printed circuit board 160e and the package substrate 140e. The contact pad 151e can be, for example, a ball grid array (ball grid array, BGA) method (for example, solder ball). The contact pad 154e may be formed between the printed circuit board 160e and the contact pad 151e, and may be used to electrically connect the printed circuit board 160e and the package substrate 140e.

隔離層110e可安置於印刷電路板160e上且鄰近屏蔽層120e的內側表面及接觸焊墊150e的內側表面。與圖1所示的隔離層110相同，隔離層110e可藉由使用觸變材料或熱熔材料而形成。此外，可對所述觸變材料或所述熱熔材料進行紫外光固化或熱固化。 The isolation layer 110e may be disposed on the printed circuit board 160e and adjacent to the inner surface of the shield layer 120e and the inner surface of the contact pad 150e. Like the isolation layer 110 shown in FIG. 1, the isolation layer 110e can be formed by using a thixotropic material or a hot-melt material. In addition, the thixotropic material or the hot-melt material may be cured by ultraviolet light or heat.

屏蔽層120e可形成為覆蓋半導體晶片131e、132e及133e中安置於最上層上的半導體晶片133e的上表面、以及隔離層110e的側表面。塑模單元112e可形成於半導體晶片131e、132e及133e與隔離層110e之間、以及半導體晶片131e、132e及133e與屏蔽層120e之間。塑模單元112e可藉由使用環氧系材料(epoxy-based material)、熱固性材料(thermosetting material)、熱塑性材料(thermoplastic material)、經紫外光處理的材料(UV-processed material)等而形成。在圖7中，長寬比可為將屏蔽層120e的高度(b”)除以隔離層110e的側表面部分及屏蔽層120e的側表面部分的厚度(a”)所得。當半導體封裝100e的長寬比高時，半導體封裝100e在印刷電路板160e上所佔的面積可減小，且此減小可增大半導體封裝100e的積體化程度。根據示例性實施例，半導體封裝100e的長寬比可等於或大於1，且在各種實施例中，半導體封裝100e的長寬比可等於或大於5。 The shield layer 120e may be formed to cover the upper surface of the semiconductor wafer 133e disposed on the uppermost layer among the semiconductor wafers 131e, 132e, and 133e, and the side surface of the isolation layer 110e. The mold unit 112e may be formed between the semiconductor wafers 131e, 132e, and 133e and the isolation layer 110e, and between the semiconductor wafers 131e, 132e, and 133e, and the shield layer 120e. The mold unit 112e can be formed by using an epoxy-based material, a thermosetting material, a thermoplastic material, a UV-processed material, or the like. In FIG. 7, the aspect ratio may be obtained by dividing the height (b") of the shielding layer 120e by the side surface portion of the isolation layer 110e and the thickness (a") of the side surface portion of the shielding layer 120e. When the aspect ratio of the semiconductor package 100e is high, the area occupied by the semiconductor package 100e on the printed circuit board 160e can be reduced, and this reduction can increase the degree of integration of the semiconductor package 100e. According to an exemplary embodiment, the aspect ratio of the semiconductor package 100e may be equal to or greater than 1, and in various embodiments, the aspect ratio of the semiconductor package 100e may be equal to or greater than 5.

具有多晶片封裝結構的半導體封裝100e的屏蔽層120e可藉由三維印刷來達成，且因此可達成半導體封裝100e的高長寬比。因此，可在晶片層次上進行電磁干擾屏蔽。所述高長寬比可有助於高度積體化。 The shielding layer 120e of the semiconductor package 100e having a multi-chip packaging structure can be achieved by three-dimensional printing, and thus a high aspect ratio of the semiconductor package 100e can be achieved. Therefore, electromagnetic interference shielding can be performed at the wafer level. The high aspect ratio can contribute to high integration.

儘管可能已將半導體晶片131e、132e及133e闡述為靠近所述晶片具有貫通電極153e，然而各種實施例未必僅限於此。可使用各種眾所習知的方法來使半導體晶片131e、132e及133e互連至彼此且互連至接觸焊墊151e。舉例而言，可存在經由用於分隔各晶片的隔離層的所述晶片之間的連接。 Although the semiconductor wafers 131e, 132e, and 133e may have been explained as having through electrodes 153e close to the wafer, various embodiments are not necessarily limited to this. Various well-known methods may be used to interconnect the semiconductor wafers 131e, 132e, and 133e to each other and to the contact pad 151e. For example, there may be a connection between the wafers via an isolation layer used to separate the wafers.

圖8是根據示例性實施例的半導體封裝100f的剖視圖。 8 is a cross-sectional view of a semiconductor package 100f according to an exemplary embodiment.

參照圖8，半導體封裝100f可實現為包括以多層結構堆疊的半導體晶片131f、132f及133f的多晶片封裝結構。第一層間隔離層171f可夾置於封裝基板140f與半導體晶片131f之間。第二層間隔離層172f可夾置於半導體晶片131f與半導體晶片132f之間，且第三層間隔離層173f可夾置於半導體晶片132f與半導體晶片133f之間。 Referring to FIG. 8, the semiconductor package 100f may be implemented as a multi-chip package structure including semiconductor wafers 131f, 132f, and 133f stacked in a multilayer structure. The first interlayer isolation layer 171f may be sandwiched between the packaging substrate 140f and the semiconductor wafer 131f. The second interlayer isolation layer 172f may be sandwiched between the semiconductor wafer 131f and the semiconductor wafer 132f, and the third interlayer isolation layer 173f may be sandwiched between the semiconductor wafer 132f and the semiconductor wafer 133f.

半導體晶片132f可經由導線181f而電性連接至封裝基板140f且可與封裝基板140f交換訊號。同樣地，半導體晶片133f可經由導線182f而電性連接至封裝基板140f且可與封裝基板140f交換訊號。半導體晶片131f、132f及133f的平面面積(plan area)可彼此不同。半導體晶片131f的平面面積可大於半導體晶片132f的平面面積，且半導體晶片132f的平面面積可大於半導體晶片 133f的平面面積。然而，半導體晶片131f、132f及133f的平面面積並非僅限於此。 The semiconductor chip 132f can be electrically connected to the packaging substrate 140f through the wire 181f and can exchange signals with the packaging substrate 140f. Similarly, the semiconductor chip 133f can be electrically connected to the package substrate 140f via the wire 182f and can exchange signals with the package substrate 140f. The plan areas of the semiconductor wafers 131f, 132f, and 133f may be different from each other. The planar area of the semiconductor wafer 131f may be larger than the planar area of the semiconductor wafer 132f, and the planar area of the semiconductor wafer 132f may be larger than the semiconductor wafer 133f plane area. However, the planar areas of the semiconductor wafers 131f, 132f, and 133f are not limited to this.

半導體封裝100f可相似於半導體封裝100e，且因此將不再詳述諸多相似的組件。半導體封裝100f可包括與半導體封裝100e的對應部件相似的隔離層110f、屏蔽層120f、半導體晶片131f、132f及133f、封裝基板140f、接觸焊墊150f、151f、154f、以及印刷電路板160f。 The semiconductor package 100f may be similar to the semiconductor package 100e, and therefore many similar components will not be described in detail. The semiconductor package 100f may include an isolation layer 110f, a shield layer 120f, semiconductor wafers 131f, 132f, and 133f similar to corresponding parts of the semiconductor package 100e, a package substrate 140f, contact pads 150f, 151f, 154f, and a printed circuit board 160f.

與塑模單元112e相似的塑模單元112f可填充其中於屏蔽層120f與封裝基板140f之間安置有半導體晶片131f、132f及133f的內部空間。塑模單元112f可藉由使用環氧系材料、熱固性材料、熱塑性材料、經紫外光處理的材料等而形成。 The mold unit 112f similar to the mold unit 112e may fill the internal space in which the semiconductor wafers 131f, 132f, and 133f are disposed between the shield layer 120f and the package substrate 140f. The mold unit 112f can be formed by using an epoxy-based material, a thermosetting material, a thermoplastic material, a material treated with ultraviolet light, or the like.

圖8所示的半導體封裝100f與圖7所示的半導體封裝100e的不同之處在於半導體晶片131f、132f及133f的平面面積彼此不同，且半導體晶片132f及133f分別經由導線181f及182f而電性連接至封裝基板140f。 The difference between the semiconductor package 100f shown in FIG. 8 and the semiconductor package 100e shown in FIG. 7 is that the planar areas of the semiconductor wafers 131f, 132f, and 133f are different from each other, and the semiconductor chips 132f and 133f are electrically conductive through the wires 181f and 182f, respectively Connected to the package substrate 140f.

除導線181f及182f之外，半導體晶片131f、132f及133f亦可藉由各種眾所習知的方法而彼此通訊且與封裝基板140f通訊。舉例而言，可存在經由用於分隔各晶片的隔離層的所述晶片之間或晶片與封裝基板140f之間的連接。 In addition to the wires 181f and 182f, the semiconductor chips 131f, 132f, and 133f can also communicate with each other and the package substrate 140f by various well-known methods. For example, there may be a connection between the wafers or between the wafer and the package substrate 140f via an isolation layer for separating each wafer.

圖9是根據示例性實施例的半導體封裝100g的剖視圖。參照圖9，半導體封裝100g可實現為堆疊式封裝結構。 9 is a cross-sectional view of a semiconductor package 100g according to an exemplary embodiment. Referring to FIG. 9, the semiconductor package 100g may be implemented as a stacked package structure.

半導體封裝100g可包括印刷電路板160g、形成於印刷電 路板160g上的第一半導體封裝131g及形成於第一半導體封裝131g上的第二半導體封裝132g。 The semiconductor package 100g may include a printed circuit board 160g, formed on a printed circuit board The first semiconductor package 131g on the road board 160g and the second semiconductor package 132g formed on the first semiconductor package 131g.

第一半導體封裝131g可包括第一封裝基板140g、及裝設於第一封裝基板140g上的半導體晶片130g。第一封裝基板140g可經由接觸焊墊151g及154g而電性連接至印刷電路板160g。半導體晶片130g可為例如中央處理單元、控制器、或應用專用積體電路等微處理器。根據示例性實施例，半導體晶片130g可為用於行動電話或智慧型電話中的應用程式處理器。半導體晶片130g可經由接觸焊墊151g而與印刷電路板160g及連接至印刷電路板160g的其他裝置交換電訊號。 The first semiconductor package 131g may include a first packaging substrate 140g, and a semiconductor chip 130g mounted on the first packaging substrate 140g. The first packaging substrate 140g may be electrically connected to the printed circuit board 160g via the contact pads 151g and 154g. The semiconductor wafer 130g may be a microprocessor such as a central processing unit, a controller, or an application-specific integrated circuit. According to an exemplary embodiment, the semiconductor chip 130g may be an application processor used in a mobile phone or a smart phone. The semiconductor chip 130g can exchange electrical signals with the printed circuit board 160g and other devices connected to the printed circuit board 160g through the contact pad 151g.

第二半導體封裝132g可包括第二封裝基板142g、裝設於第二封裝基板142g上的半導體晶片135g及136g、接觸焊墊152g及153g、以及導線181g及182g。儘管其被示出具有兩個半導體晶片135g及136g，然而其並非僅限於此。可將三或更多個半導體晶片堆疊成多層結構。半導體晶片135g及136g可為同一類型的半導體晶片。半導體晶片135g及136g可為例如以下中的至少一者：動態隨機存取記憶體(dynamic random-access memory，DRAM)、靜態隨機存取記憶體(static random-access memory，SRAM)、快閃記憶體(flash memory)、電可抹除可程式化唯讀記憶體(electrically erasable programmable read-only memory，EEPROM)、參數隨機存取記憶體(parameter random-access memory，PRAM)、磁電阻隨機存取記憶體(magnetoresistive random-access memory， MRAM)、及電阻式隨機存取記憶體(resistive random-access memory，RRAM)。 The second semiconductor package 132g may include a second package substrate 142g, semiconductor chips 135g and 136g mounted on the second package substrate 142g, contact pads 152g and 153g, and wires 181g and 182g. Although it is shown to have two semiconductor wafers 135g and 136g, it is not limited to this. Three or more semiconductor wafers can be stacked into a multilayer structure. The semiconductor wafers 135g and 136g may be the same type of semiconductor wafer. The semiconductor chips 135g and 136g may be, for example, at least one of the following: dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory (Flash memory), electrically erasable programmable read-only memory (EEPROM), parameter random-access memory (PRAM), magnetoresistive random access Memory (magnetoresistive random-access memory, MRAM), and resistive random-access memory (RRAM).

第一層間隔離層171g可夾置於半導體晶片135g與第二封裝基板142g之間，且第二層間隔離層172g可夾置於半導體晶片135g與半導體晶片136g之間。半導體晶片135g及136g可分別經由導線181g及導線182g而電性連接至第二封裝基板142g。 The first interlayer isolation layer 171g may be sandwiched between the semiconductor wafer 135g and the second packaging substrate 142g, and the second interlayer isolation layer 172g may be sandwiched between the semiconductor wafer 135g and the semiconductor wafer 136g. The semiconductor chips 135g and 136g may be electrically connected to the second packaging substrate 142g via wires 181g and wires 182g, respectively.

接觸焊墊153g可用於在第一封裝基板140g與第二封裝基板142g之間進行電性連接。接觸焊墊153g可形成為球柵陣列。 The contact pad 153g can be used to electrically connect the first package substrate 140g and the second package substrate 142g. The contact pad 153g may be formed as a ball grid array.

接地單元150g可用於使半導體晶片130g以及半導體晶片135g及136g接地。 The ground unit 150g may be used to ground the semiconductor wafer 130g and the semiconductor wafers 135g and 136g.

隔離層110g可形成為鄰近第一半導體封裝131g及第二半導體封裝132g。詳言之，隔離層110g可藉由鄰近第一封裝基板140g的側表面及第二封裝基板142g的側表面而形成為鄰近半導體晶片130g以及半導體晶片135g及136g。隔離層110g可藉由使用觸變材料或熱熔材料而形成。此外，可對所述觸變材料或所述熱熔材料進行紫外光固化或熱固化。 The isolation layer 110g may be formed adjacent to the first semiconductor package 131g and the second semiconductor package 132g. In detail, the isolation layer 110g may be formed adjacent to the semiconductor chip 130g and the semiconductor chips 135g and 136g by being adjacent to the side surface of the first package substrate 140g and the side surface of the second package substrate 142g. The isolation layer 110g can be formed by using a thixotropic material or a hot-melt material. In addition, the thixotropic material or the hot-melt material may be cured by ultraviolet light or heat.

屏蔽層120g可形成為覆蓋半導體晶片136g的上表面及隔離層110g的外表面。塑模單元112g可形成於半導體晶片130g、135g、及136g與隔離層110g之間、以及半導體晶片130g、135g、及136g與屏蔽層120g之間。塑模單元112g可藉由使用環氧系材料、熱固性材料、熱塑性材料、經紫外光處理的材料等而形成。根據圖9所示的示例性實施例，長寬比可定義為藉由將屏蔽層120g 的高度(b''')除以隔離層110g的側表面部分的厚度與屏蔽層120g的側表面部分的厚度之和(a''')而獲得的值。當半導體封裝100g的長寬比高時，半導體封裝100g在印刷電路板160g上所佔的相對面積可減小，且因此可增大半導體封裝100g的積體化程度。 The shield layer 120g may be formed to cover the upper surface of the semiconductor wafer 136g and the outer surface of the isolation layer 110g. The mold unit 112g may be formed between the semiconductor wafers 130g, 135g, and 136g and the isolation layer 110g, and between the semiconductor wafers 130g, 135g, and 136g and the shield layer 120g. The mold unit 112g can be formed by using an epoxy-based material, a thermosetting material, a thermoplastic material, a material treated with ultraviolet light, or the like. According to the exemplary embodiment shown in FIG. 9, the aspect ratio can be defined as by shielding the layer 120g The height (b′″) is a value obtained by dividing the thickness (a′″) of the thickness of the side surface portion of the isolation layer 110 g and the thickness of the side surface portion of the shield layer 120 g. When the aspect ratio of the semiconductor package 100g is high, the relative area occupied by the semiconductor package 100g on the printed circuit board 160g can be reduced, and thus the degree of integration of the semiconductor package 100g can be increased.

具有堆疊式封裝結構的半導體封裝100g的屏蔽層120g可藉由三維印刷來達成，且因此可達成半導體封裝100g的高長寬比。 The shielding layer 120g of the semiconductor package 100g having a stacked packaging structure can be achieved by three-dimensional printing, and thus a high aspect ratio of the semiconductor package 100g can be achieved.

圖10是根據示例性實施例的半導體封裝100h的剖視圖。 FIG. 10 is a cross-sectional view of a semiconductor package 100h according to an exemplary embodiment.

參照圖10，半導體封裝100h可實現為其中半導體晶片130h以倒裝晶片結構(flip-chip structure)裝設於封裝基板140h上的半導體封裝結構。半導體封裝100h可包括隔離層110h、屏蔽層120h、半導體晶片130h、封裝基板140h、接觸焊墊150h、及印刷電路板160h。圖10所示的半導體封裝100h與圖7所示的半導體封裝100e的不同之處在於，一個半導體晶片130h是以倒裝晶片結構進行裝設。半導體封裝100h的組件具有與半導體封裝100e的組件相同的參考編號，僅對參考編號附有不同的英文字母，其中相同的參考編號指代相同的元件。因此，將不再對其予以贅述。將不再對半導體封裝100h的與圖7所示的組件相同的組件予以詳細闡述。 Referring to FIG. 10, the semiconductor package 100h may be implemented as a semiconductor package structure in which the semiconductor wafer 130h is mounted on the package substrate 140h in a flip-chip structure. The semiconductor package 100h may include an isolation layer 110h, a shield layer 120h, a semiconductor wafer 130h, a package substrate 140h, a contact pad 150h, and a printed circuit board 160h. The difference between the semiconductor package 100h shown in FIG. 10 and the semiconductor package 100e shown in FIG. 7 is that one semiconductor wafer 130h is mounted in a flip-chip structure. The components of the semiconductor package 100h have the same reference number as the components of the semiconductor package 100e, and only different English letters are attached to the reference number, where the same reference number refers to the same element. Therefore, it will not be repeated here. The components of the semiconductor package 100h that are the same as those shown in FIG. 7 will not be described in detail.

半導體晶片130h可以倒裝晶片結構裝設於封裝基板140h上。半導體晶片130h可經由接觸焊墊152h而電性連接至封裝基板140h。封裝基板140h可經由接觸焊墊151h而電性連接至 印刷電路板160h。半導體晶片130h可經由接觸焊墊151h及152h而與連接至印刷電路板160h的其他裝置交換電訊號。接觸焊墊154h可安置於接觸焊墊151h與印刷電路板160h之間，且可用於經由接觸焊墊151h而在印刷電路板160h與半導體晶片130h之間進行電性連接。 The semiconductor wafer 130h may be mounted on the packaging substrate 140h in a flip-chip structure. The semiconductor wafer 130h may be electrically connected to the package substrate 140h via the contact pad 152h. The package substrate 140h may be electrically connected to the contact pad 151h Printed circuit board 160h. The semiconductor chip 130h can exchange electrical signals with other devices connected to the printed circuit board 160h through the contact pads 151h and 152h. The contact pad 154h may be disposed between the contact pad 151h and the printed circuit board 160h, and may be used to electrically connect the printed circuit board 160h and the semiconductor wafer 130h via the contact pad 151h.

底填充構件(under-fill member)114h可形成於半導體晶片130h的下表面與封裝基板140h的上表面之間、以及接觸焊墊152h之間。 An under-fill member 114h may be formed between the lower surface of the semiconductor wafer 130h and the upper surface of the package substrate 140h, and between the contact pads 152h.

隔離層110h可由與圖7所示的隔離層110e相同的材料形成。屏蔽層120h可形成為與圖7所示的屏蔽層120e實質上相同的結構。根據圖10所示的本發明示例性實施例，長寬比可定義為藉由將屏蔽層120h的高度(b'''')除以隔離層110h的側表面部分的厚度與屏蔽層120h的側表面部分的厚度之和(a'''')而獲得的值。當半導體封裝100h的長寬比高時，半導體封裝100h在印刷電路板160h上所佔的相對面積可減小，且因此可增大半導體封裝100h的積體化程度。 The isolation layer 110h may be formed of the same material as the isolation layer 110e shown in FIG. 7. The shielding layer 120h may be formed in substantially the same structure as the shielding layer 120e shown in FIG. 7. According to the exemplary embodiment of the present invention shown in FIG. 10, the aspect ratio can be defined as the height (b'''') of the shielding layer 120h divided by the thickness of the side surface portion of the isolation layer 110h and the thickness of the shielding layer 120h The value obtained by the sum of the thicknesses of the side surface portions (a''''). When the aspect ratio of the semiconductor package 100h is high, the relative area occupied by the semiconductor package 100h on the printed circuit board 160h can be reduced, and thus the degree of integration of the semiconductor package 100h can be increased.

圖11A至圖11E是用於闡述根據示例性實施例的一種半導體封裝1000的製造製程的圖。 11A to 11E are diagrams for explaining a manufacturing process of a semiconductor package 1000 according to an exemplary embodiment.

參照圖11A，可在基板140d上對接觸焊墊150d及151d進行圖案化。基板140d可在其上表面上具有接觸焊墊150d及151d。舉例而言，接觸焊墊150d可用於接地，且接觸焊墊151d可用於訊號傳輸或接地。基板140d可為例如雙面印刷電路板(double- sided PCB)或多層印刷電路板(multi-layer PCB)。 Referring to FIG. 11A, the contact pads 150d and 151d may be patterned on the substrate 140d. The substrate 140d may have contact pads 150d and 151d on its upper surface. For example, the contact pad 150d can be used for grounding, and the contact pad 151d can be used for signal transmission or grounding. The substrate 140d may be, for example, a double-sided printed circuit board (double- sided PCB) or multi-layer PCB (multi-layer PCB).

參照圖11B，可在基板140d上安置半導體晶片130d。近來，對具有更多功能性及更小的可攜式裝置的需求已迅速增加，且因此技術已使得電子產品中的電子組件微型化及重量減輕。 Referring to FIG. 11B, a semiconductor wafer 130d may be placed on the substrate 140d. Recently, the demand for portable devices with more functionality and smaller size has rapidly increased, and thus technology has made miniaturization and weight reduction of electronic components in electronic products.

為此，不僅需要用於減小單獨的組件的大小的技術，且亦需要系統晶片(system on chip，SOC)技術來將多個單獨的組件整合至一個晶片中、或者需要系統級封裝(system in package，SIP)技術來將多個單獨的裝置整合至一個封裝中。 To this end, not only a technology for reducing the size of individual components, but also system on chip (SOC) technology is needed to integrate multiple individual components into one chip, or a system-in-package is required in package (SIP) technology to integrate multiple individual devices into one package.

在用於將所述多個單獨的裝置整合至一個封裝中的系統級封裝技術中，半導體晶片的數目可根據半導體封裝的用途而變化。本發明不將封裝中的半導體晶片的數目限制於單個數目。半導體晶片的數目可相依於各種設計及實施準則。 In a system-in-package technology for integrating the plurality of individual devices into one package, the number of semiconductor wafers may vary according to the use of the semiconductor package. The invention does not limit the number of semiconductor wafers in the package to a single number. The number of semiconductor chips can depend on various design and implementation criteria.

參照圖11C，可形成隔離層110d，其中隔離層110d可為觸變材料或熱熔材料。所述觸變材料可包括以下中的至少一者：例如，複合精細氧化矽、膨土、表面經處理的碳酸鈣的細粒、氫化蓖麻油、金屬皂、硬脂酸鋁、聚醯胺蠟、氧化聚乙烯、及亞麻籽聚合油。 Referring to FIG. 11C, an isolation layer 110d may be formed, where the isolation layer 110d may be a thixotropic material or a hot-melt material. The thixotropic material may include at least one of the following: for example, composite fine silica, bentonite, fine particles of surface-treated calcium carbonate, hydrogenated castor oil, metal soap, aluminum stearate, polyamide wax , Oxidized polyethylene, and linseed polymer oil.

隔離層110d的所述熱熔材料可包括以下中的至少一者：例如，聚氨酯、聚脲、聚氯乙烯、聚苯乙烯、丙烯腈-丁二烯-苯乙烯(acrylonitrile butadiene styrene；ABS)、聚醯胺、丙烯酸、及聚對苯二甲酸丁二酯(PBTP)。 The hot melt material of the isolation layer 110d may include at least one of the following: for example, polyurethane, polyurea, polyvinyl chloride, polystyrene, acrylonitrile butadiene styrene (ABS), Polyamide, acrylic acid, and polybutylene terephthalate (PBTP).

參照圖11D，可將屏蔽層120d形成為覆蓋半導體晶片 130d。隔離層110d可夾置於屏蔽層120d與半導體晶片130d之間。屏蔽層120d的上表面與側表面彼此交匯的屏蔽層120d的邊緣120edge可為90°或實質上90°。然而，本發明的各種實施例未必僅限於此。根據示例性實施例，屏蔽層120d的邊緣120edge可具有預定曲率半徑。 Referring to FIG. 11D, the shield layer 120d may be formed to cover the semiconductor wafer 130d. The isolation layer 110d may be sandwiched between the shielding layer 120d and the semiconductor wafer 130d. The edge 120edge of the shielding layer 120d where the upper surface and the side surfaces of the shielding layer 120d meet each other may be 90° or substantially 90°. However, the various embodiments of the present invention are not necessarily limited to this. According to an exemplary embodiment, the edge 120edge of the shielding layer 120d may have a predetermined radius of curvature.

藉由使用高指數觸變材料(high index thixotropic material)來形成屏蔽層120d，使得屏蔽層120d可藉由三維印刷而形成，且因此屏蔽層120d的邊緣120edge可具有預定曲率半徑。可使包括先前根據圖1及圖3至圖10所述的示例性實施例的半導體封裝(半導體封裝100、及100a至100h)中的任意一者的產品微型化及高度積體化。隨後將參照圖12至圖16闡述此態樣。 By using a high index thixotropic material to form the shielding layer 120d, the shielding layer 120d can be formed by three-dimensional printing, and thus the edge 120edge of the shielding layer 120d can have a predetermined radius of curvature. Products including any of the semiconductor packages (semiconductor packages 100, and 100a to 100h) of the exemplary embodiments previously described according to FIGS. 1 and 3 to 10 can be miniaturized and highly integrated. This aspect will be explained later with reference to FIGS. 12 to 16.

如圖11D所示，隔離層110d亦可形成於半導體晶片130d的上表面上。此外，根據另一示例性實施例，隔離層110d可僅形成於半導體晶片130d的側表面上。 As shown in FIG. 11D, the isolation layer 110d may also be formed on the upper surface of the semiconductor wafer 130d. In addition, according to another exemplary embodiment, the isolation layer 110d may be formed only on the side surface of the semiconductor wafer 130d.

屏蔽層120d可形成為減小由半導體晶片130d所產生的電磁波導致的電磁干擾，且亦減小由半導體封裝1000外部所產生的電磁波對半導體晶片130d的電磁干擾。 The shielding layer 120d may be formed to reduce electromagnetic interference caused by electromagnetic waves generated by the semiconductor wafer 130d, and also reduce electromagnetic interference of the semiconductor wafer 130d by electromagnetic waves generated outside the semiconductor package 1000.

根據示例性實施例，隔離層110d或屏蔽層120d可由觸變材料或熱熔材料形成，以藉由圖12至圖16所示的三維印刷來達成高長寬比。 According to an exemplary embodiment, the isolation layer 110d or the shielding layer 120d may be formed of a thixotropic material or a hot-melt material to achieve a high aspect ratio by three-dimensional printing shown in FIGS. 12 to 16.

圖11E是圖11D所示的邊緣120edge的放大圖。參照圖11E，在位於屏蔽層120d的邊界部分處且屏蔽層120d的上表面與 側表面彼此交匯的邊緣120edge’可具有曲率半徑120r，且可具有與曲率半徑120r的倒數值(reciprocal value)對應的曲率。曲率半徑120r可小於或等於屏蔽層120d的厚度120t。亦即，曲率半徑120r的最大值可等於或小於屏蔽層120d的厚度120t。 FIG. 11E is an enlarged view of the edge 120edge shown in FIG. 11D. 11E, at the boundary portion of the shielding layer 120d and the upper surface of the shielding layer 120d and The edges 120edge' where the side surfaces meet each other may have a radius of curvature 120r, and may have a curvature corresponding to the reciprocal value of the radius of curvature 120r. The radius of curvature 120r may be less than or equal to the thickness 120t of the shield layer 120d. That is, the maximum value of the radius of curvature 120r may be equal to or less than the thickness 120t of the shielding layer 120d.

根據示例性實施例，屏蔽層120d是藉由其中高觸變材料經由分配器的噴嘴排出的製程而形成。因此，如圖11E所示，屏蔽層120d的邊緣120edge’可具有預定曲率半徑120r。將參照圖12至圖16更詳細地闡述藉由三維印刷來形成屏蔽層120d的方法。 According to an exemplary embodiment, the shielding layer 120d is formed by a process in which high thixotropic material is discharged through the nozzle of the dispenser. Therefore, as shown in FIG. 11E, the edge 120edge' of the shielding layer 120d may have a predetermined radius of curvature 120r. The method of forming the shielding layer 120d by three-dimensional printing will be explained in more detail with reference to FIGS. 12 to 16.

圖12是根據示例性實施例的用於製造半導體封裝100及100a至100h中的至少一者的三維列印機300的示意性立體圖。三維列印機300可藉由使用半導體封裝100及100a至100h中的每一者中的觸變材料或熱熔材料來形成具有高長寬比的隔離層。在圖12的說明中，為方便說明，三維列印機300的組件可被省略或誇大。 12 is a schematic perspective view of a three-dimensional printer 300 for manufacturing at least one of semiconductor packages 100 and 100a to 100h according to an exemplary embodiment. The three-dimensional printer 300 may form an isolation layer having a high aspect ratio by using a thixotropic material or a hot-melt material in each of the semiconductor packages 100 and 100a to 100h. In the description of FIG. 12, for convenience of explanation, components of the three-dimensional printer 300 may be omitted or exaggerated.

參照圖12，三維列印機300可包括分配頭單元300A、框架單元(frame unit)350、頭運輸單元360、晶片運輸單元370、及量測單元380。根據示例性實施例，三維列印機300可更包括用於控制分配頭單元300A及頭運輸單元360的控制單元(未示出)，使得分配頭單元300A在半導體晶片上形成隔離層或屏蔽層，進而可使所述半導體晶片具有高長寬比。 Referring to FIG. 12, the three-dimensional printer 300 may include a distribution head unit 300A, a frame unit 350, a head transport unit 360, a wafer transport unit 370, and a measurement unit 380. According to an exemplary embodiment, the 3D printer 300 may further include a control unit (not shown) for controlling the distribution head unit 300A and the head transport unit 360 so that the distribution head unit 300A forms an isolation layer or a shielding layer on the semiconductor wafer , And thus the semiconductor wafer can have a high aspect ratio.

框架單元350是用以固定三維列印機300的固定單元，且分配頭單元300A、頭運輸單元360、晶片運輸單元370、及量測 單元380可安置於框架單元350上。 The frame unit 350 is a fixed unit for fixing the three-dimensional printer 300, and distributes the head unit 300A, the head transport unit 360, the wafer transport unit 370, and the measurement The unit 380 may be placed on the frame unit 350.

分配頭單元300A可將適宜的材料分配至晶片運輸單元370中的半導體晶片上。頭運輸單元360可連接至分配頭單元300A。頭運輸單元360可在第一方向(方向x)、第二方向(方向y)、及第三方向(方向z)上移動分配頭單元300A。此外，頭運輸單元360可使分配頭單元300A旋轉。 The distribution head unit 300A can distribute suitable materials onto the semiconductor wafers in the wafer transport unit 370. The head transportation unit 360 may be connected to the distribution head unit 300A. The head transport unit 360 may move the distribution head unit 300A in the first direction (direction x), the second direction (direction y), and the third direction (direction z). In addition, the head transport unit 360 can rotate the dispensing head unit 300A.

晶片運輸單元370可在第二方向(方向y)上移動半導體晶片。晶片運輸單元370可在第二方向(方向y)上移動由分配頭單元300A形成有隔離層及屏蔽層的半導體晶片，且可將其上尚未形成隔離層及屏蔽層的半導體晶片移動至鄰近分配頭單元300A。 The wafer transport unit 370 may move the semiconductor wafer in the second direction (direction y). The wafer transport unit 370 can move the semiconductor wafer formed with the isolation layer and the shielding layer by the distribution head unit 300A in the second direction (direction y), and can move the semiconductor wafer on which the isolation layer and the shielding layer have not been formed to the adjacent distribution The head unit 300A.

量測單元380可量測半導體晶片的重量並調整所述半導體晶片的位置。量測單元380可包括用於清潔分配頭單元300A的噴嘴330及332的模組。 The measuring unit 380 can measure the weight of the semiconductor wafer and adjust the position of the semiconductor wafer. The measuring unit 380 may include a module for cleaning the nozzles 330 and 332 of the dispensing head unit 300A.

分配頭單元300A可在半導體晶片200上形成隔離層210(參照圖13)及屏蔽層220(參照圖13)。將參照圖13給出詳細說明。 The distribution head unit 300A may form the isolation layer 210 (see FIG. 13) and the shielding layer 220 (see FIG. 13) on the semiconductor wafer 200. A detailed explanation will be given with reference to FIG. 13.

圖13是用於闡述根據示例性實施例的一種藉由使用圖12所示的三維列印機300來製造半導體封裝100及100a至100h中的至少一者的方法的圖。圖13是圖12所示的分配頭單元300A的圖，為方便說明，其僅概念地示意之。 13 is a diagram for explaining a method of manufacturing at least one of the semiconductor packages 100 and 100a to 100h by using the three-dimensional printer 300 shown in FIG. 12 according to an exemplary embodiment. FIG. 13 is a diagram of the distribution head unit 300A shown in FIG. 12, which is only conceptually illustrated for convenience of explanation.

參照圖13，可將接觸焊墊230連接至接觸焊墊240，接觸焊墊240連接至半導體晶片200的內部電路。根據示例性實施 例，接觸焊墊240可為可焊接的金屬球柵陣列。此外，接觸焊墊230可相對於形成於封裝基板上的電路圖案而藉由高溫焊接迴流(high temperature soldering reflow)來形成。 Referring to FIG. 13, the contact pad 230 may be connected to the contact pad 240, and the contact pad 240 is connected to the internal circuit of the semiconductor wafer 200. According to exemplary implementation For example, the contact pad 240 may be a solderable metal ball grid array. In addition, the contact pad 230 may be formed by high temperature soldering reflow relative to the circuit pattern formed on the package substrate.

可藉由使用幫浦結構310將屏蔽材料注射至注射單元中而於半導體晶片200的上表面上形成屏蔽層220。根據示例性實施例，屏蔽材料可為觸變材料或熱熔材料。屏蔽層220可藉由其中屏蔽材料經由注射單元而注射的分配製程而形成，且因此屏蔽層220可具有包括具有預定曲率半徑的邊緣(參照圖11E)的方形形狀。 The shielding layer 220 may be formed on the upper surface of the semiconductor wafer 200 by using the pump structure 310 to inject the shielding material into the injection unit. According to an exemplary embodiment, the shielding material may be a thixotropic material or a hot-melt material. The shielding layer 220 may be formed by a dispensing process in which the shielding material is injected through an injection unit, and thus the shielding layer 220 may have a square shape including an edge (refer to FIG. 11E) having a predetermined radius of curvature.

此外，可藉由將絕緣材料注射至幫浦結構312的注射單元322中而於半導體晶片200的側表面上形成隔離層210。絕緣材料可為觸變材料或熱熔材料。 In addition, the isolation layer 210 may be formed on the side surface of the semiconductor wafer 200 by injecting an insulating material into the injection unit 322 of the pump structure 312. The insulating material may be a thixotropic material or a hot-melt material.

根據示例性實施例，可經由光源340而對屏蔽材料及絕緣材料進行熱固化或紫外光固化。 According to an exemplary embodiment, the shielding material and the insulating material may be thermally cured or ultraviolet cured via the light source 340.

圖14是用於闡述根據示例性實施例的一種藉由使用圖12所示的三維列印機300來製造半導體封裝100及100a至100h中的至少一者的方法的圖。圖14是用於詳細闡述圖13所示的幫浦結構312的運作的剖視圖。 14 is a diagram for explaining a method of manufacturing at least one of the semiconductor packages 100 and 100a to 100h by using the three-dimensional printer 300 shown in FIG. 12 according to an exemplary embodiment. FIG. 14 is a cross-sectional view for explaining the operation of the pump structure 312 shown in FIG. 13 in detail.

參照圖14，幫浦結構312可包括注射單元322、管324、螺鑽幫浦(auger pump)326、旋轉環(rotation ring)328、及噴嘴332。可將絕緣材料210’裝載於注射單元322中，且可藉由自外部施加的壓力而使絕緣材料210’經由管324流入旋轉環328中。絕 緣材料210’可為觸變材料或熱熔材料。 14, the pump structure 312 may include an injection unit 322, a tube 324, an auger pump 326, a rotation ring 328, and a nozzle 332. The insulating material 210' may be loaded in the injection unit 322, and the insulating material 210' may flow into the rotating ring 328 through the tube 324 by pressure applied from the outside. Absolutely The edge material 210' may be a thixotropic material or a hot melt material.

絕緣材料210’可流入旋轉環328中的開口中，並可經由噴嘴332而在半導體晶片200的側表面上形成隔離層210。旋轉環328可根據螺鑽幫浦326的旋轉力(rotation force)來旋轉，且可藉由因螺鑽幫浦326的旋轉所產生的壓力而在噴嘴332的方向上排出絕緣材料。 The insulating material 210' may flow into the opening in the rotating ring 328, and may form the isolation layer 210 on the side surface of the semiconductor wafer 200 via the nozzle 332. The rotating ring 328 may rotate according to the rotation force of the auger pump 326, and the insulating material may be discharged in the direction of the nozzle 332 by the pressure generated by the rotation of the auger pump 326.

根據示例性實施例，亦可藉由三維列印機300來分配屏蔽材料。所述屏蔽材料可由觸變材料或熱熔材料形成。將參照圖15A至圖16詳細闡述此態樣。 According to an exemplary embodiment, the shielding material may also be distributed by the three-dimensional printer 300. The shielding material may be formed of a thixotropic material or a hot-melt material. This aspect will be explained in detail with reference to FIGS. 15A to 16.

圖15A及圖15B是用於闡述根據示例性實施例的一種藉由使用圖12所示的三維列印機300來製造半導體封裝100及100a至100h中的至少一者的方法的圖。分配頭單元300A(參照圖12)可包括噴嘴330’及塗佈分配器334。 15A and 15B are diagrams for explaining a method of manufacturing at least one of the semiconductor packages 100 and 100a to 100h by using the three-dimensional printer 300 shown in FIG. 12 according to an exemplary embodiment. The dispensing head unit 300A (refer to FIG. 12) may include a nozzle 330' and a coating dispenser 334.

參照圖15A，可經由塗佈分配器334而以觸變材料或熱熔材料塗佈半導體晶片200的上表面部分，且可藉由使用噴嘴330’而以觸變材料或熱熔材料塗佈半導體晶片200的側表面部分。半導體晶片200的上表面部分與側表面部分彼此交匯的邊緣可具有曲率。圖15B是圖15A所示的部分A15的放大圖。 15A, the upper surface portion of the semiconductor wafer 200 may be coated with a thixotropic material or hot melt material through the coating dispenser 334, and the semiconductor may be coated with a thixotropic material or hot melt material by using the nozzle 330' The side surface portion of the wafer 200. The edge where the upper surface portion and the side surface portion of the semiconductor wafer 200 meet each other may have a curvature. 15B is an enlarged view of the portion A15 shown in FIG. 15A.

參照圖15B，可藉由使用側表面處具有開口336的噴嘴330’而以觸變材料或熱熔材料塗佈半導體晶片200的側表面部分。 15B, the side surface portion of the semiconductor wafer 200 may be coated with a thixotropic material or a hot-melt material by using the nozzle 330' having an opening 336 at the side surface.

此外，根據示例性實施例，可藉由材料供應裝置來形成隔離層或屏蔽層，所述材料供應裝置包括開口336，開口336具有與 所述隔離層或所述屏蔽層的側表面相同的形狀。舉例而言，開口336可具有狹縫形狀(slit shape)。開口336可根據需要而具有各種形狀。可藉由使用側表面的開口336而輕易地對所述側表面部分執行三維印刷。 In addition, according to an exemplary embodiment, the isolation layer or the shielding layer may be formed by a material supply device including an opening 336 having an opening The side surfaces of the isolation layer or the shielding layer have the same shape. For example, the opening 336 may have a slit shape. The opening 336 may have various shapes as needed. Three-dimensional printing can be easily performed on the side surface portion by using the opening 336 on the side surface.

圖16A及圖16B是用於闡述根據示例性實施例的一種製造半導體封裝的方法的圖。圖16A及圖16B是藉由使用圖12所示的三維列印機300的噴嘴330a及330b而在半導體晶片200a及200b上形成觸變材料210a、210b、212a、及212b的方法的圖。 16A and 16B are diagrams for explaining a method of manufacturing a semiconductor package according to an exemplary embodiment. 16A and 16B are diagrams of a method of forming thixotropic materials 210a, 210b, 212a, and 212b on semiconductor wafers 200a and 200b by using the nozzles 330a and 330b of the three-dimensional printer 300 shown in FIG.

參照圖16A，可使用噴嘴330a而將觸變材料210a及212a分配至半導體晶片200a上。舉例而言，觸變材料210a可藉由高剪切應力而具有低黏度，且觸變材料212a可藉由低剪切應力而具有高黏度。 Referring to FIG. 16A, the nozzle 330a may be used to dispense the thixotropic materials 210a and 212a onto the semiconductor wafer 200a. For example, the thixotropic material 210a may have low viscosity due to high shear stress, and the thixotropic material 212a may have high viscosity due to low shear stress.

參照圖16B，可使用噴嘴330b而將觸變材料210b及212b分配至半導體晶片200b上。舉例而言，觸變材料210b可藉由高剪切應力而具有低黏度，且觸變材料212b可藉由低剪切應力而具有高黏度。 Referring to FIG. 16B, the nozzle 330b may be used to distribute the thixotropic materials 210b and 212b onto the semiconductor wafer 200b. For example, the thixotropic material 210b may have low viscosity due to high shear stress, and the thixotropic material 212b may have high viscosity due to low shear stress.

如圖16A及圖16B所示，觸變材料210a、210b、212a及212b可形成為層。此外，圖16B所示的情形可達成較圖16A所示的情形高的觸變特性。因此，圖16B所示的情形可因較高的觸變特性而達成較圖16A所示的情形高的長寬比。 As shown in FIGS. 16A and 16B, the thixotropic materials 210a, 210b, 212a, and 212b may be formed as layers. In addition, the situation shown in FIG. 16B can achieve higher thixotropic characteristics than the situation shown in FIG. 16A. Therefore, the situation shown in FIG. 16B can achieve a higher aspect ratio than the situation shown in FIG. 16A due to the higher thixotropic characteristics.

圖17是根據示例性實施例的半導體封裝1100的結構的示意圖。 FIG. 17 is a schematic diagram of a structure of a semiconductor package 1100 according to an exemplary embodiment.

參照圖17，半導體封裝1100可包括微處理單元(micro-processing unit，MPU)1110、記憶體模組1120、介面1130、圖形處理單元(graphic-processing unit，GPU)1140、功能區塊(function block)1150及連接微處理單元1110、記憶體模組1120、介面1130、圖形處理單元1140、及功能區塊1150的匯流排1160。半導體封裝1100可包括微處理單元1110及圖形處理單元1140兩者，或者半導體封裝1100可僅包括微處理單元1110及圖形處理單元1140中的一者。 Referring to FIG. 17, the semiconductor package 1100 may include a micro-processing unit (MPU) 1110, a memory module 1120, an interface 1130, a graphic-processing unit (GPU) 1140, and a function block ) 1150 and a bus 1160 connecting the micro-processing unit 1110, the memory module 1120, the interface 1130, the graphics processing unit 1140, and the functional block 1150. The semiconductor package 1100 may include both the micro processing unit 1110 and the graphics processing unit 1140, or the semiconductor package 1100 may include only one of the micro processing unit 1110 and the graphics processing unit 1140.

微處理單元1110可包括核心處理器(core processor)及二級(level-2，L2)快取。舉例而言，微處理單元1110可包括多個處理單元。所述多個處理單元中的每一者可具有相同的或不同的效能。此外，所述多個處理單元可同時活動或可不同時活動。記憶體模組1120可包括一或多個記憶體晶片且可在微處理單元1110的控制下儲存例如功能區塊1150的處理結果。介面1130可使得半導體封裝1100與外部裝置介接。舉例而言，介面1130可與照相機、液晶顯示器(liquid crystal display，LCD)、揚聲器等介接。 The micro-processing unit 1110 may include a core processor and a level-2 (L2) cache. For example, the micro-processing unit 1110 may include multiple processing units. Each of the plurality of processing units may have the same or different performance. Furthermore, the multiple processing units may be active at the same time or may be active at different times. The memory module 1120 may include one or more memory chips and may store the processing result of the functional block 1150 under the control of the micro-processing unit 1110, for example. The interface 1130 can allow the semiconductor package 1100 to interface with external devices. For example, the interface 1130 can interface with a camera, a liquid crystal display (LCD), a speaker, and the like.

圖形處理單元1140可執行例如視訊編碼及解碼、或三維圖形(3D graphics)等圖形功能。 The graphics processing unit 1140 can perform graphics functions such as video encoding and decoding, or 3D graphics.

功能區塊1150可執行各種功能。舉例而言，當半導體封裝1100為用於行動裝置中的應用程式處理器時，功能區塊1150中的某些可執行通訊功能。 The functional block 1150 can perform various functions. For example, when the semiconductor package 1100 is an application processor used in a mobile device, some of the functional blocks 1150 can perform communication functions.

半導體封裝1100可為參照圖1至圖10所闡述的半導體 封裝100及100a至100h中的至少一者。微處理單元1110及/或圖形處理單元1140可為參照圖1至圖10所示半導體晶片130及130a至130h中的至少一者。記憶體模組1120可為參照圖1至圖10所示半導體晶片130及130a至130h中的至少一者。 The semiconductor package 1100 may be the semiconductor explained with reference to FIGS. 1 to 10 At least one of the packages 100 and 100a to 100h. The micro processing unit 1110 and/or the graphics processing unit 1140 may be at least one of the semiconductor wafers 130 and 130a to 130h shown in FIGS. 1 to 10. The memory module 1120 may be at least one of the semiconductor chips 130 and 130a to 130h shown in FIGS. 1 to 10.

介面1130及功能區塊1150可對應於參照圖1至圖10所示半導體晶片130及130a至130h中的某些。 The interface 1130 and the functional block 1150 may correspond to some of the semiconductor chips 130 and 130a to 130h shown in FIGS. 1 to 10.

半導體封裝1100可包括微處理單元1110及/或圖形處理單元1140、以及記憶體模組1120。此外，由於半導體封裝1100可將在微處理單元1110及/或圖形處理單元1140中所產生的電磁干擾快速排出至半導體封裝1100的外部，故可防止可在半導體封裝1100中發生的局部熱集中現象(partial heat concentration phenomenon)。因此，可提高半導體封裝1100的運作可靠性且半導體封裝1100可具有更高容量、更高效能、及更高可靠性。 The semiconductor package 1100 may include a micro-processing unit 1110 and/or a graphics processing unit 1140, and a memory module 1120. In addition, since the semiconductor package 1100 can quickly discharge the electromagnetic interference generated in the micro processing unit 1110 and/or the graphics processing unit 1140 to the outside of the semiconductor package 1100, the local heat concentration phenomenon that can occur in the semiconductor package 1100 can be prevented (partial heat concentration phenomenon). Therefore, the operational reliability of the semiconductor package 1100 can be improved and the semiconductor package 1100 can have higher capacity, higher performance, and higher reliability.

圖18是根據示例性實施例的包括半導體封裝的電子系統1200的圖。 FIG. 18 is a diagram of an electronic system 1200 including a semiconductor package according to an exemplary embodiment.

參照圖18，微處理單元(MPU)/圖形處理單元(GPU)1210可裝設於電子系統1200中。電子系統1200可為例如行動裝置、桌上型電腦(desk top computer)、或伺服器。此外，電子系統1200可更包括記憶體裝置1220、輸入/輸出裝置1230、及顯示裝置1240，其可電性連接至匯流排1250。微處理單元/圖形處理單元1210及記憶體裝置1220可為參照圖1至圖10所闡述的半導體封裝100及100a至100h中的至少一者。 Referring to FIG. 18, a micro processing unit (MPU)/graphic processing unit (GPU) 1210 may be installed in the electronic system 1200. The electronic system 1200 may be, for example, a mobile device, a desktop top computer, or a server. In addition, the electronic system 1200 may further include a memory device 1220, an input/output device 1230, and a display device 1240, which may be electrically connected to the bus 1250. The micro processing unit/graphic processing unit 1210 and the memory device 1220 may be at least one of the semiconductor packages 100 and 100a to 100h described with reference to FIGS. 1 to 10.

圖19是包括半導體封裝1310的電子裝置的示意性立體圖。 19 is a schematic perspective view of an electronic device including a semiconductor package 1310.

圖19說明其中電子系統1200應用於行動電話1300中的實例。根據示例性實施例，行動電話1300可為包括安裝及執行應用程式的功能的智慧型電話。行動電話1300可包括用於接收應用程式的安裝資料的通訊模組、用於儲存應用程式的安裝資料的記憶體模組、及用於基於應用程式的安裝資料來安裝應用程式及執行所安裝的應用程式的應用程式處理器(AP)。所述應用程式處理器可包括微處理單元或圖形處理單元。所述應用程式處理器及/或所述記憶體可包括半導體封裝1310。半導體封裝1310可為參照圖1至圖10所闡述的半導體封裝100及100a至100h中的至少一者。 FIG. 19 illustrates an example in which the electronic system 1200 is applied to the mobile phone 1300. According to an exemplary embodiment, the mobile phone 1300 may be a smart phone including functions to install and execute application programs. The mobile phone 1300 may include a communication module for receiving the installation data of the application, a memory module for storing the installation data of the application, and an application-based installation data for installing the application and executing the installed The application processor (AP) of the application. The application processor may include a micro-processing unit or a graphics processing unit. The application processor and/or the memory may include a semiconductor package 1310. The semiconductor package 1310 may be at least one of the semiconductor packages 100 and 100a to 100h explained with reference to FIGS. 1 to 10.

行動電話1300在具有高可靠性的同時可包括半導體封裝1310，半導體封裝1310包括高效能應用程式處理器及高容量記憶體裝置，且因此行動電話1300可被微型化且可具有高效能。 The mobile phone 1300 may include a semiconductor package 1310 while having high reliability. The semiconductor package 1310 includes a high-performance application processor and a high-capacity memory device, and thus the mobile phone 1300 may be miniaturized and may have high performance.

此外，電子系統1200可應用於可攜式膝上型電腦、MP3播放機、導航裝置、固態磁碟(solid state disk，SSD)、汽車、或家用電器。 In addition, the electronic system 1200 can be applied to portable laptop computers, MP3 players, navigation devices, solid state disks (SSDs), automobiles, or household appliances.

應理解，本文所述示例性實施例應僅被視為具有說明性意義而非用於限制目的。在每一示例性實施例中對特徵或態樣的說明應通常被視為亦適用於其他示例性實施例中的其他相似特徵或態樣。 It should be understood that the exemplary embodiments described herein should be considered only for illustrative purposes and not for limiting purposes. The description of features or aspects in each exemplary embodiment should generally be considered to be applicable to other similar features or aspects in other exemplary embodiments.

儘管已參照圖闡述了一或多個示例性實施例，然而此項 技術中具有通常知識者應理解，可對其作出各種形式及細節上的變化，而此並不背離由以下申請專利範圍所界定的精神及範圍。 Although one or more exemplary embodiments have been described with reference to the drawings, this item Those with ordinary knowledge in the technology should understand that they can make various changes in form and detail without departing from the spirit and scope defined by the scope of the following patent applications.

100‧‧‧半導體封裝 100‧‧‧Semiconductor packaging

110‧‧‧隔離層 110‧‧‧ isolation layer

120‧‧‧屏蔽層 120‧‧‧Shield

130‧‧‧半導體晶片 130‧‧‧Semiconductor chip

140‧‧‧封裝基板 140‧‧‧Package substrate

150、151‧‧‧接觸焊墊 150, 151‧‧‧ contact pad

a‧‧‧距離 a‧‧‧Distance

b‧‧‧高度 b‧‧‧height

Claims (11)

一種半導體封裝，包括：半導體晶片，裝設於基板上；以及屏蔽層，覆蓋所述半導體晶片的至少一部分；其中所述屏蔽層的側表面部分的厚度小於所述屏蔽層的所述側表面部分的高度，其中所述屏蔽層包括邊緣，所述屏蔽層的上表面與所述屏蔽層的側表面在所述邊緣上彼此接觸，所述邊緣具有預定曲率半徑，所述預定曲率半徑小於所述屏蔽層的所述上表面的厚度與所述屏蔽層的所述側表面的厚度之和。 A semiconductor package includes: a semiconductor wafer mounted on a substrate; and a shielding layer covering at least a portion of the semiconductor wafer; wherein a thickness of a side surface portion of the shielding layer is smaller than the side surface portion of the shielding layer Height, wherein the shielding layer includes an edge, an upper surface of the shielding layer and a side surface of the shielding layer contact each other on the edge, the edge has a predetermined radius of curvature, the predetermined radius of curvature is less than the The sum of the thickness of the upper surface of the shield layer and the thickness of the side surface of the shield layer. 如申請專利範圍第1項所述的半導體封裝，其中所述半導體封裝包括多晶片封裝。 The semiconductor package as described in item 1 of the patent application range, wherein the semiconductor package includes a multi-chip package. 如申請專利範圍第1項所述的半導體封裝，其中所述屏蔽層的所述側表面部分的所述厚度小於所述屏蔽層的所述側表面部分的所述高度的五分之一。 The semiconductor package according to item 1 of the patent application range, wherein the thickness of the side surface portion of the shield layer is less than one fifth of the height of the side surface portion of the shield layer. 如申請專利範圍第1項所述的半導體封裝，其中所述屏蔽層的上表面與所述屏蔽層的側表面形成實質上90°的角度。 The semiconductor package as described in item 1 of the patent application range, wherein the upper surface of the shield layer and the side surface of the shield layer form an angle of substantially 90°. 如申請專利範圍第1項所述的半導體封裝，更包括位於所述半導體晶片與所述屏蔽層之間的隔離層，所述隔離層包含觸變材料或熱熔材料。 The semiconductor package according to item 1 of the scope of the patent application further includes an isolation layer between the semiconductor wafer and the shielding layer, the isolation layer containing a thixotropic material or a hot-melt material. 如申請專利範圍第5項所述的半導體封裝，其中所述屏蔽層包含金屬材料。 The semiconductor package as described in item 5 of the patent application range, wherein the shielding layer includes a metal material. 如申請專利範圍第5項所述的半導體封裝，其中所述屏蔽層及所述隔離層中的至少一者是藉由三維印刷形成。 The semiconductor package as described in item 5 of the patent application range, wherein at least one of the shielding layer and the isolation layer is formed by three-dimensional printing. 一種製造半導體封裝的方法，所述製造半導體封裝的方法包括：將半導體晶片裝設於基板上；形成覆蓋所述半導體晶片的至少一部分的隔離層，所述隔離層包含觸變材料或熱熔材料；以及形成屏蔽層，所述屏蔽層覆蓋所述隔離層及所述半導體晶片的至少一部分，其中形成所述屏蔽層包括藉由使用觸變材料或熱熔材料的三維印刷來形成所述屏蔽層，且其中所述屏蔽層包括邊緣，所述屏蔽層的上表面與所述屏蔽層的側表面在所述邊緣上彼此接觸，所述邊緣具有預定曲率半徑，所述預定曲率半徑小於所述屏蔽層的所述上表面的厚度與所述屏蔽層的所述側表面的厚度之和。 A method for manufacturing a semiconductor package, which includes: mounting a semiconductor wafer on a substrate; forming an isolation layer covering at least a portion of the semiconductor wafer, the isolation layer containing a thixotropic material or a hot-melt material And forming a shielding layer covering the isolation layer and at least a portion of the semiconductor wafer, wherein forming the shielding layer includes forming the shielding layer by three-dimensional printing using a thixotropic material or a hot-melt material , And wherein the shielding layer includes an edge, an upper surface of the shielding layer and a side surface of the shielding layer are in contact with each other on the edge, the edge has a predetermined radius of curvature, the predetermined radius of curvature is smaller than the shielding The sum of the thickness of the upper surface of the layer and the thickness of the side surface of the shielding layer. 如申請專利範圍第8項所述的製造半導體封裝的方法，其中所述隔離層的厚度與所述屏蔽層的厚度之和小於所述隔離層的高度。 The method for manufacturing a semiconductor package as described in item 8 of the patent application range, wherein the sum of the thickness of the isolation layer and the thickness of the shielding layer is less than the height of the isolation layer. 如申請專利範圍第8項所述的製造半導體封裝的方法，其中所述隔離層的厚度與所述屏蔽層的厚度之和小於所述隔離層的高度的五分之一。 The method for manufacturing a semiconductor package as described in item 8 of the patent application range, wherein the sum of the thickness of the isolation layer and the thickness of the shielding layer is less than one fifth of the height of the isolation layer. 如申請專利範圍第8項所述的製造半導體封裝的方法，其中所述隔離層是藉由材料供應裝置形成，所述材料供應裝置包括開口，所述開口具有與對應的所述隔離層的側表面形狀相同的形狀。 The method of manufacturing a semiconductor package as described in item 8 of the patent application range, wherein the isolation layer is formed by a material supply device including an opening having a side corresponding to the isolation layer The shape of the surface is the same.
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