TWI690923B - Memory and operating method thereof - Google Patents

Abstract

A memory includes a memory array, multiple match lines and multiple sets of search lines. The memory array includes multiple memory cells. Each memory cell includes an output terminal, two rectifier elements and two resistor elements. The two resistor elements are configured to store two bits representing a data status. The match lines are coupled to output terminals of the memory cells respectively. Each set of search lines includes a first search line and a second search line. A first resistor element and a first rectifier element of the same memory cell are connected in series between the first search line of the same set of search lines and the output terminal. A second resistor element and a second rectifier element of the same memory cell are connected in series between the second search line of the same set of search lines and the output terminal.

Description

Memory and operation method

This disclosure relates to a memory and its operating method, and in particular to a content addressable memory and its operating method.

With the development of science and technology, the ability to carry out fast and massive data operations is the goal pursued by more and more products. And in order to extend the standby time of electronic products, while performing a large number of calculations, it is also necessary to reduce power consumption.

Content addressable memory is a special type of memory. According to the data word provided by the user, all storage units in the memory can be searched to generate the address of the storage unit storing this data word. Therefore, the features of content-addressable memory with lower power consumption and suitable for high-speed search procedures are expected to meet the aforementioned requirements. How to balance the reliability of the operation and the size of the memory unit is one of the important topics in this field.

An aspect of the present disclosure relates to a memory, including: a memory cell array, a plurality of matching lines, and a plurality of pairs of search lines. The memory cell array includes a plurality of memory cells. Any one of the memory cells includes an output terminal, two rectifier elements and Two resistance elements. The two resistance elements are configured to store two bit values representing the state of the data. The matching lines are respectively coupled to the output ends of the memory cells. The search lines are respectively coupled to the memory cells. Any one of the plural search lines includes a first search line and a second search line. The first resistive element and the first rectifying element of the same memory cell are connected in series between the first search line of the same pair of search lines and the output end of the memory cell. The second resistance element and the second rectifying element of the same memory cell are connected in series between the second search line of the same pair of search lines and the output end of the memory cell.

An aspect of the present disclosure relates to a method of operating a memory, including: configuring the resistance values of the first resistance element and the second resistance element of each of the plurality of memory cells to store two bit values representing the data state; The multiplexing circuits respectively receive the plural search character values of the search data and output the bias voltage to the first search line or the second search line of the plural pair search lines according to the plural search character values; through the first search line or The second search line provides a bias voltage to the first resistance element or the second resistance element in the plurality of memory cells, respectively, to generate a reading current value to a corresponding one of the plurality of matching lines; and detect the reading current value to output Represents search results that match the value of the search character with the status of the data.

100, 100a, 100b ‧‧‧ addressable memory

120‧‧‧Memory Cell Array

122、C[1,1]~C[3,4]‧‧‧memory cell

140‧‧‧Control circuit

142、U[1]~U[3]‧‧‧multiplex circuit

160‧‧‧detection circuit

W1~W4‧‧‧Save data

DIN‧‧‧Search data

RS‧‧‧Search results

DIN[1]~DIN[3], DIN[k]‧‧‧ search character value

BIA[1]~BIA[3], BIA[k], INH[k]‧‧‧bias

SLn[1]~SLn[3], SL[1]~SL[3], SLn[k], SL[k]‧‧‧Search line

ML[1]~ML[4], ML[j]‧‧‧‧matching line

OUT[1]~OUT[4]‧‧‧Read current value

Ra, Rb‧‧‧resistance element

122a, 122b‧‧‧Rectifier

Dia, Dib‧‧‧Diode components

N1‧‧‧ output

Io‧‧‧Output current

A1, A2, A3

FIG. 1 is a block diagram of a content addressable memory according to some embodiments of the present disclosure.

FIG. 2 is a schematic circuit diagram of a content addressable memory according to some embodiments of the present disclosure.

FIG. 3A illustrates a multi-purpose power supply according to some embodiments of the present disclosure Circuit diagram of circuit and memory cell.

FIG. 3B is a schematic circuit diagram of another multiplex circuit and memory cell according to other embodiments of the present disclosure.

FIG. 4 is a schematic circuit diagram of another multiplex circuit and memory cell according to other embodiments of the present disclosure.

FIG. 5A is a schematic diagram illustrating the operation of a multiplexed circuit and a memory cell according to some embodiments of the present disclosure.

FIG. 5B is a schematic diagram illustrating the operation of another multiplexing circuit and memory cell according to other embodiments of the present disclosure.

FIG. 6 is a perspective view of a content addressable memory according to some embodiments of the present disclosure.

FIG. 7 is a perspective view showing another addressable memory according to other embodiments of the present disclosure.

The following is a detailed description of the embodiments in conjunction with the drawings, but the specific embodiments described are only used to explain the case, not to limit the case, and the description of the structural operation is not used to limit the order of execution, any component The recombined structure and the resulting devices with equal effects are all covered by the disclosure.

Terms used throughout the specification and the scope of patent application, unless otherwise specified, usually have the ordinary meaning that each term is used in this field, in the content disclosed herein, and in special content.

The words "include", "have", etc. used in this article, Both are open terms, meaning "including but not limited to". In addition, "and/or" as used in this article includes any one or more of the listed items and all combinations thereof.

With regard to "coupled" or "connected" as used in this article, it can mean that two or more elements are in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, or two or more Elements interoperate or act.

The terms "first", "second", "third", etc. used in this article do not specifically refer to order or order, nor are they intended to limit this disclosure. They are merely used to distinguish the same technology The term describes the element or operation only.

Please refer to Figure 1. FIG. 1 is a block diagram of a content addressable memory 100 according to some embodiments of the present disclosure. As shown in FIG. 1, the content addressable memory 100 includes a memory cell array 120, a control circuit 140, and a detection circuit 160. The memory cell array 120 includes a plurality of memory cells 122 arranged in an array. In operation, the control circuit 140 is used to receive the search data DIN and selectively output the bias voltage to the corresponding memory cells in the memory cell array 120 for data comparison according to the search data DIN. When a bias voltage is applied to the memory cells in the memory cell array 120, the memory cells will output corresponding output currents according to the state of the data stored in the memory cells. The detection circuit 160 receives a plurality of output currents output by the memory cell array 120, and outputs search results RS according to the corresponding reading current values OUT[1] to OUT[4] of the plurality of output currents. In an embodiment, the detection circuit 160 includes a current detection amplifier circuit (sense amplifier) and an encoder circuit (encoder). The current detection amplifier circuit will read the current value OUT[1] ~OUT[4] amplification, the encoding circuit generates the search result RS based on the amplified read current value OUT[1]~OUT[4].

For example, as shown in FIG. 1, the memory cells 122 in the memory cell array 120 store a total of four stored data, which are respectively the first stored data W1 "110" and the second stored data W2 "101" 3. The third stored data W3 "111" and the fourth stored data W4 "000". In this exemplary description, each stored data W1~W4 contains three characters, each composed of three different memory cells 122. It is stored, but this document does not limit the single stored data to three characters. The number of characters in each stored data can be determined according to the actual application, for example, each pen contains 8 characters and 16 characters Or 32 characters or other positive integer characters.

In the embodiment shown in FIG. 1, it is assumed that the search data DIN includes three character values "101". Since only the first character value in the memory cell storing the first stored data W1 "110" matches, so The read current value OUT[1] received by the detection circuit 160 is a unit size. Since the first, second, and third character values in the memory cell storing the second stored data W2 "101" all match, the read current value OUT[2] received by the detection circuit 160 is three units size. Since the first and third character values in the memory cell storing the third storage data W3 "111" match, the read current value OUT[3] received by the detection circuit 160 is two units in size. Since the second character value in the memory cell storing the fourth stored data W4 "000" matches, the read current value OUT[4] received by the detection circuit 160 is a unit size. In this way, by reading the current values OUT[1] to OUT[4] received by the detection circuit 160 and using the largest of them (such as: reading the current value OUT[2]) as the search result RS, Find match Search the address of the memory cell of the data DIN "101" (ie, the three memory cells storing the second stored data W2).

In some embodiments of the content addressable memory 100, the character value stored in the memory cell 122 allows the data state "X" to be stored, which is represented as "don't care". When the character value of the memory cell 122 is set to "X", regardless of the search character value being "1" or "0", the comparison result of the corresponding memory cell 122 is consistent.

For example, assuming that a certain stored data in the memory cell array 120 is "10X", no matter whether the search data DIN is "101" or "100", the data states of the multiple memory cells storing "10X" are all consistent. Therefore, regardless of whether the search data DIN is "101" or "100", the corresponding read current value received by the detection circuit 160 is three units in size.

Please refer to Figure 2. FIG. 2 is a schematic circuit diagram of a content addressable memory 100 according to some embodiments of the present disclosure. As shown in FIG. 2, the content addressable memory 100 includes a memory cell array 120, a control circuit 140, a search line, and a match line. The memory cell array 120 includes a plurality of memory cells 122 arranged in an array. The control circuit 140 includes a plurality of multiplex circuits 142. The number of memory cells 122 included in each row of the memory cell array 120 is the same as the number of matching lines, that is, it is related to the total number of data stored in the addressable memory 100. The number of memory cells 122 included in each row of the memory cell array 120 is the same as the logarithm of the search line, that is, related to the number of bits included in each stored data. For example, if the content addressable memory 100 includes 1024 pieces of stored data, the number of memory cells 122 in each row may be 1024. If each stored data contains 8 bits, then each row of memory cells 122 can be 8.

In this embodiment, for convenience of description, the content addressable memory 100 includes 4 pieces of stored data, and each piece of stored data includes 3 bits as an example for description, but this case is not limited to this. In other words, the content addressable memory 100 will include three pairs of search lines SLn[1]~SLn[3] and SL[1]~SL[3] and four matching lines ML[ 1]~ML[4], the control circuit 140 includes three multiplex circuits U[1]~U[3], and the memory cell array 120 includes twelve memory cells C[1,1]~C[3,4] For example, but this case is not limited to this.

As shown in FIG. 2, in structure, the multiplex circuit U[1] is coupled to the memory cells C[1,1]~C[1,4] through the first pair of search lines SLn[1] and SL[1]. The multiplex circuit U[2] is coupled to the memory cells C[2,1]~C[2,4] through the second pair of search lines SLn[2] and SL[2]. The multiplex circuit U[3] is coupled to the memory cells C[3,1]~C[3,4] through the third pair of search lines SLn[3] and SL[3]. Matching line ML[1] is coupled to the output of memory cells C[1,1]~C[3,1]. Matching line ML[2] is coupled to the output of memory cells C[1,2]~C[3,2]. The matching line ML[3] is coupled to the output of memory cells C[1,3]~C[3,3]. Matching line ML[4] is coupled to the output of memory cells C[1,4]~C[3,4].

In operation, the search data DIN contains three search character values DIN[1]~DIN[3] as an example. The multiplexing circuit U[1] is used to selectively turn on the search line SLn[1] or the search line SL[1] in the first pair of search lines according to the search character value DIN[1] in the search data DIN, so that The search character value DIN[1] is compared with the state of the data stored in memory cells C[1,1]~C[1,4]. Similarly, the multiplexing circuit U[2] is used to selectively turn on the search line SLn[2] or the search line SL[2] in the second pair of search lines according to the search character value DIN[2] in the search data DIN , To search the data value stored in the character value DIN[2] and memory cells C[2,1]~C[2,4] To compare. The multiplexing circuit U[3] is used to selectively turn on the search line SLn[3] or the search line SL[3] in the third pair of search lines according to the search character value DIN[3] in the search data DIN, so that The search character value DIN[3] is compared with the state of the data stored in memory cells C[3,1]~C[3,4].

In other words, the memory cells coupled to the same pair of search lines share the same one in the multiplex circuit. For example, memory cells C[1,1]~C[1,4] coupled to the search lines SLn[1] and SL[1] share the multiplex circuit U[1]. The memory cells C[2,1]~C[2,4] coupled to the search lines SLn[2] and SL[2] share the multiplex circuit U[2]. The memory cells C[3,1]~C[3,4] coupled to the search lines SLn[3] and SL[3] share the multiplex circuit U[3]. In other words, the state of the data stored in any one of memory cells C[1,1]~C[1,4] is compared with the search character value DIN[1], memory cell C[2,1]~ The state of the data stored in any one of C[2,4] is compared with the search character value DIN[2], and the memory stored in any one of C[3,1]~C[3,4] The data status is compared with the search character value DIN[3].

Specifically, please refer to Figure 3A for the detailed circuit of the memory cell. FIG. 3A is a schematic circuit diagram of a multiplexing circuit 142 and a memory cell 122 according to some embodiments of the present disclosure. As shown in FIG. 3A, the memory cell 122 includes two rectifying elements 122a and 122b, two resistive elements Ra and Rb, and an output terminal N1. It is worth noting that any memory cell 122 in the memory cell array 120 in FIG. 2 can be implemented by the memory cell 122 in FIG. 3A. For ease of description, the search lines SLn[k], SL[k] and the matching lines ML[j] coupled to the memory cell 122 shown in FIG. 3A do not indicate that the digital index system represents the memory cell array 120 The search line and the matching line to which the unspecified memory cells 122 are correspondingly coupled.

As shown in FIG. 3A, in structure, the multiplexing circuit 142 is coupled to the memory cell 122 through a pair of search lines SLn[k] and SL[k]. The output terminal N1 of the memory cell 122 is coupled to the matching line ML[j]. Specifically, the resistive element Ra and the rectifying element 122a coupled to the memory cell 122 of the same pair of search lines are connected in series between the search line SLn[k] and the output terminal N1 of the memory cell 122. The resistance element Rb and the rectifying element 122b of the memory cell 122 coupled to the same pair of search lines are connected in series between the search line SL[k] and the output terminal N1 of the memory cell. In other words, the resistance element Ra and the rectifying element 122a of the same memory cell 122 are connected in series between the search line SLn[k] of the same pair of search lines and the output terminal N1 of the memory cell 122. The resistance element Rb and the rectifying element 122b of the same memory cell 122 are connected in series between the search line SL[k] of the same pair of search lines and the output terminal N1 of the memory cell.

For example, in some embodiments, as shown in FIG. 3A, the first end of the resistive element Ra is coupled to the search line SLn[k], and the second end of the resistive element Ra is coupled to the first end of the rectifying element 122a, The second terminal of the rectifying element 122a is coupled to the output terminal N1. The first end of the resistance element Rb is coupled to the search line SL[k], the second end of the resistance element Rb is coupled to the first end of the rectification element 122b, and the second end of the rectification element 122b is coupled to the output end N1.

In some other embodiments, as shown in FIG. 3B, the first end of the rectifying element 122a is coupled to the search line SLn[k], and the second end of the rectifying element 122a is coupled to the first end of the resistive element Ra, and the resistive element Ra The second terminal of is coupled to the output terminal N1. The first end of the rectifying element 122b is coupled to the search line SL[k], the second end of the rectifying element 122b is coupled to the first end of the resistance element Rb, and the second end of the resistance element Rb is coupled to the output end N1.

It is worth noting that in some other embodiments, the search line SLn[k] and the output terminal N1 may be as shown in FIG. 3A, and the search line SL[k] and the output terminal N1 may be as shown in FIG. 3B. As shown. Alternatively, the search line SLn[k] and the output terminal N1 may be as shown in FIG. 3B, and the search line SL[k] and the output terminal N1 may be as shown in FIG. 3A.

In addition, in this case, the rectifying elements 122a and 122b can be implemented by the diode elements Dia and Dib as shown in FIG. For example, the diode elements Dia and Dib may be pn junction diodes, schottky diodes, ovonic threshold switches or Mott insulators. insulator) etc.

In operation, the resistive elements Ra and Rb in the memory cell 122 are configured to store the first bit value and the second bit value representing the data state. Specifically, the resistance value of the resistance element Ra represents the first bit value. The resistance value of the resistance element Rb represents the second bit value. In this disclosure, the low resistance value represents the logical value "1", and the high resistance value represents the logical value "0".

In some embodiments, the memory cell 122 can store one of two data states. The two data states include data state "0" and data state "1". The resistance values of the resistive elements Ra and Rb of the memory cell 122 representing different data states "0" or "1" are shown in Table 1 below.

When the state of the data stored in the memory cell 122 is "0", the resistance value of the resistance element Ra is set to low, the first bit value it represents has a logical value of "1", and the resistance value of the resistance element Rb is set to high, which represents The second bit value of has a logical value "0".

When the data state of the memory cell 122 is "1", the resistance value of the resistance element Ra is set to high, the first bit value it represents has a logic value of "0", and the resistance value of the resistance element Rb is set to low, which represents The second bit value has a logical value "1".

In addition, in some other embodiments, the memory cell 122 may store one of three data states. The three data states include data state "0", data state "1" and data state "X". The resistance values of the resistance elements Ra and Rb of the memory cells 122 representing different data states "0", "1" or "X" are shown in Table 2 respectively.

When the state of the data stored in the memory cell 122 is "0", the resistance value of the resistance element Ra is set to low, the first bit value it represents has a logical value of "1", and the resistance value of the resistance element Rb is set to high, which represents The second bit value of has a logical value "0".

When the data state of the memory cell 122 is "1", the resistance value of the resistance element Ra is set to high, the first bit value it represents has a logic value of "0", and the resistance value of the resistance element Rb is set to low, which represents The second bit value has a logical value "1".

When the data state of the memory cell 122 is "X", the resistance value of the resistance element Ra is set to low, the first bit value it represents has a logical value of "1", and the resistance value of the resistance element Rb is set to low, which represents The second bit value has a logical value "1".

Please refer to Figure 5A. FIG. 5A is a schematic diagram illustrating the operation of a multiplexing circuit 142 and a memory cell 122 according to some embodiments of the present disclosure. The multiplexing circuit 142 is used to selectively turn on the first search line SLn[k] or the second search line SL[k] of the coupled pair of search lines according to the search character value DIN[k] to search for The character value DIN[k] is compared with the state of the data stored in the memory cell 122.

Specifically, in some embodiments, as shown in FIG. 5A, when the search character value DIN[k] is "1", the multiplexing circuit 142 uses the search character value DIN[k] as "1" The bias voltage BIA[k] is applied to the memory cell 122 through the search line SL[k] corresponding to “1”, and the search line SLn[k] corresponding to “0” is in a floating state. When the search character value DIN[k] is "0" (not shown in the figure), the multiplexing circuit 142 will bias the bias voltage BIA[k] according to "0" search character value DIN[k] by corresponding to " The search line SLn[k] of "0" is applied to the memory cell 122, and the search line SL[k] corresponding to "1" is in an open state. In this way, the memory cell 122 receiving the bias voltage BIA[k] outputs the corresponding output current Io to the matching line ML[j] according to the corresponding resistance element Ra or Rb.

In other partial embodiments, as shown in FIG. 5B, when the search character value DIN[k] is "1", the multiplexing circuit 142 is used to apply the positive bias voltage BIA[k] through the search line SL[k] It is applied to the memory cell 122 and used to apply the non-positive bias INH[k] to the search line SLn[k] corresponding to “0”. When the search character value DIN[k] is "0" (not shown in the figure), the multiplexing circuit 142 is used to apply the positive bias voltage BIA[k] to the memory cell 122 through the search line SLn[k], and used The non-positive bias INH[k] is applied to the search line SL[k] corresponding to "1". Among them, the non-positive bias INH[k] may be a negative bias or a voltage close to zero. In this way, by non-positive bias INH[k], the non-corresponding resistive elements and rectifying elements in the memory cell 122 will not output extra current to the matching line ML[j], resulting in an inaccurate output current Io .

Regarding how the memory cell outputs the corresponding output current Io according to the corresponding resistance element Ra or Rb, please refer to FIG. 5A and Table 3 together.

As shown in Table 3, in some embodiments, since the memory cell 122 has two resistance elements Ra or Rb, when both resistance elements Ra or Rb are set to a high resistance value, the state of the stored data is disabled (disabled). When the storage state of the memory cell 122 is disabled, no matter what the value of the search character is, it will output a low current, which is regarded as a mismatch.

As shown in FIG. 5A, when the search character value DIN[k] is "1", the resistive element Rb in the memory cell 122 will receive the bias voltage BIA[k], and the rectifying element 122a will cause the bias voltage BIA[ k] Does not flow through the resistive element Ra. Because the larger the resistance value through the bias voltage BIA[k], the smaller the output current Io, and the smaller the resistance value through the bias voltage BIA[k], the larger the output current Io. Therefore, when the data state in the memory cell 122 is "0", the resistance element Rb is high resistance, the output current Io is low current, and when the data state in the memory cell 122 is "1", the resistance element Rb is low Resistance, output current Io is high current. In other words, as shown in Table 3, when the search character value is "1", the level of the output current Io is opposite to the level of the resistance of the resistance element Rb. Therefore, according to the output current Io being a high current, the state of the data in the memory cell 122 can be determined to match the search character value. On the other hand, when the output current Io is a low current, it can be determined that the data state in the memory cell 122 does not match the value of the search character.

Similarly, as shown in FIG. 5A, when the search character value DIN[k] is "0", the resistive element Ra in the memory cell 122 will receive the bias voltage BIA[k], and the rectifying element 122b will cause the bias The voltage BIA[k] does not flow through the resistance element Rb. Therefore, when the data state in the memory cell 122 is "0", the resistance element Ra is low resistance, and the output current Io is high current, and when the data state in the memory cell 122 is "1", the resistance element Ra is high Resistance, output current Io is low current. In other words In other words, as shown in Table 3, when the search character value is "0", the level of the output current Io is opposite to that of the resistance element Ra. Therefore, according to the output current Io being a high current, the state of the data in the memory cell 122 can be determined to match the search character value. On the other hand, when the output current Io is a low current, it can be determined that the data state in the memory cell 122 does not match the value of the search character.

It can be seen that when the state of the data stored in the memory cell itself matches the corresponding search character value, the memory cell will output a high current. Conversely, when the state of the data stored in the memory cell itself does not match the corresponding search character value, the memory cell will output a low current.

In this way, the resistance elements Ra and Rb in the memory cell 122 respectively store the corresponding first bit value and second bit value to represent different data states, and the multiplex circuit 142 according to the search character value is "1 "Apply the bias voltage BIA[k] to the resistive element Rb in the memory cell 122 through the search line SL[k], or the bias voltage BIA[k] through the search line SLn[k] according to the value of the search character "0" The resistance element Ra applied to the memory cell 122 can know whether the data state of the memory cell 122 matches the search character value according to the corresponding output current Io. In addition, by the rectifying elements 122a and 122b, it can be ensured that no leakage current flows from the resistance element on the non-biased side.

Please refer back to Figure 2. As shown in Figure 2, when the search character value DIN[1] is "1", the multiplex circuit U[1] turns on the search line SL[1] to bias the bias BIA[1] through the search line SL[1 ] Is applied to memory cells C[1,1]~C[1,4] to compare the second bit value and search character value of memory cells C[1,1]~C[1,4] respectively Whether DIN[1] matches. Conversely, when the search character value DIN[1] is "0", the multiplex circuit U[1] turns on the search line SLn[1] to bias the BIA[1] through the search line SLn[1] is applied to memory cells C[1,1]~C[1,4] to compare the first bit value and search of memory cells C[1,1]~C[1,4] Whether the character value DIN[1] matches.

For example, suppose the search character values DIN[1]~DIN[3] are "1", "0", "1", and memory cells C[1,1]~C[3,1] are stored separately. The data status is "1", "1", "0". According to Table 3, the output currents of memory cells C[1,1]~C[3,1] are "high", "low", and "low", respectively. Therefore, the matching line ML[1] received from the memory cells The reading current value OUT[1] of the total current of C[1,1]~C[3,1] is a unit size.

By analogy, suppose the memory cells C[1,2]~C[3,2], C[1,3]~C[3,3], C[1,4]~C[3,4] are stored separately The data status is "1", "0", "1" and "1", "1", "1" and "0", "0", "0", then memory cell C[1,2]~ The output currents of C[3,2], C[1,3]~C[3,3], C[1,4]~C[3,4] are "high", "high", and "high" respectively And "high", "low", "high" and "low", "high", "low". Therefore, the read current values OUT[2]~OUT[4] received by the matching lines ML[2]~ML[4] are respectively three, two, and one unit size.

As a result, the detection circuit 160 is based on the largest of the read current values OUT[1] to OUT[4] received from the self-matching lines ML[1] to ML[4] (that is, a three-unit read The current value OUT[2]) is output as the search result RS, and the memory cells C[1,2]~C[3,2] matching the search data DIN of “101” can be found.

Please refer to Figure 6. FIG. 6 is a perspective view of a content addressable memory 100a according to some embodiments of the present disclosure. In part In the embodiment, the content addressable memory 100 in FIG. 2 can be implemented based on the content addressable memory 100a in FIG. 6. In the embodiment of FIG. 6, elements similar to the embodiment of FIG. 2 are denoted by the same element symbols. As shown in FIG. 6, the search lines SL[1] to SL[3] included in the first area A1 may be disposed on the substrate or the first conductive layer. The transmission line, the multiplex circuit and the matching lines ML[1] and ML[2] included in the second area A2 transmitting the search character values DIN[1] to DIN[3] can be disposed on the second conductive layer. The search lines SLn[1]~SLn[3] included in the third area A3 may be disposed on the third conductive layer. In some embodiments, the conductive layer may be made of polysilicon material, metal material or other conductive materials. The search line, matching line, transmission line or other connecting lines can be implemented by laying patterned metal wires in the conductor layer.

Please refer to Figure 7. FIG. 7 is a schematic perspective view of another content-addressable memory 100b according to other embodiments of the present disclosure. In some embodiments, the content addressable memory 100 in FIG. 2 can be implemented based on the content addressable memory 100b in FIG. 7. In the embodiment of FIG. 7, elements similar to the embodiment of FIG. 2 are denoted by the same element symbols. As shown in FIG. 7, the transmission line, the multiplexing circuit, and the search lines SL[1]~SL[3] included in the first area A1 of the transmission search character value DIN[1]~DIN[3] can be set at On the substrate or the first conductive layer. The matching lines ML[1] and ML[2] included in the second area A2 may be disposed on the second conductive layer. The search lines SLn[1]~SLn[3] included in the third area A3 may be disposed on the third conductive layer.

It is worth noting that the content described in Figures 1 to 7 above can address the circuit structure and/or operation of the memory 100. In other embodiments, it can also be used in other types of memory. Reveal content is not based on limit.

Although the disclosed method is shown and described herein as a series of steps or events, it should be understood that the order of the steps or events shown should not be interpreted as limiting. For example, some steps may occur in a different order and/or simultaneously with other steps or events other than those shown and/or described herein. In addition, not all of the steps shown here are necessary to implement one or more aspects or embodiments described herein. In addition, one or more steps herein may also be performed in one or more separate steps and/or stages.

It should be noted that, in the case of no conflict, the various drawings, embodiments, and features and circuits in the present disclosure may be combined with each other. The circuits shown in the drawings are for illustrative purposes only, and are simplified to make the description concise and easy to understand, and are not intended to limit the case. In addition, the various devices, units, and components in the foregoing embodiments may be implemented by various types of digital or analog circuits, or may be implemented by different integrated circuit chips, or integrated into a single chip. The above is only an example, and the disclosure is not limited thereto.

To sum up, in this case, through the application of the above embodiments, the resistance elements Ra and Rb in the memory cell 122 respectively store the corresponding first bit value and second bit value to represent different data states, and through multiplexing The circuit 142 applies the bias voltage BIA[k] to the resistive element Ra or Rb in the memory cell 122 according to the search character value "1" or "0", and then the data of the memory cell 122 can be obtained according to the corresponding output current Io Whether the status matches the search character value. In addition, by the rectifying elements 122a and 122b, it can be ensured that no leakage current flows from the resistance element on the non-biased side.

Although this disclosure has been disclosed as above by way of implementation, it is not intended to limit this disclosure. Those with ordinary knowledge in the technical field can make various changes and modifications within the spirit and scope of this disclosure, so this The scope of protection of the disclosure shall be deemed as defined by the scope of the attached patent application.

122‧‧‧Memory Cell

142‧‧‧multiplex circuit

DIN[k]‧‧‧Search character value

BIA[k]‧‧‧bias

SLn[k], SL[k]‧‧‧ search line

Ra, Rb‧‧‧resistance element

122a, 122b‧‧‧Rectifier

N1‧‧‧ output

ML[j]‧‧‧ Matching line

Claims (9)

A memory, including: a memory cell array, including a plurality of memory cells, any one of the memory cells includes: an output terminal; a first rectifying element and a second rectifying element; and a first resistance element And a second resistive element, the two resistive elements are configured to store two bit values representing a data state; a plurality of matching lines, the plurality of matching lines are respectively coupled to the output terminals of the memory cells; And a plurality of pairs of search lines, the plurality of pairs of search lines are respectively coupled to the memory cells, any one of the plurality of pairs of search lines includes a first search line and a second search line, the same memory cell of the first The resistance element and the first rectification element are connected in series between the first search line of the same pair of search lines and the output end of the same memory cell, and the second resistance element and the second rectification element of the same memory cell are connected in series Between the second search line of the same pair of search lines and the output end of the same memory cell. The memory according to claim 1, wherein the two bit values include a first bit value and a second bit value, and the data state includes one of a first data state and a second data state In addition, when the first bit value has a first logical value and the second bit value has a second logical value, it represents the first data state, and the first bit value has the second logical value and When the second bit value has the first logical value, it represents the second data state. The memory according to claim 1, wherein the two bit values include a first bit value and a second bit value, and the data state includes a first data state, a second data state, and a first One of the three data states, where the first bit value has a first logical value and the second bit value has a second logical value represents the first data state, the first bit value has When the second logical value and the second bit value have the first logical value, the second data state is represented. The first bit value has the first logical value and the second bit value has the first In the case of a logical value, it represents the state of the third data. The memory according to claim 1, further comprising: a plurality of multiplex circuits, the plurality of multiplex circuits are respectively coupled to the plurality of search lines, and the plurality of multiplex circuits are used to selectively conduct according to a search data The first search line or the second search line corresponding to the search lines of the plural pairs. The memory according to claim 4, wherein the memory cells coupled to the same pair of search lines share the same one of the multiplex circuits. The memory according to claim 4, wherein the search data includes a plurality of search character values, and any one of the search character values includes one of a first logical value and a second logical value, when When one of the plurality of search character values is the first logic value, the corresponding one of the plurality of multiplex circuits turns on the first search line, and when one of the plurality of search character values is the first logic value When two logical values The corresponding one of the multiplexed circuits turns on the second search line. The memory according to claim 4, wherein the search data includes a plurality of search character values, and any one of the search character values includes one of a first logical value and a second logical value, when When one of the plurality of search character values is the first logic value, a corresponding one of the plurality of multiplex circuits outputs a positive bias to the first search line and outputs a non-positive bias to the first Two search lines, when one of the plurality of search character values is the second logical value, the corresponding one of the plurality of multiplex circuits outputs the positive bias to the second search line and outputs the non-positive bias Press to the first search line. The memory according to claim 1, wherein a first end of the first resistance element is coupled to the first search line, and a second end of the first resistance element is coupled to a first end of the first rectifier element End, a second end of the first rectifying element is coupled to the output end, a first end of the second resistive element is coupled to the second search line, and a second end of the second resistive element is coupled to the first A first end of the two rectifying elements, a second end of the second rectifying element are coupled to the output end. The memory according to claim 1, wherein a first end of the first rectifying element is coupled to the first search line, and a second end of the first rectifying element is coupled to a first end of the first resistive element End, a second end of the first resistance element is coupled to the output end, a first end of the second rectification element is coupled to the second search line, and a second end of the second rectification element is coupled to the first A first end of the two resistance elements, a second end of the second resistance element are coupled to the output end.

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