TWI690923B - Memory and operating method thereof - Google Patents
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本揭示內容是關於一種記憶體與其操作方法,且特別是有關於一種內容可定址記憶體與其操作方法。 This disclosure relates to a memory and its operating method, and in particular to a content addressable memory and its operating method.
隨著科技發展,能夠進行快速且大量的資料運算是越來越多產品追求的目標。而且為了延長電子產品的待機時間,在進行大量運算的同時,還需要降低功率消耗。 With the development of science and technology, the ability to carry out fast and massive data operations is the goal pursued by more and more products. And in order to extend the standby time of electronic products, while performing a large number of calculations, it is also necessary to reduce power consumption.
內容可定址記憶體(Content addressable memory)為一種特殊類型的記憶體。可根據使用者提供的數據字,搜尋記憶體內全部的儲存單元以產生儲存這個數據字的儲存單元的位址。因此,內容可定址記憶體較低耗能且適用於高速搜尋程序的特性,可望能達到前述需求。而如何兼顧操作的可靠性和記憶體單元的尺寸是本領域重要的課題之一。 Content addressable memory is a special type of memory. According to the data word provided by the user, all storage units in the memory can be searched to generate the address of the storage unit storing this data word. Therefore, the features of content-addressable memory with lower power consumption and suitable for high-speed search procedures are expected to meet the aforementioned requirements. How to balance the reliability of the operation and the size of the memory unit is one of the important topics in this field.
本揭示內容的一態樣係關於一種記憶體,包含:記憶胞陣列、複數條匹配線和複數對搜尋線。記憶胞陣列包含複數個記憶胞。記憶胞之任一者包含輸出端、二個整流元件和 二個電阻元件。二個電阻元件經配置以儲存代表資料狀態之二個位元值。匹配線分別耦接記憶胞的輸出端。搜尋線分別耦接記憶胞。複數對搜尋線之任一者包含第一搜尋線和第二搜尋線。同一個記憶胞的第一電阻元件和第一整流元件串聯於同一對搜尋線的第一搜尋線和此記憶胞的輸出端之間。同一個記憶胞的第二電阻元件和第二整流元件串聯於同一對搜尋線的第二搜尋線和此記憶胞的該輸出端之間。 An aspect of the present disclosure relates to a memory, including: a memory cell array, a plurality of matching lines, and a plurality of pairs of search lines. The memory cell array includes a plurality of memory cells. Any one of the memory cells includes an output terminal, two rectifier elements and Two resistance elements. The two resistance elements are configured to store two bit values representing the state of the data. The matching lines are respectively coupled to the output ends of the memory cells. The search lines are respectively coupled to the memory cells. Any one of the plural search lines includes a first search line and a second search line. The first resistive element and the first rectifying element of the same memory cell are connected in series between the first search line of the same pair of search lines and the output end of the memory cell. The second resistance element and the second rectifying element of the same memory cell are connected in series between the second search line of the same pair of search lines and the output end of the memory cell.
本揭示內容的一態樣係關於一種記憶體的操作方法,包含:配置複數個記憶胞各自的第一電阻元件和第二電阻元件的阻值以儲存代表資料狀態之二個位元值;複數個多工電路分別接收搜尋資料的複數個搜尋字元值並根據複數個搜尋字元值分別輸出偏壓至複數對搜尋線中的第一搜尋線或第二搜尋線;透過第一搜尋線或第二搜尋線分別提供偏壓至複數個記憶胞中的第一電阻元件或第二電阻元件,以產生讀取電流值至複數條匹配線中相應一者;以及偵測讀取電流值以輸出代表搜尋字元值與資料狀態是否匹配的搜尋結果。 An aspect of the present disclosure relates to a method of operating a memory, including: configuring the resistance values of the first resistance element and the second resistance element of each of the plurality of memory cells to store two bit values representing the data state; The multiplexing circuits respectively receive the plural search character values of the search data and output the bias voltage to the first search line or the second search line of the plural pair search lines according to the plural search character values; through the first search line or The second search line provides a bias voltage to the first resistance element or the second resistance element in the plurality of memory cells, respectively, to generate a reading current value to a corresponding one of the plurality of matching lines; and detect the reading current value to output Represents search results that match the value of the search character with the status of the data.
100、100a、100b‧‧‧內容可定址記憶體 100, 100a, 100b ‧‧‧ addressable memory
120‧‧‧記憶胞陣列 120‧‧‧Memory Cell Array
122、C[1,1]~C[3,4]‧‧‧記憶胞 122、C[1,1]~C[3,4]‧‧‧memory cell
140‧‧‧控制電路 140‧‧‧Control circuit
142、U[1]~U[3]‧‧‧多工電路 142、U[1]~U[3]‧‧‧multiplex circuit
160‧‧‧偵測電路 160‧‧‧detection circuit
W1~W4‧‧‧儲存資料 W1~W4‧‧‧Save data
DIN‧‧‧搜尋資料 DIN‧‧‧Search data
RS‧‧‧搜尋結果 RS‧‧‧Search results
DIN[1]~DIN[3]、DIN[k]‧‧‧搜尋字元值 DIN[1]~DIN[3], DIN[k]‧‧‧ search character value
BIA[1]~BIA[3]、BIA[k]、INH[k]‧‧‧偏壓 BIA[1]~BIA[3], BIA[k], INH[k]‧‧‧bias
SLn[1]~SLn[3]、SL[1]~SL[3]、SLn[k]、SL[k]‧‧‧搜尋線 SLn[1]~SLn[3], SL[1]~SL[3], SLn[k], SL[k]‧‧‧Search line
ML[1]~ML[4]、ML[j]‧‧‧匹配線 ML[1]~ML[4], ML[j]‧‧‧‧matching line
OUT[1]~OUT[4]‧‧‧讀取電流值 OUT[1]~OUT[4]‧‧‧Read current value
Ra、Rb‧‧‧電阻元件 Ra, Rb‧‧‧resistance element
122a、122b‧‧‧整流元件 122a, 122b‧‧‧Rectifier
Dia、Dib‧‧‧二極體元件 Dia, Dib‧‧‧Diode components
N1‧‧‧輸出端 N1‧‧‧ output
Io‧‧‧輸出電流 Io‧‧‧Output current
A1、A2、A3‧‧‧區域 A1, A2, A3
第1圖係根據本揭示內容之部分實施例繪示一種內容可定址記憶體的方塊示意圖。 FIG. 1 is a block diagram of a content addressable memory according to some embodiments of the present disclosure.
第2圖係根據本揭示內容之部分實施例繪示一種內容可定址記憶體的電路示意圖。 FIG. 2 is a schematic circuit diagram of a content addressable memory according to some embodiments of the present disclosure.
第3A圖係根據本揭示內容之部分實施例繪示一種多工電 路和記憶胞的電路示意圖。 FIG. 3A illustrates a multi-purpose power supply according to some embodiments of the present disclosure Circuit diagram of circuit and memory cell.
第3B圖係根據本揭示內容之其他部分實施例繪示另一種多工電路和記憶胞的電路示意圖。 FIG. 3B is a schematic circuit diagram of another multiplex circuit and memory cell according to other embodiments of the present disclosure.
第4圖係根據本揭示內容之其他部分實施例繪示另一種多工電路和記憶胞的電路示意圖。 FIG. 4 is a schematic circuit diagram of another multiplex circuit and memory cell according to other embodiments of the present disclosure.
第5A圖係根據本揭示內容之部分實施例繪示一種多工電路和記憶胞的操作示意圖。 FIG. 5A is a schematic diagram illustrating the operation of a multiplexed circuit and a memory cell according to some embodiments of the present disclosure.
第5B圖係根據本揭示內容之其他部分實施例繪示另一種多工電路和記憶胞的操作示意圖。 FIG. 5B is a schematic diagram illustrating the operation of another multiplexing circuit and memory cell according to other embodiments of the present disclosure.
第6圖係根據本揭示內容之部分實施例繪示一種內容可定址記憶體的立體示意圖。 FIG. 6 is a perspective view of a content addressable memory according to some embodiments of the present disclosure.
第7圖係根據本揭示內容之其他部分實施例繪示另一種內容可定址記憶體的立體示意圖。 FIG. 7 is a perspective view showing another addressable memory according to other embodiments of the present disclosure.
下文係舉實施例配合所附圖式作詳細說明,但所描述的具體實施例僅用以解釋本案,並不用來限定本案,而結構操作之描述非用以限制其執行之順序,任何由元件重新組合之結構,所產生具有均等功效的裝置,皆為本揭示內容所涵蓋的範圍。 The following is a detailed description of the embodiments in conjunction with the drawings, but the specific embodiments described are only used to explain the case, not to limit the case, and the description of the structural operation is not used to limit the order of execution, any component The recombined structure and the resulting devices with equal effects are all covered by the disclosure.
在全篇說明書與申請專利範圍所使用之用詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在此揭示之內容中與特殊內容中的平常意義。 Terms used throughout the specification and the scope of patent application, unless otherwise specified, usually have the ordinary meaning that each term is used in this field, in the content disclosed herein, and in special content.
在本文中所使用的用詞『包含』、『具有』等等, 均為開放性的用語,即意指『包含但不限於』。此外,本文中所使用之『及/或』,包含相關列舉項目中一或多個項目的任意一個以及其所有組合。 The words "include", "have", etc. used in this article, Both are open terms, meaning "including but not limited to". In addition, "and/or" as used in this article includes any one or more of the listed items and all combinations thereof.
關於本文中所使用之『耦接』或『連接』,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。 With regard to "coupled" or "connected" as used in this article, it can mean that two or more elements are in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, or two or more Elements interoperate or act.
關於本文中所使用之『第一』、『第二』、『第三』...等,並非特別指稱次序或順位的意思,亦非用以限定本揭示,其僅僅是為了區別以相同技術用語描述的元件或操作而已。 The terms "first", "second", "third", etc. used in this article do not specifically refer to order or order, nor are they intended to limit this disclosure. They are merely used to distinguish the same technology The term describes the element or operation only.
請參考第1圖。第1圖係根據本揭示內容之部分實施例繪示一種內容可定址記憶體100的方塊示意圖。如第1圖所示,內容可定址記憶體100包含記憶胞陣列120、控制電路140和偵測電路160。記憶胞陣列120包含以陣列方式排列的複數個記憶胞122。操作上,控制電路140用以接收搜尋資料DIN,並根據搜尋資料DIN選擇性地輸出偏壓至記憶胞陣列120中相應的記憶胞以進行資料比對。當偏壓被施加於記憶胞陣列120中的記憶胞時,記憶胞會根據自身所儲存的資料狀態不同而輸出對應的輸出電流。偵測電路160接收記憶胞陣列120輸出的多個輸出電流,並根據多個輸出電流相應的讀取電流值OUT[1]~OUT[4]輸出搜尋結果RS。於一實施例中,偵測電路160包含電流偵測放大電路(sense amplifier)以及編碼電路(encoder),電流偵測放大電路將讀取電流值OUT[1]
~OUT[4]放大,編碼電路基於放大後的讀取電流值OUT[1]~OUT[4]產生搜尋結果RS。
Please refer to Figure 1. FIG. 1 is a block diagram of a content
舉例來說,如第1圖中所示,記憶胞陣列120當中的記憶胞122共儲存了四筆儲存資料,分別為第一筆儲存資料W1「110」、第二筆儲存資料W2「101」、第三筆儲存資料W3「111」和第四筆儲存資料W4「000」,於此例示性說明中每一筆儲存資料W1~W4分別包含三個字元,分別由三個不同的記憶胞122加以儲存,但本揭示文件並不以單筆儲存資料包含三個字元為限,可依實際應用而決定每筆儲存資料的字元數目,例如每筆包含8個字元、16個字元或32個字元或其他正整數個字元數。
For example, as shown in FIG. 1, the
於第1圖所示的實施例中,假設搜尋資料DIN包含三個字元值「101」,由於儲存第一筆儲存資料W1「110」的記憶胞中只有第一個字元值相符,因此,偵測電路160接收到的讀取電流值OUT[1]為一單位大小。由於儲存第二筆儲存資料W2「101」的記憶胞中第一、第二和第三個字元值皆相符,因此,偵測電路160接收到的讀取電流值OUT[2]為三單位大小。由於儲存第三筆儲存資料W3「111」的記憶胞中第一和第三字元值相符,因此,偵測電路160接收到的讀取電流值OUT[3]為二單位大小。由於儲存第四筆儲存資料W4「000」的記憶胞中第二個字元值相符,因此,偵測電路160接收到的讀取電流值OUT[4]為一單位大小。如此一來,藉由偵測電路160接收的讀取電流值OUT[1]~OUT[4]並以其中的最大者(如:讀取電流值OUT[2])作為搜尋結果RS,便能找到符合
搜尋資料DIN「101」的記憶胞(即,儲存有第二筆儲存資料W2的三個記憶胞)所在的位址。
In the embodiment shown in FIG. 1, it is assumed that the search data DIN includes three character values "101". Since only the first character value in the memory cell storing the first stored data W1 "110" matches, so The read current value OUT[1] received by the
其中,於內容可定址記憶體100的一些實施例中,記憶胞122所儲存的字元值允許儲存資料狀態「X」,其代表為「隨意(don’t care)」。當記憶胞122字元值設定為「X」時,不論搜尋字元值為「1」或「0」,對應的此記憶胞122的比對結果皆為相符。
In some embodiments of the content
舉例來說,假設記憶胞陣列120中某一筆儲存資料為「10X」,則不論搜尋資料DIN為「101」或「100」時,儲存「10X」的多個記憶胞的資料狀態皆為相符,因此,不論搜尋資料DIN為「101」或「100」時,偵測電路160接收到相應的讀取電流值都為三單位大小。
For example, assuming that a certain stored data in the
請參考第2圖。第2圖係根據本揭示內容之部分實施例繪示一種內容可定址記憶體100的電路示意圖。如第2圖所示,內容可定址記憶體100包含記憶胞陣列120、控制電路140、搜尋線和匹配線。記憶胞陣列120包含以陣列方式排列的複數個記憶胞122。控制電路140包含複數個多工電路142。記憶胞陣列120中每一列所包含的記憶胞122的個數與匹配線的數量相同,也就是與內容可定址記憶體100的總儲存資料筆數有關。記憶胞陣列120中每一行所包含的記憶胞122的個數與搜尋線的對數相同,也就是與每筆儲存資料所包含的位元數目有關。例如,內容可定址記憶體100若包含1024筆儲存資料,則每一列的記憶胞122可為1024個。若每筆儲存資料包含8個位元數,則每一行的記憶胞122可為8個。
Please refer to Figure 2. FIG. 2 is a schematic circuit diagram of a content
在本實施例中,為了方便說明起見,將以內容可定址記憶體100包含4筆儲存資料,且每筆儲存資料包含3個位元數為例進行說明,但本案不以此為限。換句話說,在本案說明書和圖式中,將以內容可定址記憶體100包含三對搜尋線SLn[1]~SLn[3]和SL[1]~SL[3]和四條匹配線ML[1]~ML[4],控制電路140包含三個多工電路U[1]~U[3],記憶胞陣列120包含十二個記憶胞C[1,1]~C[3,4]為例進行說明,但本案不以此為限。
In this embodiment, for convenience of description, the content
如第2圖所示,結構上,多工電路U[1]透過第一對搜尋線SLn[1]和SL[1]耦接記憶胞C[1,1]~C[1,4]。多工電路U[2]透過第二對搜尋線SLn[2]和SL[2]耦接記憶胞C[2,1]~C[2,4]。多工電路U[3]透過第三對搜尋線SLn[3]和SL[3]耦接記憶胞C[3,1]~C[3,4]。匹配線ML[1]耦接記憶胞C[1,1]~C[3,1]的輸出端。匹配線ML[2]耦接記憶胞C[1,2]~C[3,2]的輸出端。匹配線ML[3]耦接記憶胞C[1,3]~C[3,3]的輸出端。匹配線ML[4]耦接記憶胞C[1,4]~C[3,4]的輸出端。 As shown in FIG. 2, in structure, the multiplex circuit U[1] is coupled to the memory cells C[1,1]~C[1,4] through the first pair of search lines SLn[1] and SL[1]. The multiplex circuit U[2] is coupled to the memory cells C[2,1]~C[2,4] through the second pair of search lines SLn[2] and SL[2]. The multiplex circuit U[3] is coupled to the memory cells C[3,1]~C[3,4] through the third pair of search lines SLn[3] and SL[3]. Matching line ML[1] is coupled to the output of memory cells C[1,1]~C[3,1]. Matching line ML[2] is coupled to the output of memory cells C[1,2]~C[3,2]. The matching line ML[3] is coupled to the output of memory cells C[1,3]~C[3,3]. Matching line ML[4] is coupled to the output of memory cells C[1,4]~C[3,4].
操作上,以搜尋資料DIN包含三個搜尋字元值DIN[1]~DIN[3]為例。多工電路U[1]用以根據搜尋資料DIN中的搜尋字元值DIN[1]選擇性地導通第一對搜尋線中的搜尋線SLn[1]或搜尋線SL[1],以將搜尋字元值DIN[1]和記憶胞C[1,1]~C[1,4]所儲存的資料狀態進行比對。相似地,多工電路U[2]用以根據搜尋資料DIN中的搜尋字元值DIN[2]選擇性地導通第二對搜尋線中的搜尋線SLn[2]或搜尋線SL[2],以將搜尋字元值DIN[2]和記憶胞C[2,1]~C[2,4]所儲存的資料狀 態進行比對。多工電路U[3]用以根據搜尋資料DIN中的搜尋字元值DIN[3]選擇性地導通第三對搜尋線中的搜尋線SLn[3]或搜尋線SL[3],以將搜尋字元值DIN[3]和記憶胞C[3,1]~C[3,4]所儲存的資料狀態進行比對。 In operation, the search data DIN contains three search character values DIN[1]~DIN[3] as an example. The multiplexing circuit U[1] is used to selectively turn on the search line SLn[1] or the search line SL[1] in the first pair of search lines according to the search character value DIN[1] in the search data DIN, so that The search character value DIN[1] is compared with the state of the data stored in memory cells C[1,1]~C[1,4]. Similarly, the multiplexing circuit U[2] is used to selectively turn on the search line SLn[2] or the search line SL[2] in the second pair of search lines according to the search character value DIN[2] in the search data DIN , To search the data value stored in the character value DIN[2] and memory cells C[2,1]~C[2,4] To compare. The multiplexing circuit U[3] is used to selectively turn on the search line SLn[3] or the search line SL[3] in the third pair of search lines according to the search character value DIN[3] in the search data DIN, so that The search character value DIN[3] is compared with the state of the data stored in memory cells C[3,1]~C[3,4].
換言之,耦接於同一對搜尋線的記憶胞共用多工電路中的同一者。例如,耦接於搜尋線SLn[1]和SL[1]的記憶胞C[1,1]~C[1,4]共用多工電路U[1]。耦接於搜尋線SLn[2]和SL[2]的記憶胞C[2,1]~C[2,4]共用多工電路U[2]。耦接於搜尋線SLn[3]和SL[3]的記憶胞C[3,1]~C[3,4]共用多工電路U[3]。也就是說,記憶胞C[1,1]~C[1,4]中任一者所儲存的資料狀態與搜尋字元值DIN[1]進行比對,記憶胞C[2,1]~C[2,4]中任一者所儲存的資料狀態與搜尋字元值DIN[2]進行比對,記憶胞C[3,1]~C[3,4]中任一者所儲存的資料狀態與搜尋字元值DIN[3]進行比對。 In other words, the memory cells coupled to the same pair of search lines share the same one in the multiplex circuit. For example, memory cells C[1,1]~C[1,4] coupled to the search lines SLn[1] and SL[1] share the multiplex circuit U[1]. The memory cells C[2,1]~C[2,4] coupled to the search lines SLn[2] and SL[2] share the multiplex circuit U[2]. The memory cells C[3,1]~C[3,4] coupled to the search lines SLn[3] and SL[3] share the multiplex circuit U[3]. In other words, the state of the data stored in any one of memory cells C[1,1]~C[1,4] is compared with the search character value DIN[1], memory cell C[2,1]~ The state of the data stored in any one of C[2,4] is compared with the search character value DIN[2], and the memory stored in any one of C[3,1]~C[3,4] The data status is compared with the search character value DIN[3].
具體而言,關於記憶胞的詳細電路請參考第3A圖。第3A圖係根據本揭示內容之部分實施例繪示一種多工電路142和記憶胞122的電路示意圖。如第3A圖所示,記憶胞122包含二個整流元件122a和122b、二個電阻元件Ra和Rb、以及輸出端N1。值得說明的是,第2圖的記憶胞陣列120中的任一個記憶胞122皆可由第3A圖中的記憶胞122據以實施。為了便於說明起見,第3A圖中所繪示的記憶胞122所耦接的搜尋線SLn[k]、SL[k]和匹配線ML[j]沒有指明數字索引係代表記憶胞陣列120中不特定的記憶胞122所相應耦接的搜尋線和匹配線。
Specifically, please refer to Figure 3A for the detailed circuit of the memory cell. FIG. 3A is a schematic circuit diagram of a
如第3A圖所示,結構上,多工電路142透過一對搜尋線SLn[k]和SL[k]耦接記憶胞122。記憶胞122的輸出端N1耦接匹配線ML[j]。具體而言,耦接於同一對搜尋線之記憶胞122的電阻元件Ra和整流元件122a串聯於搜尋線SLn[k]和記憶胞122的輸出端N1之間。耦接於同一對搜尋線之記憶胞122的電阻元件Rb和整流元件122b串聯於搜尋線SL[k]和記憶胞的輸出端N1之間。換言之,同一個記憶胞122的電阻元件Ra和整流元件122a串聯於同一對搜尋線的搜尋線SLn[k]和此記憶胞122的輸出端N1之間。同一個記憶胞122的電阻元件Rb和整流元件122b串聯於同一對搜尋線的搜尋線SL[k]和此記憶胞的輸出端N1之間。
As shown in FIG. 3A, in structure, the
舉例來說,在部分實施例中,如第3A圖所示,電阻元件Ra的第一端耦接搜尋線SLn[k],電阻元件Ra的第二端耦接整流元件122a的第一端,整流元件122a的第二端耦接輸出端N1。電阻元件Rb的第一端耦接搜尋線SL[k],電阻元件Rb的第二端耦接整流元件122b的第一端,整流元件122b的第二端耦接輸出端N1。
For example, in some embodiments, as shown in FIG. 3A, the first end of the resistive element Ra is coupled to the search line SLn[k], and the second end of the resistive element Ra is coupled to the first end of the
在其他部分實施例中,如第3B圖所示,整流元件122a的第一端耦接搜尋線SLn[k],整流元件122a的第二端耦接電阻元件Ra的第一端,電阻元件Ra的第二端耦接輸出端N1。整流元件122b的第一端耦接搜尋線SL[k],整流元件122b的第二端耦接電阻元件Rb的第一端,電阻元件Rb的第二端耦接輸出端N1。
In some other embodiments, as shown in FIG. 3B, the first end of the
值得注意的是,在其他部分實施例中,搜尋線SLn[k]和輸出端N1之間可如第3A圖所示,而搜尋線SL[k]和輸出端N1之間可如第3B圖所示。或者,搜尋線SLn[k]和輸出端N1之間可如第3B圖所示,而搜尋線SL[k]和輸出端N1之間可如第3A圖所示。 It is worth noting that in some other embodiments, the search line SLn[k] and the output terminal N1 may be as shown in FIG. 3A, and the search line SL[k] and the output terminal N1 may be as shown in FIG. 3B. As shown. Alternatively, the search line SLn[k] and the output terminal N1 may be as shown in FIG. 3B, and the search line SL[k] and the output terminal N1 may be as shown in FIG. 3A.
此外,在本案中,整流元件122a和122b可由如第4圖所示之二極體元件Dia和Dib來實作。舉例來說,二極體元件Dia和Dib可為p-n接面二極體(p-n junction)、蕭特基二極體(schottky diode)、雙向定限開關(ovonic threshold switch)或莫特絕緣體(Mott insulator)等等。
In addition, in this case, the rectifying
操作上,記憶胞122中的電阻元件Ra和Rb經配置用以儲存代表資料狀態的第一位元值和第二位元值。具體而言,電阻元件Ra的電阻值代表第一位元值。電阻元件Rb的電阻值代表第二位元值。在本揭示文件中,低電阻值代表邏輯值「1」,高電阻值代表邏輯值「0」。
In operation, the resistive elements Ra and Rb in the
在部分實施例中,記憶胞122可以儲存兩種資料狀態中之一者。兩種資料狀態包含資料狀態「0」和資料狀態「1」。代表不同資料狀態「0」或「1」的記憶胞122的電阻元件Ra和Rb分別的電阻值高低如表一所示。
In some embodiments, the
當記憶胞122儲存的資料狀態為「0」,電阻元件Ra的電阻值設定為低,其代表的第一位元值具有邏輯值「1」,電阻元件Rb的電阻值設定為高,其代表的第二位元值具有邏輯值「0」。
When the state of the data stored in the
當記憶胞122的資料狀態為「1」,電阻元件Ra的電阻值設定為高,其代表的第一位元值具有邏輯值「0」,電阻元件Rb的電阻值設定為低,其代表的第二位元值具有邏輯值「1」。
When the data state of the
此外,在其他部分實施例中,記憶胞122可以儲存三種資料狀態中之一者。三種資料狀態包含資料狀態「0」、資料狀態「1」和資料狀態「X」。代表不同資料狀態「0」、「1」或「X」的記憶胞122的電阻元件Ra和Rb分別的電阻值高低如表二所示。
In addition, in some other embodiments, the
當記憶胞122儲存的資料狀態為「0」,電阻元件Ra的電阻值設定為低,其代表的第一位元值具有邏輯值「1」,電阻元件Rb的電阻值設定為高,其代表的第二位元值具有邏輯值「0」。
When the state of the data stored in the
當記憶胞122的資料狀態為「1」,電阻元件Ra的電阻值設定為高,其代表的第一位元值具有邏輯值「0」,電阻元件Rb的電阻值設定為低,其代表的第二位元值具有邏輯值「1」。
When the data state of the
當記憶胞122的資料狀態為「X」,電阻元件Ra的電阻值設定為低,其代表的第一位元值具有邏輯值「1」,電阻元件Rb的電阻值設定為低,其代表的第二位元值具有邏輯值「1」。
When the data state of the
請參考第5A圖。第5A圖係根據本揭示內容之部分實施例繪示一種多工電路142和記憶胞122的操作示意圖。多工電路142用以根據搜尋字元值DIN[k]選擇性地導通相耦接的一對搜尋線中的第一搜尋線SLn[k]或第二搜尋線SL[k],以將搜尋字元值DIN[k]和記憶胞122所儲存的資料狀態進行比對。
Please refer to Figure 5A. FIG. 5A is a schematic diagram illustrating the operation of a
具體而言,在部分實施例中,如第5A圖所示,當搜尋字元值DIN[k]為「1」時,多工電路142根據為「1」的搜尋字元值DIN[k]將偏壓BIA[k]經由對應於「1」的搜尋線SL[k]施加至記憶胞122,而對應於「0」的搜尋線SLn[k]為空接(floating)狀態。當搜尋字元值DIN[k]為「0」時(圖中未示),多工電路142根據為「0」的搜尋字元值DIN[k]將偏壓BIA[k]經由對應於「0」的搜尋線SLn[k]施加至記憶胞122,而對應於「1」的搜尋線SL[k]為空接狀態。如此一來,接收到偏壓BIA[k]的記憶胞122便會根據相應的電阻元件Ra或Rb輸出相應的輸出電流Io至匹配線ML[j]。
Specifically, in some embodiments, as shown in FIG. 5A, when the search character value DIN[k] is "1", the
在其他部分實施例中,如第5B圖所示,當搜尋字元值DIN[k]為「1」時,多工電路142用以將正偏壓BIA[k]經由搜尋線SL[k]施加至記憶胞122,並用以將非正偏壓INH[k]施加在對應於「0」的搜尋線SLn[k]。當搜尋字元值DIN[k]為「0」時(圖中未示),多工電路142用以將正偏壓BIA[k]經由搜尋線SLn[k]施加至記憶胞122,並用以將非正偏壓INH[k]施加在對應於「1」的搜尋線SL[k]。其中,非正偏壓INH[k]可為負偏壓或者近似於零的電壓。如此一來,藉由非正偏壓INH[k]便能使得記憶胞122中非對應的電阻元件和整流元件不會輸出額外的電流至匹配線ML[j],而造成輸出電流Io不準確。
In other partial embodiments, as shown in FIG. 5B, when the search character value DIN[k] is "1", the
關於記憶胞如何根據相應的電阻元件Ra或Rb輸出相應的輸出電流Io,請一併參考第5A圖和表三。 Regarding how the memory cell outputs the corresponding output current Io according to the corresponding resistance element Ra or Rb, please refer to FIG. 5A and Table 3 together.
如表三所示,於部分實施例中,由於記憶胞122具有兩個電阻元件Ra或Rb,當兩個電阻元件Ra或Rb均被設置於高電阻值時,其儲存的資料狀態為禁能(disabled)。當記憶胞122儲存資料狀態為禁能時,不論搜尋字元值為何,均會輸出低電流,視為比對不相符。
As shown in Table 3, in some embodiments, since the
如第5A圖所示,當搜尋字元值DIN[k]為「1」時,記憶胞122中的電阻元件Rb將接收到偏壓BIA[k],且整流元件122a將使得偏壓BIA[k]不會流過電阻元件Ra。由於偏壓BIA[k]經過的電阻值越大則輸出電流Io越小,而偏壓BIA[k]經過的電阻值越小則輸出電流Io越大。因此,當記憶胞122中的資料狀態為「0」時,電阻元件Rb為高電阻,輸出電流Io為低電流,而當記憶胞122中的資料狀態為「1」時,電阻元件Rb為低電阻,輸出電流Io為高電流。換言之,如表三所示,當搜尋字元值為「1」時,輸出電流Io的高低與電阻元件Rb的電阻值高低相反。因此,根據輸出電流Io為高電流者便能判斷此記憶胞122中的資料狀態與搜尋字元值相符。另一方面,當輸出電流Io為低電流時,便能判斷此記憶胞122中的資料狀態與搜尋字元值不符。
As shown in FIG. 5A, when the search character value DIN[k] is "1", the resistive element Rb in the
相似地,如第5A圖所示,當搜尋字元值DIN[k]為「0」時,記憶胞122中的電阻元件Ra將接收到偏壓BIA[k],且整流元件122b將使得偏壓BIA[k]不會流過電阻元件Rb。因此,當記憶胞122中的資料狀態為「0」時,電阻元件Ra為低電阻,輸出電流Io為高電流,而當記憶胞122中的資料狀態為「1」時,電阻元件Ra為高電阻,輸出電流Io為低電流。換言
之,如表三所示,當搜尋字元值為「0」時,輸出電流Io的高低與電阻元件Ra的電阻值高低相反。因此,根據輸出電流Io為高電流者便能判斷此記憶胞122中的資料狀態與搜尋字元值相符。另一方面,當輸出電流Io為低電流時,便能判斷此記憶胞122中的資料狀態與搜尋字元值不符。
Similarly, as shown in FIG. 5A, when the search character value DIN[k] is "0", the resistive element Ra in the
由此可知,當記憶胞自身所儲存的資料狀態與相應的搜尋字元值相符時,此記憶胞將輸出高電流。反之,當記憶胞自身所儲存的資料狀態與相應的搜尋字元值不相符時,此記憶胞將輸出低電流。 It can be seen that when the state of the data stored in the memory cell itself matches the corresponding search character value, the memory cell will output a high current. Conversely, when the state of the data stored in the memory cell itself does not match the corresponding search character value, the memory cell will output a low current.
如此一來,藉由記憶胞122中的電阻元件Ra和Rb分別儲存相應第一位元值和第二位元值以代表不同資料狀態,並透過多工電路142根據搜尋字元值為「1」將偏壓BIA[k]經由搜尋線SL[k]施加至記憶胞122中的電阻元件Rb,或根據搜尋字元值為「0」將偏壓BIA[k]經由搜尋線SLn[k]施加至記憶胞122中的電阻元件Ra,便能根據相應的輸出電流Io得知記憶胞122的資料狀態是否與搜尋字元值相符。此外,藉由整流元件122a和122b,便能確保不會有漏電流從非施加偏壓側的電阻元件流出。
In this way, the resistance elements Ra and Rb in the
請回頭參考第2圖。如第2圖所示,當搜尋字元值DIN[1]為「1」時,多工電路U[1]導通搜尋線SL[1]以將偏壓BIA[1]經由搜尋線SL[1]施加至記憶胞C[1,1]~C[1,4],以分別比對記憶胞C[1,1]~C[1,4]各自的第二位元值和搜尋字元值DIN[1]是否相符。反之,當搜尋字元值DIN[1]為「0」時,多工電路U[1]導通搜尋線SLn[1]以將偏壓BIA[1]經由搜尋線 SLn[1]施加至記憶胞C[1,1]~C[1,4],以分別比對記憶胞C[1,1]~C[1,4]各自的第一位元值和搜尋字元值DIN[1]是否相符。 Please refer back to Figure 2. As shown in Figure 2, when the search character value DIN[1] is "1", the multiplex circuit U[1] turns on the search line SL[1] to bias the bias BIA[1] through the search line SL[1 ] Is applied to memory cells C[1,1]~C[1,4] to compare the second bit value and search character value of memory cells C[1,1]~C[1,4] respectively Whether DIN[1] matches. Conversely, when the search character value DIN[1] is "0", the multiplex circuit U[1] turns on the search line SLn[1] to bias the BIA[1] through the search line SLn[1] is applied to memory cells C[1,1]~C[1,4] to compare the first bit value and search of memory cells C[1,1]~C[1,4] Whether the character value DIN[1] matches.
舉例來說,假設搜尋字元值DIN[1]~DIN[3]為「1」、「0」、「1」,而記憶胞C[1,1]~C[3,1]分別儲存的資料狀態為「1」、「1」、「0」。根據表三,記憶胞C[1,1]~C[3,1]的輸出電流分別為「高」、「低」、「低」,因此,匹配線ML[1]所接收到來自記憶胞C[1,1]~C[3,1]的電流總和的讀取電流值OUT[1]為一單位大小。 For example, suppose the search character values DIN[1]~DIN[3] are "1", "0", "1", and memory cells C[1,1]~C[3,1] are stored separately. The data status is "1", "1", "0". According to Table 3, the output currents of memory cells C[1,1]~C[3,1] are "high", "low", and "low", respectively. Therefore, the matching line ML[1] received from the memory cells The reading current value OUT[1] of the total current of C[1,1]~C[3,1] is a unit size.
依此類推,假設記憶胞C[1,2]~C[3,2]、C[1,3]~C[3,3]、C[1,4]~C[3,4]分別儲存的資料狀態為「1」、「0」、「1」和「1」、「1」、「1」和「0」、「0」、「0」,則記憶胞C[1,2]~C[3,2]、C[1,3]~C[3,3]、C[1,4]~C[3,4]的輸出電流分別為「高」、「高」、「高」和「高」、「低」、「高」和「低」、「高」、「低」。因此,匹配線ML[2]~ML[4]所接收到的讀取電流值OUT[2]~OUT[4]分別為三、二、一單位大小。 By analogy, suppose the memory cells C[1,2]~C[3,2], C[1,3]~C[3,3], C[1,4]~C[3,4] are stored separately The data status is "1", "0", "1" and "1", "1", "1" and "0", "0", "0", then memory cell C[1,2]~ The output currents of C[3,2], C[1,3]~C[3,3], C[1,4]~C[3,4] are "high", "high", and "high" respectively And "high", "low", "high" and "low", "high", "low". Therefore, the read current values OUT[2]~OUT[4] received by the matching lines ML[2]~ML[4] are respectively three, two, and one unit size.
如此一來,偵測電路160根據自匹配線ML[1]~ML[4]所接收到的讀取電流值OUT[1]~OUT[4]中最大者(即,三單位大小的讀取電流值OUT[2])作為搜尋結果RS輸出,便能找到符合搜尋資料DIN為「101」的記憶胞C[1,2]~C[3,2]。
As a result, the
請參考第6圖。第6圖係根據本揭示內容之部分實施例繪示一種內容可定址記憶體100a的立體示意圖。在部分實
施例中,第2圖中的內容可定址記憶體100可由第6圖中的內容可定址記憶體100a據以實施。在第6圖之實施例中,與第2圖之實施例相似的元件係以相同的元件符號表示。如第6圖所示,包含在第一區域A1中的搜尋線SL[1]~SL[3]可設置於基板或第一導電層上。包含在第二區域A2中傳輸搜尋字元值DIN[1]~DIN[3]的傳輸線、多工電路和匹配線ML[1]、ML[2]可設置於第二導電層上。包含在第三區域A3中的搜尋線SLn[1]~SLn[3]可設置於第三導電層上。在部分實施例中,導電層可為多晶矽材料、金屬材料或其他導電材料製成。而搜尋線、匹配線、傳輸線或其他連接線可由在導體層中鋪設圖案化的金屬導線據以實施。
Please refer to Figure 6. FIG. 6 is a perspective view of a content
請參考第7圖。第7圖係根據本揭示內容之其他部分實施例繪示另一種內容可定址記憶體100b的立體示意圖。在部分實施例中,第2圖中的內容可定址記憶體100可由第7圖中的內容可定址記憶體100b據以實施。在第7圖之實施例中,與第2圖之實施例相似的元件係以相同的元件符號表示。如第7圖所示,包含在第一區域A1中的傳輸搜尋字元值DIN[1]~DIN[3]的傳輸線、多工電路和搜尋線SL[1]~SL[3]可設置於基板或第一導電層上。包含在第二區域A2中匹配線ML[1]、ML[2]可設置於第二導電層上。包含在第三區域A3中的搜尋線SLn[1]~SLn[3]可設置於第三導電層上。
Please refer to Figure 7. FIG. 7 is a schematic perspective view of another content-
值得注意的是,上述第1圖~第7圖所描述的內容可定址記憶體100的電路結構及/或操作,在其他部分實施例中,亦可使用於其他型態的記憶體中,本揭示內容並不以此為
限。
It is worth noting that the content described in Figures 1 to 7 above can address the circuit structure and/or operation of the
雖然本文將所公開的方法示出和描述為一系列的步驟或事件,但是應當理解,所示出的這些步驟或事件的順序不應解釋為限制意義。例如,部分步驟可以以不同順序發生和/或與除了本文所示和/或所描述之步驟或事件以外的其他步驟或事件同時發生。另外,實施本文所描述的一個或多個態樣或實施例時,並非所有於此示出的步驟皆為必需。此外,本文中的一個或多個步驟亦可能在一個或多個分離的步驟和/或階段中執行。 Although the disclosed method is shown and described herein as a series of steps or events, it should be understood that the order of the steps or events shown should not be interpreted as limiting. For example, some steps may occur in a different order and/or simultaneously with other steps or events other than those shown and/or described herein. In addition, not all of the steps shown here are necessary to implement one or more aspects or embodiments described herein. In addition, one or more steps herein may also be performed in one or more separate steps and/or stages.
需要說明的是,在不衝突的情況下,在本揭示內容各個圖式、實施例及實施例中的特徵與電路可以相互組合。圖式中所繪示的電路僅為示例之用,係簡化以使說明簡潔並便於理解,並非用以限制本案。此外,上述各實施例中的各個裝置、單元及元件可以由各種類型的數位或類比電路實現,亦可分別由不同的積體電路晶片實現,或整合至單一晶片。上述僅為例示,本揭示內容並不以此為限。 It should be noted that, in the case of no conflict, the various drawings, embodiments, and features and circuits in the present disclosure may be combined with each other. The circuits shown in the drawings are for illustrative purposes only, and are simplified to make the description concise and easy to understand, and are not intended to limit the case. In addition, the various devices, units, and components in the foregoing embodiments may be implemented by various types of digital or analog circuits, or may be implemented by different integrated circuit chips, or integrated into a single chip. The above is only an example, and the disclosure is not limited thereto.
綜上所述,本案透過應用上述各個實施例中,藉由記憶胞122中的電阻元件Ra和Rb分別儲存相應第一位元值和第二位元值以代表不同資料狀態,並透過多工電路142根據搜尋字元值為「1」或「0」將偏壓BIA[k]施加至記憶胞122中的電阻元件Ra或Rb,便能根據相應的輸出電流Io得知記憶胞122的資料狀態是否與搜尋字元值相符。此外,藉由整流元件122a和122b,便能確保不會有漏電流從非施加偏壓側的電阻元件流出。
To sum up, in this case, through the application of the above embodiments, the resistance elements Ra and Rb in the
雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本揭示內容,所屬技術領域具有通常知識者在不脫離本揭示內容之精神和範圍內,當可作各種更動與潤飾,因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。 Although this disclosure has been disclosed as above by way of implementation, it is not intended to limit this disclosure. Those with ordinary knowledge in the technical field can make various changes and modifications within the spirit and scope of this disclosure, so this The scope of protection of the disclosure shall be deemed as defined by the scope of the attached patent application.
122‧‧‧記憶胞 122‧‧‧Memory Cell
142‧‧‧多工電路 142‧‧‧multiplex circuit
DIN[k]‧‧‧搜尋字元值 DIN[k]‧‧‧Search character value
BIA[k]‧‧‧偏壓 BIA[k]‧‧‧bias
SLn[k]、SL[k]‧‧‧搜尋線 SLn[k], SL[k]‧‧‧ search line
Ra、Rb‧‧‧電阻元件 Ra, Rb‧‧‧resistance element
122a、122b‧‧‧整流元件 122a, 122b‧‧‧Rectifier
N1‧‧‧輸出端 N1‧‧‧ output
ML[j]‧‧‧匹配線 ML[j]‧‧‧ Matching line
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US20150206586A1 (en) * | 2014-01-20 | 2015-07-23 | National Tsing Hua University | Non-volatile ternary content-addressable memory 4t2r cell with rc-delay search |
US20180204616A1 (en) * | 2017-01-13 | 2018-07-19 | Samsung Electronics Co., Ltd. | Memory device comprising resistance change material and method for driving the same |
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US20150206586A1 (en) * | 2014-01-20 | 2015-07-23 | National Tsing Hua University | Non-volatile ternary content-addressable memory 4t2r cell with rc-delay search |
US20180204616A1 (en) * | 2017-01-13 | 2018-07-19 | Samsung Electronics Co., Ltd. | Memory device comprising resistance change material and method for driving the same |
US20190108880A1 (en) * | 2017-01-13 | 2019-04-11 | Samsung Electronics Co., Ltd. | Memory device comprising resistance change material and method for driving the same |
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