CN114692076A - Memristor chip and operation method thereof - Google Patents
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Abstract
The embodiment of the application provides a memristor chip, which comprises a control circuit, a memristor array and a processing circuit; when matrix multiplication calculation is carried out, firstly, the control circuit sets memristors in 2F rows and N columns in the memristor array to different resistance states for representing a matrix in the F rows and the N columns, wherein two memristors in each column of the memristors in the 2F rows and the N columns represent one value in the matrix; and then converting N numerical values in the vectors of the N rows and the 1 column into corresponding N voltages, respectively applying the voltages corresponding to the numerical values of the 1 st row to the N th row in the vectors to the memristors of the 1 st column to the N th column, and processing the output of the 2F rows of the memristors by the processing circuit to obtain a multiplication result of the matrix of the F rows and the N columns and the vector of the N rows and the 1 column. By means of the memristor chip, matrix vector multiplication operation can be unloaded to the memristor array, internal calculation is achieved, calculation speed is improved, and energy consumption is reduced.
Description
Technical Field
The application relates to the field of integrated circuits, in particular to a memristor chip and an operation method thereof.
Background
The complexity of the current computing device when performing matrix multiplication computation through a device manufactured based on a Complementary Metal Oxide Semiconductor (CMOS) such as a Central Processing Unit (CPU) is high, data interaction between the CPU and a memory needs to be frequently performed, Input and Output (IO) resources of the memory are occupied, high delay is caused, the computing efficiency is low, and the requirement of a mass data computing scene cannot be met. Meanwhile, a large amount of calculation occupies the calculation power of the CPU, and affects the overall performance of the computing device.
Disclosure of Invention
The embodiment of the application discloses a memristor chip and an operation method thereof, which can realize matrix vector multiplication operation based on a memristor array, realize internal calculation, reduce the times of transporting data from a memory to a CPU, improve the calculation speed and reduce the energy consumption.
In a first aspect, embodiments of the present application provide a memristor chip including a control circuit, a memristor array, and a processing circuit, wherein,
a control circuit to: setting memristors in 2F rows and N columns in a memristor array to different resistance states, wherein the memristors in the 2F rows and the N columns are used for representing a matrix in the F rows and the N columns, and two memristors in each column represent one value in the matrix;
converting N values in the vector of the N rows and the 1 column into corresponding N voltages, and applying voltages corresponding to the numerical values of the 1 st row to the k th row in the vector to the memristors of the 1 st column to the k th column respectively, so that the multiplication device determines the multiplication result of the matrix of the F rows and the N columns and the vector of the N rows and the 1 column based on the current in the memristors of the 2F rows, wherein the N voltages are all smaller than the voltage for changing the resistance value of the memristors, and k is smaller than or equal to N;
and the processing circuit is used for processing the output of the 2F row memristor to obtain a multiplication result of a matrix of F rows and N columns and a vector of N rows and 1 column.
The memristors in the memristor array are set to be in different resistance states through the control circuit and used for representing different values in the matrix, then each value in the vector is converted into corresponding voltage, matrix vector multiplication is further completed, matrix vector multiplication calculation is unloaded to the memristor array, memory calculation is achieved, data carrying between the memory and a CPU can be reduced, complexity of the matrix vector multiplication is reduced, calculation speed is improved, and energy consumption is reduced.
In one possible implementation manner, the processing circuit is configured to detect output currents of every two rows of memristors in the memristor array, and use the output currents of every two rows of memristors as a result of multiplication of the matrix of the F rows and the N columns and the vector of the N rows and the 1 column.
The control circuit sets each memristor in the memristor array to be in a corresponding resistance state according to a numerical value in the matrix, then converts the value in the vector into corresponding voltage to be applied to the memristor array, so that different currents can be generated on a connecting line connecting each row of memristors, and the processing circuit processes the currents output by the memristor array, so that the result of multiplying the matrix and the vector can be obtained.
In a possible implementation manner, the processing circuit includes F subtractors and F comparators, each two rows of memristors in the memristor array are connected to one subtracter, an output end of each subtracter is connected to one comparator, outputs of the F comparators form a binary hash code, which is a result of dimension reduction of multiplication operation of the matrix of the F rows and the N columns and the vector of the N rows and the 1 column, wherein one row of each two rows of memristors is connected to a forward input end of the subtracter, and the other row of each two rows of memristors is connected to a reverse input end of the same subtracter.
When matrix multiplication is carried out through the memristor array, different currents can be generated on a connecting line of two rows of memristors connected with the same subtracter, the subtracter subtracts input currents of two input ends to obtain output voltage, and the comparator determines a matrix vector multiplication result according to the output voltage of each subtracter.
In a possible implementation manner, setting memristors in 2F rows and N columns in a memristor array to different resistance states specifically includes: the control circuit sequentially applies different voltages to the memristors in each row according to the resistance state of each memristor in the memristors in the N columns and the 2F rows determined by the processor, sets each memristor in the corresponding resistance state, when the control circuit applies the voltages to the memristors in the s-th row, firstly grounds the negative electrodes of the memristors in the s-th row, then applies the voltages to the positive electrodes of the memristors in the s-th row to enable the resistance value of each memristor in the s-th row to be in the first resistance state or the second resistance state, then disconnects the connection between the negative electrodes of the memristors in the s-th row and the ground, and applies the voltages to the memristors in the next row, wherein the resistance value of the first resistance state is smaller than that of the second resistance state, and the value of s is 1-2F.
The control circuit is used for respectively setting the memristors of each row when the resistance state of each memristor in the memristor array is set, disconnecting the memristors of other rows from the ground when the first row is set, preventing the resistance states of the memristors of other rows from being changed, disconnecting the memristors of the row from the ground after the resistance state of the memristors of the first row is set, and preventing the resistance state of the memristors of the first row from being changed when voltage is applied to other rows.
In one possible implementation, the control circuit is specifically configured to: in the matrix of the ith1Line j (th)1When the column value is 1, the ith in the memristor array is compared1Line j (th)1Setting the memristors of the columns to be in the first resistance state, and setting the ith resistance state in the memristor array1Row +1, j1The memristors of the +1 column are set to the second resistance state; in the matrix of the ith2Line j (th)2When the column value is-1, the ith in the memristor array is compared2Line j (th)2Setting the memristors of the columns to be in the second resistance state, and setting the ith resistance state in the memristor array2Row +1, j2The memristors of the +1 column are set to the first resistance state.
Each memristor has multiple resistance states, two memristors which are connected to the same subtracter in the memristor array and located on the same row represent one value, the two memristors are set to different resistance states, the two memristors are enabled to have different configuration combinations to represent different values, and the memristor array can be used for representing matrixes formed by different values.
In one possible implementation, the control circuit is specifically configured to: at the i-th3Line j (th)3When the resistance state of the memristor of the column is in the first resistance state, the column moves to the ith3Line j (th)3Memristors of a column apply a forward voltage; or, in the i-th4Line j (th)4When the resistance state of the memristor of the column is the second resistance state, the ith resistance state is changed4Line j (th)4The memristors of the column apply a reverse voltage.
In a possible implementation manner, each subtracter is used for subtracting an input current of a positive input end and an input current of a negative input end to obtain an output voltage; each comparator is used for comparing the output voltage of the corresponding subtracter with 0 volt voltage and outputting high level when the output voltage is greater than the 0 volt voltage; or when the voltage is less than or equal to the 0 volt, outputting a low level.
In a second aspect, an embodiment of the present application provides a logic operation method, applied to the memristor chip described in the first aspect, where the method includes:
the control circuit sets memristors in 2F rows and N columns in the memristor array to different resistance states, wherein the memristors in the 2F rows and the N columns are used for representing a matrix in the F rows and the N columns, and two memristors in each column represent one value in the matrix;
converting N values in vectors of N rows and 1 columns into corresponding N voltages, and applying voltages corresponding to the 1 st row numerical values to the N rows of numerical values in the vectors to memristors of the 1 st column to the N columns respectively, wherein the N voltage values are all smaller than the voltage for changing the resistance of the memristors;
the processing circuit processes the output of the memristor passing through the 2F rows to obtain the multiplication result of the matrix of the F rows and the N columns and the vector of the N rows and the 1 column.
In one possible implementation, the processing circuit processes an output through the 2F row memristor, and includes: the processing circuit detects the output current of every two rows of memristors, and takes the output current of every two rows of memristors as a result of multiplication of the matrix of the F rows and the N rows and the vector of the N rows and the 1 row.
In one possible implementation, the processing circuit includes F subtractors and F comparators, one subtracter is connected to every two rows of memristors in the memristor array, each subtracter is connected to one comparator, and outputs of the F comparators form a binary hash code.
In a possible implementation manner, the processing circuit includes F subtractors and F comparators, each two rows of memristors in the memristor array are connected to one subtracter, one row of each two rows of memristors is connected to a forward input end of the subtracter, the other row of each two rows of memristors is connected to a reverse input end of the same subtracter, an output end of each subtracter is connected to one comparator, and outputs of the F comparators form a binary hash code, which is a result of dimension reduction of multiplication operation of the matrix of the F rows and the N columns and the vector of the N rows and the 1 column.
In a possible implementation manner, the control circuit sets memristors in N rows and N columns of a 2F memristor array to different resistance states, the control circuit sequentially applies different voltages to the memristors in each row according to the resistance state of each memristor in the memristors in the N columns and the 2F rows determined by the processor, sets each memristor in the corresponding resistance state, when the control circuit applies the voltage to the memristor in the s row, firstly, the negative electrode of the memristor in the s row is grounded, then, the voltage is applied to the positive electrode of each memristor in the s row, the resistance value of each memristor in the s row is made to be in the first resistance state or the second resistance state, then, the connection between the negative electrode of the memristor in the s row and the ground is disconnected, and the voltage is applied to the memristor in the next row, wherein the resistance value of the first resistance state is smaller than that of the second resistance state, and the value of s is 1 to 2F.
In one possible implementation, the ith in the matrix1Line j (th)1When the column value is 1, the control circuit stores the ith in the memristor array1Line j (th)1The memristors of the columns are set to be in a first resistance state, and the ith resistance state in the memristor array is set1Row +1, j1The memristors of the +1 column are set to a second resistance state; in the matrix of the ith2Line j (th)2When the column value is-1, the ith in the memristor array is memorized2Line j (th)2The memristors of the columns are set to be in a second resistance state, and the ith resistance state in the memristor array is set2Row +1, j2The memristors of the +1 column are set to the first resistance state.
In one possible implementation, the control circuit is in the ith3Line j (th)3When the resistance state of the memristor of the column is in the first resistance state, the resistance state is towards the ith3Line j (th)3Memristors of a column apply a forward voltage; or, in the i-th4Line j (th)4When the resistance state of the memristor of the column is the second resistance state, the ith resistance state is changed4Line j (th)4The memristors of the column apply a reverse voltage.
In a third aspect, embodiments of the present application further provide a computing device including the memristor chip described in the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a similar hashing algorithm;
FIG. 2 is a schematic diagram of a memristor chip provided by an embodiment of the present application;
FIG. 3 is a schematic diagram of another memristor chip provided by an embodiment of the present application;
FIG. 4 is a schematic diagram of another memristor chip provided by an embodiment of the present application;
fig. 5 is a schematic flow chart of implementing matrix vector multiplication based on a memristor chip according to an embodiment of the present application.
Detailed Description
To help those skilled in the art to better understand the technical solutions of the present application, some concepts related to the embodiments of the present application will be first described.
A memristor, called a memory resistor (memristor), is a resistor with a function of memorizing a resistance value. The memristor is a bipolar device and comprises a positive pole and a negative pole, and the resistance value of the memristor changes along with the change of the voltage applied to the positive pole and the negative pole of the memristor. When positive voltage is applied to the anode and the cathode of the memristor, if the value of the positive voltage is smaller than the value of the starting voltage corresponding to the memristor, the resistance value of the memristor is kept unchanged; if the value of the forward voltage applied to the memristor is larger than the value of the starting voltage and smaller than the value of the first critical voltage, the larger the applied forward voltage is, the smaller the resistance value of the memristor is; if the value of the forward voltage applied to the memristor is larger than or equal to the value of the first critical voltage, the resistance value of the memristor will not change after being reduced to the minimum value. When negative voltage is applied to the positive electrode and the negative electrode of the memristor, if the value of the negative voltage is smaller than that of the starting voltage, the resistance value of the memristor is kept unchanged; if the negative voltage applied to the memristor is larger than the starting voltage and smaller than the second threshold voltage, the resistance value of the memristor is larger when the applied negative voltage is larger, and when the applied negative voltage is larger than or equal to the second threshold voltage, the resistance value of the memristor does not change after being increased to the maximum value. When the voltage applied to the anode and the cathode of the memristor is removed, the memristor keeps the resistance value when the voltage is removed, so that the function of memorizing the resistance value is achieved. The positive voltage and the negative voltage are voltage differences between a voltage applied to the positive pole of the memristor and a voltage applied to the negative pole of the memristor, and when the voltage differences are positive, the positive voltage is applied between the positive pole and the negative pole of the memristor, and when the voltage differences are negative, the negative voltage is applied between the positive pole and the negative pole of the memristor. The first threshold voltage and the second threshold voltage may have the same or different values.
The Local Sensitive Hashing (LSH) algorithm is commonly used for dimensionality reduction of high-dimensional data, and further accelerates the speed and accuracy of searching.
Random hyperplane hashing is one of LSH algorithms, taking a text as an example, when a data fingerprint is generated through random hyperplane hashing coding, firstly, each word in the text is coded into a vector with the length of F, and N words in the text correspond to an F-N matrix, namely a feature matrix corresponding to the text; then recording the occurrence frequency of each word in the text, and forming a vector T by the occurrence frequency of each word, namely a weight vector corresponding to the text, wherein the weight vector T is a vector of N x 1 because of N words; multiplying the feature matrix by the weight vector T to obtain a vector S of F x 1; and finally, converting the negative number in the S into-1, and converting the non-negative number into 1 to obtain the data fingerprint corresponding to the text after dimension reduction.
The simhash algorithm is one of random hyperplane hashes, and plays an important role in webpage deduplication and text deduplication. The main idea of the simhash algorithm is to reduce dimensions, taking a text as an example, by mapping a feature vector of a high dimension corresponding to the text into a feature vector of a low dimension, and then determining the similarity of the text by calculating a hamming distance (hamming distance) between two texts. As shown in fig. 1, fig. 1 is a schematic flow chart of a similar hash algorithm, and the simhash algorithm is divided into five steps: the method comprises the following steps of word segmentation, Hash (hash) calculation, weighting, merging and dimension reduction, and specifically comprises the following steps:
a. word segmentation
The main purpose of word segmentation is to segment a given sentence or text, encode each word to obtain a feature vector corresponding to each word, and set a weight (weight) for each feature vector. For example, taking 5 words obtained by segmenting a text, the weights include five levels from 1 to 5, feature vectors of the five words are w1, w2, w3, w4 and w5, and the assigned weights are 4, 3, 1, 2 and 0.
b. Computing hashes
And calculating a hash value of each feature vector through a hash function, wherein the hash value is an n-bit signature consisting of 1 and-1. For example, as shown in fig. 1, if n is equal to 3, hash values obtained by computing the feature vectors corresponding to the above five words through a hash function are: h (w1) ═ 1, -1, 1], h (w2) [ -1,1, 1], h (w3) [ -1, -1, -1], h (w4) [ -1, -1, 1], and h (w5) [ -1,1, -1 ].
c. Weighting
After the hash value of each feature vector is calculated, a weight result W corresponding to each word is calculated based on the feature vector of each word and the weight of each word in step a, where W (W1) [ -1, -1, 1] × 4 ═ 4, -4, 4], W (W2) [ -1,1, 1] ═ 3 [ -3, 3], W (W3) [ -1, -1, -1] × 1 ═ 1, -1, -1], W (W4) [ -1, -1, 1] × 2 [ -2, -2, 2], W (W5) [ -1,1, -1] × 0 ═ 0, 0.
d. Merging
And accumulating the weighted results of the feature vectors to obtain the n-bit signature corresponding to the text. Taking the above five words as an example, the signature of 3 bits corresponding to the above five words is obtained by adding up [4-3+1-2+0, -4+3-1-2+0, 4+3-1+2+0] ═ 0, -4, 8.
e. Reducing vitamin
And d, for each digit value in the n-bit signature obtained in the step d, if the digit value is greater than 0, setting the value of the digit to 1, and if the digit value is less than or equal to 0, setting the value of the digit to 0, thereby obtaining the simhash value corresponding to the text. The simhash value obtained after dimensionality reduction of [0, -4, 8] is [0, 0, 1 ].
It should be noted that the essence of the above-mentioned weighting and merging calculation is a process of matrix-multiplying the feature matrix composed of the feature vector of each word by the weight vector composed of the weight corresponding to each word. For example, the corresponding weighting and merging operations of the five words in the above example may be implemented by matrix multiplication as follows:
the complexity of matrix multiplication calculation performed by a Central Processing Unit (CPU) or other devices manufactured based on a Complementary Metal Oxide Semiconductor (CMOS) is high in the current computing device, data interaction needs to be frequently performed between the CPU and a memory, Input and Output (IO) resources of the memory are occupied, high delay and energy consumption are brought, efficiency is low, and the requirement of a mass data calculation scene cannot be met. Meanwhile, a large amount of calculation occupies the calculation power of the CPU, and affects the overall performance of the computing device.
In order to solve the above problem, an embodiment of the present application provides a memristor-based chip for implementing a matrix vector multiplication operation. The memristor chip comprises a control circuit, a memristor array with 2m rows and N columns and a processing circuit, wherein when multiplication between a matrix with F rows and N columns and a vector with N rows and 1 columns needs to be calculated, the control circuit sets the memristors with 2F rows and N columns to be in different resistance states by applying different voltages to the memristors with 2F rows and N columns. The memristors in 2F rows and one column are used for identifying the numerical value of one column in the matrix of F rows and N columns, namely, two memristors in each column of memristors are used for representing one value in the matrix of F rows and N columns. The control circuit sets memristors in 2F rows and N columns in a memristor array to different configurations, and is used for representing a matrix of the F rows and the N columns, converting each numerical value in a vector of the N rows and the 1 column into a corresponding voltage to obtain N voltages, then applying voltages corresponding to numerical values in the 1 st row to the N th row in the vector to the memristors in the 1 st column to the N th column respectively, namely applying the voltage corresponding to the numerical value in the first row in the vector to the memristor in the first column, applying the voltage corresponding to the numerical value in the second row in the vector to the memristor in the second column, applying the voltage corresponding to the numerical value in the k row in the vector to the memristor in the k column, and so on. After voltages corresponding to the numerical values of the 1 st row to the Nth row in the vector are respectively applied to the memristors of the 1 st column to the Nth column, the processing circuit processes the output of the memristors of the 2F row to obtain an output result. And realizing multiplication operation between the matrix with F rows and N columns and the vector with N rows and 1 columns. The value of the N voltages obtained through conversion according to the N values in the vector is smaller than the starting voltage capable of changing the resistance value of the memristor, the ratio of the N voltages is the same as the ratio of the N values in the vector, N is smaller than or equal to N, and F is smaller than or equal to m.
The processing circuit comprises m subtracters and m comparators, wherein each two rows of memristors in the memristor array are connected with one subtracter, one row of each two rows of memristors is connected with the positive input end of the subtracter, the other row of each two rows of memristors is connected with the negative input end of the same subtracter, and the output end of each subtracter is connected with one comparator. The processing circuit detects the output current of every two rows of memristors in the memristor array, processes the output current of every two rows of memristors and uses the processed output current as a result of multiplication of the matrix of the F rows and the N rows and the vectors of the N rows and the 1 column. Specifically, the subtracter processes the current output by the two rows of memristors to obtain an output voltage, the comparator compares the voltage output by the subtracter with a voltage of 0v, and the outputs of the F comparators form a binary hash code, which is a result of dimension reduction of the multiplication operation of the matrix of the F rows and the N columns and the vector of the N rows and the 1 column.
Taking implementation of a simhash algorithm based on the memristor array as an example, the multiplication device and the operation method thereof provided by the embodiment of the application are introduced, and the weighting, merging, dimension reduction and other calculation processes in the simhash algorithm can be unloaded to the encoder comprising the memristor to be performed based on the memristor array, so that internal calculation is realized, the calculation complexity is reduced, the data movement in the calculation process is reduced, the calculation efficiency is improved, and the energy consumption is reduced.
Fig. 2 is a schematic diagram of a hash-based encoding system provided in an embodiment of the present application, where the hash-based encoding system includes a CPU20 and a memristor chip 30, where the CPU20 is configured to perform word segmentation on a text, encode each word to obtain a feature vector corresponding to each word, convert each feature vector into a hash value through an LSH algorithm, and set a weight for each word. The memristor chip 30 is configured to calculate a product between the hash value corresponding to each word and the weight, and convert the calculated result into a sequence represented by 0 and 1, so as to obtain a data fingerprint corresponding to the text.
As shown in fig. 3, the memristor chip 30 includes a control circuit 31, a memristor array 32, and a processing circuit 33 the control circuit 31 includes a first control circuit 310 and a second control circuit 32033. The memristor array 32 includes a plurality of memristors, and bit lines and word lines connecting each memristor in the memristor array, a positive stage of each memristor being connected with one bit line, and a negative stage being connected with one word line. Different resistance values of the memristor can be used for representing different values, for example, different resistance values of the memristor are used for representing 0 and 1, a resistance value larger than or equal to a first threshold value is used for representing 0, and a resistance value smaller than the first threshold value is used for representing 1. The first control circuit 310 is connected with each bit line, the second control circuit 320 is connected with each word line, and the first control circuit 310 and the second control circuit 320 output different voltages to the memristor through the bit lines and the word lines, so that different memristors are at different resistance values to represent different values. Each word line output of the memristor array 32 is an input to a processing circuit 33, the processing circuit 33 being configured to convert an output signal of the memristor array 32 to a 0 or 1 output.
The first control circuit 310 includes a first read-write control circuit 311 and a first switch array 312, the first control circuit 310 is connected with bit lines of the memristor array 32; the second control circuit 320 includes a second read-write control circuit 321 and a second switch array 322, and the second control circuit 320 is connected to the word lines of the memristor array 32. The first control circuit 310 and the second control circuit 320 can select a memristor needing to be read or written through a switch array, and then the read or the write of the memristor is realized by applying a voltage to the selected memristor. Reading the memristor means acquiring the resistance value of the memristor, and determining the value represented by the memristor according to the resistance value of the memristor; writing to a memristor refers to bringing the memristor to different resistance values by applying different voltages to the memristor to represent the different values.
In the embodiment of the present application, the memristor is divided into a first resistance state and a second resistance state according to the difference of resistance values of the memristor, the resistance value corresponding to the first resistance state is smaller than the resistance value corresponding to the second resistance state, and in the embodiment of the present application, the first resistance state is referred to as a low resistance state, and the second resistance state is referred to as a high resistance state. If 1 is represented by the low-resistance state of the memristor, and 0 is represented by the high-resistance state, when 1 needs to be written into the memristor in the 2 nd row and 3 rd column in fig. 3, the switch connected with the 3 rd column bit line in the first switch array 312 is closed, the switch connected with the 2 nd row word line in the second switch array 322 is closed, and then a forward voltage is applied to the memristor in the 2 nd row and 3 rd column through the first read-write control circuit 311 to set the memristor to the low-resistance state. If the value of the memristor in the 2 nd row and the 3 rd column needs to be read, after the switch connected with the 3 rd column bit line in the first switch array 312 is closed and the switch connected with the 2 nd row word line in the second switch array 322 is closed, the first read-write control circuit 311 applies a forward voltage to the memristor, reads the value of the current flowing through the memristor, and when the value of the current is greater than or equal to the threshold value, the memristor is in a low resistance state, which represents 1, and when the value of the current is less than the threshold value, the memristor is in a high resistance state, which represents 0.
In this embodiment of the application, the processing module 33 includes m subtractors and m comparators, a positive input end of one of the m subtractors is connected to one word line, that is, connected to the cathodes of one row of memristors, and a negative input end of the same subtracter is connected to another word line, that is, connected to the cathodes of another row of memristors. The output end of each subtracter is connected with one input end of a comparator, and the other input end of the comparator is grounded. In the embodiment of the present application, for convenience of description, m rows and n columns of memristors connected to the forward input end of the subtractor in the memristor array 32 are referred to as an array a, and m rows and n columns of memristors connected to the reverse input end of the subtractor in the memristor array 32 are referred to as an array B.
As shown in fig. 4, array a includes m rows and n columns of memristors, array B also includes m rows and n columns of memristors, array a includes m rows of word lines and n columns of bit lines, array B includes m rows of word lines and n columns of bit lines, and array a and array B share the same n columns of bit lines. I.e. if A is usedijThe memristor of ith row and jth column in array A is represented by BijRepresenting the memristor in the ith row and the jth column in array B. The memristor of the jth column in each row in the array A and the anode of the memristor of the jth column in each row in the array B are connected to the same column bit line, and the word line of the ith row in the array A and the word line of the ith row in the array B are connected to two input ends of the same subtracter. Wherein m and n are both positive integers greater than 1, i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n.
In the embodiment of the application, a memristor A in an array A is usedijAnd in array BMemristor BijThe memristors in the ith row and the jth column in the array A and the memristors in the ith row and the jth column in the array B which are connected with the same subtracter in a negative electrode mode jointly represent a real number. If each memristor includes a high resistance state and a low resistance state, the two memristors can form four different combinations in common, which can be used to represent 4 real numbers. Since the simhash usually converts the feature vector corresponding to each word into 1 and-1, for example, the above five words are respectively expressed as h (w1) ═ 1, -1,1]，h(w2)＝[-1，1，1]，h(w3)＝[1，-1，-1]，h(w4)＝[-1，-1，1]，h(w5)＝[1，1，-1]Therefore, in the embodiment of the present application, the memristor a in the array a and the array B is passedijAnd BijReal numbers that can be expressed are shown in table 1 below. It will be appreciated that in figure 4 the word lines of array a are connected to the positive input of the subtractor and the word lines of array B are connected to the negative input of the subtractor and so will be aijLow resistance state and BijHigh impedance state of (1) is represented by AijHigh resistance state of and BijThe low resistance state of (1) represents, and the correspondence in table 1 is only an example and is not to be understood as a specific limitation. For example, if the word line of array A is connected to the inverting input terminal of the subtractor and the word line of array B is connected to the inverting input terminal of the subtractor, A may be usedijHigh resistance state of and BijThe low resistance state of (A) represents 1ijLow resistance state and BijThe high resistance state of (2) represents-1. Typically, to reduce power consumption, two high resistance states are used to represent 0.
TABLE 1
| Aij | Bij | Value of |
| Low resistance state | |
1 |
| High resistance state | Low resistance state | -1 |
| High resistance state | |
0 |
| Low resistance state | |
0 |
An implementation method of the simhash algorithm provided in the embodiment of the present application is described below with reference to fig. 3 and fig. 4, and as shown in fig. 5, fig. 5 is a schematic flow diagram of a memristor-based hash coding method provided in the embodiment of the present application.
S501, the CPU converts the words in the target text into hash values and configures weight for each word.
The method for converting the words in the target text into the hash value by the CPU20 can refer to step 1 and step b in the above steps of the simhash algorithm, and will not be described in detail here.
S502, the CPU determines the target memristor and the address of the target memristor, and determines the resistance state of each memristor in the target memristor according to the hash value corresponding to each word.
After converting each word in the text into hash values represented by 1 and-1 and assigning a weight to each word, the CPU20 determines the target memristors required to represent the words and the address of each of the target memristors, based on the number of words and the length of each hash value. If the number of words corresponding to a text is N, the number of bits of a hash value corresponding to each word is F, each memristor connected to the same subtracter in the array A and the array B is required to represent one bit of the hash value, so that each word needs to be represented by the memristors in the F arrays A and the memristors in the F arrays B, the CPU20 determines that the memristors in the 2F rows and the N columns need to be gated as target memristors, and the addresses of the target memristors include the addresses of the memristors in the 2F rows and the N columns. For example, the CPU20 may select memristors in rows 1 through F in array a and 1 through F in array B as target memristors. In fig. 4, the memristor in each column represents a hash value corresponding to a word, and the two memristors connected to the same subtractor in the same column of the array a and the array B represent a digital value in the hash value together.
After determining the target memristor, the CPU20 needs to determine the resistance state of each memristor in the target memristor according to the hash value corresponding to each word, as shown in table 1, at aijAnd BijIn a group of memristors, use AijLow resistance state of (1) and (B)ijHigh resistance state of (1) represents 1, AijHigh resistance state of and BijThe low resistance state of (2) represents-1. If a word corresponds to a hash value of [1, -1, 1]]The word is represented by the first column of memristors in the memristor array as shown in FIG. 4, then the CPU20 determines to convert A into A11Set to a low resistance state, B11Set to a high resistance state for representing 1, A21Set to a high resistance state, B21Set to a low resistance state for representing-1, A31Set to a low resistance state, B31Set to the high resistance state for 1.
It is to be understood that, after determining the resistance state of each of the target memristors, the CPU20 may send the address of one of the target memristors and the resistance state of the memristor to the first control circuit in the form of the address + resistance state identification, for example, 1 represents that the resistance state of one of the target memristors is a high resistance state, and 0 represents that the resistance state of one of the target memristors is a low resistance state.
S503, the memristor chip receives the address of the target memristor sent by the CPU and the resistance state of each memristor in the target memristor, and each target memristor is set to be the corresponding resistance state.
The CPU20, after determining the address of each memristor and the state of each of the target memristors, sends the address of the target memristor and the resistance state of each of the target memristors to the memristor chip 32. After the memristor chip 32 receives the address of the target memristor and the resistance state of each memristor in the target memristor, the memristor chip 32 sets each memristor in each row in the target memristor to the corresponding resistance state in sequence. Specifically, the target memristor includes N columns in 2F rows, and the first switch array 312 in the first control circuit 310 closes the switches on the N columns of bit lines where the target memristor is located first, and closes the switches on the word lines connected to one of the rows of memristors in the target memristors in the 2F rows, so as to gate the N memristors in the row. Then grounding the second read-write control circuit 321, applying a positive voltage or a negative voltage to the positive electrode of each memristor of the gated row by the first read-write control circuit 311 through the bit lines of the N columns according to the resistance state corresponding to the gated memristor of the gated row, and setting the memristor to be in a low resistance state or a high resistance state; and then the switch on the word line of the row which is gated is turned off, the switch on the word line connected with the memristor of the next row is turned on, the N memristors of the next row are gated, and then the N memristors of the row are set to be the corresponding resistance states by the first read-write control circuit 311 until all the memristors of the N columns of the 2F rows are set to be the corresponding resistance states according to the method, so that the words corresponding to the text are written into the memristor array. When positive voltage is applied to the positive pole of the memristor, the memristor is placed in a low-resistance state, and when negative voltage is applied to the positive pole of the memristor, the memristor is placed in a high-resistance state.
Illustratively, taking the five words w1, w2, w3, w4 and w5 as examples, the CPU20 converts each word into a hash with a bit number of 3, which is h (w1) ═ 1, -1, respectively]，h(w2)＝[-1，1，1]，h(w3)＝[1，-1，-1]，h(w4)＝[-1，-1，1]，h(w5)＝[1，1，-1]. The memristor chip 32 requires 6 rows and 5 columns for 30 memristors to represent these five words. Where 6 memristors per column are used to represent a word, for example, w1 is represented by three memristors in the first three rows and the first column of array A and three memristors in the first three rows and the first column of array B. If CPU20 determines to use the bit lines of column 1 through column 5 in array A and array B, the word lines of row 1 through row 3 in array A, and the word lines of row 1 through row 3 in array B30 memristors connected on the line are used as target memristors. I.e. 6 memristors in the first column in fig. 4 are used to represent h (w1), a11And B11Represents 1, A21And B21Represents-1, A31And B31Indicating 1, the CPU20 determines to be a according to table 111Set to a low resistance state, B11Set to a high resistance state for representing 1, A21Set to a high resistance state, B21Set to a low resistance state for representing-1, A31Set to a low resistance state, B31Set to the high resistance state for 1. The CPU20 determines the resistance states of the 30 memristors described above according to the method described above, and then sends them to the memristor chip 32.
After the memristor chip 32 receives addresses of 30 memristors sent by the CPU20 and the resistance state of each memristor, the memristor chip 32 closes switches connected with bit lines of the 1 st column to the 5 th column in the first switch array 312, then grounds the second read-write control circuit 321, and closes a switch connected with a word line of the first row in the array a; since the first row of array A is strobed with A11、A12、A13、A14And A15The resistance states corresponding to the five memristors are a low resistance state, a high resistance state, a low resistance state, a high resistance state and a low resistance state in sequence. The first read/write control circuit 311 goes through the bit line to A11Applying a forward voltage to A12Applying a reverse voltage to A13Applying a forward voltage to A14Applying a reverse voltage to A15A forward voltage is applied to set the 5 memristors gated on the first row of array a to the resistance state determined by CPU 20.
After the memristors in the first row of the array A are set to the corresponding resistance states, the switch connected with the word line in the first row of the array B is closed, the five memristors in the first row of the array B are gated, and meanwhile, the switch connected with the word line in the first row of the array A is opened, so that the resistance states of the memristors in the first row of the array A are prevented from changing when voltage is applied through the first read-write control circuit 311. The first row of array B is strobed with B11、B12、B13、B14And B15The resistance states corresponding to the five memristors are a high resistance state, a low resistance state, a high resistance state, a low resistance state and a high resistance state in sequenceA resistive state. The first read/write control circuit 311 goes through the bit line to B11Applying a reverse voltage to B12Applying a forward voltage to B13Applying a reverse voltage to B14Applying a forward voltage to B15A reverse voltage is applied to set the 5 memristors gated in the first row of array B to the resistance state determined by CPU 20. After the memristors in the first row of array a and the first row of array B are set to the corresponding resistance states, the value of the first bit of h (w1) -h (w5) is written into the memristor array 32. Based on the same method, the memristors in the 6 rows are sequentially set to the resistance states determined by the CPU20, and then the writing of h (w1) -h (w5) into the memristor array 32 can be realized.
S504, the memristor chip receives the weight sent by the CPU, the weight corresponding to each word is converted into corresponding target voltage, and the corresponding target voltage is applied to the bit line where the target memristor is located.
The CPU20 transmits the weight corresponding to each word to the first read/write control circuit 311, and the first read/write control circuit 311 converts the value of each weight into a corresponding voltage. For example, the first read-write control circuit 311 can convert the weights into voltages of the same ratio according to the ratio between the weights, and then apply the voltage corresponding to each word to the memristor used to represent the word. For example, the weight vector corresponding to the above five words w 1-w 5 is [4, 3, 1, 2, 0], and the first read/write control circuit 311 converts the weight value of 4 into a voltage of 4V, the weight value of 3 into a voltage of 3V, and so on. Since weight 4 is a weight of w1, the memristor connected to the bit line of the first column in the memristor array 32 represents w1, then a voltage of 4V is applied to the bit line of the first column, a voltage of 3V is applied to the bit line of the second column, a voltage of 1V is applied to the bit line of the third column, a voltage of 2V is applied to the bit line of the fourth column, and a weight of w5 is 0, then no voltage is applied to the bit line of the fifth column. The target voltage is smaller than a starting voltage capable of changing the resistance of the memristor.
After the first read-write control circuit 311 applies a corresponding target voltage to the target memristor, different currents are generated on each word line of the array a and the array B, after the currents on the two word lines connected to the same subtracter pass through the subtracter, the output voltage of the subtracter is compared with 0 voltage, and if the output voltage of the subtracter is greater than 0V, the comparator outputs a high level, which represents 1; if the output voltage of the subtracter is less than 0V, the comparator outputs a low level, which represents 0. And acquiring the level output by the comparator to obtain the data fingerprint corresponding to the text, namely completing the multiplication operation of the feature matrix corresponding to the text and the weight vector.
The memristors in the memristor array are set to be in different resistance states through the control circuit and used for representing different values in the matrix, then each value in the vector is converted into corresponding voltage, matrix vector multiplication is further completed, matrix vector multiplication calculation is unloaded to the memristor array, memory calculation is achieved, data carrying between the memory and a CPU can be reduced, complexity of the matrix vector multiplication is reduced, calculation speed is improved, and energy consumption is reduced.
The embodiment of the application further provides a computing device, the computing device comprises the memristor chip, and the computing device performs logic operation of matrix vector multiplication through the memristor chip.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same. Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A memristor chip, comprising a control circuit, a memristor array, and a processing circuit, wherein,
the control circuit is configured to: setting memristors in 2F rows and N columns in the memristor array to different resistance states, wherein the memristors in the 2F rows and the N columns are used for representing a matrix of F rows and N columns, and two memristors in each column represent one value in the matrix;
converting N values in a vector of N rows and 1 columns into corresponding N voltages, and applying voltages corresponding to the 1 st row numerical values to the N rows and the N columns of memristors respectively, wherein the N voltage values are all smaller than the voltage for changing the resistance of the memristors;
the processing circuit is used for processing the output of the 2F row memristor.
2. The memristor chip of claim 1, the processing circuitry to detect the output current of every two rows of memristors and take the output current of every two rows of memristors as a result of multiplication of the matrix of the F rows and the N columns by the vector of the N rows and the 1 column.
3. The memristor chip of claim 1, the processing circuitry to include F subtractors and F comparators, one subtracter connected to every two rows of memristors in the memristor array, one comparator connected to each subtracter, the outputs of the F comparators to form a binary hash code.
4. The memristor chip according to any one of claims 1 to 3, wherein the control circuit is configured to set the memristors in 2F rows and N columns in the memristor array to different resistance states, and specifically comprises:
according to the resistance state of each memristor in the memristors in the 2F rows and the N columns, which is determined by the processor, grounding the negative electrode of the memristor in the s-th row in the memristor array; applying voltage to the positive electrode of each memristor in the s-th row of memristors to enable the resistance value of each memristor in the s-th row of memristors to be in a first resistance state or a second resistance state, wherein the resistance value of the first resistance state is smaller than that of the second resistance state, and the value of s is 1-2F;
after applying a voltage to the positive electrode of the s-th row memristor, disconnecting the negative electrode of the s-th row memristor from ground.
5. The memristor chip of claim 4, wherein the control circuitry is specifically to:
in the matrix of the ith1Line j (th)1When the column value is 1, the ith in the memristor array is compared1Line j (th)1Setting the memristors of the columns to be in the first resistance state, and setting the ith resistor in the memristor array1Row +1, j1The memristors of the +1 column are set to the second resistance state; in the matrix of the ith2Line j (th)2When the column value is-1, the ith in the memristor array is compared2Line j (th)2Setting the memristors of the columns to be in the second resistance state, and setting the ith resistance state in the memristor array2Row +1, j2The memristors of the +1 column are set to the first resistance state.
6. The memristor chip of claim 4 or 5, wherein the control circuit is specifically to:
at the i-th3Line j (th)3When the resistance state of the memristor of the column is the first resistance state, the resistance state is changed to the ith resistance state3Line j (th)3Memristors of a column apply a forward voltage; or
At the i-th4Line j (th)4When the resistance state of the memristor of the column is the second resistance state, the resistance state is changed to the ith resistance state4Line j (th)4The memristors of the column apply a reverse voltage.
7. A logical operation method applied to the memristor chip as claimed in claims 1 to 6, the method comprising:
the control circuit sets memristors in 2F rows and N columns in the memristor array to different resistance states, wherein the memristors in the 2F rows and the N columns are used for representing a matrix of the F rows and the N columns, and two memristors in each column represent one value in the matrix;
converting N values in a vector of N rows and 1 columns into corresponding N voltages, and applying voltages corresponding to the 1 st row numerical values to the N rows and the N columns of memristors respectively, wherein the N voltage values are all smaller than the voltage for changing the resistance of the memristors;
processing circuitry processes outputs through the 2F rows of memristors.
8. The method of claim 7, wherein the processing circuitry processes the output through the 2F row of memristors, comprising:
the processing circuit detects the output current of every two rows of memristors, and takes the output current of every two rows of memristors as a result of multiplication of the matrix of the F rows and the N rows and the vector of the N rows and the 1 row.
9. The method of claim 7, the processing circuit comprising F subtractors and F comparators, one subtracter connected to every two rows of memristors in the memristor array, one comparator connected to each subtracter, the outputs of the F comparators forming a binary hash code.
10. The method of any of claims 7 to 9, wherein the control circuitry sets memristors of 2F rows and N columns of the memristor array to different resistance states, comprises:
in the matrix of the ith1Line j (th)1When the column value is 1, the ith in the memristor array is compared1Line j (th)1Setting the memristors of the columns to be in the first resistance state, and setting the ith resistance state in the memristor array1Row +1, j1The memristors of the +1 column are set to the second resistance state; in the matrix of the ith2Line j (th)2When the column value is-1, the ith in the memristor array is compared2Line j (th)2Setting the memristors of the columns to be in the second resistance state, and setting the ith resistance state in the memristor array2Row +1, j2The memristors of the +1 column are set to the first resistance state.
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| CN117271435B (en) * | 2023-11-17 | 2024-02-13 | 中国人民解放军国防科技大学 | Memristor-based in-memory logic circuit and full-array parallel computing method |
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