TWI690154B - Amplifier circuit and associated compensation circuit - Google Patents

Abstract

An amplifier circuit has a multi-stage amplifier, a compensation capacitor, and compensation circuits. The multi-stage amplifier has amplifiers cascaded between an input port and an output port of the multi-stage amplifier. The amplifiers include at least a first-stage amplifier, a second-stage amplifier and a third-stage amplifier. The compensation capacitor is coupled between the output port of the multi-stage amplifier and an output port of the first-stage amplifier. The compensation circuits include a first compensation circuit and a second compensation circuit. The first compensation circuit is coupled to the output port of the first-stage amplifier. The second compensation circuit is coupled to an output port of the second-stage amplifier.

Description

Amplifier circuit and related compensation circuit

The present invention relates to an amplifier design, and more particularly, to a multi-stage amplifier circuit (multi-stage amplifier circuit) having at least one zero and at least one pole inserted by a compensation circuit.

The performance obtained from a single-stage amplifier is usually not sufficient for many applications. Therefore, multi-stage amplifiers that cascade some amplification stages are used to achieve the desired performance. Taking a three-stage amplifier as an example, the output of the first-stage amplifier is used as the input of the second-stage amplifier, and the output of the second-stage amplifier is used as the input of the third-stage amplifier. To suppress thermal noise, a first-stage amplifier with large transconductance is used. However, unity-gain bandwidth (UGB)/unity-gain frequency (UGF) is positively related to the transconductance of the first-stage amplifier. In other words, the larger the transconductance of the first-stage amplifier, the higher the unity-gain frequency, and the larger the unity-gain bandwidth. In the case where the first-stage amplifier is configured to have a large transconductance, the two high-frequency non-dominant poles of the third-stage amplifier are located at a frequency lower than the unity gain frequency. Therefore, the three-stage amplifier becomes unstable.

The unity gain bandwidth/unity gain frequency is inversely related to Miller capacitance. To solve the stability problem, one solution is to increase the Miller capacitance, thereby reducing the unity gain frequency Rate and reduce the unity gain bandwidth to achieve stability improvement. However, the dominant pole is also inversely related to the Miller capacitance. Therefore, the main pole is shifted to a lower frequency, which causes the in-band gain to decrease. Therefore, a three-stage amplifier with large Miller capacitance has poor in-band signal quality.

Therefore, a novel frequency compensation design is needed to enhance the stability of the multi-stage amplifier circuit without reducing the in-band gain of the multi-stage amplifier circuit.

One of the objects of the present invention is to provide a multi-stage amplifier circuit and related compensation circuit to solve the above problems.

According to the first aspect of the present invention, there is provided an amplifier circuit including a multi-stage amplifier, a compensation capacitor, and a plurality of compensation circuits. The multi-stage amplifier includes a plurality of amplifiers cascaded between the input end and the output end of the multi-stage amplifier, and the plurality of amplifiers includes at least a first-stage amplifier, a second-stage amplifier, and a third-stage amplifier. The compensation capacitor is coupled between the output of the multi-stage amplifier and the output of the first-stage amplifier. And, the plurality of compensation circuits include a first compensation circuit and a second compensation circuit. The first compensation circuit is coupled to the output terminal of the first-stage amplifier; the second compensation circuit is coupled to the output terminal of the second-stage amplifier.

According to a second aspect of the present invention, a compensation circuit is provided, including a high-pass filter, an auxiliary amplifier, a capacitor, and a resistor. The high-pass filter has an input and an output; the input of the auxiliary amplifier is coupled to the output of the high-pass filter; a capacitor is coupled between the input of the high-pass filter and the output of the auxiliary amplifier; and, the resistor It is coupled between the output terminal of the auxiliary amplifier and the bias voltage.

In the above technical solution, the provided multi-stage amplifier circuit and compensation circuit can be used to enhance the stability of the multi-stage amplifier circuit without reducing the in-band gain of the multi-stage amplifier circuit.

Those of ordinary skill in the art can understand these and other objects of the present invention without any doubt after reading the following detailed description of the preferred embodiments shown in the drawings.

100, 1000: amplifier circuit

102: Three-stage amplifier

112: Combination circuit

114: first-stage amplifier

116: Second-stage amplifier

118: third stage amplifier

S _IN : source signal

N _IN , P ₁₁ , P ₂₁ , P ₃₁ , P ₄₁ , P ₅₁ , P ₉₁ : input

N _OUT , P ₁₂ , P ₂₂ , P ₃₂ , P ₄₂ , P ₅₂ , P ₉₂ : output

_Co1 , _Co2 , _Co3 : output capacitance

R _o1 , R _o2 , R _o3 : output resistance

C _d1 , C _d2 , C _B1 , C _F1 , C _B2 : capacitance

R _d1 , R _d2 , R _B1 , R _F1 , R _B2 : resistance

104_1: the first compensation circuit

104_2: Second compensation circuit

C _L : load capacitance

R _L : load resistance

S _OUT : output signal

C _m1 , C _m2 , ..., C _m(N-2) , C _m(N-1) : compensation capacitor

P ₁ : main pole

P ₂ , P ₃ : secondary pole

P _d : inserted pole

Z _d : inserted zero point

400, 500, 600, 900: compensation circuit

402, 902: auxiliary amplifier

V _IN : input of the compensation circuit

V _B1 , V _B2 , V _B3 : bias voltage

502: High-pass filter

FIG. 1 is a schematic diagram of an amplifier circuit described according to an embodiment of the invention.

FIG. 2 is a schematic diagram of the concept of the proposed frequency compensation (unit gain bandwidth control) scheme according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a detailed frequency response curve of the amplifier circuit shown in FIG. 1 according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a first compensation circuit design according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a second compensation circuit design according to an embodiment of the present invention.

Figure 6 depicts a schematic diagram of a compensation circuit with a high-pass filter located outside the loop formed by the auxiliary amplifier and the capacitor.

Fig. 7 depicts a schematic diagram of a compensation circuit with a high-pass filter located in a loop formed by an auxiliary amplifier and a capacitor.

FIG. 8 is a circuit diagram of the compensation circuit shown in FIG. 5 or FIG. 7 according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of a third compensation circuit design according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of another amplifier circuit described according to an embodiment of the present invention.

In the following detailed description, for the purpose of illustration, many specific details are set forth so that those with ordinary knowledge in the technical field can more thoroughly understand the embodiments of the present invention. However, it is obvious that one can implement a without these specific details One or more embodiments, different embodiments can be combined according to requirements, and should not be limited to the embodiments listed in the drawings.

The following description is a preferred embodiment of the present invention. The following embodiments are only used to illustrate the technical features of the present invention, and are not intended to limit the scope of the present invention. Certain words are used throughout the specification and patent application to refer to specific components. Those of ordinary skill in the art should understand that manufacturers may use different terms to refer to the same components. This specification and the scope of patent application do not use differences in names as a way to distinguish components, but rather differences in functions of components as a basis for differentiation. The scope of the present invention should be determined with reference to the appended patent application scope. The terms "comprising" and "including" mentioned in the following description and patent application are open-ended terms, so they should be interpreted as meaning "including, but not limited to...". Furthermore, the term "coupled" means an indirect or direct electrical connection. Therefore, if it is described that one device is coupled to another device, it means that the device may be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

As used herein, the term "basic" or "approximately" means that within the acceptable range, those with ordinary knowledge in the technical field can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "substantially equal" refers to a method that can be accepted by a person with ordinary knowledge in the technical field and has a certain error from "completely equal" without affecting the correctness of the result.

FIG. 1 is a schematic diagram of an amplifier circuit described according to an embodiment of the present invention. As an example and not limiting sense, the amplifier circuit 100 can be used in audio applications. As shown in FIG. 1, the amplifier circuit 100 is a multi-stage amplifier circuit, including a multi-stage amplifier (for example, a three-stage amplifier 102), a plurality of compensation circuits (for example, a first compensation circuit 104_1 and a second compensation circuit 104_2), and , Multiple compensation capacitors (for example, C _m1 and C _m2 ). Each of the compensation capacitors C _m1 and C _m2 is used for Miller compensation. Therefore, the compensation capacitors C _m1 and C _{m2 are} used to implement a nested Miller compensation (NMC) scheme. However, this is for illustrative purposes only and is not meant to limit the invention. In some embodiments of the present invention, the compensation capacitor C _m2 may be optional. For example, regarding the proposed frequency compensation (unity gain bandwidth control) scheme, the compensation capacitor C _m2 can be omitted according to actual design considerations.

The three-stage amplifier 102 has three amplifiers, including a first-stage amplifier 114, a second-stage amplifier 116, and a third-stage amplifier 118, which are cascaded between the input terminal N _IN and the output terminal N _OUT of the third-stage amplifier 102 between. For example, the first-stage amplifier 114 serves as the input stage of the three-stage amplifier 102, and the third-stage amplifier 118 serves as the output stage of the three-stage amplifier 102. In addition, a combining circuit (combining circuit) 112 is used to generate and feed the first stage by combining the source signal S _IN received at the input terminal N _IN and the feedback signal obtained from the output signal S _OUT generated at the output terminal N _OUT P input of the amplifier 114 is an input signal _11. The transconductance of the first-stage amplifier 114 is denoted by G _m1 , the transconductance of the second-stage amplifier 116 is denoted by G _m2 , and the transconductance of the third-stage amplifier 118 is denoted by G _m3 . It should be noted that, in order to obtain negative feedback loops (negative feedback loops) through the compensation capacitors C _m1 and C _{m2, the} gains of the second-stage amplifier 116 and the third-stage amplifier 118 in this embodiment are positive and positive, respectively. Negative, the present invention does not limit the gain sign of the first-stage amplifier 114. For example, the gain of the first-stage amplifier 114 may be negative. In addition, the output resistance and output capacitance of the first-stage amplifier 114 are denoted by R _o1 and C _o1 respectively; the output resistance and output capacitance of the second-stage amplifier 116 are denoted by R _o2 and C _o2 , respectively; The output resistance and output capacitance are denoted by R _o3 and C _o3 respectively. The load driven by the amplifier circuit 100 may be equivalent to the load capacitance C _L and the load resistance R _L , but the embodiment of the present invention does not make any limitation on this.

The compensation capacitor C _{m1 is} coupled to the output terminal N _OUT of the third-stage amplifier 102 (which is also coupled to the output terminal P _{32 of the} third-stage amplifier 118) and the output terminal P _{12 of the} first-stage amplifier 114 (which is also coupled to Between the input terminals P ₂₁ ) of the second-stage amplifier 116. The optional compensation capacitor C _{m2 is} coupled to the output N _OUT of the third-stage amplifier 102 (which is also coupled to the output P _{32 of the} third-stage amplifier 118) and the output P _{22 of the} second-stage amplifier 116 (which is also It is coupled between the input terminals P ₃₁ ) of the third-stage amplifier 118.

In this embodiment, the first compensation circuit 104_1 is coupled to the output terminal P _{12 of the} first-stage amplifier 114, and the second compensation circuit 104_2 is coupled to the output terminal P _{22 of the} second-stage amplifier 116. For example, the first compensation circuit 104_1 and/or the second compensation circuit 104_2 may be implemented using a damping-factor-control (DFC) circuit. Therefore, the first compensation circuit 104_1 may be equivalent to the capacitor C _d1 and the series resistance R _d1 , and/or the second compensation circuit 104_2 may be equivalent to the capacitor C _d2 and the series resistance R _d2 . For low-frequency signals, the capacitor C _d2 is open-circuited, thereby disconnecting the resistor R _d2 from the tertiary amplifier 102. For high-frequency signals, the capacitor C _d2 is short-circuited, thereby connecting the resistor R _d2 to the third-stage amplifier 102 to reduce the gain of the second-stage amplifier. In the embodiment of the present invention, the resistance value of the resistor R _d1 is deliberately set to be very small. Since the resistance value of the resistor R _d1 is very small, the first compensation circuit 104_1 presents the capacitance of the capacitor C _d1 to low-frequency signals or Three-stage amplifier 102 for high-frequency signals. In some embodiments, the resistance value of the resistance R _d2 is larger than the resistance value of the resistor R _d1.

The key feature of the proposed amplifier circuit 100 is the use of multiple compensation circuits to achieve frequency compensation (eg, unity gain bandwidth control). Unlike the conventional damping factor control frequency compensation, the first compensation circuit 104_1 and the second compensation circuit 104_2 are set to insert at least one zero point and at least one pole point, wherein, at each inserted zero point and pole point, the amplifier circuit The open-loop gain of 100 is greater than 1 (ie, 0dB). That is, when the frequency of the source signal S _IN is equal to the frequency of the inserted zero or pole, the open-loop gain of the amplifier circuit 100 is greater than 0 dB.

In the following, the symbol of the capacitor may also represent the capacitance value of the capacitor, and the symbol of the resistance may also represent the resistance value of the resistor. For example, the compensation capacitance C _m2 may be regarded as having a capacitance value C _m2 ; and, the resistance R _d1 may be regarded as having a resistance value R _d1 .

FIG. 2 is a schematic diagram of the concept of the proposed frequency compensation (unit gain bandwidth control) scheme according to an embodiment of the present invention. In the case where the amplifier circuit 100 shown in FIG. 1 is modified to omit the first compensation circuit 104_1 and the second compensation circuit 104_2, the modified amplifier circuit does not have the proposed frequency compensation (unity gain bandwidth control), and The modified amplifier circuit has a frequency response curve F _old as shown in FIG. 2, where each pole is represented by a cross symbol. In another case of the amplifier circuit 100 shown in FIG. 1, the amplifier circuit 100 has a first compensation circuit for inserting a zero point Z _d and a pole P _d for frequency compensation (unity gain bandwidth control) according to the present invention 104_1 and the second compensation circuit 104_2, and the amplifier circuit 100 shown in FIG. 1 has a frequency response curve F _new as shown in FIG. 2, where each pole is represented by a cross symbol, and each zero point is represented by a circle Circle symbol (circle symbol) said. The open-loop transfer function of the amplifier circuit is represented by H(s). Therefore, the open-loop gain of the amplifier circuit can be expressed as | H ( s )|.

Regarding the case where the amplifier circuit 100 is modified to omit the first compensation circuit 104_1 and the second compensation circuit 104_2, the modified three-stage amplifier circuit has three poles, including a low-frequency main pole P ₁ and two high-frequency secondary poles P ₂ and P ₃ . The unity gain bandwidth/unity gain frequency is determined by dividing the transconductance _Gm1 of the first-stage amplifier 114 by the capacitance value of the compensation capacitor _Cm2 . Therefore, the unity gain bandwidth UGB _old is equal to G _m1 /C _m2 . As mentioned above, in order to suppress thermal noise, a first-stage amplifier with a large transconductance can be used. However, the larger the transconductance of the first-stage amplifier, the higher the unity-gain frequency, and the larger the unity-gain bandwidth. As shown in the frequency response curve F _old in FIG. 2, the frequencies of the two high-frequency secondary poles P ₂ and P ₃ are lower than the unity gain frequency. In other words, at each high-frequency secondary pole P ₂ and P ₃ , the modified open-loop gain of the three-stage amplifier circuit without the proposed frequency compensation (unity gain bandwidth control) is greater than 1 (ie, 0dB). Therefore, the modified three-stage amplifier circuit without the proposed frequency compensation (unity gain bandwidth control) becomes unstable.

According to the proposed frequency compensation (unity gain bandwidth control) scheme, the first compensation circuit 104_1 and the second compensation circuit 104_2 are added to insert a zero point (eg, intermediate frequency zero point) Z _d and a secondary pole (eg, intermediate frequency secondary pole point) )P _d . As shown in FIG. 2, the frequency of the secondary pole P _d is less than the frequency of the zero point Z _d . In this way, the unity gain bandwidth is shrunk by a shrinkage factor k, where k=Z _d /P _d , Z _d represents the frequency of the zero point being inserted, and P _d represents the frequency of the pole being inserted. Specifically, the unity gain bandwidth UGB _new is equal to G _m1 /(k*C _m2 ). As mentioned above, in order to suppress thermal noise, a first-stage amplifier with a large transconductance can be used, thereby increasing the unity gain bandwidth. However, due to the insertion of the secondary pole P _d and the zero point Z _d , the unity gain bandwidth UGB _new under the condition that the transconductance G _{m1 of the} first-stage amplifier 114 is large to suppress thermal noise can be accurately controlled. More specifically, the ratio of the frequency of the inserted zero point Z _{d to} the frequency of the inserted secondary pole P _d (that is, the shrinkage factor k) can be appropriately adjusted to adjust the unity gain bandwidth UGB _new , thereby ensuring that the amplifier circuit 100 meets Stability standards.

As shown in the frequency response curve F _new in FIG. 2, the two high-frequency secondary poles P ₂ ′ and P ₃ ′ are at frequencies higher than the unity gain frequency. In other words, at each high-frequency secondary pole P ₂ ′ and P ₃ ′, the open-loop gain of the amplifier circuit 100 with the proposed frequency compensation (unity gain bandwidth control) is less than 1 (ie, 0 dB). In this way, the amplifier circuit 100 with the proposed frequency compensation (unity gain bandwidth control) is unconditional in closed-loop operation due to the zero point Z _d and the secondary pole P _d inserted by the first compensation circuit 104_1 and the second compensation circuit 104_2 (unconditionally) stable.

The unity gain bandwidth/unity gain frequency is inversely related to the capacitance value of the compensation capacitor C _m1 connected between the output terminal N _{OUT of the} amplifier circuit 100 and the output terminal P _{12 of the} first-stage amplifier 114. In addition, the low-frequency main pole P ₁ ′ is also negatively related to the capacitance value of the compensation capacitor C _m1 connected between the output terminal N _{OUT of the} amplifier circuit 100 and the output terminal P _{12 of the} first-stage amplifier 114. Since the unity gain bandwidth can be sufficiently contracted by the contraction factor k controlled by the zero point Z _d and the secondary pole P _d , the stability of the amplifier circuit 100 can be ensured without increasing the capacitance value of the compensation capacitor C _m1 . In other words, the frequency of the main pole P ₁ ′ remains the same (similar to P ₁ ), thereby avoiding the reduction in in-band gain caused by shifting the main pole P ₁ ′ to a lower frequency, that is, it does not reduce the in-band Gain.

In short, the amplifier circuit 100 (implemented by inserting the zero point Z _d and the secondary pole P _d ) with the proposed frequency compensation (unity gain bandwidth control) can be unconditionally stable without reducing the in-band gain.

Please refer to Figure 1 in conjunction with Figure 3. FIG. 3 is a schematic diagram of a detailed frequency response curve of the amplifier circuit 100 shown in FIG. 1 according to an embodiment of the present invention. The aforementioned primary pole P ₁ ′ is represented by P _{1, LHP} in the third diagram, the aforementioned secondary pole P _{d is} represented by P _{2, LHP} in the third diagram, and the aforementioned zero point Z _d In Fig. 3 _{, it is} represented by Z _{1, LHP} . It can be seen from FIG. 3 that the inserted zero point Z _{1, LHP is} mainly controlled by the second compensation circuit 104_2 (for example, the capacitance value of the capacitor C _d2 and the resistance value of the resistor R _d2 ), and the inserted secondary pole P2 _{, LHP} is controlled by at least the first compensation circuit 104_1 and the second compensation circuit 104_2 (for example, the capacitance value of the capacitor C _d1 , the capacitance value of the capacitor C _d2 , and the resistance value of the resistor R _d2 ). The contraction factor k (k=Z _d /P _d ) can be expressed by the following equation.

，其中，G_m3

1/R_L,R_d2=G_d2

, Where G _m3

1/R _L , R _d2 =G _d2

Therefore, the shrinkage factor k depends on the capacitance value of the capacitor C _d1 , the capacitance value of the compensation capacitor C _m1 , the resistance value of the resistor R _d2 , and the transconductance G _{m2 of the} second-stage amplifier 116. The shrinkage factor k can be set to a value greater than 1 (ie, k>1) to increase stability, and can be determined by the capacitance value of the capacitor C _d1 , the compensation capacitance C _m1 , the resistance R _d2 , and the second-stage amplifier The transconductance G _{m2 of} 116 is precisely controlled. In this embodiment, the contraction factor k should be controlled to provide sufficient in-band phase margin (PM) so that the amplifier circuit 100 is unconditionally stable in closed-loop operation. For example, the contraction factor k may be set to a value less than 10 (ie, k<10) so that the in-band PM is greater than 35 degrees. However, this is for illustrative purposes only and is not meant to limit the invention.

As shown in Figure 3, one of the high frequency secondary poles P _3,LHP depends on the capacitance value of the compensation capacitor C _m2 and the resistance value of the resistor R _d2 , and the other zero point (for example, high frequency zero point) Z _2,LHP depends on The capacitance value of the capacitor C _d1 and the resistance value of the resistor R _d1 . By appropriately setting the capacitance value of the compensation capacitor C _m2, the resistance value of the resistor R _d2, the capacitance and resistance values of the resistance R _d1 capacitor C _d1 can be controlled high frequency pole P _{3, LHP} zero frequency, and Z _{2, The LHPs} are at the same frequency, that is, the high frequency sub-pole P _{3, LHP} is cancelled by the high frequency zero point Z _{2, LHP} .

FIG. 4 is a schematic diagram of a first compensation circuit design according to an embodiment of the present invention. The compensation circuit 400 includes an auxiliary amplifier 402 having a transconductance _Gmd1 , a capacitor C _B1 and a resistor R _B1 . In this embodiment, the gain of the auxiliary amplifier 402 is negative. The input terminal P _{41 of the} auxiliary amplifier 402 is coupled to the input V _{IN of the} compensation circuit 400. The capacitor C _{B1 is} coupled between the input terminal P ₄₁ and the output terminal P ₄₂ of the auxiliary amplifier 402. The resistor R _{B1 is} coupled between the output terminal P ₄₂ of the auxiliary amplifier 402 and the bias voltage V _B1 (eg, ground voltage). Since the input V _{IN of the} compensation circuit 400 is coupled to the input terminal P _{41 of the} auxiliary amplifier 402 (for example, the gate of the input transistor in the auxiliary amplifier 402 ), the compensation circuit 400 has a characteristic of high input impedance. Regarding the amplifier circuit 100 shown in FIG. 1, the output of the low-noise first-stage amplifier 114 (that is, the input of the second-stage amplifier 116) requires high impedance. Therefore, the first compensation circuit 104_1 may be implemented using the compensation circuit 400 shown in FIG. 4, wherein the input V _{IN of the} compensation circuit 400 is coupled to the output terminal P _{12 of the} first-stage amplifier 114.

的電阻值。當使用第4圖所示的補償電路400來實現第一補償電路104_1時，C_d1=G_md1*C_B1*R_B1以及

。輔助放大器402的跨導G_md1可以設定為較大值以使電容C_d1具有大的電容值。然而，當補償電路400的輸入V_IN處的小擺幅帶內信號被具有大跨導G_md1的輔助放大器402放大時，可能導致放大器飽和(saturation)。結果是，當補償電路400的輸入V_IN處的帶內信號擺幅超過具有大跨導G_md1的輔助放大器402的小信號範圍時，補償電路400將無法執行第一補償電路104_1所需的電容倍增功能。為了增加具有大跨導G_md1的輔助放大器402的補償電路400的帶內信號範圍，本發明提出了另一種補償電路設計，其中， 高通濾波器(high-pass filter，HPF)被添加到第4圖所示的補償電路400中。應當說明的是，本發明實施例中的電阻(例如，R_B1、R_F1等)並不局限於傳統意義上的多晶矽電阻(poly resistor)，而可以是由主動元件和/或被動元件實現的能夠用於提供等效阻抗值或等效電阻的任意元件，例如，用於實現電阻功能的二極管接法電晶體(diode-connected transistor)、電流源(current source)、阱電阻(nell resistor)、主動電阻(active resistor)、被動電阻(passive resistor)等等。 The compensation circuit 400 uses capacitance multiplication technology. Therefore, the compensation circuit 400 can be considered to have a capacitance value equal to G _md1 *C _B1 *R _B1 . In addition, the compensation circuit 400 may be considered to have

Resistance value. When the compensation circuit 400 shown in FIG. 4 is used to implement the first compensation circuit 104_1, C _d1 =G _md1 *C _B1 *R _B1 and

. The transconductance G _{md1 of the} auxiliary amplifier 402 can be set to a large value so that the capacitance C _d1 has a large capacitance value. However, when the small swing in-band signal at the input V _IN of the compensation circuit 400 is amplified by the auxiliary amplifier 402 having a large transconductance G _md1 , it may cause amplifier saturation. As a result, when the in-band signal swing at the input V _IN of the compensation circuit 400 exceeds the small signal range of the auxiliary amplifier 402 with a large transconductance G _md1 , the compensation circuit 400 will not be able to perform the capacitance required by the first compensation circuit 104_1 Multiplier function. In order to increase the in-band signal range of the compensation circuit 400 of the auxiliary amplifier 402 with a large transconductance _Gmd1 , the present invention proposes another compensation circuit design in which a high-pass filter (HPF) is added to the fourth In the compensation circuit 400 shown in the figure. It should be noted that the resistors (for example, R _B1 , R _F1, etc.) in the embodiments of the present invention are not limited to poly resistors in the traditional sense, but can be implemented by active components and/or passive components Any element that can be used to provide an equivalent impedance value or equivalent resistance, for example, a diode-connected transistor for implementing a resistance function, a current source (current source), a well resistor (nell resistor), Active resistor (active resistor), passive resistor (passive resistor), etc.

FIG. 5 is a schematic diagram of another compensation circuit design according to an embodiment of the present invention. The main difference between the compensation circuits 400 and 500 is that the compensation circuit 500 has a high-pass filter (HPF) 502 included therein, wherein the input terminal P _{51 of the} high-pass filter (HPF) 502 is coupled to the input V of the compensation circuit 500 _IN , and the output terminal P _{52 of the} high-pass filter (HPF) 502 is coupled to the input terminal P _{41 of the} auxiliary amplifier 402. The in-band signal with a larger swing is attenuated by a high-pass filter (HPF) 502 to fall within the small signal range of the auxiliary amplifier 402 with a large transconductance _Gmd1 . Therefore, when the large swing in-band signal at the input V _IN of the compensation circuit 400 is amplified by the auxiliary amplifier 402 having a large transconductance G _md1 , it will not cause the amplifier to saturate. Due to the use of a high-pass filter (HPF) 502, the in-band signal range of the compensation circuit 500 may be large/wide. In addition, the compensation circuit 500 has a high input impedance because the input V _{IN of the} compensation circuit 500 is coupled to the input terminal P _{41 of the} auxiliary amplifier 402 through a high-pass filter (HPF) 502. Regarding the amplifier circuit 100 shown in FIG. 1, the output of the low-noise first-stage amplifier 114 (that is, the input of the second-stage amplifier 116) requires high impedance. Therefore, the first compensation circuit 104_1 can be implemented using the compensation circuit 500 shown in FIG. 5, wherein the input V _{IN of the} compensation circuit 500 is coupled to the output terminal P _{12 of the} first-stage amplifier 114.

。高通濾波器(HPF)502可使用電阻R_F1和電容C_F1來實現，電阻R_F1的一端耦接於偏置電壓V_B3，另一端通過電容C_F1耦接於補償電路600的輸入V_IN。由於高通濾波器(HPF)502位於由輔助放大器402和電容C_B1形成的迴路的外部，因此，看向高通濾波器(HPF)502的電容值C_d1為C_d1A∥C_F1(即

)，而看向高通濾波器 (HPF)502的電阻值R_d1為R_d1A∥R_F1(即

)。然而，原本預期會看到Cd1A，但由於Cd1A//CF1後的電容由CF1(CF1<<Cd1A)主導，因此由於負載效應，電容倍增會操作失敗。 It should be noted that in order to achieve the desired damping operation, the compensation circuit 500 needs to place the high-pass filter (HPF) 502 in a loop formed by the auxiliary amplifier 402 and the capacitor C _B1 . Please refer to Figure 6 in conjunction with Figure 7. Figure 6 depicts a schematic diagram of a compensation circuit with a high-pass filter (HPF) located outside the loop formed by the auxiliary amplifier and the capacitor. Figure 7 depicts a schematic diagram of a compensation circuit with a high-pass filter (HPF) located in a loop formed by an auxiliary amplifier and a capacitor. As shown in FIG. 6, the compensation circuit 600 has a high-pass filter (HPF) 502 which is located outside the loop formed by the auxiliary amplifier 402 and the capacitor C _B1 . The capacitance value C _d1A of the auxiliary amplifier 402 is G _md1 *R _B1 *C _B1 , and the resistance value R _d1A of the auxiliary amplifier 402 is

. The high-pass filter (HPF) 502 can be implemented using a resistor R _F1 and a capacitor C _F1 . _One end of the resistor R _F1 is coupled to the bias voltage V _B3 , and the other end is coupled to the input V _{IN of the} compensation circuit 600 through the capacitor C _F1 . Since the high-pass filter (HPF) 502 is located outside the loop formed by the auxiliary amplifier 402 and the capacitor C _B1 , the capacitance value C _d1 of the high-pass filter (HPF) 502 is C _d1A ∥C _F1 (ie

), and the resistance value of the high-pass filter (HPF) 502 R _d1 is R _d1A ∥R _F1 (ie

). However, it was originally expected to see Cd1A, but since the capacitance after Cd1A//CF1 is dominated by CF1 (CF1<<Cd1A), the capacitance multiplication will fail due to load effects.

。 對於低頻信號，等效電容G_md1(HPF)*R_B1*C_B1和等效電阻

都是開路的。對於高頻信號，補償電路500呈現被放大的電容G_md1(HPF)*R_B1*C_B1來控制單位增益帶寬。沒有負載效應影響電容倍增操作。 As shown in FIG. 7, the compensation circuit 500 has a high-pass filter (HPF) 502 located in a loop formed by the auxiliary amplifier 402 and the capacitor C _B1 . As described above, the high-pass filter (HPF) 502 can be implemented using the resistor R _F1 and the capacitor C _F1 . Since the high-pass filter (HPF) 502 is located in the loop formed by the auxiliary amplifier 402 and the capacitor C _B1 , the capacitance value C _d1 of the high-pass filter (HPF) 502 is G _md1 (HPF)*R _B1 *C _B1 , And looking at the resistance value R _d1 of the high-pass filter (HPF) 502 as

. For low-frequency signals, the equivalent capacitance G _md1 (HPF)*R _B1 *C _B1 and equivalent resistance

It's all open. For high-frequency signals, the compensation circuit 500 presents the amplified capacitance G _md1 (HPF)*R _B1 *C _B1 to control the unity gain bandwidth. There is no load effect that affects the capacitance multiplication operation.

FIG. 8 is a circuit diagram of the compensation circuit 500 shown in FIG. 5 or FIG. 7 according to an embodiment of the present invention. As shown in FIG. 8, one end of the capacitor C _B1 and one end of the capacitor C _F1 are coupled to the input V _IN , and the other end of the capacitor C _F1 is coupled to the gate of the input transistor of the auxiliary amplifier 402 and the capacitor C The other end of _B1 is coupled to the drain of the output transistor of the auxiliary amplifier 402. Therefore, the high-pass filter (HPF) 502 is located in the loop formed by the capacitor C _B1 and the auxiliary amplifier 402, thereby avoiding the load effect. It should be noted that the circuit design of the auxiliary amplifier 402 shown in FIG. 8 is for illustrative purposes only, and is not meant to limit the present invention. That is, in some embodiments of the present invention, the auxiliary amplifier 402 may be implemented using a circuit design different from that shown in FIG. 8.

FIG. 9 is a schematic diagram of yet another compensation circuit design according to an embodiment of the present invention. The compensation circuit 900 includes a transconductance G _md2 auxiliary amplifier 902, a capacitor C _B2 and resistor R _B2. In this embodiment, the gain of the auxiliary amplifier 902 is negative. The output terminal P _{92 of the} auxiliary amplifier 902 is coupled to the input V _{IN of the} compensation circuit 900. The capacitor C _{B2 is} coupled between the input terminal P ₉₁ and the output terminal P ₉₂ of the auxiliary amplifier 902. The resistor R _{B2 is} coupled between the input terminal P ₉₁ of the auxiliary amplifier 902 and the bias voltage V _B2 (eg, ground voltage). The compensation circuit 900 can be applied to a large swing signal at the input V _IN of the compensation circuit 900. Regarding the amplifier circuit 100 shown in FIG. 1, the output of the second-stage amplifier 116 (which is also the input of the third-stage amplifier 118) may have a large swing for class AB operation. Therefore, the second compensation circuit 104_2 may be implemented using the compensation circuit 900 shown in FIG. 9, where the input V _{IN of the} compensation circuit 900 is coupled to the output terminal P _{22 of the} second-stage amplifier 116. However, this is for illustrative purposes only and is not meant to limit the invention. In some embodiments of the present invention, the second compensation circuit 104_2 may be implemented using the compensation circuit 400/500 so that the output of the second stage amplifier 116 (which is also the input of the third stage amplifier 118) may benefit from the compensation circuit 400/ 500 provides high impedance. These alternative designs all fall within the scope of the present invention.

The multi-stage amplifier used in the amplifier circuit 100 is a three-stage amplifier. However, the same frequency response (unity gain bandwidth control) scheme can be extended and applied to multi-stage amplifiers with more than three amplifier stages. FIG. 10 is a schematic diagram of another amplifier circuit described according to an embodiment of the present invention. By way of example, and not limitation, amplifier circuit 1000 can be used in audio applications. As shown in FIG. 10, the amplifier circuit 1000 is a multi-stage amplifier circuit, including an amplifier AMP ₁ -AMP _N , (N-1) compensation circuits CMP ₁ -CMP _N-1 and (N-1) compensation capacitors C An N-level amplifier composed of _m1- C _m(N-1) , where N is a positive integer greater than 3 (ie, N>3). Each of the compensation capacitors C _m1 -C _m(N-1) is used for Miller compensation. However, regarding the proposed frequency compensation (unity gain bandwidth control) scheme, the compensation capacitors C _m2 -C _m(N-1) are optional. In other words, in some embodiments of the present invention, the compensation capacitances C _m2 -C _m(N-1) may be omitted according to actual design considerations. The compensation circuit CMP ₁ can be implemented using the compensation circuit 400/500. According to actual design considerations, each of the compensation circuits CMP ₂ -CMP _N-1 may be implemented using one of the compensation circuits 400, 500, and 900. According to the proposed frequency response (unity gain bandwidth control) scheme, at least one zero point and at least one pole point are inserted by the compensation circuits CMP ₁ -CMP _N-1 . In this way, the amplifier circuit proposed by the present invention can have enhanced stability without reducing in-band gain.

Although the embodiments and advantages of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations can be made to the present invention without departing from the spirit of the present invention and the scope defined by the scope of the patent application, for example, New embodiments can be derived by combining parts of different embodiments. The described embodiments are used in all respects for illustrative purposes only and not to limit the invention. The scope of protection of the present invention shall be subject to the scope defined by the attached patent application. Those with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention.

The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: amplifier circuit

102: Three-stage amplifier

112: Combination circuit

114: first-stage amplifier

116: Second-stage amplifier

118: third stage amplifier

S _IN : source signal

N _IN , P ₁₁ , P ₂₁ , P ₃₁ : input terminal

N _OUT , P ₁₂ , P ₂₂ , P ₃₂ : output

_Co1 , _Co2 , _Co3 : output capacitance

R _o1 , R _o2 , R _o3 : output resistance

C _d1 , C _d2 : capacitance

R _d1 , R _d2 : resistance

104_1: the first compensation circuit

104_2: Second compensation circuit

C _L : load capacitance

R _L : load resistance

S _OUT : output signal

C _m1 , C _m2 : compensation capacitor

Claims (7)

An amplifier circuit includes a multi-stage amplifier including a plurality of amplifiers cascaded between an input end and an output end of the multi-stage amplifier; the amplifier circuit further includes: a compensation circuit, the compensation circuit It includes: a high-pass filter with an input end and an output end; the input end of the high-pass filter is coupled to the output end of one of the multi-stage amplifiers: an auxiliary amplifier, the input end of which is coupled to the high-pass filter The output of the capacitor; the capacitor, coupled between the input of the high-pass filter and the output of the auxiliary amplifier; and the resistor, coupled between the output of the auxiliary amplifier and the bias voltage. The amplifier circuit according to item 1 of the patent application scope further includes: a compensation capacitor coupled between the output terminal of the multi-stage amplifier and the output terminal of the first-stage amplifier in the multi-stage amplifier. The amplifier circuit according to item 1 of the patent application scope, wherein the compensation circuit is a damping factor control circuit. The amplifier circuit according to item 1 of the patent application scope, wherein one of the amplifiers is the second-stage amplifier in the multi-stage amplifier. The amplifier circuit according to item 1 of the patent application scope, wherein one of the amplifiers is the first-stage amplifier in the multi-stage amplifier. The amplifier circuit according to item 1 of the patent application range, wherein the bias voltage is a ground voltage. The amplifier circuit according to item 1 of the patent application scope, wherein the plurality of amplifiers include at least a first-stage amplifier, a second-stage amplifier, and a third-stage amplifier.

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