TWI690044B - 3d interconnect component for fully molded packages - Google Patents

Abstract

A method of making a semiconductor component package can include providing a substrate comprising conductive traces, soldering a surface mount device (SMD) to the substrate with solder, encapsulating the SMD on the substrate with a first mold compound over and around the SMD to form a component assembly, and mounting the component assembly to a temporary carrier with a first side of the component assembly oriented towards the temporary carrier. The method can further include mounting a semiconductor die comprising a conductive interconnect to the temporary carrier adjacent the component assembly, encapsulating the component assembly and the semiconductor die with a second mold compound to form a reconstituted panel, and exposing the conductive interconnect and the conductive traces at the first side and the second side of the component assembly with respect to the second mold compound.

Description

Fully molded 3D interconnect components

This disclosure claims the rights and interests of US Provisional Patent No. 62/154,218 titled "3D Interconnect Component for Fully Molded Packages" filed on April 29, 2015 (including the date of application), the disclosure content of which is incorporated herein by reference in.

This disclosure relates to a three-dimensional (3D) interconnection component or assembly of a fully molded package, including a rotating solderable assembly. A fully molded package may include a plurality of integrated semiconductor devices, including a component assembly, the plurality of integrated semiconductor devices being used for wearable technology, Internet of Things (IoT) devices, or both.

Semiconductor devices are common in modern electronic products. Semiconductor devices have different numbers of electrical components and density of electrical components. Discrete semiconductor devices generally contain one type of electrical components, such as light emitting diodes (LEDs), small signal transistors, resistors, capacitors, inductors, and power metal oxide semiconductor field effect transistors (MOSFETs). Integrated semiconductor devices generally contain hundreds to millions of electrical components. Integration Examples of embedded semiconductor devices include microcontrollers, microprocessors, charge-coupled devices (CCD), solar cells, and digital micromirror devices (DMD).

Semiconductor devices perform a variety of functions, such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and establishing visual projections for television displays. Semiconductor devices can be found in the fields of entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor devices can also be found in military applications, aviation, automobiles, industrial controllers, and office equipment.

Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material allows its electrical conductivity to be manipulated by applying an electric field or base current or through a doping process. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

A semiconductor device contains active and passive electrical structures. Active structures (including bipolar and field effect transistors) control the flow of current. By changing the level of doping and the level at which an electric field or base current is applied, the transistor promotes or limits the flow of current. Passive structures (including resistors, capacitors, and inductors) establish the relationship between voltage and current necessary to perform various electrical functions. The passive structure and the active structure are electrically connected to form a circuit, which enables the semiconductor device to perform high-speed computing and other practical functions.

Generally, two complicated manufacturing processes are used to manufacture semiconductor devices, namely, front-end manufacturing and back-end manufacturing, each of which may involve hundreds of steps. The front-end manufacturing involves forming a plurality of semiconductor die on the surface of a semiconductor wafer. Each semiconductor die is generally the same and contains The circuit formed by electrically connecting the active component and the passive component. Subsequent manufacturing involves singulation of individual semiconductor die from the finished wafer and packaging of the die to provide structural support and environmental isolation. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the other word, and may accordingly refer to both a single semiconductor device and multiple semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices generally consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. The smaller semiconductor die size can be achieved through the improvement of the previous procedure, thereby obtaining semiconductor die with smaller higher density active and passive devices. The second-stage procedure can obtain semiconductor device packages with smaller coverage areas through the improvement of electrical interconnection and packaging materials.

The post-processing of semiconductor die can also include many surface mount devices (SMD), passive components, or a combination of the two, which are used to connect semiconductor die or integrated circuits to the substrate surface and the PCB without using one of the PCBs Through hole. A quad flat package (QFP) uses an SMD. SMD includes leads extending from each of the four sides of the package. These leads are sometimes referred to as "gull wing leads." The QFP leads provide electrical input/output (I/O) interconnection between the semiconductor die in the package and the PCB or substrate on which the QFP is mounted. Other SMD packages are made without leads and often refer to flat leadless packages. An example of a flat leadless package is a four-sided flat leadless package (QFN) and double-sided flat no-lead (DFN) packages. QFN packaging conventions include semiconductor dies connected to lead frames for packaged I/O interconnects by wire bonding.

The integration of passive components in fan-out wafer-level packaging (FO-WLP) is generally performed by directly placing the passive components on a temporary carrier tape and then molding or encapsulating the passive components. In the case of an embedded wafer level ball grid array (eWLB), the active surface of the semiconductor die and the passive components can be attached to a tape and then overmolded or encapsulated to form and reconstruct Wafer or panel. After the tape is released, the semiconductor die and the terminals or contact pads of the passive component can be exposed, and a redistribution layer can be applied to the plate so that the conductive traces can be connected to the passive component. Typically, SMD passives soldered to the substrate are attached to the core layer within the substrate to form the application of embedded die in the substrate.

There are opportunities to improve semiconductor manufacturing. Therefore, in one aspect, a method of manufacturing a semiconductor device package may include: providing a substrate including conductive traces; using solder to solder a plurality of surface mount devices (SMD) to the substrate; Encapsulating the plurality of SMDs on the substrate by using a first molding compound above the plurality of SMDs and surrounding one of the plurality of SMDs; and singly cutting the plurality of SMDs by separating the substrate to expose the Equal conductive traces and form a plurality of component assemblies, the plurality of component assemblies is included on the first side of one of the component assemblies Face and exposed conductive traces on the second side of one of the component assemblies, the second side of the component assemblies is opposite the first side of the component assemblies. The method may further include: providing a temporary carrier; installing at least one of the component assemblies to the temporary carrier, wherein the first side of the at least one component assembly and the exposed conductive traces are oriented into Towards the temporary carrier; mounting a semiconductor die including a conductive interconnect to the temporary carrier, the semiconductor die being adjacent to the at least one of the component assemblies; at the at least one single-cut component assembly And when the semiconductor die is mounted to the temporary carrier, a second molding compound is used to encapsulate the at least one of the component assemblies and the semiconductor die to form a reconstructed plate; and to make the conductive mutual The exposed conductive traces are exposed to the first side or the second side of the at least one component assembly with respect to the second molding compound. The method may further include: forming a first redistribution layer over the second molding compound to electrically connect the conductive interconnect and the exposed conductive traces; and singulating the reconstructed sheet.

The method for manufacturing a semiconductor device package may further include a substrate including a two-layer laminate layer, a printed circuit board (PCB), or a blank molded compound plate. The assembly may include passive devices. The semiconductor die may be an embedded semiconductor die, the embedded semiconductor die including a conductive interconnect coupled to the semiconductor die and exposed relative to the second molding compound. The conductive interconnect may include copper bumps, pillars, posts, or thick RDL traces. Welding of the at least one of the single-cut component assemblies to the substrate The material may be contained in the semiconductor device package and not exposed relative to the semiconductor device package.

In another aspect, a method of making a semiconductor device package may include: providing a substrate including conductive traces; attaching an SMD to the substrate using solder to form a device assembly; mounting The assembly to a temporary carrier, wherein a first side of the assembly is oriented toward the temporary carrier; a semiconductor die including a conductive interconnect is mounted to the temporary carrier, the semiconductor die is adjacent to the Component assembly; when the component assembly and the semiconductor die are mounted to the temporary carrier, a mold compound is used to encapsulate the component assembly and the semiconductor die to form a reconstructed plate; and the conductive mutual The conductive traces are exposed to the first side or the second side of the assembly relative to the molding compound.

The method for manufacturing a semiconductor device package may further include a substrate, the substrate including a two-layer laminate layer, a PCB, or a blank molded compound plate. Before mounting the assembly to the temporary carrier, additional molding compound above and around the SMD can be used to encapsulate the SMD on the substrate. The semiconductor die may be an embedded semiconductor die, the embedded semiconductor die includes a conductive interconnect coupled to the semiconductor die and exposed with respect to the molding compound, wherein the conductive interconnect includes copper bumps, pillars, Uprights, or thick RDL traces. The solder coupling the component assembly to the substrate may be contained in the component assembly and not exposed relative to the component assembly. The conductive interconnects and conductive traces can be exposed by removing the temporary carrier from the reconstructed plate and grinding the reconstructed plate. The first redistribution layer may be formed on Reconstruct the top of the board to electrically connect the conductive interconnects and the conductive traces, and the second redistribution layer can be formed opposite the first redistribution layer to electrically connect the exposed conductive traces to form a package through the semiconductor device Electrical connection of thickness.

In another aspect, a method of manufacturing a semiconductor device package may include: providing a substrate including conductive traces; attaching an SMD to the substrate using solder; mounting the SMD and the substrate To a temporary carrier; mounting a semiconductor die including a conductive interconnect that is adjacent to the SMD; applying a molding compound over the temporary carrier; and making the conductive interconnect and the conductive traces Relative to the molding compound is exposed.

The method of making a semiconductor device package may further include mounting a semiconductor die including conductive interconnects, the semiconductor die being adjacent to the temporary carrier. The semiconductor die including semiconductor interconnects can be mounted adjacent to the SMD. The molding compound can be dispensed to encapsulate the SMD and semiconductor die to form a reconstituted sheet. The method may further include: single-cutting the substrate to expose the conductive traces to the first side of the substrate; and mounting the SMD and the substrate to the temporary carrier, wherein the first side of the substrate and the exposed conductive traces are oriented Into a temporary carrier. The substrate may include one or two laminate layers, a printed circuit board (PCB), or a blank molded compound board. The conductive interconnect may include copper bumps, pillars, posts, or thick RDL traces.

Those of ordinary skill in the art will be able to clearly understand the aforementioned and other aspects, features, and advantages from the embodiments, drawings, and patent application scope.

14‧‧‧Semiconductor die/component

18‧‧‧back side/back surface

20‧‧‧acting surface

22‧‧‧conductive layer/contact pad/bonding pad

26‧‧‧Insulation layer/passivation layer

28‧‧‧conductive interconnection/electrical interconnection structure

30‧‧‧Reconstructed sheet/sheet/reconstructed wafer/wafer

32‧‧‧Saw blade/laser cutting tool

40‧‧‧Gap/Saw

41‧‧‧ Adhesive

42‧‧‧Encapsulation

44‧‧‧Embedded semiconductor die

50‧‧‧Substrate/Laminate/Printed Circuit Board (PCB)/Blank Molded Compound Sheet/PCB Strip/Lead Frame

52‧‧‧ Base material core/core material/core

54‧‧‧ conductive trace

56‧‧‧First surface

58‧‧‧welding pad

60‧‧‧Second surface

62‧‧‧Insulation layer/passivation layer

64‧‧‧Insulation layer/passivation layer

68‧‧‧ opening

70‧‧‧SMD/Passive components/Active components/SMD technology/Passive parts

72‧‧‧terminal/contact pad

74‧‧‧ solder/solder paste/Sn connection

78‧‧‧Encapsulation/first molding compound

80‧‧‧Saw blade/laser cutting tool

82‧‧‧3D interconnection assembly/assembly assembly/SMD assembly assembly/assembly/molded passive part/molded assembly

84‧‧‧ conductive trace

86‧‧‧First side/first side surface

88‧‧‧Second side

100‧‧‧Temporary carrier/carrier/substrate

102‧‧‧Interface layer/tape/carrier tape/carrier tape material

104‧‧‧Saw path/distance/space/gap

110‧‧‧Second encapsulation/molding compound

112‧‧‧reconstructed sheet/wafer

114‧‧‧Grinding machine

116‧‧‧Front surface/Bottom surface

118‧‧‧Back surface/Top surface/Second surface/Side

120‧‧‧First stacked interconnect structure/Stacked interconnect structure/Interconnect structure/First stacked interconnect/Redistribution layer

122‧‧‧Insulation layer/passivation layer/conductive layer

124‧‧‧conductive layer/redistribution layer

126‧‧‧Insulation layer/passivation layer

128‧‧‧Bump/ball/interconnect structure

130‧‧‧Second Stacked Interconnect Structure/Stacked Interconnect Structure/Interconnect Structure/Second Stacked Interconnect Structure/Redistribution Layer

132‧‧‧Insulation layer/passivation layer/conductive layer

134‧‧‧conductive layer/redistribution layer

136‧‧‧Insulation layer/passivation layer

138‧‧‧ opening

139‧‧‧POP solder pad/SMD solder pad

140‧‧‧Saw blade/laser cutting tool

142‧‧‧Semiconductor package/semiconductor package/package

144‧‧‧Bottom surface

146‧‧‧Top surface

H‧‧‧ Height

H1‧‧‧ Height

H2‧‧‧ Height

Hm‧‧‧Height

Hs‧‧‧Height

L‧‧‧Length

W‧‧‧Width

FIG. 1 shows an embedded semiconductor die cut from the reconstructed sheet 30.

2A to 2F illustrate the formation of a component assembly, an SMD component assembly, or a 3D interconnection component.

3A to 3F illustrate the formation of a semiconductor device package including a solderable device assembly, an SMD device assembly, or a 3D interconnection device.

The disclosure includes one or more aspects or embodiments in the following description with reference to the drawings, in which similar numbers represent the same or similar elements. Those of ordinary skill in the art should understand that the description is intended to cover alternatives, modifications, and equivalents that can be included within the spirit and scope of the present disclosure as defined by the scope of the accompanying patent application, as well as by The equivalents supported by the following disclosure and drawings. In the description, many specific details are explained, such as specific configurations, components, and procedures, to provide a thorough understanding of the present disclosure. In other cases, in order not to confuse this disclosure, specific details of well-known procedures and manufacturing techniques are not described. In addition, The various embodiments shown in the figures are illustrative representatives and are not necessarily drawn to scale.

The disclosure, its aspects, and implementations are not limited to the specific equipment, material types, or other system component examples or methods disclosed herein. It is envisaged that many additional components, manufacturing, and assembly processes that are well known in the art that are consistent with manufacturing and packaging are used in conjunction with specific implementations from the present disclosure. Accordingly, for example, although specific implementations are disclosed, such implementations and implemented components may include any components, models, types, materials, and versions of components used for such systems and implementations as are well known in the art. , Quantity, and/or the like, these systems and implemented components are consistent with the intended operation.

This text uses the words "exemplary", "example" or its various forms to mean an example, case, or illustration. Any form or design described herein as "exemplary" or as an "instance" is not necessarily considered to be better or superior to other forms or designs. In addition, the examples are provided for the purpose of clarity and understanding only and are not intended to limit or limit the disclosed subject matter or related parts of the disclosure in any way. It should be understood that numerous additional or alternative examples of different categories may be presented, but are omitted for brevity.

Where the following examples, embodiments, and implementations refer to examples, those of ordinary skill in the art should understand that other manufacturing devices and examples can be intermixed with or replace the devices and examples provided. Where the above description refers to specific embodiments, it should be apparent that several modifications can be made without departing from its spirit, and Obviously, these examples and implementations can also be applied to other technologies. Accordingly, the disclosed subject matter is intended to include all such changes, modifications, and changes, all of which fall within the spirit and scope of this disclosure and the knowledge of those with ordinary knowledge in the technical field to which they belong.

Generally speaking, two complicated manufacturing procedures are used to manufacture semiconductor devices: front-end manufacturing and back-end manufacturing. The front-end manufacturing involves forming a plurality of grains on the surface of a semiconductor wafer. Each die on the wafer contains active electrical components and passive electrical components that are electrically connected to form a functional circuit. Active electrical components (such as transistors and diodes) have the ability to control the flow of current. Passive electrical components (such as capacitors, inductors, resistors, and transformers) establish the relationship between voltage and current necessary to perform circuit functions.

A series of process steps are used to form the passive component and the active component above the surface of the semiconductor wafer, including doping, deposition, optical lithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping procedure modifies the conductivity of the semiconductor material in the active device, transforms the semiconductor material into an insulator, a conductor, or dynamically changes the conductivity of the semiconductor material in response to an electric field or base current. Transistors contain regions configured to the different types and doping levels necessary to enable the transistor to promote or limit the flow of current when an electric field or base current is applied.

Active components and passive components are formed by layers of materials with different electrical properties. Layers can be formed by various deposition techniques, The deposition technique is partly determined by the type of material deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating procedures. In general, the layers are patterned to form active component parts, passive component parts, or electrical connection parts between the components.

Optical lithography can be used to pattern the layer, which involves depositing a photosensitive material (eg, photoresist) over the layer to be patterned. Use light to transfer a pattern from a photomask to a photoresist. In one embodiment, a solvent is used to remove the portion of the photoresist pattern that is exposed to light, and the portion of the underlying layer to be patterned is exposed. In another embodiment, a solvent is used to remove the unreceived portion of the photoresist pattern (negative photoresist), and expose the portion of the underlying layer to be patterned. Remove the rest of the photoresist, leaving a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material in areas or voids formed by a previous deposition/etching process by using techniques such as electroless and electrolytic plating.

Patterning is the basic operation of removing the part of the top layer on the surface of the semiconductor wafer. Optical lithography, photomasks, masks, oxide or metal removal, photography and stencil printing, and microlithography can be used to remove portions of semiconductor wafers. Optical lithography includes: forming a pattern in a proportional reticle or a reticle; and transferring the pattern to the surface layer of the semiconductor wafer. Optical lithography uses a two-step process to form the horizontal dimensions of active and passive components on the surface of a semiconductor wafer. The first step is to transfer the pattern of the proportional mask or mask to the photoresist layer. Photoresist system undergoes structure and properties when exposed to light Change one of the photosensitive materials. The procedure for changing the structure and properties of the photoresist occurs as a negative-acting photoresist or a positive-acting photoresist. The second step is to transfer the photoresist layer to the wafer surface. The transfer occurs when etching to remove the portion of the top layer of the semiconductor wafer that is not covered by the photoresist. The chemistry of the photoresist keeps the photoresist substantially intact and resists removal by the chemical etching solution while removing the portion of the top layer of the semiconductor wafer that is not covered by the photoresist. Depending on the specific photoresist used and the desired result, the process of forming, exposing, and removing the photoresist, as well as the process of removing part of the semiconductor wafer, can be modified.

In a negative-acting photoresist, the photoresist is exposed and changes from a soluble state to an insoluble state in a process called polymerization. During polymerization, the unpolymerized material is exposed or exposed to an energy source, and the polymer forms a cross-linked material, which is a resist. In most negative photoresists, the polymer is polyisoprene. A chemical solvent or developer is used to remove the soluble portion (ie, the unexposed portion), leaving holes in the photoresist layer corresponding to the opaque pattern on the proportional mask. A mask whose pattern exists in an opaque area is called a clear-field mask.

In a positive-acting photoresist, the photoresist is exposed and changes from a relatively insoluble state to a more soluble state in a process called photosolubilization. In photolysis, the relatively insoluble photoresist is exposed to appropriate light energy and converted into a more soluble state. In the development process, the photo-dissolved portion of the photoresist can be removed by a solvent. Basic positive photoresist polymer is phenol-formaldehyde polymer, also known as phenol-formaldehyde phenol Aldehyde resin. The soluble portion (ie, the exposed portion) is removed with a chemical solvent or developer, leaving holes in the photoresist layer corresponding to the transparent patterns on the proportional mask. A mask in which a pattern exists in a transparent area is called a dark-field mask.

After removing the top part of the semiconductor wafer that is not covered by the photoresist, the remaining part of the photoresist is removed, leaving a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material in areas or voids formed by a previous deposition/etching process by using techniques such as electroless and electrolytic plating.

Depositing a thin film of material above an existing pattern will increase the underlying pattern and create a non-uniform flat surface. A uniform flat surface may be beneficial or required for the production of smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniform flat surface. Flattening involves polishing the surface of the wafer with a polishing pad. Abrasive materials and corrosive chemicals are added to the surface of the wafer during polishing. Instead, mechanical grinding is used for planarization without using corrosive chemicals. In some embodiments, purely mechanical grinding is achieved by using a belt grinding machine, a standard wafer backgrinder, or other similar machines. The combined grinding mechanical action and chemical corrosion action remove any irregularities, resulting in a uniform flat surface.

Back-end manufacturing refers to cutting or singulating the finished wafer into individual semiconductor die and then packaging the semiconductor die for structural support and environmental isolation. In order to single-cut the semiconductor die, along the saw (saw street) or scribe the non-functional area of the wafer to cut the wafer. Use laser cutting tools or saw blades to cut wafers. After singulation, individual semiconductor dies are mounted to the packaging substrate, which includes contacts or contact pads for interconnection with other system components. Next, the contact pads formed above the semiconductor die are connected to the contact pads in the package. Solder bumps, stud bumps, conductive paste, redistribution layers, or wire bonding can be used to make electrical connections. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. Next, the packaged product is inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

The electrical system may be an independent system that uses semiconductor devices to perform one or more electrical functions. Alternatively, the electrical system may be a sub-component of a larger system. For example, the electrical system may be part of a cellular radiotelephone, part of a personal digital assistant (PDA), part of a digital video camera (DVC), or part of other electronic communication devices. Alternatively, the electrical system may be a graphics card, a network interface card, or other signal processing card that can be inserted into the computer. The semiconductor package may include a microprocessor, memory, special application integrated circuit (ASIC), logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction may be beneficial or necessary for products to be accepted by the market. To achieve higher density, the distance between semiconductor devices must be reduced.

By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can Manufactured with cheaper components and streamlined manufacturing processes. The resulting device is less likely to fail and the manufacturing cost is lower, making consumers less expensive.

However, when combining one or more semiconductor packages on a single substrate, it is not practical to form an RDL layer over a standard solderable passive component with solder or tin (Sn) terminals, because the solder or Sn can be Melt during subsequent processing, causing electrical failure. Therefore, other alternatives are used to reduce failures, such as using more expensive components with bare Cu terminals instead of Sn or solderable components, thereby reducing costs by reducing failures. An alternative to using standard solderable passive components in the case of solder or Sn soldering includes placing SMD passives on the substrate core layer to form embedded die, devices, or components in the substrate, which allows Use solderable passive components while reducing the risk of melting solder and Sn during subsequent processing, and the resulting failures. However, placing SMD passives in the substrate will increase the thickness of the package, and will require a much larger prefabricated substrate area, thereby increasing size and cost, both of which are undesirable.

FIG. 1 shows a cross-sectional view of a plurality of semiconductor dies 14 formed according to the previous manufacturing methods and processes as outlined above and included in a reconstructed plate, sheet, reconstructed wafer, or crystal Within 30. More specifically, the semiconductor die 14 may be formed by a semiconductor wafer or a native wafer, or as a part of a semiconductor wafer or a native wafer, which has a structure support A base substrate material, such as but not limited to silicon, Germanium, gallium arsenide, indium phosphide, or silicon carbide. A plurality of semiconductor dies or components 14 can be formed on the native wafer and can be separated by one of the non-active inter-die wafer regions or saw streets as described above. The sawing path provides a singulation area for singulation of the semiconductor wafer into individual semiconductor dies 14 for inclusion in the reconstructed sheet or wafer 30, which may also include embedding Type grain plate.

Each semiconductor die 14 has a back side or back surface 18 and an active surface 20, the active surface 20 being opposite the back side 18. The active surface 20 contains an analog circuit or a digital circuit. The analog circuit or digital circuit is implemented as an active device, a passive device, a conductive layer, and a dielectric layer formed in the die, and is electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 20 to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuits. The semiconductor die 14 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

A PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process is used to form a conductive layer 22 above the active surface 20. The conductive layer 22 may be one or more layers of aluminum (Al), copper (Cu), Sn, nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 22 operates as a contact pad or bonding pad that is electrically coupled or electrically connected to the circuit on the active surface 20. The conductive layer 22 may be formed as contact pads arranged side by side at a first distance from the edge of the semiconductor die 14 as shown in FIG. 1. Alternatively, the conductive layer 22 may be formed as The contact pads offset in multiple rows such that a first row of contact pads is arranged at a first distance from the edge of the die, and a second row of contact pads alternating with the first row is arranged at a distance from the crystal The edge of the grain reaches a second distance.

FIG. 1 also shows an optional insulating layer or passivation layer 26 conformally applied over the active surface 20 and over the conductive layer 22. The insulating layer 26 may include one or more layers, which are applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable procedures. The insulating layer 26 may include, but is not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), polymer, polyimide, One or more layers of benzocyclobutene (BCB), polybenzoxazole (PBO), or other materials with similar insulating and structural properties. Alternatively, the semiconductor die 14 is packaged without using any PBO layer, and the insulating layer 26 may be formed of different materials or omitted altogether. In another embodiment, the insulating layer 26 includes a passivation layer that is formed above the active surface 20 but not above the conductive layer 22. When the insulating layer 26 exists and is formed over the conductive layer 22, an opening is formed completely through the insulating layer 26 to expose at least a portion of the conductive layer 22, thereby achieving subsequent mechanical and electrical interconnection. Alternatively, when the insulating layer 26 is omitted, the conductive layer 22 is exposed, thereby achieving subsequent electrical interconnection without forming an opening.

FIG. 1 also shows a conductive interconnection or electrical interconnection structure 28. The conductive interconnection or electrical interconnection structure 28 may be formed as a tube, pillar, post, thick RDLS, bump, formed of copper or other suitable conductive material. Or a columnar object, which is provided above the conductive layer 22 and is coupled or connected to the conductive Layer 22. Patterning and metal deposition procedures (such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition procedures) can be used to directly form conductive interconnects 28 On the conductive layer 22. The conductive interconnect 28 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd), or other suitable conductive materials and may include one or more UBM layers. In some embodiments, the conductive interconnect 28 can be formed by depositing a photoresist layer over the semiconductor die 14 and the conductive layer 22. A portion of the photoresist layer can be exposed and removed by an etching and development process, and the conductive interconnect 28 can be formed in the removed portion of the photoresist and above the conductive layer 22 in the form of copper pillars using a selective plating process. The photoresist layer can be removed, leaving conductive interconnect 28, which provides subsequent mechanical and electrical interconnection and a standoff relative to active surface 20. The conductive interconnect 28 may include a height H1 in the range of 10 to 100 micrometers (μm) or a height in the range of 20 to 50 μm, or a height of about 35 μm.

Paste printing, compression molding, transfer molding, liquid encapsulation molding, lamination, vacuum lamination, spin coating, or other suitable applicator may be used to deposit the encapsulation 42 around a plurality of semiconductor die 14. The encapsulant 42 may be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with suitable filler. The semiconductor die 14 may be embedded in the encapsulant 42 together. The encapsulant 42 may be non-conductive and environmentally protect the semiconductor die 14 from external elements and contaminants.

The orientation of the semiconductor die 14 may be upward, where the active surface 20 is oriented away from the carrier on which the semiconductor die 14 is mounted, or alternatively may be installed downward, where the active surface 20 is oriented toward the surface where the semiconductor die 14 is mounted Carrier. Therefore, the adhesive 41 may be included above or omitted from the back surface 18 of the semiconductor die 14 depending on the procedure used to encapsulate the semiconductor die 14 and form the plate 30, the plate 30 Contains semiconductor die 14 that are fully molded in the core of the encapsulant 42 or in the epoxy core.

The sheet 30 may optionally undergo a curing procedure to cure the encapsulant 42. The surface of the encapsulant 42 may be substantially coplanar with the adhesive 41. Alternatively, the encapsulant 42 may be substantially coplanar with the back side 18, which is exposed by removing the carrier and the interface layer. The sheet material 30 may include a coverage area or form factor of any shape and size, including a circle, a rectangle, or a square, such as similar to a 300 mm semiconductor wafer including a circular coverage area having a diameter of 300 millimeters (mm) The appearance size of the appearance size. It can also be formed in any other desired size.

The sheet 30 may undergo an optional grinding operation using a grinder to flatten the surface and reduce the thickness of the sheet 30. Chemical etching can also be used to remove and planarize a portion of the encapsulant 42 in the sheet 30. Therefore, one surface of the conductive interconnect 28 may be exposed at one edge or perimeter of the plate 30 with respect to the encapsulant 42 to provide an electrical connection between the semiconductor die 14 and the subsequently formed redistribution layer or interconnect structure. A saw blade or laser cutting tool 32 may be used to cut the sheet 30 into individual embedded semiconductor dies 44 through the gap or saw 40. The embedded semiconductor die 44 can then be used as a subsequent shape Part of the packaged semiconductor component, as discussed in more detail below. However, the embedded semiconductor die 44 may also be fully testable after the conductive interconnect 28 is applied and before the embedded semiconductor die 44 is singulated or assembled from the sheet 30 into the reconstructed sheet 112 shown in FIG. 3C .

In some cases, the embedded semiconductor die 44 may be as US Patent Application No. 13/632,062 (now USP 8,535,978) entitled "Die Up Fully Molded Fan-out Wafer Level Packaging" filed on April 29, 2015 ), the entire disclosure content of the case is incorporated by reference.

2A shows a cross-sectional profile of a substrate, laminate, printed circuit board (PCB), or blank molded compound sheet 50. FIG. The substrate 50 may include: conductive traces 54 formed on the first surface 56 of the substrate core or core material 52; and land pads 58 formed on the substrate core or One of the core materials 52 is above the second surface 60 and the second surface 60 is opposite to the first surface 56. When the base material 50 is formed as a blank molded compound sheet, the core material 52 may include the same, similar, or similar to the encapsulant 42, encapsulant or first molding compound 78, or second encapsulant or molding compound 110, Or functionally equivalent materials or material properties.

The conductive trace 54 and the bonding pad 58 may be patterned and deposited over the substrate core 52 of the substrate 50. In some cases, the conductive traces 54 may be formed as one or more redistribution layer (RDL) or RDL patterns on the two, which may be formed on only the first surface 56, only the second surface 60, or On or above both the first surface 56 and the second surface 60. Similarly, the solder pad 58 may be formed on or above only the first surface 56, only the second surface 60, or both the first surface 56 and the second surface 60.

Conductive trace 54, solder pad 58, or both may be one or more of Al, Cu, Sn, Ni, Au, Ag, Ti/Cu, TiW/Cu, or coupling agent/Cu or other suitable conductive materials Floor. PVD, CVD, electrolytic plating, electroless plating, or other suitable procedures may be used to form conductive traces 54, solder pads 58, or both. In one embodiment, the conductive trace 54, the bonding pad 58, or both may include a Ti barrier layer, a Cu seed layer, and a Cu layer formed above the Ti barrier layer and the Cu seed layer, and may be provided and subsequent Electrical interconnection of components mounted to the substrate or laminate layer 50. In some cases, the substrate or laminate layer 50 may be purchased or obtained as a preformed or prefabricated item, and the two-layer laminate substrate 50 may include 130 microns (μm) or about 130 μm (such as between 30 and 200 μm Within a range) of a core 52.

The insulating layer or passivation layer 62 may be disposed above the conductive trace 54 and the first surface 56. Similarly, an insulating layer or passivation layer 64 may be disposed above the bonding pad 58 and the second surface 60. The insulating layers 62 and 64 can be SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO formed by PVD, CVD, screen printing, spin coating, spray coating, lamination, sintering, or thermal oxidation , One or more layers of epoxy resin, solder resist material, or other materials with similar insulation and structural properties. In some cases, insulating layers or passivation layers 62 and 64 may be included in the preformed or prefabricated substrate or laminate layer 50. Opening in insulating layer 64 68 may be formed over a portion of the solder pad 58 to facilitate subsequent electrical interconnection with one or more terminals or contact pads 72 on a surface mount device (SMD) (such as the SMD 70 shown in FIG. 2B).

2B shows the surface mounting of the terminal 72 of the SMD 70 to the substrate or laminate layer 50 using solder or solder paste 74. The SMD 70 may have a desired size and include passive components, active components, solderable passive components (such as resistors or capacitors), other semiconductor dies, ICs, wafer-level chip scale packages (WLCSP), and other components. The size of SMD 70 can be sized according to JDEC standard using metric codes or imperial codes, where metric codes give the length and width of SMD components in tens of millimeters, and imperial codes give the length and width of SMD components in hundreds of inches, With some exceptions. In some cases, a 0201 SMD package size may be used, which includes dimensions of about 0.25 mm x 0.125 mm (or .0098 in x 0.0049 in). In other cases, the size of the 0201 package may include a size of 0.6 mm × 0.3 mm (or 0.024 in × 0.012 in). In any case, in some cases, the size of the SMD can be selected to be consistent with the overall configuration and design of the final package, as described in more detail below.

The solder 74 may be placed on the solder pad 58 to promote electrical communication between the SMD 70 and the substrate 50. The solder 74 may include Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof in combination with an optional flux solution. For example, the solder 74 may be eutectic Sn/Pb, high-lead solder, or lead-free solder. Evaporation, electrolytic plating, electroless plating, ball drop, or screen printing procedures can be used Solder 74 is deposited over the substrate 50 and on the solder pad 58. In some embodiments, the solder 74 is Sn solder paste, which is deposited on the substrate 50 and the solder pad 58 using screen printing. After the SMD 70 is coupled to the substrate 50 with the solder 74, the solder 74 may undergo a reflow process or be reflowed to improve the electrical contact between the SMD 70 and the solder pad 58. After reflow, the substrate 50 and SMD 70 may optionally undergo one or more of aqueous cleaning, automated optical inspection (AOI), and plasma cleaning.

Figure 2C shows that the first encapsulation or molding can be performed using paste printing, compression molding, transfer molding, liquid encapsulation molding, lamination, vacuum lamination, spin coating, or other suitable applicator Compound 78 is optionally deposited to surround the plurality of SMD 70. The encapsulant 78 may be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with suitable filler. In some cases, encapsulant 78 may be the same as or similar to encapsulant 42 used in forming embedded semiconductor die 44. The SMD 70 may be embedded in the encapsulant 78 on the substrate 50 together. The encapsulant 78 may be non-conductive and environmentally protect the SMD 70 from external elements and contaminants. After molding or encapsulation, the molded substrate 50 and SMD 70 can undergo post-mold cleaning (PMC) and testing to identify and mark any bad, defective, or non-working SMD 70 in the molded substrate . Although the encapsulation or first molding compound 78 is shown formed or arranged to surround the SMD 70 to facilitate or make it easier to install the final assembly assembly 82 to the temporary carrier 100, as shown in FIG. 3A, the encapsulation or first A molding compound 78 may be optional and may be omitted altogether. In some embodiments, in the encapsulate or the first molding compound 78 series In a completely optional case, the installation of the final assembly assembly 82 to the temporary carrier 100 may be performed without the encapsulant or the first molding compound 78.

As shown in FIG. 2D, the molded substrate 50 can then be singulated into individual component assemblies, SMD component assemblies, or containing encapsulants 78 using a saw blade or laser cutting tool 80 between the SMD 70 The 3D interconnecting assembly 82 of the mold cover. The single cut of the molded substrate 50 can separate the substrate 50 to expose the conductive traces 54 and form a plurality of component assemblies or SMD component assemblies 82. Component assembly 82 may include exposed conductive traces 84, including conductive traces 54, solder pads 58, or both. The exposed conductive trace 84 may be exposed on only the first side 86 of the component assembly 82, only the second side 88 of the component assembly 82, or both the first side 86 and the second side 88, wherein the first side 86 It may be opposite to the second side 88. For the mounting assembly 82, the first side 86 and the second side 88 may be flat, flat, or substantially the same. The component assembly 82 may include a height H in the range of 0.4 to 0.8 mm, 0.5 to 0.7 mm, or about 0.6 mm (such as 0.62 mm). The height H may be the sum of the height Hm of the molding compound and the height Hs of the substrate. The height of the molding compound Hm may be in the range of 0.1 to 0.3 mm, or be about 0.2 mm, such as 0.22 mm. The height Hs of the molding compound may be in the range of 0.2 to 0.6 mm, or about 0.4 mm. The component assembly 82 may also have a length L in the range of 0.9 to 1.3 mm, 1.0 to 1.2 mm, or about 1.1 mm.

2E shows a cross-sectional profile view of the component assembly 82, the figure shows the width W of the component assembly 82, and shows the direction of the component assembly 82, the The direction is perpendicular or orthogonal to the direction of the view shown in FIG. 2D. The width W of the assembly 82 may be in the range of 0.2 to 0.6 mm, 0.3 to 0.5 mm, or about 0.4 mm, such as 0.43 mm. Although exemplary measurements of the length L, width W, and height H of the assembly 82 are given for 0201 SMD 70, SMDs of different sizes can also be used, which will result in the length L, width W, and And the corresponding difference in height H. The view of FIG. 2E also shows the exposed conductive traces 84 on the first side 86 of the component assembly 82 and the second side 88 of the component assembly 82, which can be used for subsequent electrical connection and packaging integration, as described with respect to FIG. 3A As discussed in Figure 3F.

2F shows a perspective view of the component assembly 82, where the exposed conductive traces 84 on the first side 86 of the component assembly are visible. FIG. 2F also shows the relative positioning and orientation of the length L, width W, and height H of the assembly 82.

3A shows a temporary carrier or substrate 100 that contains a temporary base material or sacrificial base material, such as silicon, polymer, stainless steel, or other suitable low-cost rigid materials for structural support. An optional interface layer or double-sided tape 102 may be formed over the temporary carrier 100 as a temporary adhesive film or etch stop layer. In one embodiment, the carrier 100 may include an annular membrane frame with an open central portion, which supports the tape around the tape 102.

One or more (such as plural) component assemblies 82 can be mounted to the temporary carrier 100 and the interface layer 102, wherein the first side 86 of the component assembly 82 and the exposed conductive traces 84 are oriented toward the temporary carrier 100, and the conductive trace 54 is oriented vertically. Accordingly, the second side 88 of the component assembly 82 and the opposite ends of the exposed conductive traces 84 can be oriented away from the temporary carrier 100, or facing upwards, enabling subsequent vertical interconnection within the final semiconductor component package. Therefore, the assembly assembly 82 can be vertical from a horizontal position held on the uncut substrate 50, or rotated 90 degrees relative to the horizontal position. Therefore, the conductive trace 54 may adopt one of the vertical orientations when installed on the temporary carrier 100, rather than the horizontal orientation that is maintained when installed on the portion of the substrate 50 that is not singulated, two of the component assemblies 82 The sides include exposed conductive traces 84, exposed solder pads 58, or both.

FIG. 3B shows that the embedded semiconductor die 44 of FIG. 1 is mounted face up to the temporary carrier 100 and the interface layer 102 with the back side 18 oriented toward the temporary carrier 100 and the active surface 20 oriented away from the temporary carrier 100. The semiconductor die 14 may be placed above the temporary carrier 100 using a pick-and-place operation or other suitable operations. As shown in FIG. 1, the adhesive 41 may be optionally disposed between the back side 18 of the semiconductor die 14 and the temporary carrier 100. The adhesive 41 (when present) may be a thermal epoxy resin, an epoxy resin, a B-stage epoxy resin film, an ultraviolet (UV) B-stage film containing an optional acrylic polymer, or other suitable materials. In one embodiment, an adhesive 41 may be placed above the back side 18 before the semiconductor die 14 is mounted above the temporary carrier 100. Alternatively, the adhesive 41 may be disposed above the temporary carrier 100 before mounting the embedded semiconductor die 44 to the temporary carrier 100. In other embodiments, the embedded semiconductor crystal The pellet 41 can be directly mounted to the interface layer or the support tape 102 or the temporary carrier 100 without using the adhesive 41.

Each embedded semiconductor die 44 may be mounted to the temporary carrier 100, and each embedded semiconductor die 44 is adjacent to or laterally contacts the corresponding component assembly 82. When installed above the temporary carrier 100, the pair of embedded semiconductor die 44 and the component assembly 82 can be separated by a space or gap 104 to provide a saw path or distance 104 for a semiconductor component package to be formed later. In some cases, a portion of the space 104 may be used for a fan-out interconnect structure formed later. Although FIGS. 3A and 3B show that the component assembly 82 is mounted to the temporary carrier 100 before the embedded semiconductor die 44, in other cases, the embedded semiconductor die 44 may be first mounted to the temporary carrier 100 before the component assembly 82 . During the installation of the embedded semiconductor die 44 and the component assembly 82 to the temporary carrier 100, the component assembly 82 may also be installed, coupled, or attached to the embedded semiconductor die 44. For installation, the component assembly 82 can also be flipped, such that the first side 86 thereof is oriented toward the temporary carrier 100 so that the conductive traces 54 are oriented vertically instead of horizontally, so that the conductive traces 54 can provide through Through the final semiconductor component package 142, a vertical interconnection extending completely between the front surface 116 and the back surface 118 of the reconstructed sheet 112 or the semiconductor component package 142. In another case, the component assembly and SMD 70 may be installed horizontally, or the component assembly and SMD 70 may be installed rotated 90 degrees relative to the one shown in FIG. 3B so that the conductive trace 54 is parallel to the temporary carrier 100 Or substantially parallel, such as within 0 to 10 degrees, 0 to 5 degrees, or 0 to 1 degree.

FIG. 3C shows that a second encapsulant or molding compound 110 is used to encapsulate a plurality of component assemblies 82 and embedded semiconductor die 44 or semiconductor die 14. The second encapsulant or molding compound 110 is formed to surround the device The assembly 82, the embedded semiconductor die 44 or the semiconductor die 14, and formed in the space 104, while the single-cut component assembly 82, the embedded semiconductor die 44, and the semiconductor die 14 are mounted to the temporary carrier 100 To form a reconstructed sheet or wafer 112. The second encapsulate 110 may be similar to or the same as the first encapsulate 78, encapsulate 42, or both, and may use paste printing, compression molding, transfer molding, liquid encapsulation molding, lamination , Vacuum lamination, spin coating, or other suitable applicator deposition. The second encapsulant 110 may be a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with suitable filler, which may be non-conductive and environmentally friendly to embed The semiconductor die 44 and the assembly 82 are protected from external elements and contaminants. In some cases, the reconstructed plate or wafer 112 may also include at least one via hole or vertical interconnection in the substrate, the at least one via hole or vertical interconnection between the bottom surface 116 and the top surface 118 of the reconstructed plate 112 It extends between and can be exposed on the bottom surface 116 and the top surface 118 of the reconstructed sheet 112.

The reconstructed board 112 may undergo a grinding operation using one of the grinders 114 to flatten the front surface 116 of the reconstructed board 112 and reduce the thickness of the reconstructed board 112. Chemical etching can also be used to remove and planarize a portion of the reconstructed sheet 112. The grinding operation may expose the conductive interconnects 28 of the embedded semiconductor die 44 and expose the exposed conductive traces 84 The second encapsulant 110 is exposed on the first side 86 of the assembly 82. The reconstructed plate 112 may also undergo a grinding operation using one of the grinders 114 to flatten the back surface 118 of the reconstructed plate 112 and reduce the thickness of the reconstructed plate 112. The grinding operation may also expose the exposed conductive trace 84 to the second side 88 of the assembly 82 relative to the second encapsulant 110.

FIG. 3D shows that a first build-up interconnect structure 120 is formed above the front surface 116 of the reconstructed sheet 112. The stacked interconnect structure 120 may include any desired number of conductive layers and insulating layers, depending on the configuration, design, and routing needs of the final device or semiconductor device package 142. A non-limiting example of stacked interconnect structure 120 is shown and described with respect to FIG. 3D. The stacked interconnect structure 120 may include a conductive layer or redistribution layer (RDL) 124 that is patterned and deposited on the embedded semiconductor die 44 (including the conductive interconnect 28) and the device assembly 82 (Including solder pads 58 and exposed conductive traces 84) above. In some cases, the conductive layer 124 may be directly formed on or contact the front surface 116 of the reconstructed plate 112. In other cases, an intermediate insulating layer or passivation layer 122 may be formed on the conductive layer 124 and the front surface 116 or disposed between the conductive layer 124 and the front surface 116. When the intermediate insulating layer or the passivation layer 122 is present, the insulating layer 122 may be SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyacrylic acid formed by PVD, CVD, screen printing, spin coating, spray coating, sintering, or thermal oxidation. One or more layers of imine, BCB, PBO, or other materials with similar insulating and structural properties.

The conductive layer 124 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti/Cu, TiW/Cu, or coupling agent/Cu or other suitable conductive materials. The conductive layer 124 may be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable procedures. In one embodiment, the conductive layer 124 is an RDL, which includes a TiW seed layer, a Cu seed layer, and a Cu layer formed above the TiW seed layer and the Cu seed layer. In order to transmit electrical signals among points within the completed semiconductor device package, conductive layer 124 may be among conductive interconnects 28, bonding pads 58, exposed conductive traces 84, and other features within completed semiconductor device package 142 Provide electrical interconnection.

When the positions of the embedded semiconductor die 44 and the assembly assembly 82 change from their normal positions, such as during the placement and encapsulation on the temporary carrier 100 to form the reconstructed sheet 112, the embedded semiconductor die 44 and the assembly assembly The actual or actual position of 82 may not be sufficiently aligned with the nominal design of the stacked interconnect structure 120 or the conductive layer 124 to provide the desired reliability of package interconnects given the desired routing density and pitch tolerance. When the position of the embedded semiconductor die 44 and the device assembly 82 is small, there is no need to adjust the position of the conductive layer 124 to properly align the conductive layer 124 with the embedded semiconductor die 44 and the device assembly 82. However, when the position of the embedded semiconductor die 44 and the component assembly 82 within the reconstructed sheet 112 changes so that the nominal position cannot provide proper alignment with and exposure to the conductive layer 122, it may be By Adaptive Patterning ^TM or unit specific patterning (hereinafter, “unit specific patterning”) as described in more detail in US Patent Application No. 13/891,006 filed on May 9, 2013 The adjustment of the position of the stacked interconnect structure 120, the disclosure content of the case is incorporated herein by reference. Therefore, the position, alignment, or position and alignment of the interconnect structure 120 and the conductive layer 124 can be moved by xy, by rotation by the angle θ, by both, or by nominal positions relative to them, etc. Or it is adjusted relative to the reference point or reference point on the reconstructed plate 112, so as to maintain a constant alignment between the embedded semiconductor die 44 and the module package outline and between the component assembly 82 and the module package outline.

FIG. 3D further shows that the insulating layer or passivation layer 126 is conformally applied over the conductive layer 124 and the insulating layer 122 (if present) and contacts the conductive layer 124 and the insulating layer 122. The insulating layer 126 may be SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, applied using PVD, CVD, screen printing, spin coating, spraying, sintering, thermal oxidation, or other suitable procedures. One or more layers of dry film resist, or other materials with similar insulating and structural properties. The insulating layer 126 may be patterned, and a portion of the insulating layer 126 may be removed by etching, laser drilling, mechanical drilling, or other suitable procedures to form an opening completely through the insulating layer 126 to expose the conductive layer 124. The opening in the insulating layer 126 may be used to receive bumps, balls, or interconnect structures 128.

The conductive bump material can be deposited on the portion of the conductive layer 124 (which can be formed as an under bump metallization (UBM) pad) by using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process To form bumps 128. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and their combinations can be combined with an optional flux solution. For example, the bump material may be eutectic Sn/Pb, high-lead solder, or lead-free solder. A suitable attachment or bonding procedure may be used to bond the bump material to the conductive layer 124. In one embodiment, the bump material may be reflowed by heating the bump material above its melting point to form the bump 128. In some applications, the bump 128 is reflowed a second time to improve the electrical contact to the conductive layer 124. The bump 128 may also be compression bonded or thermocompression bonded to the conductive layer 124. The bump 128 represents a type of interconnect structure that can be formed over the conductive layer 124. The bump 128 may also include pillar bumps, micro bumps, or other electrical interconnects.

3E shows a reconstructed sheet 112, in which a first stacked interconnect structure 120 is formed on the reconstructed sheet 112, and the reconstructed sheet 112 is removed from the temporary carrier 100, after which the temporary carrier may optionally undergo a grinding operation ( This polishing operation is similar to the polishing operation of FIG. 3C, but it is on the back surface 118 instead of the front surface 116) to planarize the back surface 118 to reduce the thickness of the reconstructed sheet 112 and to expose the exposed conductive traces 84 The second encapsulant 110 or the back surface 118 is exposed to the second side 88 of the assembly 82. Thus, in various embodiments, the exposed conductive traces 84 (such as conductive traces 54 and solder pads 58) may be exposed on only the first side 86, only on the second side 88, or may be exposed on the first side Both 86 and the second side 88. In some cases, the exposed conductive trace 84 is exposed relative to the second encapsulant 110, while in other cases, the exposed conductive trace 84 is relative to the first side 86, the second side 88, or both Exposed.

With the exposed conductive trace 84 exposed to the second side 88 of the assembly 82, the second stacked interconnect structure 130 may be formed over the back surface 118 of the reconstructed sheet 112. The stacked interconnect structure 130 may include any desired number of conductive layers and insulating layers, depending on the configuration, design, and routing needs of the final device or semiconductor device package 142. A non-limiting example of stacked interconnect structure 130 is shown and described with respect to FIG. 3E. The stacked interconnect structure 130 may include a conductive layer or redistribution layer (RDL) 134 that is patterned and deposited over the embedded semiconductor die 44 and the device assembly 82 (including the bonding pad 58 and Above exposed conductive trace 84). In some cases, the conductive layer 134 may be directly formed on or contact the back surface 118 of the reconstructed plate 112. In other cases, an intermediate insulating layer or passivation layer 132 may be formed on the conductive layer 134 and the back surface 118 or disposed between the conductive layer 134 and the back surface 118. When the intermediate insulating layer or the passivation layer 132 is present, the insulating layer 132 may be SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyacrylic formed by PVD, CVD, screen printing, spin coating, spray coating, sintering, or thermal oxidation One or more layers of imine, BCB, PBO, or other materials with similar insulating and structural properties.

The conductive layer 134 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti/Cu, TiW/Cu, or coupling agent/Cu or other suitable conductive materials. The conductive layer 134 may be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable procedures. In one embodiment, the conductive layer 134 is an RDL or fan-out RDL, which includes A TiW seed layer, a Cu seed layer, and a Cu layer formed above the TiW seed layer and the Cu seed layer. In order to transmit electrical signals among points within the completed semiconductor device package, conductive layer 134 may provide electrical interconnection between bonding pads 58, exposed conductive traces 84, and other features within completed semiconductor device package 142 .

When the positions of the embedded semiconductor die 44 and the assembly assembly 82 change from their normal positions, such as during the placement and encapsulation on the temporary carrier 100 to form the reconstructed sheet 112, the embedded semiconductor die 44 and the assembly assembly The actual or actual position of 82 may not be sufficiently aligned with the nominal design of the stacked interconnect structure 130 or the conductive layer 134 to provide the desired reliability of package interconnects given the desired routing density and pitch tolerance. When the positions of the embedded semiconductor die 44 and the device assembly 82 are small, there is no need to adjust the position of the conductive layer 134 to properly align the conductive layer 134 with the embedded semiconductor die 44 and the device assembly 82. However, when the position of the embedded semiconductor die 44 and the component assembly 82 within the reconstructed sheet 112 changes so that the nominal position cannot provide proper alignment with and exposure to the conductive layer 132, it may be The position of the stacked interconnect structure 130 is adjusted by cell-specific patterning. Therefore, the position, alignment, or position and alignment of the interconnect structure 130 and the conductive layer 134 can be moved by xy, by rotation of the angle θ, by both, or by nominal positions relative to them, etc. Or it is adjusted relative to the reference point or reference point on the reconstructed plate 112, so as to maintain a constant alignment between the embedded semiconductor die 44 and the module package outline and between the component assembly 82 and the module package outline.

FIG. 3E further shows that the insulating layer or passivation layer 136 is conformally applied over the conductive layer 134 and the insulating layer 132 (if present) and contacts the conductive layer 134 and the insulating layer 132. The insulating layer 136 may be SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable procedures. One or more layers of dry film resist, or other materials with similar insulating and structural properties. The insulating layer 136 may be patterned, and a portion of the insulating layer 136 may be removed by etching, laser drilling, mechanical drilling, or other suitable procedures to form an opening 138 completely through the insulating layer 136 to expose the conductive Layer 134. The opening 138 in the insulating layer 136 may expose a portion of the conductive layer 134 (which is formed as a POP pad or SMD pad 139 formed on the top routing layer of the second stacked interconnect structure 130) for receiving Bumps, balls, or interconnect structures 128 and other devices, packages, SMDs, surface mount devices (SMD), surface mount components (such as packaged ICs, passive components, connectors, mechanical parts, EMI shielding), or to Installation of substrates or other devices.

After forming the first stacked interconnection structure 120 and the second stacked interconnection structure 130, the reconstructed sheet material and the first stacked interconnection 120 and the second stacked interconnection 130 may be cut into single pieces using a saw blade or a laser cutting tool 140 Individual semiconductor package 142.

FIG. 3F shows an enlarged view of the semiconductor package 142 of FIG. 3E. As shown, the reconstructed sheet or wafer 112 may include a height H1 of about 0.43 mm, and includes a first stacked interconnect structure 120 and a second stacked The overall package height H2 of the height of the interconnect structure 130 may be 0.5 mm, or about 0.5 mm, such as 0.3 mm to 0.7 mm. The first stacked interconnect structure 120 and the second stacked interconnect structure 130 may be coupled to the conductive traces 54 of the through-mold and the solder pads 58 of the SMD 70, and directly electrically connect the conductive traces 54 of the through mold and the The solder pads 58 of the SMD 70 provide vertical electrical interconnection between the bottom surface 144 of the package 142 and the top surface 146 of the package 142. In some cases, component assembly 82 may be sawn slightly larger than the height or thickness H1 of the finished product, so that the conductive traces 54 extending vertically through the mold may be exposed during the top and bottom grinding steps, such as using as shown in FIG. 3C The grinder 114 grinds the back surface 118 before grinding the front surface 116 and before forming the second stacked interconnect structure 130, as shown in FIG. 3E.

Improved integration and reduced size of semiconductor packages 142, including the inclusion of component assemblies 82 with solder or Sn connections 74, are particularly suitable for small electronic systems (such as smart watches) and require reduced external dimensions or possibly the smallest The appearance of other IoT devices. The method of embedding the solderable component 82 in the core of the 3D fan-out wafer level package or semiconductor component package 142 may include: using solder reflow to attach the passive component or active component 70 to a substrate or PCB strip 50; Overmolding the strip to encapsulate the assembly 70; cutting the strip to form discrete molded assemblies 82; and placing at least one molded assembly 82 on a temporary carrier 100 so that the conductive traces within the assembly 82 54 is vertically oriented, and the first side surface 86 is oriented toward and attached to the carrier 100.

The method may further include: placing at least one semiconductor die 14 having conductive interconnects 28 or Cu-plated bumps on the temporary carrier tape 102, the semiconductor die 14 being adjacent to the assembly or molded passive member 82; encapsulation Temporary carrier 100 to form reconstructed sheet or wafer 112; grind reconstructed sheet 112 to expose conductive interconnects or Cu bumps 28 on semiconductor die 14 and conductive traces 54 (conductive traces 54) within mold assembly 82 At least two of them are electrically connected to an SMD, passive component, or active component 70) without exposing the solder 74 embedded in the component assembly or the molded component 82; and forming a first stacked interconnect structure or redistribution layer 120 on the reconstructed plate 112 to electrically connect at least one contact pad 22 on the semiconductor die 14 to at least one terminal 72 on the SMD or embedded passive component 70. Alternatively, a second stacked interconnect structure or redistribution layer 130 may be formed on the opposite second surface or side 118 of the reconstructed sheet 112, contacting one of the conductive traces 54 within the assembly or discrete molding assembly 82 At least one of them makes electrical connection through the height H1 or thickness of the semiconductor device package 142 to the contact pad or bonding pad 22 on the semiconductor die 14.

As shown in FIG. 3F, the semiconductor device package 142 may include one or more semiconductor dies 14 and SMD technology 70. The SMD technology 70 may include other semiconductor dies, ICs, passive devices, and wafer-level chip scale packaging (WLCSP) And other components, the SMD technology 70 is mounted to the embedded semiconductor die 44 and is included in the semiconductor device package 142, instead of mounting the SMD 70 to the conventional substrate or PCB and from the semiconductor die 14 to the conventional substrate or PCB The embedded semiconductor die 44 deviates.

Therefore, the semiconductor component package 142 can provide many advantages, including: integrating and using standard low-cost 0201 passive parts with Sn terminals; for easy installation to the interface layer or carrier tape material 102, the SMD 70 includes a flat first side surface 86; the height H1 of the conductive trace 54 passing through the semiconductor component package 142 is used or manipulated into a 3D or vertical interconnection structure to achieve a PoP configuration; 0201 passive parts are integrated within a thickness of 0.5mm; compatible with full molding Wafer-level fan-out semiconductor package design (including Deca M-Series ^TM package); and external component assembly does not require additional internal procedures or equipment and does not require additional cycle time.

In some variations of the semiconductor device package 142, the length L of the device assembly 82 may extend and include more SMD or passive members 70 and more conductive traces 54 through the mold. In some cases, the substrate 50 may be formed as a multilayer substrate to add additional conductive traces 54 through the mold. In other cases, the SMD or passive member 70 may be installed above the opposing first surface 56 and second opposing surface 60 of the substrate 50 or the substrate core 52. When the SMD 70 is installed above the opposite surface of the substrate 50, one or both sides of the substrate 50 with the SMD 70 may be molded or encapsulated. In still other cases, small active Si semiconductor dies can be incorporated on the substrate 50 with the SMD 70. In addition, in the case when the SMD 70 is included in the semiconductor device package 142 including a single-sided (2D) package structure, the 2D package structure may be formed without the second stacked interconnect structure or the RDL 130, so that the device The assembly 82 can be mounted to the interface layer or sheet carrier tape 102 in a horizontal orientation, and the substrate or lead frame 50 It may face upwards so that the POP or SMD solder pad 139 is exposed during the sheet grinding process or the pre-grinding process, as shown in FIG. 3C.

Although this disclosure includes several embodiments in different forms, the details of specific embodiments are presented in the drawings and the description written below, and understanding the disclosure is regarded as an example and principle of the disclosed method and system, and is not intended to make The broad aspects of the disclosed concepts are limited to the illustrated embodiments. In addition, those of ordinary skill in the art should understand that other structures, manufacturing devices, and examples may be intermixed with or replace the devices and examples provided. Where the above description refers to specific embodiments, it should be apparent that several modifications can be made without departing from the spirit thereof, and it is obvious that these embodiments and implementations can also be applied to other technologies. Accordingly, the disclosed subject matter is intended to include all such changes, modifications, and changes, all of which fall within the spirit and scope of this disclosure and the knowledge of those with ordinary knowledge in the technical field to which they belong. Therefore, it is obvious that various modifications and changes can be made to it without departing from the broader spirit and scope of the invention as set forth in the scope of the accompanying patent application. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

14‧‧‧Semiconductor die/component

18‧‧‧back side/back surface

20‧‧‧acting surface

22‧‧‧conductive layer/contact pad/bonding pad

26‧‧‧Insulation layer/passivation layer

28‧‧‧conductive interconnection/electrical interconnection structure

30‧‧‧Reconstructed sheet/sheet/reconstructed wafer/wafer

32‧‧‧Saw blade/laser cutting tool

40‧‧‧Gap/Saw

41‧‧‧ Adhesive

42‧‧‧Encapsulation

44‧‧‧Embedded semiconductor die

Claims (20)

A method of manufacturing a semiconductor device package includes: providing a substrate including conductive traces; using solder to solder a plurality of surface mount devices (SMD) to the substrate; using a first molded compound capsule Sealing the plurality of SMDs on the substrate, the first molding compound is above or around the plurality of SMDs; the plurality of SMDs are singulated by separating the substrate to expose the conductive traces Wires and form a plurality of component assemblies that include exposed conductive traces on one of the first sides of the component assemblies and a second side of the component assemblies, the component assemblies The second side is opposite to the first side of the assembly; providing a temporary carrier; installing at least one of the assembly to the temporary carrier, wherein the first of the at least one assembly The sides and the exposed conductive traces are oriented toward the temporary carrier; mounting a semiconductor die including a conductive interconnect to the temporary carrier, the semiconductor die adjacent to the at least one of the component assemblies When the at least one single-cut component assembly and the semiconductor die are mounted to the temporary carrier, a second molding compound is used to encapsulate the The at least one of the component assemblies and the semiconductor die to form a reconstructed panel; exposing the conductive interconnect and the exposed conductive traces to the at least one with respect to the second molding compound The first side or the second side in a component assembly; forming a first redistribution layer above the second molding compound to electrically connect the conductive interconnect and the exposed conductive traces; and Cut the reconstructed sheet in one piece. The method of claim 1, wherein the substrate comprises a two-layer laminate layer, a printed circuit board (PCB), or a blank molded compound board. The method of claim 1, wherein the component assemblies include passive devices. The method of claim 1, wherein the semiconductor die is an embedded semiconductor die, the embedded semiconductor die including the conductive interconnect coupled to the semiconductor die and exposed relative to the second molding compound. The method of claim 1, wherein the conductive interconnect comprises copper bumps, pillars, posts, or thick RDL traces. The method of claim 1, wherein the solder coupling the at least one of the singulated device assemblies to the substrate is contained in the semiconductor device package and is not exposed relative to the semiconductor device package . A method for manufacturing a semiconductor component package includes: providing a substrate including conductive traces; attaching a surface mount device (SMD) to the substrate using solder to form a component assembly; mounting the component Assembly to a temporary carrier, wherein a first side of the assembly is oriented towards the temporary carrier; a semiconductor die including a conductive interconnect is mounted to the temporary carrier, the semiconductor die is adjacent to the assembly When the component assembly and the semiconductor die are mounted on the temporary carrier, a molding compound is used to encapsulate the component assembly and the semiconductor die to form a reconstructed sheet; and the conductive interconnect and the Equal conductive traces are exposed to the first side or the second side of the assembly relative to the molding compound. The method of claim 7, wherein the substrate comprises a two-layer laminate, a printed circuit board (PCB), or a blank molded compound board. The method of claim 7, further comprising encapsulating the SMD on the substrate with an additional molding compound before mounting the assembly to the temporary carrier, the additional molding compound over and around the SMD . The method of claim 7, wherein the semiconductor die is an embedded semiconductor die, which includes a phase coupled to the semiconductor die For the conductive interconnect exposed to the molding compound, where the conductive interconnect includes copper bumps, pillars, posts, or thick RDL traces. The method of claim 7, wherein the solder coupling the component assembly to the substrate is contained in the component assembly and is not exposed relative to the component assembly. The method of claim 7, wherein exposing the conductive interconnect and the conductive traces further comprises: removing the temporary carrier from the reconstructed sheet and grinding the reconstructed sheet. The method of claim 7, further comprising: forming a first redistribution layer above the reconstructed sheet to electrically connect the conductive interconnects and the conductive traces; and forming the first redistribution layer opposite A second redistribution layer electrically connects the exposed conductive traces to pass through a thickness of the semiconductor device package to form an electrical connection. A method of manufacturing a semiconductor device package includes: providing a substrate including conductive traces; attaching a surface mount device (SMD) to the substrate using solder; mounting the SMD and the substrate to a A temporary carrier; mounting a semiconductor die including a conductive interconnect, the semiconductor die adjacent to the SMD; applying a molding compound over the temporary carrier; and The conductive interconnect and the conductive traces are exposed relative to the molding compound. The method of claim 14, further comprising mounting the semiconductor die including the conductive interconnect, the semiconductor die adjacent to the temporary carrier. The method of claim 14, further comprising mounting the semiconductor die including the conductive interconnect, the semiconductor die adjacent to the SMD. The method of claim 14, further comprising applying a molding compound to encapsulate the SMD and the semiconductor die, thereby forming a reconstructed plate. The method of claim 14, further comprising: single-cutting the substrate to expose the conductive traces to a first side of the substrate; and mounting the SMD and the substrate to the temporary carrier, wherein the substrate The first side of the material and the exposed conductive traces are oriented toward the temporary carrier. The method of claim 14, wherein the substrate comprises a two-layer laminate layer, a printed circuit board (PCB), or a blank molded compound board. The method of claim 14, wherein the conductive interconnect comprises copper bumps, pillars, pillars, or thick RDL traces.

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